Transcript
Low Cost, Low Power, Differential ADC Driver AD8137
Data Sheet FEATURES
ADC drivers Automotive vision and safety systems Automotive infotainment systems Portable instrumentation Battery-powered applications Single-ended-to-differential converters Differential active filters Video amplifiers Level shifters
8
+IN
VOCM 2
7
PD
VS+ 3
6
VS–
+OUT 4
5
–OUT
04771-0-001
AD8137 –IN 1
Figure 1.
3 G=1
2 1 0 –1
G=5
–2 –3
G=2
–4 –5 G = 10
–6 –7 –8 –9
04771-0-002
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
NORMALIZED CLOSED-LOOP GAIN (dB)
Fully differential Extremely low power with power-down feature 2.6 mA quiescent supply current @ 5 V 450 µA in power-down mode @ 5 V High speed 110 MHz large signal 3 dB bandwidth @ G = 1 450 V/µs slew rate 12-bit SFDR performance @ 500 kHz Fast settling time: 100 ns to 0.02% Low input offset voltage: ±2.6 mV max Low input offset current: 0.45 µA max Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Externally adjustable gain Wide supply voltage range: 2.7 V to 12 V Available in small SOIC package Qualified for automotive applications
–10
RG = 1kΩ VO, dm = 0.1V p-p –11 –12 0.1 1
10 FREQUENCY (MHz)
100
1000
Figure 2. Small Signal Response for Various Gains
GENERAL DESCRIPTON The AD8137 is a low cost differential driver with a rail-to-rail output that is ideal for driving ADCs in systems that are sensitive to power and cost. The AD8137 is easy to apply, and its internal common-mode feedback architecture allows its output commonmode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides inherently balanced outputs as well as suppression of even-order harmonic distortion products. Fully differential and single-ended-to-differential gain configurations are easily realized by the AD8137. External feedback networks consisting of four resistors determine the
closed-loop gain of the amplifier. The power-down feature is beneficial in critical low power applications. The AD8137 is manufactured on Analog Devices, Inc., proprietary second-generation XFCB process, enabling it to achieve high levels of performance with very low power consumption. The AD8137 is available in the small 8-lead SOIC package and 3 mm × 3 mm LFCSP package. It is rated to operate over the extended industrial temperature range of −40°C to +125°C.
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
AD8137
Data Sheet
TABLE OF CONTENTS Features .............................................................................................. 1
Test Circuits ..................................................................................... 21
Applications ....................................................................................... 1
Theory of Operation ...................................................................... 22
Functional Block Diagram .............................................................. 1
Applications Information .............................................................. 23
General Descripton .......................................................................... 1
Analyzing a Typical Application with Matched RF and RG Networks...................................................................................... 23
Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 Maximum Power Dissipation ..................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10
Estimating Noise, Gain, and Bandwith with Matched Feedback Networks .................................................................... 23 Driving an ADC with Greater than 12-Bit Performance ...... 27 Outline Dimensions ....................................................................... 29 Ordering Guide .......................................................................... 30 Automotive Products ................................................................. 30
Typical Performance Characteristics ........................................... 11
REVISION HISTORY 7/12—Rev. D to Rev. E Changes to Features Section and Applications Section ............... 1 Added AD8137W ............................................................... Universal Updated Outline Dimensions ....................................................... 28 Changes to Ordering Guide .......................................................... 29 Added Automotive Products Section .......................................... 29 7/10—Rev. C to Rev. D Changes to Power-Down Section, Added Figure 68, Renumbered Subsequent Figures ................................................. 24 Changes to Ordering Guide .......................................................... 27 12/09—Rev. B to Rev. C Changes to Product Title, Applications Section, and General Description Section .......................................................................... 1 Changes to Input Resistance Parameter Unit, Table 3 ................. 5 Added EPAD Mnemonic/Description, Table 6 ............................ 7 Added Figure 61; Renumbered Sequentially .............................. 17 Moved Test Circuits Section.......................................................... 18 Changes to Power Down Section ................................................. 24 Updated Outline Dimensions ....................................................... 26
8/04—Rev. 0 to Rev. A. Added 8-Lead LFCSP......................................................... Universal Changes to Layout .............................................................. Universal Changes to Product Title and Figure 1 ...........................................1 Changes to Specifications .................................................................3 Changes to Absolute Maximum Ratings ........................................6 Changes to Figure 4 and Figure 5 ....................................................7 Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48, and Figure 58; Renumbered Sequentially ......................................7 Changes to Figure 32...................................................................... 12 Changes to Figure 40...................................................................... 13 Changes to Figure 55...................................................................... 16 Changes to Table 7 and Figure 63................................................. 18 Changes to Equation 19 ................................................................. 19 Changes to Figure 64 and Figure 65............................................. 20 Changes to Figure 66...................................................................... 22 Added Driving an ADC with Greater Than 12-Bit Performance Section ...................................................................... 22 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 5/04—Revision 0: Initial Version
7/05—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 24
Rev. E | Page 2 of 32
Data Sheet
AD8137
SPECIFICATIONS VS = ±5 V, VOCM = 0 V (@ 25°C, differential gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C). Table 1. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time Noise/Harmonic Performance SFDR Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current
Conditions
Min
Typ
VO, dm = 0.1 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V step VO, dm = 3.5 V step G = 2, VI, dm = 12 V p-p triangle wave
64 63 79 79
76
VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V AD8137W only: TMIN-TMAX TMIN to TMAX TMIN to TMAX
−2.6 −5.0
450 100 85 90 76 8.25 1
dB dB nV/√Hz pA/√Hz
110
±0.7 3 0.5 0.1
Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM Dynamic Performance −3 dB Bandwidth Slew Rate Gain
−4 −4
66 66
Each single-ended output, RL, dm = 1 kΩ AD8137W only: TMIN-TMAX
VS− + 0.55 VS− + 0.55
1.0 0.45 0.45
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p
V V KΩ KΩ pF dB dB
VS+ − 0.55 VS+ − 0.55
V V mA dB
800 400 1.8 79
AD8137W only: TMIN-TMAX
0.992 0.990
AD8137W only: TMIN-TMAX
−4 −4
Input Resistance Input Offset Voltage AD8137W only: TMIN-TMAX f = 100 kHz to 1 MHz Rev. E | Page 3 of 32
−28 −28
58 63 1.000
35 ±11 18
mV mV µV/°C µA µA µA dB
+4 +4
20 −64
f = 1 MHz
VOCM Input Characteristics Input Voltage Range
Input Voltage Noise
+2.6 +5.0
91
AD8137W only: TMIN-TMAX Differential Common-mode Common-mode ∆VICM = ±1 V AD8137W only: TMIN-TMAX
Unit
MHz MHz MHz MHz V/µs Ns Ns
AD8137W only: TMIN-TMAX Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range
Max
1.008 1.008
MHz V/µs V/V V/V
+4 +4
V V
+28 +28
kΩ mV mV nV/√Hz
AD8137 Parameter Input Bias Current CMRR
Data Sheet Conditions
Min
Typ 0.3
AD8137W only: TMIN-TMAX ∆VO, dm/∆VOCM, ∆VOCM = ±0.5 V AD8137W only: TMIN-TMAX
62 62
75
AD8137W only: TMIN-TMAX
+2.7 +2.7
Power Supply Operating Range Quiescent Current Quiescent Current, Disabled PSRR
3.2 AD8137W only: TMIN-TMAX Power-down = low AD8137W only: TMIN-TMAX ∆VS = ±1 V AD8137W only: TMIN-TMAX
PD Pin Threshold Voltage Input Current
AD8137W only: TMIN-TMAX Power-down = high/low AD8137W only: TMIN-TMAX
OPERATING TEMPERATURE RANGE
750 79 79
Rev. E | Page 4 of 32
Unit µA µA dB dB
±6 ±6 3.60 3.65 900 900
V V mA mA µA µA dB dB
VS− + 1.7 VS− + 1.7 170/240 180/245 +125
V V µA µA °C
91
VS− + 0.7 VS− + 0.7 150/210 −40
Max 1.1 1.1
Data Sheet
AD8137
VS = 5 V, VOCM = 2.5 V (@ 25°C, differential gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C). Table 2. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time Noise/Harmonic Performance SFDR Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current
Conditions
Min
Typ
VO, dm = 0.1 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V step VO, dm = 3.5 V step G = 2, VI, dm = 7 V p-p triangle wave
63 61 76 76
75
VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V AD8137W only: TMIN-TMAX TMIN to TMAX TMIN to TMAX
−2.7 −5.0
375 110 90 89 73 8.25 1
dB dB nV/√Hz pA/√Hz
107
±0.7 3 0.5 0.1
Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM Dynamic Performance −3 dB Bandwidth Slew Rate Gain
+2.7 +5.0 0.9 0.45 0.45
89 1 1
AD8137W only: TMIN-TMAX Differential Common-mode Common-mode ∆VICM = ±1 V AD8137W only: TMIN-TMAX
64 64
Each single-ended output, RL, dm = 1 kΩ AD8137W only: TMIN-TMAX
VS− + 0.45 VS− + 0.45
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p
V V kΩ kΩ pF dB dB
VS+ − 0.45 VS+ − 0.45
V V mA dB
800 400 1.8 90
AD8137W only: TMIN-TMAX
0.980 0.975
AD8137W only: TMIN-TMAX
1 1
AD8137W only: TMIN-TMAX
−25 −25
VOCM Input Characteristics Input Voltage Range Input Resistance Input Offset Voltage
Rev. E | Page 5 of 32
60 61 1.000
1.020 1.020 4 4
35 ±7.5
mV mV µV/°C µA µA µA dB
4 4
20 −64
f = 1 MHz
Unit
MHz MHz MHz MHz V/µs ns ns
AD8137W only: TMIN-TMAX Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range
Max
+25 +25
MHz V/µs V/V V/V V V kΩ mV mV
AD8137 Parameter Input Voltage Noise Input Bias Current CMRR
Data Sheet Conditions f = 100 kHz to 5 MHz
Min
AD8137W only: TMIN-TMAX ∆VO, dm /∆VOCM, ∆VOCM = ±0.5 V AD8137W only: TMIN-TMAX
62 62
AD8137W only: TMIN-TMAX
+2.7 +2.7
Power Supply Operating Range Quiescent Current Quiescent Current, Disabled PSRR
AD8137W only: TMIN-TMAX Power-down = high/low AD8137W only: TMIN-TMAX
OPERATING TEMPERATURE RANGE
450 79 79
Rev. E | Page 6 of 32
0.9 0.9
50/110
Unit nV/√Hz µA µA dB dB
±6 ±6 2.8 2.8 600 600
V V mA mA µA µA dB dB
VS− + 1.5 VS− + 1.5 60/120 60/125 +125
V V µA µA °C
91
VS− + 0.7 VS− + 0.7
−40
Max
75
2.6 AD8137W only: TMIN-TMAX Power-down = low AD8137W only: TMIN-TMAX ∆VS = ±1 V AD8137W only: TMIN-TMAX
PD Pin Threshold Voltage Input Current
Typ 18 0.25
Data Sheet
AD8137
VS = 3 V, VOCM = 1.5 V (@ 25°C, differential gain = 1, RL, dm = RF = RG = 1 kΩ, unless otherwise noted, TMIN to TMAX = −40°C to +125°C). Table 3. Parameter DIFFERENTIAL INPUT PERFORMANCE Dynamic Performance −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time Noise/Harmonic Performance SFDR Input Voltage Noise Input Current Noise DC Performance Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current
Conditions
Min
Typ
VO, dm = 0.1 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V p-p AD8137W only: TMIN-TMAX VO, dm = 2 V step VO, dm = 3.5 V step G = 2, VI, dm = 5 V p-p triangle wave
61 58 62 62
73
VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V AD8137W only: TMIN-TMAX TMIN to TMAX TMIN to TMAX
−2.75 −5.25
340 110 100 89 71 8.25 1
dB dB nV/√Hz pA/√Hz
93
±0.7 3 0.5 0.1
Input Resistance Input Capacitance CMRR Output Characteristics Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM Dynamic Performance −3 dB Bandwidth Slew Rate Gain
Each single-ended output, RL, dm = 1 kΩ AD8137W only: TMIN-TMAX
1 1
64 64
0.9 0.4 0.4
V V kΩ kΩ pF dB dB
VS+ − 0.37 VS+ − 0.37
V V mA dB
20 −64
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p AD8137W only: TMIN-TMAX
0.960 0.955
AD8137W only: TMIN-TMAX
1.0 1.0
Input Resistance Input Offset Voltage AD8137W only: TMIN-TMAX f = 100 kHz to 5 MHz AD8137W only: TMIN-TMAX Rev. E | Page 7 of 32
−25 −25
61 59 1.00
1.040 1.040 2.0 2.0
35 ±5.5 18 0.3
mV mV µV/°C µA µA µA dB
2 2 800 400 1.8 80
VS− + 0.37 VS− + 0.37
f = 1 MHz
VOCM Input Characteristics Input Voltage Range
Input Voltage Noise Input Bias Current
+2.75 +5.25
87
AD8137W only: TMIN-TMAX Differential Common-mode Common-mode ∆VICM = ±1 V AD8137W only: TMIN-TMAX
Unit
MHz MHz MHz MHz V/µs Ns Ns
AD8137W only: TMIN-TMAX Open-Loop Gain Input Characteristics Input Common-Mode Voltage Range
Max
+25 +25 0.7 0.7
MHz V/µs V/V V/V V V kΩ mV mV nV/√Hz µA µA
AD8137 Parameter CMRR
Data Sheet Conditions ∆VO, dm /∆VOCM, ∆VOCM = ±0.5 V AD8137W only: TMIN-TMAX
Min 62 62
AD8137W only: TMIN-TMAX
+2.7 +2.7
Power Supply Operating Range Quiescent Current Quiescent Current, Disabled PSRR
2.3 AD8137W only: TMIN-TMAX Power-down = low AD8137W only: TMIN-TMAX ∆VS = ±1 V AD8137W only: TMIN-TMAX
PD Pin Threshold Voltage Input Current
Typ 74
AD8137W only: TMIN-TMAX Power-down = high/low AD8137W only: TMIN-TMAX
OPERATING TEMPERATURE RANGE
345 78 78
Rev. E | Page 8 of 32
Unit dB dB
±6 ±6 2.5 2.5 460 460
V V mA mA µA µA dB dB
VS− + 1.5 VS− + 1.5 10/70 10/75 +125
V V µA µA °C
90
VS− + 0.7 VS− + 0.7 8/65 −40
Max
Data Sheet
AD8137
ABSOLUTE MAXIMUM RATINGS The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a 1 kΩ differential load on the output. RMS output voltages should be considered when dealing with ac signals.
Table 4. Parameter Supply Voltage VOCM Power Dissipation Input Common-Mode Voltage Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature
Rating 12 V VS+ to VS− See Figure 3 VS+ to VS− −65°C to +125°C −40°C to +125°C 300°C 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
Airflow reduces θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead SOIC (125°C/W) and 8-lead LFCSP (θJA = 70°C/W) on a JEDEC standard 4-layer board. θJA values are approximations. 3.0
Table 5. Thermal Resistance Package Type 8-Lead SOIC/2-Layer 8-Lead SOIC/4-Layer 8-Lead LFCSP/4-Layer
θJA 157 125 70
θJC 56 56 56
Unit °C/W °C/W °C/W
MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8137 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8137. Exceeding a junction temperature of 175°C for an extended period can result in changes in the silicon devices, potentially causing failure.
2.5 LFCSP
2.0
1.5
1.0 SOIC-8 0.5
0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board
ESD CAUTION
Rev. E | Page 9 of 32
04771-0-022
MAXIMUM POWER DISSIPATION (W)
θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air.
AD8137
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8
+IN
VOCM 2
7
PD
VS+ 3
6
VS–
+OUT 4
5
–OUT
04771-0-001
AD8137 –IN 1
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. 1 2
Mnemonic −IN VOCM
3 4 5 6 7 8
VS+ +OUT −OUT VS− PD +IN EPAD
Description Inverting Input. An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the operation of the amplifier remains linear. Positive Power Supply Voltage. Positive Side of the Differential Output. Negative Side of the Differential Output. Negative Power Supply Voltage. Power Down. Noninverting Input. Exposed paddle may be connected to either ground plane or power plane.
Rev. E | Page 10 of 32
Data Sheet
AD8137
TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, differential gain = 1, RG = RF = RL, dm = 1 kΩ, VS = 5 V, TA = 25°C, VOCM = 2.5V. Refer to the basic test circuit in Figure 60 for the definition of terms. 3
3
G=1
–1
G=2
G=5
–2 –3 –4 –5 G = 10
–6 –7 –8 –9 –10 –11 –12 0.1
RG = 1kΩ VO, dm = 0.1V p-p 1
10 FREQUENCY (MHz)
100
1000
3
–2 –3
G=2
G=5
–4 –5 G = 10
–6 –7 –8 –9 –10
RG = 1kΩ –11 VO, dm = 2.0V p-p –12 0.1 1
10 FREQUENCY (MHz)
100
1000
4 VS = +5
2
VS = +3
3
VS = +5
2
1 0
VS = +3
1 VS = ±5
–1
CLOSED-LOOP GAIN (dB)
–2 –3 –4 –5 –6 –7 –8 –9
0 VS = ±5
–1 –2 –3 –4 –5 –6 –7
–11 –12
VO, dm = 0.1V p-p 1
10 100 FREQUENCY (MHz)
–9 –10 –11
1000
VO, dm = 2.0V p-p 1
Figure 6. Small Signal Frequency Response for Various Power Supplies
04771-0-005
04771-0-003
–8
–10
10 100 FREQUENCY (MHz)
1000
Figure 9. Large Signal Frequency Response for Various Power Supplies
3
4
2
3
1
2
0
T = +25°C
CLOSED-LOOP GAIN (dB)
1
–1
T = +85°C
–2 –3
T = +25°C
–4
T = +125°C
–5
T = –40°C
–6 –7 –8 –9
0 –1 T = +85°C
–2 –3 –4
T = +125°C
–5 –6 –7
04771-0-006
–8
–10 –11
VO, dm = 0.1V p-p
–12 1
10 100 FREQUENCY (MHz)
–9 –10
VO, dm = 2.0V p-p
–11
1000
Figure 7. Small Signal Frequency Response at Various Temperatures
T = –40°C 04771-0-007
CLOSED-LOOP GAIN (dB)
–1
Figure 8. Large Signal Frequency Response for Various Gains
Figure 5. Small Signal Frequency Response for Various Gains
CLOSED-LOOP GAIN (dB)
G=1
1 0
04771-0-004
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1 0
04771-0-002
NORMALIZED CLOSED-LOOP GAIN (dB)
2
1
10 100 FREQUENCY (MHz)
1000
Figure 10. Large Signal Frequency Response at Various Temperatures
Rev. E | Page 11 of 32
AD8137
Data Sheet
3
3 RL, dm = 1kΩ
2
RL, dm = 500Ω
2
1
1 0 RL, dm = 2kΩ
–1
CLOSED-LOOP GAIN (dB)
–2 –3 –4 –5 –6 –7 –8 –9
–3 –4 –5 –6 –7
RL, dm = 2kΩ
–8 RL, dm = 500Ω
VO, dm = 0.1V p-p 1
10 100 FREQUENCY (MHz)
–10
RL, dm = 1kΩ
–11 –12
1000
VO, dm = 2V p-p 1
Figure 11. Small Signal Frequency Response for Various Loads
04771-0-043
04771-0-041
–11 –12
10 100 FREQUENCY (MHz)
1000
Figure 14. Large Signal Frequency Response for Various Loads
3
3
2
1 0
–2 –3
CLOSED-LOOP GAIN (dB)
CF = 1pF
–1
CF = 0pF
2
CF = 0pF
1 0
CF = 2pF
–4 –5 –6 –7 –8 –9
CF = 1pF
–1 –2 –3
CF = 2pF
–4 –5 –6 –7 –8
04771-0-008
–9
–10 –11 –12
VO, dm = 0.1V p-p 1
10 100 FREQUENCY (MHz)
04771-0-009
CLOSED-LOOP GAIN (dB)
–2
–9
–10
–10 –11 –12
1000
VO, dm = 2.0V p-p 1
Figure 12. Small Signal Frequency Response for Various CF
10 100 FREQUENCY (MHz)
1000
Figure 15. Large Signal Frequency Response for Various CF
2
3 VOCM = 4V
1
VOCM = 2.5V
2
0
1
–1
0
–2
CLOSED-LOOP GAIN (dB)
VOCM = 1V
–3 –4 –5 –6 –7 –8 –9 –10
–1 0.5V p-p
–2 –3 –4 –5 –6 –7
2V p-p
–8 –9
04771-0-042
CLOSED-LOOP GAIN (dB)
–1
–11 –12 –13
VO, dm = 0.1V p-p 1
10 100 FREQUENCY (MHz)
0.1V p-p
–10
1V p-p 04771-0-044
CLOSED-LOOP GAIN (dB)
0
–11 –12
1000
1
Figure 13. Small Signal Frequency Response at Various VOCM
10 100 FREQUENCY (MHz)
1000
Figure 16. Frequency Response for Various Output Amplitudes
Rev. E | Page 12 of 32
AD8137 4
3
3
2
2
1
1 RF = 500Ω RF = 2kΩ
–2 –3
RF = 1kΩ
–4 –5 –6 –7 –8
G=1 VS = ±5V VO, dm = 0.1V p-p
–9 –10 –11 1
RF = 500Ω
RF = 1kΩ
–6 –7 –8 G=1 VO, dm = 2V p-p 10 100 FREQUENCY (MHz)
1
1000
Figure 20. Large Signal Frequency Response for Various RF
–40 G=1 VO, dm = 2V p-p
–50
–75
VS = +3V
–80 VS = +5V
–85
G=1 VO, dm = 2V p-p
–60
DISTORTION (dBc)
VS = ±5V –90
VS = +3V
–70
VS = +5V
–80
VS = ±5V
–90
–95
–100
04771-0-045
–100 –105 0.1
1 FREQUENCY (MHz)
04771-0-063
DISTORTION (dBc)
–5
1000
10 100 FREQUENCY (MHz)
RF = 2kΩ
–4
–9
–65
–110 0.1
10
Figure 18. Second Harmonic Distortion vs. Frequency and Supply Voltage
1 FREQUENCY (MHz)
10
Figure 21. Third Harmonic Distortion vs. Frequency and Supply Voltage
–50
–50 –55
–2 –3
–10 –11
Figure 17. Small Signal Frequency Response for Various RF
–70
0 –1
04771-0-036
0 –1
CLOSED-LOOP GAIN (dB)
4
04771-0-037
CLOSED-LOOP GAIN (dB)
Data Sheet
FC = 500kHz SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
–55
VS = +3V
–60
–60
DISTORTION (dBc)
VS = +5V –70 –75
VS = +3V
–80
VS = +3V
–70 –75 –80 VS = +5V –85
–85
VS = +3V
VS = +5V
–90 04771-0-027
–90 –95 –100 0.25
–65
1.25
2.25
3.25
4.25 5.25 6.25 VO, dm (V p-p)
7.25
8.25
–100 0.25
9.25
Figure 19. Harmonic Distortion vs. Output Amplitude and Supply, FC = 500 kHz
FC = 2MHz SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
–95 1.25
2.25
3.25
4.25 5.25 6.25 VO, dm (V p-p)
7.25
8.25
04771-0-026
DISTORTION (dBc)
VS = +5V –65
9.25
Figure 22. Harmonic Distortion vs. Output Amplitude and Supply, FC = 2 MHz
Rev. E | Page 13 of 32
AD8137
Data Sheet
–40
–40 VO, dm = 2V p-p
–50
–50
–60
–60
DISTORTION (dBc)
RL, dm = 200Ω
–70
–80
RL, dm = 1kΩ RL, dm = 500Ω
–90
–80 RL, dm = 1kΩ –90
1 FREQUENCY (MHz)
RL, dm = 500Ω
–100
04771-0-032
–100 –110 0.1
RL, dm = 200Ω
–70
–110 0.1
10
Figure 23. Second Harmonic Distortion at Various Loads
04771-0-033
DISTORTION (dBc)
VO, dm = 2V p-p
1 FREQUENCY (MHz)
10
Figure 26. Third Harmonic Distortion at Various Loads
–40
–40 VO, dm = 2V p-p RG = 1kΩ
VO, dm = 2V p-p RG = 1kΩ
–50
–50
G=5 –70 G=1
–80
–60 –70
G=2 –80 G=1
–90
–90
–100
–100
–110 0.1
1 FREQUENCY (MHz)
–110 0.1
10
Figure 24. Second Harmonic Distortion at Various Gains
1 FREQUENCY (MHz)
10
Figure 27. Third Harmonic Distortion at Various Gains
–40
–40 VO, dm = 2V p-p G=1
VO, dm = 2V p-p G=1 –50
–60
–60
RF = 500Ω
–70
–80 RF = 2kΩ –90
–110 0.1
1 FREQUENCY (MHz)
–80 –90
RF = 1kΩ
–100
–70
RF = 500Ω
–100
RF = 2kΩ
–110 0.1
10
Figure 25. Second Harmonic Distortion at Various RF
RF = 1kΩ 1 FREQUENCY (MHz)
Figure 28. Third Harmonic Distortion at Various RF
Rev. E | Page 14 of 32
04771-0-031
DISTORTION (dBc)
–50
04771-0-030
DISTORTION (dBc)
G=5
04771-0-035
DISTORTION (dBc)
–60
04771-0-034
DISTORTION (dBc)
G=2
10
Data Sheet
AD8137 –50
–50 FC = 500kHz VO, dm = 2V p-p SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
–60
DISTORTION (dBc)
–70
–80
–90
–110 0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–80
–90
–100
04771-0-028
–100
–70
–110 0.5
4.5
04771-0-029
DISTORTION (dBc)
–60
FC = 500kHz VO, dm = 2V p-p SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
0.7
0.9
1.1
VOCM (V)
Figure 29. Harmonic Distortion vs. VOCM, VS = 5 V
1.5 1.7 VOCM (V)
1.9
2.1
2.3
2.5
Figure 32. Harmonic Distortion vs. VOCM, VS = 3 V 1000
1 10
04771-0-046
10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
10
1 10
100M
04771-0-047
VOCM NOISE (nV/√Hz)
100
INPUT VOLTAGE NOISE (nV/√Hz)
1.3
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100M
Figure 33. VOCM Voltage Noise vs. Frequency
Figure 30. Input Voltage Noise vs. Frequency –10
20 VIN, cm = 0.2V p-p INPUT CMRR = ∆VO, cm/∆VIN, cm
10
VO, cm = 0.2V p-p VOCM CMRR = ∆VO, dm/∆VOCM
–20
0 –30
VOCM CMRR (dB)
–20 –30 –40 –50
–40
–50 –60
–70 –80 1
10 FREQUENCY (MHz)
04771-0-012
–60 –70
04771-0-013
CMRR (dB)
–10
–80 1
100
10 FREQUENCY (MHz)
Figure 34. VOCM CMRR vs. Frequency
Figure 31. CMRR vs. Frequency
Rev. E | Page 15 of 32
100
AD8137
Data Sheet 2.0
8 INPUT × 2
1.0
AMPLITUDE (V)
4 2 0 –2
0.5 0 ERROR = VO, dm - INPUT
–0.5 TSETTLE = 110ns
–1.0
–6 250ns/DIV –8
04771-0-016
–4
–1.5 50ns/DIV
–2.0 TIME (ns)
TIME (ns)
Figure 38. Settling Time (0.02%)
Figure 35. Overdrive Recovery 1.5
100
CF = 0pF 75
2V p-p
1.0 CF = 1pF CF = 0pF
50 CF = 0pF
1V p-p
0.5
CF = 1pF
25
VO, dm (V)
VO, dm (mV)
ERROR (V) 1DIV = 0.02%
CF = 0pF VO, dm = 3.5V p-p
INPUT
OUTPUT
VOLTAGE (V)
VO, dm
1.5
6
04771-0-040
G=2
0 –25
CF = 1pF 0
–0.5
VO, dm = 100mV p-p
10ns/DIV
–100
04771-0-015
–1.0 –75
20ns/DIV –1.5
04771-0-014
–50
TIME (ns)
TIME (ns)
Figure 36. Small Signal Transient Response for Various Feedback Capacitances
Figure 39. Large Signal Transient Response for Various Feedback Capacitances
100
1.5 75
RS = 111, CL = 5pF 1.0
50 RS = 111, CL = 5pF
0.5
VO, dm (V)
0 –25
RS = 60.4, CL = 15pF
RS = 60.4, CL = 15pF 0
–0.5
–75 20ns/DIV –100
04771-0-039
–50
–1.0 20ns/DIV –1.5
04771-0-038
VO, dm (V)
25
TIME (ns)
Figure 37. Small Signal Transient Response for Various Capacitive Loads
TIME (ns)
Figure 40. Large Signal Transient Response for Various Capacitive Loads
Rev. E | Page 16 of 32
Data Sheet
AD8137 1000
–5 PSRR = ∆VO, dm/∆VS –15
100
OUTPUT IMPEDANCE (Ω)
PSRR (dB)
–25 –35 –PSRR
–45
+PSRR
–55 –65
10
1
–85 0.1
1
10 FREQUENCY (MHz)
04771-0-061
04771-0-011
0.1 –75
0.01 0.01
100
Figure 41. PSRR vs. Frequency
0.1
1 10 FREQUENCY (MHz)
100
Figure 44. Single-Ended Output Impedance vs. Frequency 4.0
1 0
3.5 2V p-p
–3
3.0
–4 –5
VO, cm (V)
–6 –7
VS = +5
VS = ±5
–8
1V p-p 2.5
2.0
–9 VS = +3
–12 –13 –14
VO, dm = 0.1V p-p 1
1.5
04771-0-010
–11
10 100 FREQUENCY (MHz)
20ns/DIV 1.0
1000
TIME (ns)
Figure 45. VOCM Large Signal Transient Response
Figure 42. VOCM Small Signal Frequency Response for Various Supply Voltages
700
350
–300
345
–305
500
VOP SWING FROM RAIL (mV)
VS+ – VOP
400 300 200 100 0
VS = +5V
VS = +3V
–100 –200 –300 VON – VS–
–400 –500 –600 –700 200
1k RESISTIVE LOAD (Ω)
VON – VS– 340
–310
335
–315 VS+ – VOP
330
–320
325
320 –40
10k
–325
–330 –20
0
20 40 60 TEMPERATURE (°C)
80
100
120
Figure 43. Output Saturation Voltage vs. Output Load Figure 46. Output Saturation Voltage vs. Temperature
Rev. E | Page 17 of 32
VON SWING FROM RAIL (mV)
600
04771-0-049
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
04771-0-050
–10
04771-0-065
CLOSED-LOOP GAIN (dB)
–1 –2
AD8137
Data Sheet
10
2.55
VOS, dm
0
0
–0.1
5
–0.2
10
–0.3 –40
VOS, cm (mV)
5
VOS, dm (mV)
0.1
–15 –20
0
20 40 60 TEMPERATURE (°C)
80
100
2.50
2.45
2.40
2.35
2.30 –40
120
–20
0
20 40 60 TEMPERATURE (°C)
80
100
120
Figure 50. Supply Current vs. Temperature
1.2
70
1.0
50
0.8
30
(µA)
0.6
IV
OCM
0.4
10
–10
0.2
–0.2 –0.4 0.50
1.50
2.50 VACM (V)
3.50
–50 –70
4.50
0
Figure 48. Input Bias Current vs. Input Common-Mode Voltage, VACM
0.40
0.5
1.0
1.5
2.0
2.5 3.0 VOCM (V)
3.5
4.0
4.5
5.0
Figure 51. VOCM Bias Current vs. VOCM Input Voltage
3
0.35
04771-0-056
–30
0 04771-0-059
INPUT BIAS CURRENT (µA)
Figure 47. Offset Voltage vs. Temperature
04771-0-051
VOS, cm
2.60
04771-0-052
0.2
15
SUPPLY CURRENT (mA)
0.3
–0.1
2
IBIAS
0 IOS
0.20
–1
0.15
–2
IOS (nA)
0.25
–0.3
0.10 –40
–3 –20
0
20 40 60 TEMPERATURE (°C)
80
100
120
Figure 49. Input Bias and Offset Current vs. Temperature
–0.5 –40
04771-0-054
–0.4 04771-0-053
IBIAS (µA)
1
VOCM CURRENT (µA)
–0.2 0.30
–20
0
20 40 60 TEMPERATURE (°C)
80
100
Figure 52. VOCM Bias Current vs. Temperature
Rev. E | Page 18 of 32
120
Data Sheet
AD8137 1.5
VS = +5V
VS = ±2.5V G = 1 (RF = RG = 1kΩ) RL, dm = 1kΩ INPUT = 1Vp-p @ 1MHz
4 1.0
SUPPLY CURRENT (mA)
3 2 VS = +3V
VO, cm
1 0 –1 VS = ±5V
–2 –3
–5 –5
–4
–3
–2
–1
0 VOCM
1
2
3
4
0
–0.5
–1.0
04771-0-060
–4
VO, dm 0.5
–0.5V PD
2µs/DIV
–2.0V
–1.5
04771-0-066
5
5 TIME (µs)
Figure 53. VO, cm vs. VOCM Input Voltage
Figure 56. Power-Down Transient Response
40
3.6
20
3.2 PD (0.8V TO 1.5V) 2.8
SUPPLY CURRENT (mA)
–20 –40 –60 –80
2.4 2.0 1.6 1.2
04771-0-057
0.8
–100 –120 0
0.5
1.0
1.5
2.0 2.5 3.0 PD VOLTAGE (V)
3.5
4.0
4.5
0.4 100ns/DIV 0
04771-0-024
PD CURRENT (µA)
0
5.0 TIME (ns)
Figure 57. Power-Down Turn-On Time
Figure 54. PD Current vs. PD Voltage 3.4
3
PD (1.5V TO 0.8V) IS+
3.0
0
–1
–2
IS–
–3 0
0.5
1.0
1.5
2.0 2.5 3.0 PD VOLTAGE (V)
3.5
4.0
4.5
2.6 2.2 1.8 1.4 1.0 0.6 40ns/DIV
0.2
5.0
TIME (ns)
Figure 58. Power-Down Turn-Off Time
Figure 55. Supply Current vs. PD Voltage
Rev. E | Page 19 of 32
04771-0-025
SUPPLY CURRENT (mA)
1
04771-0-058
SUPPLY CURRENT (mA)
2
AD8137
Data Sheet
25 VS = ±5V VOCM = 0V G = +1
15
10
5
0 –5
–4
–3
–2
–1
0
1
2
3
4
POWER-DOWN VOLTAGE (V)
5
04771-071
SUPPLY CURRENT (mA)
20
Figure 59. Supply Current vs. Power-Down Voltage
Rev. E | Page 20 of 32
Data Sheet
AD8137
TEST CIRCUITS RF 50Ω
MIDSUPPLY
AD8137
VOCM
52.3Ω TEST SIGNAL SOURCE
–
+ RL, dm 1kΩ
–
50Ω
RG = 1kΩ
VO, dm +
CF
04771-0-023
VTEST
CF
RG = 1kΩ
52.3Ω
RF
Figure 60. Basic Test Circuit
RF = 1kΩ
52.3Ω VTEST
RG = 1kΩ
MIDSUPPLY
VOCM
52.3Ω TEST SIGNAL SOURCE
50Ω
RS
–
+
AD8137
CL, dm
–
+ RS
RG = 1kΩ RF = 1kΩ
Figure 61. Capacitive Load Test Circuit, G = 1
Rev. E | Page 21 of 32
RL, dm VO, dm 04771-0-062
50Ω
AD8137
Data Sheet
THEORY OF OPERATION 100
The AD8137 is a low power, low cost, fully differential voltage feedback amplifier that features a rail-to-rail output stage, common-mode circuitry with an internally derived commonmode reference voltage, and bias shutdown circuitry. The amplifier uses two feedback loops to separately control differential and common-mode feedback. The differential gain is set with external resistors as in a traditional amplifier, and the output commonmode voltage is set by an internal feedback loop, controlled by an external VOCM input. This architecture makes it easy to set arbitrarily the output common-mode voltage level without affecting the differential gain of the amplifier.
80 60 40 20 –20 –40 –60 –80 –100
–160
–IN CN
+OUT
04771-0-017
CC
Figure 62. Block Diagram
From Figure 62, the input transconductance stage is an H-bridge whose output current is mirrored to high impedance nodes CP and CN. The output section is traditional H-bridge driven circuitry with common emitter devices driving nodes +OUT and −OUT. The 3 dB point of the amplifier is defined as
BW =
0.001
0.01 0.1 1 FREQUENCY (MHz)
10
100
Figure 63. Open-Loop Gain and Phase
ACM
CC
04771-0-021
–140
VOCM
CP +IN
PHASE (DEGREES)
–120
–180 –200 0.0001
–OUT
OPEN-LOOP GAIN (dB)
0
gm 2π × C C
where: gm is the transconductance of the input stage. CC is the total capacitance on node CP/CN (capacitances CP and CN are well matched). For the AD8137, the input stage gm is ~1 mA/V and the capacitance CC is 3.5 pF, setting the crossover frequency of the amplifier at 41 MHz. This frequency generally establishes an amplifier’s unity gain bandwidth, but with the AD8137, the closed-loop bandwidth depends upon the feedback resistor value as well (see Figure 17). The open-loop gain and phase simulations are shown in Figure 63.
In Figure 62, the common-mode feedback amplifier ACM samples the output common-mode voltage, and by negative feedback forces the output common-mode voltage to be equal to the voltage applied to the VOCM input. In other words, the feedback loop servos the output common-mode voltage to the voltage applied to the VOCM input. An internal bias generator sets the VOCM level to approximately midsupply; therefore, the output common-mode voltage is set to approximately midsupply when the VOCM input is left floating. The source resistance of the internal bias generator is large and can be overridden easily by an external voltage supplied by a source with a relatively small output resistance. The VOCM input can be driven to within approximately 1 V of the supply rails while maintaining linear operation in the common-mode feedback loop. The common-mode feedback loop inside the AD8137 produces outputs that are highly balanced over a wide frequency range without the requirement of tightly matched external components, because it forces the signal component of the output commonmode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180° apart in phase.
Rev. E | Page 22 of 32
Data Sheet
AD8137
APPLICATIONS INFORMATION Output balance is measured by placing a well-matched resistor divider across the differential voltage outputs and comparing the signal at the divider’s midpoint with the magnitude of the differential output. By this definition, output balance is equal to the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential mode voltage:
ANALYZING A TYPICAL APPLICATION WITH MATCHED RF AND RG NETWORKS Typical Connection and Definition of Terms Figure 64 shows a typical connection for the AD8137, using matched external RF/RG networks. The differential input terminals of the AD8137, VAP and VAN, are used as summing junctions. An external reference voltage applied to the VOCM terminal sets the output common-mode voltage. The two output terminals, VOP and VON, move in opposite directions in a balanced fashion in response to an input signal.
Output Balance =
VAN = VAP
RF VIP
VAP
VOCM VIN
VON
+
AD8137 RG
VAN
(4)
The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two internal common-mode tap resistors in Figure 62, to equal the voltage set at the VOCM terminal. This ensures that
– RL, dm VO, dm
VOP
–
+
CF
04771-0-055
RF
VOP = VOCM +
VON = VOCM −
The differential output voltage is defined as VO, dm = VOP − VON
(1)
Common-mode voltage is the average of two voltages. The output common-mode voltage is defined as
VO , cm
VO , dm
(5)
2
and
Figure 64. Typical Connection
VOP + VON = 2
(3)
∆VO , dm
The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other.
CF
RG
∆VO , cm
VO , dm
(6)
2
ESTIMATING NOISE, GAIN, AND BANDWITH WITH MATCHED FEEDBACK NETWORKS Estimating Output Noise Voltage and Bandwidth
(2)
Output Balance Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 180° out of phase with each other. It is the internal common-mode feedback loop that forces the signal component of the output commonmode toward zero, resulting in the near perfectly balanced differential outputs of identical amplitude and are exactly 180° out of phase. The output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. Low frequency output balance is ultimately limited by the mismatch of an on-chip voltage divider.
The total output noise is the root-sum-squared total of several statistically independent sources. Because the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 7 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed-loop gains. For most applications, 1% resistors are sufficient. Table 7. Recommended Values of Gain-Setting Resistors and Voltage Gain for Various Closed-Loop Gains Gain 1 2 5 10
Rev. E | Page 23 of 32
RG (Ω) 1k 1k 1k 1k
RF (Ω) 1k 2k 5k 10 k
3 dB Bandwidth (MHz) 72 40 12 6
Total Output Noise (nV/√Hz) 18.6 28.9 60.1 112.0
AD8137
Data Sheet
The differential output voltage noise contains contributions from the AD8137’s input voltage noise and input current noise as well as those from the external feedback networks.
Feedback Factor Notation When working with differential drivers, it is convenient to introduce the feedback factor β, which is defined as
The contribution from the input voltage noise spectral density is computed as
R Vo_n 1 = vn 1 + F , or equivalently, vn/β RG
(7)
where vn is defined as the input-referred differential voltage noise. This equation is the same as that of traditional op amps. The contribution from the input current noise of each input is computed as Vo_n 2 = in (RF )
(8)
where in is defined as the input noise current of one input. Each input needs to be treated separately because the two input currents are statistically independent processes.
β≡
(14)
This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched.
Input Common-Mode Voltage The linear range of the VAN and VAP terminals extends to within approximately 1 V of either supply rail. Because VAN and VAP are essentially equal to each other, they are both equal to the amplifier’s input common-mode voltage. Their range is indicated in the specifications tables as input common-mode range. The voltage at VAN and VAP for the connection diagram in Figure 64 can be expressed as VAN = VAP = VACM = RF (V IP + V IN ) RG R +R × + R + R × VOCM 2 G G F F
The contribution from each RG is computed as
R Vo_n 3 = 4 kTRG F RG
RG RF + RG
(9)
(15)
This result can be intuitively viewed as the thermal noise of each RG multiplied by the magnitude of the differential gain.
where VACM is the common-mode voltage present at the amplifier input terminals.
The contribution from each RF is computed as
Using the β notation, Equation (15) can be written as
Vo_n 4 = 4 kTRF
(16)
or equivalently,
Voltage Gain
VACM = VICM + β(VOCM − VICM)
The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the signal definitions and Figure 64. Referring to Figure 64, CF = 0 and setting VIN = 0, one can write:
(17)
where VICM is the common-mode voltage of the input signal, that is
VICM ≡
VIP − VAP VAP − VON = RG RF
(11)
RG VAN = VAP = VOP RF + RG
(12)
Solving the previous two equations and setting VIP to Vi gives the gain relationship for VO, dm/Vi. R VOP − VON = VO, dm = F Vi RG
VACM = βVOCM + (1 − β)VICM
(10)
(13)
VIP + VIN 2
For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges.
Calculating Input Impedance The input impedance of the circuit in Figure 64 depends on whether the amplifier is being driven by a single-ended or a differential signal source. For balanced differential input signals, the differential input impedance (RIN, dm) is simply RIN, dm = 2RG
An inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to VIN and setting VIP = 0. For a balanced differential input, the gain from VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP − VIN.
(18)
For a single-ended signal (for example, when VIN is grounded and the input signal drives VIP), the input impedance becomes
Rev. E | Page 24 of 32
R IN =
RG RF 1− 2(RG + R F )
(19)
Data Sheet
AD8137 5V
0.1µF
0.1µF 1kΩ
1kΩ VOCM
3 8 2 1
VIN
1.0nF
5
+
VDD VIN–
AD8137 –
AD7450A
4 6
VREFB
2.5V
1kΩ
1kΩ
50Ω
VIN+ GND
1.0nF
2.5kΩ
+1.88V +1.25V +0.63V
VACM WITH VREFB = 0
VREF
ADR525A 2.5V SHUNT VREFA REFERENCE
04771-0-018
+2.5V GND –2.5V
50Ω
Figure 65. AD8137 Driving AD7450A, 12-Bit ADC 5V
The input impedance of a conventional inverting op amp configuration is simply RG; however, it is higher in Equation 19 because a fraction of the differential output voltage appears at the summing junctions, VAN and VAP. This voltage partially bootstraps the voltage across the input resistor RG, leading to the increased input resistance.
0.1µF
VIN 0V TO 5V
1kΩ 3
1kΩ
8
VOCM
2 1
Input Common-Mode Swing Considerations
5
+
AD8137 –
4 6
1kΩ 0.1µF
One way to avoid the input common-mode swing limitation is to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p swinging about a baseline at 2.5 V, and VREF is connected to a low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and is swinging about 2.5 V. Using the results in Equation 17, VACM is calculated to be equal to VICM because VOCM = VICM. Therefore, VICM swings from 1.25 V to 3.75 V, which is well within the input common-mode voltage limits of the AD8137. Another benefit seen by this example is that because VOCM = VACM = VICM, no wasted common-mode current flows. Figure 66 illustrates a way to provide the low-Z bias voltage. For situations that do not require a precise reference, a simple voltage divider suffices to develop the input voltage to the buffer.
TO AD7450A VREF
0.1µF
Consider the case in Figure 65, where VIN is 5 V p-p swinging about a baseline at ground and VREFB is connected to ground. The input signal to the AD8137 is originating from a source with a very low output resistance. The circuit has a differential gain of 1.0 and β = 0.5. VICM has an amplitude of 2.5 V p-p and is swinging about ground. Using the results in Equation 16, the common-mode voltage at the inputs of the AD8137, VACM, is a 1.25 V p-p signal swinging about a baseline of 1.25 V. The maximum negative excursion of VACM in this case is 0.63 V, which exceeds the lower input common-mode voltage limit.
1kΩ 5V
10µF
+
+
AD8031
0.1µF
–
10kΩ
ADR525A 2.5V SHUNT REFERENCE
04771-0-019
In some single-ended-to-differential applications, when using a single-supply voltage, attention must be paid to the swing of the input common-mode voltage, VACM.
Figure 66. Low-Z Bias Source
Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8137. In this case, the biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain The 3 dB bandwidth of the AD8137 decreases proportionally to increasing closed-loop gain in the same way as a traditional voltage feedback operational amplifier. For closed-loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as
f −3dB , VO, dm =
RG × (72 MHz) RG + R F
(20)
or equivalently, β(72 MHz). This estimate assumes a minimum 90° phase margin for the amplifier loop, a condition approached for gains greater than 4. Lower gains show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin.
Rev. E | Page 25 of 32
AD8137
Data Sheet
Estimating DC Errors
Driving a Capacitive Load
Primary differential output offset errors in the AD8137 are due to three major components: the input offset voltage, the offset between the VAN and VAP input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the input and output commonmode voltages in conjunction with matching errors in the feedback network.
A purely capacitive load reacts with the bondwire and pin inductance of the AD8137, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance. The resistor and load capacitance forms a first-order, low-pass filter; therefore, the resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs.
The first output error component is calculated as
R + RG Vo_e1 = VIO F , or equivalently as VIO/β RG
(21)
Figure 37 and Figure 40 illustrate transient response vs. capacitive load and were generated using series resistors in each output and a differential capacitive load.
where VIO is the input offset voltage.
Layout Considerations
The second error is calculated as (22)
Standard high speed PCB layout practices should be adhered to when designing with the AD8137. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins.
(23)
To minimize stray capacitance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. Small amounts of stray summing-node capacitance cause peaking in the frequency response, and large amounts can cause instability. If some stray summing-node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors.
R + RG RG RF Vo_e 2 = I IO F = I IO (RF ) RG RF + RG where IIO is defined as the offset between the two input bias currents. The third error voltage is calculated as Vo_e3 = Δenr × (VICM − VOCM)
where Δenr is the fractional mismatch between the two feedback resistors. The total differential offset error is the sum of these three error sources.
Additional Impact of Mismatches in the Feedback Networks The internal common-mode feedback network still forces the output voltages to remain balanced, even when the RF/RG feedback networks are mismatched. The mismatch, however, causes a gain error proportional to the feedback network mismatch. Ratio-matching errors in the external resistors degrade the ability to reject common-mode signals at the VAN and VIN input terminals, similar to a four resistor, difference amplifier made from a conventional op amp. Ratio-matching errors also produce a differential output component that is equal to the VOCM input voltage times the difference between the feedback factors (βs). In most applications using 1% resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored.
Terminating a Single-Ended Input Controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD8137. The input resistance presented by the AD8137 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into account. The Thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. An exact solution to the problem requires solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. An iterative solution is also possible and is easier, especially considering the fact that standard resistor values are generally used.
Rev. E | Page 26 of 32
Data Sheet
AD8137
Figure 67 shows the AD8137 in a unity-gain configuration, and with the following discussion, provides a good example of how to provide a proper termination in a 50 Ω environment. +5V
Power-Down The AD8137 features a PD pin that can be used to minimize the quiescent current consumed when the device is not being used. PD is asserted by applying a low logic level to Pin 7. The threshold between high and low logic levels is nominally 1.1 V above the negative supply rail. See Table 1 to Table 3 for the threshold limits.
0.1µF
50Ω VIN
SIGNAL SOURCE
2V p-p RT 52.3Ω
3
1kΩ 0V
The AD8137 PD pin features an internal pull-up network that enables the amplifier for normal operation. The AD8137 PD pin can be left floating (that is, no external connection is required) and does not require an external pull-up resistor to ensure normal on operation (see Figure 68).
–
8
VOCM
2 1
1.02kΩ
5
+
AD8137 –
4 6
Do not connect the PD pin directly to VS+ in ±5 V applications. This can cause the amplifier to draw excessive supply current (see Figure 59) and may induce oscillations and/or stability issues.
0.1µF –5V
04771-0-020
+ 1kΩ
Figure 67. AD8137 with Terminated Input
+VS
The 52.3 Ω termination resistor, RT, in parallel with the 1 kΩ input resistance of the AD8137 circuit, yields an overall input resistance of 50 Ω that is seen by the signal source. To have matched feedback loops, each loop must have the same RG if it has the same RF. In the input (upper) loop, RG is equal to the 1 kΩ resistor in series with the (+) input plus the parallel combination of RT and the source resistance of 50 Ω. In the upper loop, RG is therefore equal to 1.03 kΩ. The closest standard value is 1.02 kΩ and is used for RG in the lower loop. Things become more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source generator VIN is two times the amplitude of its output signal when terminated in 50 Ω. Therefore, a 2 V p-p terminated amplitude is produced by a 4 V p-p amplitude from VS. The Thevenin equivalent circuit of the signal source and RT must be used when calculating the closed-loop gain because RG in the upper loop is split between the 1 kΩ resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output voltage when terminated in 50 Ω because RT must always be greater than 50 Ω. In this case, RT is 52.3 Ω and the Thevenin voltage and resistance are 2.04 V p-p and 25.6 Ω, respectively. Now the upper input branch can be viewed as a 2.04 V p-p source in series with 1.03 kΩ. Because this is to be a unity-gain application, a 2 V p-p differential output is required, and RF must therefore be 1.03 kΩ × (2/2.04) = 1.01 kΩ ≈ 1 kΩ. This example shows that when RF and RG are large compared to RT, the gain reduction produced by the increase in RG is essentially cancelled by the increase in the Thevenin voltage caused by RT being greater than the output resistance of the signal source. In general, as RF and RG become smaller in terminated applications, RF needs to be increased to compensate for the increase in RG.
+VS 50kΩ 5kΩ
PD
Q1
Q2 REF A
150kΩ 04771-072
1kΩ
–VS
Figure 68. PD Pin Circuit
DRIVING AN ADC WITH GREATER THAN 12-BIT PERFORMANCE Because the AD8137 is suitable for 12-bit systems, it is desirable to measure the performance of the amplifier in a system with greater than 12-bit linearity. In particular, the effective number of bits (ENOB) is most interesting. The AD7687, 16-bit, 250 KSPS ADC performance makes it an ideal candidate for showcasing the 12-bit performance of the AD8137. For this application, the AD8137 is set in a gain of 2 and driven single-ended through a 20 kHz band-pass filter, while the output is taken differentially to the input of the AD7687 (see Figure 69). This circuit has mismatched RG impedances and, therefore, has a dc offset at the differential output. It is included as a test circuit to illustrate the performance of the AD8137. Actual application circuits should have matched feedback networks. For an AD7687 input range up to −1.82 dBFS, the AD8137 power supply is a single 5 V applied to VS+ with VS− tied to ground. To increase the AD7687 input range to −0.45 dBFS, the AD8137 supplies are increased to +6 V and −1 V. In both cases, the VOCM pin is biased with 2.5 V and the PD pin is left floating. All voltage supplies are decoupled with 0.1 µF capacitors. Figure 70 and Figure 71 show the performance of the −1.82 dBFS setup and the −0.45 dBFS setup, respectively.
When generating the typical performance characteristics data, the measurements were calibrated to take the effects of the terminations on closed-loop gain into account. Rev. E | Page 27 of 32
AD8137
Data Sheet VS+ 1.0kΩ
20kHz
V+
GND 33Ω
499Ω VIN
+ BPF
VOCM
VDD
1nF
AD8137
AD7687 GND
– 1nF
04771-0-067
33Ω
499Ω 1.0kΩ
+2.5 VS –
0 –10
AMPLITUDE (dB OF FULL SCALE)
THD = –93.63dBc SNR = 91.10dB SINAD = 89.74dB ENOB = 14.6
0
20
40
60 80 FREQUENCY (kHz)
100
120
THD = –91.75dBc SNR = 91.35dB SINAD = 88.75dB ENOB = 14.4
–20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160
04771-0-069
0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170
04771-0-068
AMPLITUDE (dB OF FULL SCALE)
Figure 69. AD8137 Driving AD7687, 16-Bit 250 KSPS ADC
0
140
20
40
60 80 FREQUENCY (kHz)
100
120
140
Figure 71. AD8137 Performance on +6 V, −1 V Supplies, −0.45 dBFS
Figure 70. AD8137 Performance on Single 5 V Supply, −1.82 dBFS
Rev. E | Page 28 of 32
Data Sheet
AD8137
OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890)
8
4.00 (0.1574) 3.80 (0.1497)
1
5
6.20 (0.2441) 5.80 (0.2284)
4
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.51 (0.0201) 0.31 (0.0122)
0.50 (0.0196) 0.25 (0.0099)
45°
8° 0° 0.25 (0.0098) 0.17 (0.0067)
1.27 (0.0500) 0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 72. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
1.84 1.74 1.64
3.10 3.00 SQ 2.90
1.55 1.45 1.35
EXPOSED PAD
0.50 0.40 0.30
0.80 0.75 0.70 0.30 0.25 0.20
1
4 BOTTOM VIEW
TOP VIEW
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF
PIN 1 INDICATOR (R 0.15)
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 73. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-13) Dimensions shown in millimeters
Rev. E | Page 29 of 32
12-07-2010-A
PIN 1 INDEX AREA
SEATING PLANE
0.50 BSC 8
5
AD8137
Data Sheet
ORDERING GUIDE Model 1, 2 AD8137YR AD8137YR-REEL7 AD8137YRZ AD8137YRZ-REEL AD8137YRZ-REEL7 AD8137YCPZ-R2 AD8137YCPZ-REEL AD8137YCPZ-REEL7 AD8137WYCPZ-R7 AD8137YCP-EBZ AD8137YR-EBZ 1 2
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C
Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) 8-Lead Lead Frame Chip Scale Package (LFCSP_WD) LFCSP Evaluation Board SOIC Evaluation Board
Package Option R-8 R-8 R-8 R-8 R-8 CP-8-13 CP-8-13 CP-8-13 CP-8-13
Branding
HFB# HFB# HFB# H2G
Z = RoHS Compliant Part; # denotes that RoHS part may be top or bottom marked. W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS The AD8137W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. E | Page 30 of 32
Data Sheet
AD8137
NOTES
Rev. E | Page 31 of 32
AD8137
Data Sheet
NOTES
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04771-0-7/12(E)
Rev. E | Page 32 of 32
