Transcript
FEATURES Dual independent, digitally controlled VGAs −11.5 dB to +20 dB gain range 0.5 dB ± 0.1 dB step size 150 Ω differential input and output 7.5 dB noise figure at maximum gain OIP3 > 50 dBm at 200 MHz −3 dB upper frequency bandwidth of 700 MHz Multiple control interface options Parallel 6-bit control interface (with latch) Serial peripheral interface (SPI) (with fast attack) Gain up/down mode Wide input dynamic range Low power mode option Power-down control Single 5 V supply operation 40-lead, 6 mm × 6 mm LFCSP package
APPLICATIONS Differential ADC drivers High IF sampling receivers High output power IF amplification Instrumentation
FUNCTIONAL BLOCK DIAGRAM SIDE A SPI WITH FA, PARALLEL WITH LATCH, UP/DN PWUPA
VPOS
LOGIC
VINA+ 150Ω
0dB TO 31.5dB
VOUTA+ +20dB
150Ω VOUTA–
VINA– MODE0, MODE1
CONTROL CIRCUITRY
PM VINB+ 150Ω
0dB TO 31.5dB
VOUTB+ +20dB
150Ω VOUTB–
VINB– LOGIC
ADL5202 PWUPB
SIDE B SPI WITH FA, PARALLEL WITH LATCH, UP/DN
GND
09387-001
Data Sheet
Wide Dynamic Range, High Speed, Digitally Controlled VGA ADL5202
Figure 1.
GENERAL DESCRIPTION The ADL5202 is a digitally controlled, variable gain, wide bandwidth amplifier that provides precise gain control, high output IP3, and low noise figure. The excellent distortion performance and high signal bandwidth make the ADL5202 an excellent gain control device for a variety of receiver applications. The ADL5202 also incorporates a low power mode option that lowers the supply current.
The ADL5202 is powered on by applying the appropriate logic level to the PWUPx pins. The quiescent current of the ADL5202 is typically 160 mA in low power mode. When configured in high performance mode for more demanding applications, the quiescent current is 210 mA. When powered down, the ADL5202 consumes less than 14 mA and offers excellent input-to-output isolation. The gain setting is preserved during power-down.
For wide input dynamic range applications, the ADL5202 provides a broad 31.5 dB gain range with 0.5 dB resolution. The gain is adjustable through multiple gain control interface options: parallel, serial peripheral interface, and up/down.
Fabricated on an Analog Devices, Inc., high speed SiGe process, the ADL5202 provides precise gain adjustment capabilities with good distortion performance and low phase error. The ADL5202 amplifier comes in a compact, thermally enhanced 40-lead, 6 mm × 6 mm LFCSP package and operates over a temperature range of −40°C to +85°C.
Incorporating proprietary distortion cancellation techniques, the ADL5202 achieves a better than 50 dBm output IP3 at frequencies approaching 200 MHz for most gain settings.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
ADL5202
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Up/Down Interface........................................................... 16
Applications....................................................................................... 1
Truth Table .................................................................................. 17
Functional Block Diagram .............................................................. 1
Logic Timing............................................................................... 17
General Description ......................................................................... 1
Circuit Description......................................................................... 18
Revision History ............................................................................... 2
Basic Structure ............................................................................ 18
Specifications..................................................................................... 3
Applications Information .............................................................. 19
Absolute Maximum Ratings............................................................ 5
Basic Connections...................................................................... 19
ESD Caution.................................................................................. 5
ADC Driving............................................................................... 19
Pin Configuration and Functional Descriptions.......................... 6
Layout Considerations............................................................... 21
Typical Performance Characteristics ............................................. 8
Evaluation Board ............................................................................ 22
Characterization and Test Circuits............................................... 15
Evaluation Board Control Software......................................... 22
Theory of Operation ...................................................................... 16
Evaluation Board Schematics and Artwork............................ 23
Digital Interface Overview ........................................................ 16
Evaluation Board Configuration Options............................... 27
Parallel Digital Interface ............................................................ 16
Outline Dimensions ....................................................................... 29
Serial Peripheral Interface (SPI) ............................................... 16
Ordering Guide .......................................................................... 29
REVISION HISTORY 10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
Data Sheet
ADL5202
SPECIFICATIONS VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Slew Rate Input Return Loss (S11) Output Return Loss (S22) INPUT STAGE Maximum Input Swing (Differential) Differential Input Resistance Common-Mode Input Voltage CMRR GAIN Maximum Voltage Gain Minimum Voltage Gain Gain Step Size Gain Flatness Gain Temperature Sensitivity Gain Step Response Gain Conformance Error Phase Conformance Error OUTPUT STAGE Output Voltage Swing Differential Output Resistance NOISE/HARMONIC PERFORMANCE 46 MHz Second Harmonic Third Harmonic Output IP3 70 MHz Second Harmonic Third Harmonic Output IP3 140 MHz Noise Figure Second Harmonic Third Harmonic Output IP3 Output 1 dB Compression Point 300 MHz Second Harmonic Third Harmonic Output IP3
Test Conditions/Comments VOUT < 2 V p-p (5.2 dBm) 100 MHz 100 MHz
Min
Typ
Max
Unit
700 5.5 −17.7 −16.5
MHz V/ns dB dB
10.8 150 1.5 40
V p-p Ω V dB
20 −11.5 0.5 0.285 0.012 15 ±0.03 1.0
dB dB dB dB dB/°C ns dB Degrees
10 150
V p-p Ω
−92 −105 50
dBc dBc dBm
−96 −105 50
dBc dBc dBm
7.5 −86 −105 50 19.5
dB dBc dBc dBm dBm
−77 −91 47
dBc dBc dBm
VINA+, VINB+ and VINA−, VINB− pins Gain code = 111111
Gain code = 000000 Gain code = 000000 Gain code = 111111 30 MHz < fC < 200 MHz Gain code = 000000 For VIN = 0.2 V, gain code = 111111 to 000000 Over 10 dB gain range Over 10 dB gain range
VOUTx+ and VOUTx− pins At P1dB, gain code = 000000 Differential Gain code = 000000, high performance mode VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite Gain code = 000000, high performance mode VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite Gain code = 000000, high performance mode VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite Gain code = 000000, high performance mode VOUT = 2 V p-p VOUT = 2 V p-p VOUT = 2 V p-p composite
Rev. 0 | Page 3 of 32
ADL5202
Data Sheet
Parameter POWER-UP INTERFACE Power-Up Threshold
Test Conditions/Comments PWUPA, PWUPB pins Minimum voltage to enable the device Maximum voltage to enable the device
PWUPx Input Bias Current GAIN CONTROL INTERFACE VIH VIL Maximum Input Bias Current SPI TIMING fSCLK tDH tDS tPW POWER INTERFACE Supply Voltage Quiescent Current, Both Channels
Min
Typ
Max
Unit
3.3
V V µA
1.4 1
Minimum/Maximum voltage for a logic high Maximum voltage for a logic low
1.4
3.3 0.8
LATCHA and LATCHB, SCLK, SDIO, data pins 1/tSCLK Data hold time Data setup time SCLK high pulse width
1
µA
20 5 5 5
MHz ns ns ns
4.5
5.5
High performance mode TA = 85°C Low power mode TA = 85°C PWUPx low
Power-Down Current, Both Channels
V
210 250 160 180 14
V mA mA mA mA mA
Timing Diagrams tPW
tSCLK SCLK
tDH tDS ___ ___ CSA, CSB
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
D4
D3
Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS
tDS
tPW
UPDN_DAT UPDN_CLK
UP
DN
tDS
RESET
tDH
Figure 3. Up/Down Mode Timing Diagram
LATCHA, LATCHB A5 TO A0 B5 TO B0
tDH
Figure 4. Parallel Mode Timing Diagram
Rev. 0 | Page 4 of 32
09387-104
DNC
09387-103
SDIO
D2
D1
D0
09387-002
tDS tDH
Data Sheet
ADL5202
ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS PWUPA, PWUPB, A0 to A5, B0 to B5, MODE0, MODE1, PM, LATCHA, LATCHB Input Voltage, VIN+ ,VIN− Internal Power Dissipation θJA (Exposed Paddle Soldered Down) θJC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec)
Rating 5.5 3.6 V +3.6 V to −1.2 V 1.6 W 34.6°C/W 3.6°C/W 140°C −40°C to +85°C −65°C to +150°C 240°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 32
ADL5202
Data Sheet
40 39 38 37 36 35 34 33 32 31
FA_A/A2 UPDN_CLK_A/A1 UPDN_DAT_A/A0 LATCHA VINA– VINA+ PWUPA GND VOUTA– VOUTA+
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1 INDICATOR
ADL5202 TOP VIEW (Not to Scale) EXPOSED PADDLE
30 29 28 27 26 25 24 23 22 21
VOUTA– VOUTA+ VPOS VPOS VPOS VPOS VPOS VPOS VOUTB+ VOUTB–
NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO A LOW IMPEDANCE GROUND PAD.
09387-003
GS0/FA_B/B2 UPDN_CLK_B/B1 UPDN_DAT_B/B0 LATCHB VINB– VINB+ PWUPB GND VOUTB– VOUTB+
11 12 13 14 15 16 17 18 19 20
CSA/A3 1 A4 2 A5 3 MODE1 4 MODE0 5 PM 6 GND 7 SIDO/B5 8 SCLK/B4 9 GS1/CSB/B3 10
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions Pin No. 1
Mnemonic CSA/A3
2 3 4 5 6
A4 A5 MODE1 MODE0 PM
7, 18, 33, EP 8
GND SDIO/B5
9
SCLK/B4
10
GS1/CSB/B3
11
GS0/FA_B/B2
12
UPDN_CLK_B/B1
13
UPDN_DAT_B/B0
14
LATCHB
Description Channel A Select (CSA). When serial mode is enabled, a logic low (0 V ≤ CSA ≤ 0.8 V) selects Channel A. Bit 3 for Channel A Parallel Gain Control Interface (A3). Bit 4 for Channel A Parallel Gain Control Interface. Bit 5 (MSB) for Channel A Parallel Gain Control Interface. MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode. LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode. Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (1.4 V ≤ PM ≤ 3.3 V) enables low power mode. Ground. The exposed paddle (EP) must be connected to a low impedance ground pad. Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing to the SPI port. Bit 5 for Channel B Parallel Gain Control Interface (B5). Serial Clock Input in SPI Mode (SCLK). Bit 4 for Channel B Parallel Gain Control Interface (B4). MSB for Gain Step Size Control in Up/Down Mode (GS1). Channel B Select (CSB). When serial mode is enabled, a logic low (0 V ≤ CSB≤ 0.8 V) selects Channel B. Bit 3 for Channel B Parallel Gain Control Interface (B3). LSB for Gain Step Size Control in Up/Down Mode (GS0). Fast Attack (FA_B). In serial mode, a logic high (1.4 V ≤ FA_B ≤ 3.3 V) attenuates Channel B according to the FA setting in the SPI word. Bit 2 for Channel B Parallel Gain Control Interface (B2). Clock Interface for Channel B Up/Down Function (UPDN_CLK_B). Bit 1 for Channel B Parallel Gain Control Interface (B1). Data Pin for Channel B Up/Down Function (UPDN_DAT_B). Bit 0 for Channel B Parallel Gain Control Interface (B0). Channel B Latch. A logic low (0 V ≤ LATCHB ≤ 0.8 V) allows gain changes on Channel B. A logic high (1.4 V ≤ LATCHB ≤ 3.3 V) prevents gain changes on Channel B.
Rev. 0 | Page 6 of 32
Data Sheet
ADL5202
Pin No. 15 16 17 19, 21 20, 22 23, 24, 25, 26, 27, 28 29, 31 30, 32 34 35 36 37
Mnemonic VINB− VINB+ PWUPB VOUTB− VOUTB+ VPOS
Description Channel B Negative Input. Channel B Positive Input. Channel B Power-Up. A logic high (1.4 V ≤ PWUPB ≤ 3.3 V) enables Channel B. Channel B Negative Output. Channel B Positive Output. Positive Power Supply.
VOUTA+ VOUTA− PWUPA VINA+ VINA− LATCHA
38
UPDN_DAT_A/A0
39
UPDN_CLK_A/A1
40
FA_A/A2
Channel A Positive Output. Channel A Negative Output. Channel A Power-Up. A logic high (1.4 V ≤ PWUPA ≤ 3.3 V) enables Channel A. Channel A Positive Input. Channel A Negative Input. Channel A Latch. A logic low (0 V ≤ LATCHA ≤ 0.8 V) allows gain changes on Channel A. A logic high (1.4 V ≤ LATCHA ≤ 3.3 V) prevents gain changes on Channel A. Data Pin for Channel A Up/Down Function (UPDN_DAT_A). Bit 0 for Channel A Parallel Gain Control Interface (A0). Clock Interface for Channel A Up/Down Function (UPDN_CLK_A). Bit 1 for Channel A Parallel Gain Control Interface (A1). Fast Attack (FA_A). In serial mode, a logic high (1.4 V ≤ FA_A ≤ 3.3 V) attenuates Channel A according to FA setting in the SPI word. Bit 2 for Channel A Parallel Gain Control Interface (A2).
Rev. 0 | Page 7 of 32
ADL5202
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RS = RL = 150 Ω at 200 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted. 25
25
46MHz 140MHz 300MHz
20
16dB 15dB
18dB 17dB
20dB 19dB
14dB 13dB
10dB 9dB
12dB 11dB
6dB 5dB
8dB 7dB
20 15
15
10
GAIN (dB)
GAIN (dB)
10 5
5 0
0 –5
–5
–10
–10
–15
20
30
40
50
60
70
GAIN CODE
–20 10
45
50
40
45
35
40
NOISE FIGURE (dB)
–2dB –3dB
–4dB –5dB
–6dB –7dB
–8dB –9dB
–10dB –11dB
100
1000
30 25 20 15
TA = –40°C TA = +25°C TA = +85°C
MIN GAIN (–11.5dB)
35 30
MID GAIN (5dB)
25 20 15
MAX GAIN (20dB)
10
5
5 –5
0
5
10
15
20
25
PROGRAMMED GAIN (dB)
0
09387-010
–10
Figure 7. Noise Figure vs. Programmed Gain at 140 MHz
0
100
200
300
400
500
600
FREQUENCY (MHz)
09387-013
NOISE FIGURE (dB)
0dB –1dB
Figure 9. Gain vs. Frequency Response (Every 1 dB Step)
10
Figure 10. Noise Figure vs. Frequency at Max, Mid, and Min Gain Outputs
25
25
20
TA = –40°C TA = +25°C TA = +85°C
OP1dB (dBm)
20
15
10
5
INPUT MAX RATINGS BOUNDARY
0 –15
–10
–5
15
10
5
0
5
10
15
20
PROGRAMMED GAIN (dB)
Figure 8. OP1dB vs. Programmed Gain at 140 MHz
25
0
09387-005
OP1dB (dBm)
2dB 1dB
FREQUENCY (MHz)
Figure 6. Gain vs. Gain Code at 46 MHz, 140 MHz, and 300 MHz
0 –15
4dB 3dB
09387-007
10
0
50
100
150
200
250
FREQUENCY (MHz)
300
350
400
09387-008
0
09387-004
–15
Figure 11. OP1dB vs. Frequency at Maximum Gain, Three Temperatures
Rev. 0 | Page 8 of 32
Data Sheet
ADL5202 60
60
–11.5dB 0dB 10dB 20dB
55
55
–11.5dB 0dB 10dB 20dB
50
OIP3 (dBm)
OIP3 (dBm)
50
45
45 40
INPUT MAX RATINGS BOUNDARY
35
40 30
35
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
Figure 12. Output Third-Order Intercept vs. Frequency at Four Gain Codes 60
20 –4
55
1
2
3
4
5
6
TA = –40°C TA = +25°C TA = +85°C
45
45
40
40
35
35
50
100
150
200
250
300
350
400
Figure 13. Output Third-Order Intercept vs. Frequency, Three Temperatures at 2 V p-p Composite –60
30 –4
–1
0
1
2
3
4
5
6
Figure 16. Output Third-Order Intercept vs. Power, Frequency = 140 MHz, Three Temperatures –60
46MHz 140MHz 300MHz
–80
–80
IMD3 (dBc)
–70
–90
–100
–110
–110
0
5
10
15
20
PROGRAMMED GAIN (dB)
25
–120
09387-018
–5
TA = –40°C TA = +25°C TA = +85°C
–90
–100
–10
–2
POUT (dBm)
–70
–120 –15
–3
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
Figure 14. Two-Tone Output IMD3 vs. Programmed Gain, at 46 MHz, 140 MHz, 300 MHz
Figure 17. Two-Tone Output IMD3 vs. Frequency, Three Temperatures
Rev. 0 | Page 9 of 32
400
09387-021
0
09387-019
OIP3 (dBm)
50
09387-016
OIP3 (dBm)
0
60
FREQUENCY (MHz)
IMD3 (dBc)
–1
Figure 15. Output Third-Order Intercept vs. Power at Four Gain Codes, Frequency = 140 MHz at 2 V p-p Composite
50
30
–2
POUT (dBm)
TA = –40°C TA = +25°C TA = +85°C
55
–3
09387-014
0
09387-011
30
25
ADL5202
–90
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
–150
0
50
100
150
200
250
–120 350
300
FREQUENCY (MHz)
–80
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140 –6
–5
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140
50
100
150
200
250
–120 350
300
09387-028
0
HARMONIC DISTORTION HD2 (dBc)
–60
–1
0
1
2
3
4
5
6
–120
–60
–80
HARMONIC DISTORTION HD3 (dBc)
–50
–80
FREQUENCY (MHz)
TA = –40°C TA = +25°C TA = +85°C
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140 –6
–120 –5
–4
–3
–2
–1
0
1
2
3
4
5
6
POUT (dBm)
Figure 19. Harmonic Distortion vs. Frequency, Three Temperatures
Figure 22. Harmonic Distortion vs. Power, Frequency = 140 MHz, Three Temperatures 25
25
TA = –40°C TA = +25°C TA = +85°C 20
OP1dB (dBm)
20
15
10
0 –15
INPUT MAX RATINGS BOUNDARY
–10
–5
15
10
5
0
5
10
PROGRAMMED GAIN (dB)
15
20
25
0
Figure 20. OP1dB vs. Programmed Gain at 140 MHz, Low Power Mode
0
50
100
150
200
250
FREQUENCY (MHz)
300
350
400
09387-009
5
09387-006
OP1dB (dBm)
HARMONIC DISTORTION HD2 (dBc)
–70
–2
POUT (dBm)
–40 TA = –40°C TA = +25°C TA = +85°C
–3
Figure 21. Harmonic Distortion vs. Power at Four Gains, Frequency = 140 MHz
Figure 18. Harmonic Distortion vs. Frequency at Four Gain Codes
–60
–4
HARMONIC DISTORTION HD3 (dBc)
–50
–50
HARMONIC DISTORTION HD3 (dBc)
–80
–70
09387-031
–40
HARMONIC DISTORTION HD2 (dBc)
–30
–70
–40
–11.5dB 0dB 10dB 20dB
09387-026
–60
HARMONIC DISTORTION HD3 (dBc)
–60
HARMONIC DISTORTION HD2 (dBc)
–20
–11.5dB 0dB 10dB 20dB
09387-023
–50
Data Sheet
Figure 23. OP1dB vs. Frequency at Maximum Gain, Three Temperatures, Low Power Mode
Rev. 0 | Page 10 of 32
Data Sheet
ADL5202
60
60
–11.5dB 0dB 10dB 20dB
55
55
–11.5dB 0dB 10dB 20dB
50
OIP3 (dBm)
OIP3 (dBm)
50
45
45 40 35
40
INPUT MAX RATINGS BOUNDRY
30
35
0
50
100
150
200
250
300
350
400
FREQUENCY (MHz)
20 –4
09387-012
30
–3
–2
–1
0
1
2
3
4
5
6
POUT (dBm)
09387-015
25
Figure 27. Output Third-Order Intercept vs. Power at Four Gain Codes, Frequency = 140 MHz, Low Power Mode
Figure 24. Output Third-Order Intercept vs. Frequency at Four Gain Codes, Low Power Mode at 2 V p-p Composite 60
60
TA = –40°C TA = +25°C TA = +85°C
55
55
TA = –40°C TA = +25°C TA = +85°C
50
OIP3 (dBm)
OIP3 (dBm)
50
45
45 40 35
40 30
35
100
150
200
250
300
350
400
FREQUENCY (MHz)
20 –4
–60
–80
–80
IMD3 (dBc)
–70
–90
–100
–110
–110
5
10
15
20
PROGRAMMED GAIN (dB)
1
2
3
4
5
6
–90
–100
25
09387-022
IMD3 (dBc)
–70
0
0
TA = –40°C TA = +25°C TA = +85°C
46MHz 140MHz 300MHz
–5
–1
Figure 28. Output Third-Order Intercept vs. Power, Three Temperatures, Low Power Mode at 2 V p-p Composite
–60
–10
–2
POUT (dBm)
Figure 25. Output Third-Order Intercept vs. Frequency, Three Temperatures, Low Power Mode
–120 –15
–3
09387-020
50
Figure 26. Two-Tone Output IMD3 vs. Programmed Gain at 46 MHz, 140 MHz, 300 MHz; Low Power Mode
–120
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
Figure 29. Two-Tone Output IMD3 vs. Frequency, Three Temperatures, Low Power Mode
Rev. 0 | Page 11 of 32
400
09387-025
0
09387-017
30
25
ADL5202
–50
–90
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110
–150
0
50
100
150
200
250
300
–120 350
FREQUENCY (MHz)
–80
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130
–110
–140 –6
TA = –40°C TA = +25°C TA = +85°C
–90
–60
–100
–70
–110
–80
–120
–90
–130
–100
–140
–110 50
100
150
200
250
300
–120 350
FREQUENCY (MHz)
–2
–1
0
1
2
3
4
5
6
–120
–50 TA = –40°C TA = +25°C TA = +85°C
–80
–60
–90
–70
–100
–80
–110
–90
–120
–100
–130 –6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
–110
POUT (dBm)
Figure 34. Harmonic Distortion vs. Power, Frequency = 140 MHz, Three Temperatures, Low Power Mode
VOLTAGE
Figure 31. Harmonic Distortion vs. Frequency, Three Temperatures, Low Power Mode
HARMONIC DISTORTION HD2 (dBc)
–50
HARMONIC DISTORTION HD3 (dBc)
–80
09387-029
–40
1
CH1 200mV/DIV
CH4 1V/DIV
CH1 200mV Ω CH4 1mV Ω
M 10ns 10GS/s IT 4ps/pt
A CH4
1.12V
TIME (10ns/DIV)
Figure 35. Disable Time Domain Response
Figure 32. Enable Time Domain Response
Rev. 0 | Page 12 of 32
09387-033
4
09387-036
HARMONIC DISTORTION HD2 (dBc)
–70
0
–3
–70
–30
–150
–4
Figure 33. Harmonic Distortion vs. Power at Four Gain Codes, Frequency = 140 MHz, Low Power Mode
–20
–50
–5
POUT (dBm)
Figure 30. Harmonic Distortion vs. Frequency at Four Gain Codes, Low Power Mode
–60
–50
HARMONIC DISTORTION HD3 (dBc)
–80
–70
HARMONIC DISTORTION HD3 (dBc)
–40
09387-032
–70
HARMONIC DISTORTION HD2 (dBc)
–30
–40
–11.5dB 0dB 10dB 20dB
09387-027
–60
HARMONIC DISTORTION HD3 (dBc)
–60
HARMONIC DISTORTION HD2 (dBc)
–20
–11.5dB 0dB 10dB 20dB
09387-024
–50
Data Sheet
Data Sheet
ADL5202 CH2 500mV/DIV
0pf
VOLTAGE
TIME (10ns/DIV)
TIME (1ns/DIV)
Figure 39. Large Signal Pulse Response, 0 pF and 5.6 pF, 2 V p-p Composite
150
–20
100
–30
50
–40
0
–50
–50
–60
S11 PHASE (Degrees)
–10
S22 MAGNITUDE (dB)
200
0
300
–10
250
–20
200
–30
150
–40
100
–50
50
–60
0
–70
–50
S22 PHASE (Degrees)
0
09387-034
200mV/DIV
Figure 36. Gain Step Time Domain Response
–100 –80
–150
–90
–200 1000
100
–100 10
FREQUENCY (MHz)
–100
MAGNITUDE MAX GAIN MAGNITUDE MIN GAIN PHASE MAX GAIN PHASE MIN GAIN
–150 –200 1000
100 FREQUENCY (MHz)
Figure 37. S11 Magnitude and Phase vs. Frequency
09387-038
–80 10
MAGNITUDE MAX GAIN MAGNITUDE MIN GAIN PHASE MAX GAIN PHASE MIN GAIN
09387-035
–70
Figure 40. S22 Magnitude and Phase vs. Frequency
1.0
–60
0.8
–65
CHANNEL ISOLATION (dB)
0.6 0.4 0.2 0 –0.2 –0.4
–70
CHANNEL A TO CHANNEL B CHANNEL A = MAX GAIN CHANNEL B = ALL GAINS
–75 –80 –85 –90
CHANNEL B TO CHANNEL A CHANNEL B = MAX GAIN CHANNEL A = ALL GAINS
–0.6
–1.0 –15
–10
–5
0
5
10
15
20
PROGRAMMED GAIN (dB)
25
Figure 38. Gain Step Error, Frequency = 140 MHz
–100
0
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
Figure 41. Channel Isolation vs. Frequency
Rev. 0 | Page 13 of 32
900
1000
09387-043
–95
–0.8 09387-037
GAIN ERROR (dB)
S11 MAGNITUDE (dB)
INPUT
09387-030
VOLTAGE
CH3 50mV/DIV
5.6pf DIFFERENTIAL
Data Sheet
0
0
–10
–10
REVERSE ISOLATION (dB)
–20
–30
–40
–50
–20
–30
–40
100M
1G
FREQUENCY (Hz)
–60 10
09387-039
–60 10M
Figure 42. Reverse Isolation vs. Frequency COMMON-MODE REJECTION RATIO, CMRR (dB)
MIN MID MAX
GROUP DELAY (ns)
0.8
0.6
0.4
100
1000
FREQUENCY (MHz)
09387-040
0.2
Figure 43. Group Delay vs. Frequency at Max, Mid, and Min Gain Outputs 4.0
3.0
350MHz 300MHz 250MHz 200MHz 150MHz 100MHz 50MHz
2.0 1.5 1.0 0.5 0
0
10
20
30
40
50
GAIN CODE
60
70
09387-041
PHASE VARIATION (Degrees)
3.5
2.5
1000
Figure 45. Disable-State Reverse Isolation vs. Frequency
1.0
0 10
100 FREQUENCY (MHz)
09387-042
–50
Figure 44. Phase Variation vs. Gain Code
Rev. 0 | Page 14 of 32
60
50
40
30
20
10
0 10M
100M FREQUENCY (Hz)
Figure 46. Common-Mode Rejection Ratio vs. Frequency
1G
09387-044
REVERSE ISOLATION (dB)
ADL5202
Data Sheet
ADL5202
CHARACTERIZATION AND TEST CIRCUITS +5V
L1 1µH
L2 1µH
0.1µF
50Ω
0.1µF
50Ω
1/2 AC
50Ω TRACES
50Ω
AC
50Ω TRACES
ADL5202
0.1µF
50Ω
0.1µF
09387-060
6 A0 TO A5
Figure 47. Test Circuit for S-Parameters on Dedicated 50 Ω Differential-to-Differential Board
+5V
TC3-1T
L1 1µH
C1 0.1µF
L2 1µH
C3 0.1µF
R1 62Ω
R4 25Ω
ETC1-1-13
1/2 C2 0.1µF
6
C4 0.1µF
R2 62Ω
T2
R3 25Ω
A0 TO A5
Figure 48. Test Circuit for Distortion, Gain, and Noise
Figure 49. Differential-to-Differential Characterization Board, Circuit Side Layout
Rev. 0 | Page 15 of 32
50Ω
09387-062
AC
ADL5202
PAD LOSS = 11dB
09387-063
50Ω
T1
ADL5202
Data Sheet
THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW The ADL5202 VGA has three digital gain control options: the parallel control interface, serial peripheral interface, and gain up/down interface. The desired gain control option is selected via two control pins, MODE0 and MODE1 (see Table 4 for the truth table for the mode control pins). The gain code is in a 6-bit binary format. A voltage of between 1.4 V and 3.3 V is required for a logic high. Three pins are common to all gain control options: PM, PWUPA, and PWUPB. PM allows the user to choose operation in nominal mode or high performance mode. PWUPA and PWUPB are power-up pins for Channel A and Channel B, respectively. Physical pins are shared among the three interfaces, resulting in as many as three different functions per digital pin (see Table 3). Table 4. Digital Control Interface Selection Truth Table MODE0 0 1 0 1
Interface Parallel control Serial peripheral (SPI) Up/down Up/down
The parallel digital interface uses six binary bits (Bits[A5:A0] or Bits[B5:B0]) and a latch pin (LATCHA or LATCHB) per amplifier. The latch pin controls whether the input data latch is transparent or latched. In transparent mode, gain changes as input gain control bits change. In latched mode, gain is determined by the latched gain setting and does not change with changing input gain control bits.
SERIAL PERIPHERAL INTERFACE (SPI) The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The SPI data register consists of two bytes: six gain control bits, two attenuation step size address bits, one read/write bit, and seven don’t care bits. SDIO is the serial data input and output pin. The SCLK pin is the serial clock, and CSA or CSB is the channel select pin. LSB D0
MSB LSB MSB D1
D2
D3
D4
D5
FA0 FA1 R/W DNC DNC DNC DNC DNC DNC DNC
DO NOT CARE (7 BITS)
09387-046
GAIN CONTROL
Table 5. SPI 2-Bit Attenuation Step Size Truth Table FA1 0 0 1 1
FA0 0 1 0 1
Step Size (dB) 2 4 8 16
GAIN UP/DOWN INTERFACE The GS1 and GS0 pins control the up/down gain step function. Gain is increased by a clock pulse on the UPDN_CLK_A pin or the UPDN_CLK_B pin (rising and falling edges) when the UPDN_DAT_A or UPDN_DAT_B pin is high. Gain is decreased by a clock pulse on the UPDN_CLK_A or UPDN_CLK B pin when the UPDN_DAT_A or UPDN_CLKB pin is low. The truth table for the gain step function is shown in Table 6. Reset is detected by a rising edge latching data having one polarity, with the falling edge latching the opposite polarity. Reset results in a minimum binary gain code of 111111. Table 6. Step Size Control Truth Table GS1 0 0 1 1
GS0 0 1 0 1
Step Size (dB) 0.5 1 2 4
The step size is selectable using the GS1 and GS0 pins. The gain is limited by the top and bottom of the control range.
READ/WRITE FAST ATTACK ATTENUATION STEP SIZE ADDRESS
The fast attack feature, accessible via the SPI, allows the gain to be reduced from its present gain setting by a predetermined step size. Four different attenuation step sizes are available. The truth table for fast attack is shown in Table 5.
SPI fast attack mode is controlled by the FA_A or FA_B pin. A logic high on the FA_A or FA_B pin results in an attenuation that is selected by Bits[FA1:FA0] in the SPI register.
PARALLEL DIGITAL INTERFACE
DATA
Fast Attack
Figure 50. 16-Bit SPI Register
UPDN_DAT UPDN_CLK
To write to the SPI register, CSA or CSB must be pulled low and 16 clock pulses must be applied to SCLK. Individual channel SPI registers can be selected by pulling CSA or CSB low. By pulling the CSA and CSB pins low simultaneously, the same data can be written to both SPI registers. Rev. 0 | Page 16 of 32
UP
DN
Figure 51. Up/Down Timing
RESET
09387-045
MODE1 0 0 1 1
To read the SPI register value, the R/W bit must be set high, CSA or CSB must be pulled low, and the part must be clocked. After the register has been read out during the next 16 clock cycles, the SPI is automatically put into write mode. Note that there is only one SDIO pin. Readback from the registers should be performed individually.
Data Sheet
ADL5202 LOGIC TIMING
TRUTH TABLE
To write to the ADL5202, refer to the timing shown in Figure 2 (reproduced in this section as Figure 52). The write mode uses a 16-bit serial word on the SDIO pin. The R/W of the word must be low to write Bits[D0:D5], which are the binary weighted codes for the attenuation level (0 = minimum attenuation, 63 = maximum attenuation). The FA0 and FA1 bits control the fast attack step size. The DNC bits are nonfunctional, do not care bits. Reading the ADL5202 SPI register requires the following two steps:
Table 7. Gain Code vs. Voltage Gain Lookup Table 6-Bit Binary Gain Code 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
Voltage Gain (dB) 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5
6-Bit Binary Gain Code 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
Voltage Gain (dB) 4 3.5 3 2.5 2 1.5 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 −3 −3.5 −4 −4.5 −5 −5.5 −6 −6.5 −7 −7.5 −8 −8.5 −9 −9.5 −10 −10.5 −11 −11.5
1.
2.
Set the R/W bit high using a 16-bit word and the timing described in this section and Figure 52. All other bits are ignored when the R/W bit is high. The SDIO is used as an output during the next sequence. The written pattern is serially clocked out on SDIO using 16 clocks and the timing described in this section and Figure 52. The R/W bit automatically returns low to the write state following the read sequence.
tPW
tSCLK SCLK
tDH tDS ___ ___ CSA, CSB
SDIO
DNC
DNC
DNC
DNC
DNC
DNC
DNC
R/W
FA1
FA0
D5
Figure 52. SPI Interface Read/Write Mode Timing Diagram
Rev. 0 | Page 17 of 32
D4
D3
D2
D1
D0
09387-152
tDS tDH
ADL5202
Data Sheet
CIRCUIT DESCRIPTION BASIC STRUCTURE The ADL5202 is a dual, differential, variable gain amplifier, with each amplifier consisting of a 150 Ω digitally controlled, passive attenuator that is followed by a highly linear transconductance amplifier with feedback. 1/2 OF
ADL5202 gm AMP
ATTENUATOR
VIN–
VOUT+ VOUT–
LOGIC
REF
DIGITAL INPUTS PARALLEL, SPI, FAST ATTACK UP/DOWN
09387-047
VIN+
Figure 53. Simplified Schematic
Input System The dc voltage level at the inputs of each amplifier is set by two independent internal voltage reference circuits to approximately 1.6 V. The references are not accessible and cannot be adjusted. Each amplifier can be powered down by pulling the corresponding power-up pin down to ground (logic low). When powered down, the total current of each amplifier reduces to 7 mA (typical). The dc level at the inputs remains at approximately 1.6 V, regardless of the state of the PWUPA or PWUPB pin.
Output Amplifier The gain of the output amplifier is set to 22 dB when driving a 150 Ω load. The input and output resistance of this amplifier is set to 150 Ω in matched condition. If the load or the source resistance is different from 150 Ω, the following equations can be used to determine the resulting gain and input/output resistances. Voltage Gain = AV = 0.09 × (2000)//RL RIN = (2000 + RL)/(1 + 0.09 × RL) S21 (Gain) = 2 × RIN/(RIN + RS) × AV ROUT = (2000 + RS)/(1 + 0.09 × RS) Note that at the maximum attenuation setting, RS, as seen by the output amplifier, is the output resistance of the attenuator, which is 150 Ω. However, at minimum attenuation, RS is the source resistance that is connected to the input of the part.
The dc current to the outputs of each amplifier is supplied through two external chokes. The inductance of the chokes and the resistance of the load, in parallel with the output resistance of the device, add a low frequency pole to the response. The parasitic capacitance of the chokes adds to the output capacitance of the part. This total capacitance, in parallel with the load and output resistance, sets the high frequency pole of the device. Generally, the larger the inductance of the choke, the higher its parasitic capacitance. Therefore, this trade-off must be considered when the value and type of the choke are selected. For an operation frequency of 15 MHz to 700 MHz driving a 150 Ω load, 1 μH chokes with a self resonant frequency (SRF) of 160 MHz or higher are recommended (such as the 0805LS-102XJBB from Coilcraft). If higher value chokes are used, a 4 MHz zero, due to the internal ac-coupled feedback, causes an increase in S21 of up to 6 dB at frequencies below 4 MHz. The supply current of each amplifier consists of about 35 mA through the VPOS pin and 50 mA through the two chokes combined. The latter increases with temperature at approximately 2.5 mA per 10°C. The total choke current increases to 75 mA for high performance mode. Each amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. To minimize the parasitic capacitance, a good practice is to avoid any ground or power plane under this routing region and under the chokes.
Gain Control The gain of each amplifier can be adjusted using the parallel control interface, the serial peripheral interface, or the gain up/down interface. In general, the gain step size is 0.5 dB, but larger sizes can be programmed using the various interfaces, as described in the Digital Interface Overview section. Each amplifier has a maximum gain of +20 dB (Code 0) to −11.5 dB (Code 63). The noise figure of each amplifier is approximately 7.5 dB at maximum gain setting, and it increases as the gain is reduced. The increase in noise figure is equal to the reduction in gain. The linearity of the part measured at the output is first-order independent of the gain setting. From −4 dB to +20 dB gain, OIP3 is approximately 50 dBm into 150 Ω load at 200 MHz (0 dBm per tone). At gain settings below −4 dB, OIP3 drops to approximately 40 dBm.
Rev. 0 | Page 18 of 32
Data Sheet
ADL5202
APPLICATIONS INFORMATION To enable each channel of the ADL5202, the PWUPA or PWUPB pin must be pulled high (1.4 V≤ PWUPA/PWUPB ≤ 3.3 V). Taking PWUPA or PWUPB low puts the channels of the ADL5202 in sleep mode, reducing current consumption to approximately 7 mA per channel at ambient.
BASIC CONNECTIONS Figure 54 shows the basic connections for operating the ADL5202. A voltage between 4.5 V and 5.5 V should be applied to the VPOS pins. Each supply pin should be decoupled with at least one low inductance, surface-mount ceramic capacitor of 0.1 μF, placed as close as possible to the device.
ADC DRIVING
The outputs of the ADL5202 must be pulled up to the positive supply with 1 μH RF chokes. The differential outputs are biased to the positive supply and require ac coupling capacitors, preferably 0.1 μF. Similarly, the input pins are at bias voltages of about 1.6 V above ground and should be ac-coupled as well. The ac coupling capacitors and the RF chokes are the principle limitations for operation at low frequencies.
The ADL5202 is a highly linear, variable gain amplifier that is optimized for ADC interfacing. The output IMDs and noise floor remain constant throughout the 31.5 dB gain range. This is a valuable feature in a variable gain receiver where it is desirable to maintain a constant instantaneous dynamic range as the receiver range is modified. The output noise is 18 nV/√Hz, which is compatible with 14- or 16-bit ADCs. The two-tone IMDs are usually greater than −100 dB for −1 dBm into 150 Ω or 2 V p-p output. The 150 Ω output impedance makes the task of designing a filter for the high input impedance ADCs more straightforward.
The digital pins (mode control pins, associated SPI and parallel gain control pins, PM, PWUPA, and PWUPB) operate on a voltage of 3.3 V. BALANCED SOURCE RS RS AC 2 2
CHANNEL A GAIN CONTROL INTERFACE
0.1µF
0.1µF
10
31 VOUTA+
32 VOUTA–
33 GND
35
34 PWUPA
VINA–
VINA+
36
37
39
38 UPDN_DAT_A/A0
LATCHA
VPOS
EXPOSED PADDLE
VPOS
PM GND
VPOS
SIDO/B5
VPOS
SCLK/B4
GS1/CSB/ B3
VOUTB+ VOUTB–
VOUTB+
9
ADL5202
VOUTB–
8
MODE0
GND
7
VPOS
PWUPB
6
MODE1
VINB+
3.3V
VPOS
VINB–
5
VOUTA+
LATCHB
4
VOUTA–
A5
UPDN_DAT_B/B0
3 GAIN MODE INTERFACE
A4
UPDN_CLK_A/A1
2
CSA/A3
GS0/ FA_B/B2 UPDN_CLK_B/B1
1
FA_A/A2
40
3.3V
0.1µF
30
RL
29 0.1µF
28 27 26 25
0.1µF 1µH
22 21
1µH
0.1µF
0.1µF
0.1µF
VPOS
VPOS
24 23
BALANCED LOAD
0.1µF 0.1µF 0.1µF
0.1µF RL
BALANCED LOAD
20
19
18
17
3.3V CHANNEL B GAIN CONTROL INTERFACE
0.1µF
1µH 0.1µF
VPOS
0.1µF
RS RS AC 2 2 BALANCED SOURCE
Figure 54. Basic Connections
Rev. 0 | Page 19 of 32
09387-048
15
16
14
13
12
11
0.1µF 1µH
ADL5202
Data Sheet 5V VREF
5V 1.0µH 0.1µF
1:3
0.1µF
33Ω
75Ω
1/2
50Ω
56nH
ADL5202
75Ω
AC 0.1µF
4pF
VREF
AD9268
33Ω
56nH
0.1µF 1.0µH
09387-049
DIGITAL INTERFACE 5V
Figure 55. Wideband ADC Interfacing Example Featuring One-Half of the ADL5202 and the AD9268
0
–15 –30 –45 –60 –75
3 –90
+
4
5
2
6
–105
–1
–120
–2 –3
–135 –150
–5
0
–6
6
12
18
24
30
36
42
48
54
60
FREQUENCY (MHz)
–7
09387-051
–4
Figure 57. Measured Single-Tone Performance of the Circuit in Figure 55 for a 100 MHz Input Signal
–8 –9 –10 –11 –12 –14
–15
20
40
60
80
100
120
140
160
180
FREQUENCY (MHz)
200
Figure 56. Measured Frequency Response of Wideband ADC Interface, as Depicted in Figure 55
Figure 55 uses a 1:3 impedance transformer to provide the 150 Ω input impedance of the ADL5202 with a matched input. The outputs of the ADL5202 are biased through the two 1 μH inductors, and the two 0.1 μf capacitors on the outputs decouple the 5 V inductor voltage from the input common-mode voltage of the AD9268. The two 75 Ω resistors provide the 150 Ω load to the ADL5202 whose gain is load dependent. The 56 nH inductors and 4 pF capacitor constitute the (100 MHz – 1 dB) low-pass filter. The two 33 Ω isolation resistors suppress any switching currents from the ADC input sample-and-hold circuitry. The circuit depicted in Figure 55 provides variable gain, isolation, filtering, and source matching for the AD9268. Using this circuit with the ADL5202 in a gain of 20 dB (maximum gain), an SNR of 69 dB, and an SFDR performance of >86 dBc is achieved at 100 MHz, as shown in Figure 57.
–30 AMPLITUDE (dBFS)
0
09387-050
–15
FUNDAMENTAL1 = –7.127dBFS FUNDAMENTAL2 = –7.039dBFS 2F1 – F2 = –91.818dBc 2F2 – F1 = –87.083dBc NOISE FLOOR = –109.57dB
0
–13
Rev. 0 | Page 20 of 32
–45 –60 –75 –90
+ 2F2 – F1
F2 – F1
2F1 – F2
F1 + F2 2F1 + F2 2F2 + F1
–105 –120 –135 –150 0
6
12
18
24
30
36
42
48
54
FREQUENCY (MHz)
Figure 58. Measured Two-Tone Performance of the Circuit in Figure 55 for a 100 MHz Input Signal
60
09387-052
INSERTION LOSS (dB)
SNR = 69dB SFDR = 86dBc NOISE FLOOR = –108dB FUND = –1.035dBFS SECOND = –89.17dBc
0
AMPLITUDE (dBFS)
Figure 55 shows one-half of the ADL5202 driving a two-pole, 100 MHz low-pass filter into the AD9268. The AD9268 is a 16-bit, 125 MSPS analog-to-digital converter with a buffered wideband input, which presents a 6 kΩ differential input impedance and requires between a 1 V or 2 V input swing to reach full scale. This example uses the 2 V p-p input. For optimum performance, the ADL5202 should be driven differentially, using an impedance transformer or input balun.
Data Sheet
ADL5202 In addition, the L6 inductor shorts the ADC inputs at dc, which introduces a zero into the transfer function. The ac coupling capacitors and the bias chokes introduce additional zeros into the transfer function. The final overall frequency response takes on a band-pass characteristic, helping to reject noise outside of the intended Nyquist zone. Table 8 provides initial suggestions for prototyping purposes. Some empirical optimization may be needed to help compensate for actual PCB parasitics.
An alternative narrow-band approach is presented in Figure 59. By designing a narrow band-pass antialiasing filter between the ADL5202 and the target ADC, the output noise of the ADL5202 outside of the intended Nyquist zone can be attenuated, helping to preserve the available SNR of the ADC. In general, the SNR improves by several decibels (dB) when including a reasonable order antialiasing filter. In this example, a low loss 1:3 input transformer is used to match the 150 Ω balanced input of the ADL5202 to a 50 Ω unbalanced source, resulting in minimum insertion loss at the input.
LAYOUT CONSIDERATIONS Each amplifier has two output pins for each polarity, and they are oriented in an alternating fashion. When designing the board, care should be taken to minimize the parasitic capacitance due to the routing that connects the corresponding outputs together. A good practice is to avoid any ground or power plane under this routing region and under the chokes to minimize the parasitic capacitance.
Figure 59 is optimized for driving some of the Analog Devices popular unbuffered ADCs, such as the AD9246, AD9640, and AD6655. Table 8 includes antialiasing filter component recommendations for popular IF sampling center frequencies. Inductor L5 works in parallel with the on-chip ADC input capacitance and a portion of the capacitance presented by C4 to form a resonant tank circuit. The resonant tank helps to ensure that the ADC input acts like a real resistance at the target center frequency. 5V 5V 1µH 1:3
1nF
1nF
L1
1/2
50Ω
ADL5202
L3
L5
C2 4pF
C4 4pF
L3
L5
AC 1nF
1nF
L1
75Ω CML
AD9246 AD9640 AD6655
L6
75Ω
1µH 09387-053
DIGITAL INTERFACE 5V
Figure 59. Narrow-Band IF Sampling Solution for Unbuffered ADC Applications
Table 8. Interface Filter Recommendations for Various IF Sampling Frequencies Center Frequency 96 MHz 140 MHz 170 MHz 211 MHz
1 dB Bandwidth 27 MHz 31 MHz 25 MHz 40 MHz
L1 68 nH 47 nH 39 nH 30 nH
C2 15 pF 11 pF 10 pF 7 pF
Rev. 0 | Page 21 of 32
L3 220 nH 150 nH 120 nH 100 nH
C4 15 pF 11 pF 10 pF 7.5 pF
L5 68 nH 47 nH 47 nH 30 nH
L6 150 nH 82 nH 51 nH 43 nH
ADL5202
Data Sheet
EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE The ADL5202 evaluation board is configured with a USBfriendly interface to program the gain of the ADL5202. The software graphic user interface (see Figure 60) lets users select a particular gain mode and gain level to write to the device and also to read back data from the SDIO pin, showing the currently programmed gain setting. The software setup files can be downloaded from the ADL5202 product page at www.analog.com.
09387-054
The ADL5202 evaluation board is available with software to program the variable gain control. It is a 4-layer board with a split ground plane for analog and digital sections. Special care is taken to place the power decoupling capacitors close to the device pins. The board is designed for easy single-ended (through a Mini-Circuits TC3-1T+ RF transformer) or differential configuration for each channel.
Figure 60. Evaluation Control Software
Rev. 0 | Page 22 of 32
Data Sheet
ADL5202
EVALUATION BOARD SCHEMATICS AND ARTWORK 09387-055
Figure 61. Evaluation Board Schematic Rev. 0 | Page 23 of 32
ADL5202
Data Sheet 09387-056
Figure 62. RF Output Detail
Rev. 0 | Page 24 of 32
Data Sheet
ADL5202 09387-057
Figure 63. Schematic for the USB Section of the Evaluation Board Rev. 0 | Page 25 of 32
Data Sheet
09387-058
ADL5202
09387-059
Figure 64. Evaluation Board Top Layer
Figure 65. Evaluation Board Bottom Layer
Rev. 0 | Page 26 of 32
Data Sheet
ADL5202
EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Table 9. Bill of Materials for Main Section Components C24 to C27, C51 VPOS, 3V3 GND DUT1 INA+, INA− INB+, INB− T1, T2, C18 to C23, R8, R9, R20 to R29, R88, R89
OUTA+, OUTA− OUTB+, INB− T3, T4, C36 to C45, R63 to R82, L1 to L4 VXA, VXB
P1, P2, PWUPA, PWUPB, R30
A0 to A5, B0 to B5, LATCHA, LATCHB, PM, MODE0, MODE1 R10 to R19, R31 to R62, R84 to R87, C28 to C35, C47 to C50
Function Power supply decoupling. Nominal supply decoupling consists of a 0.1 µF capacitor to ground. Power supply connections. Evaluation device. Input interfaces. The INA+ and INA− input SMA connectors are used to drive the Channel A balun in a single-ended fashion. The INB+ and INB− input SMAs are used to drive the Channel B balun in a single-ended fashion. The default configuration of the evaluation board is for single-ended operation. T1 and T2 are 3:1 impedance ratio RF transformers that are used to transform a 50 Ω, single-ended input into a 150 Ω balanced differential signal. C18 and C19 are balun decoupling capacitors. C20 to C23 are used for dc blocking purposes. R20 to R29 are provided for generic placement of matching components. R88 and R89 are populated to ground on one side of the transformer primary, creating the 50 Ω single-ended input. Output interfaces. The OUTA+ and OUTA− output SMA connectors are used to load the Channel A balun in a single-ended fashion. The default configuration of the evaluation board is for single-ended operation. The OUTB+ and OUTB− output SMAs are used to load the Channel B balun in a singleended fashion. The default configuration of the evaluation board is for single-ended operation. T3 and T4 are 3:1 impedance ratio transformers used to transform a 50 Ω, single-ended output into a 150 Ω balanced differential load. C40 to C43 are used for ac coupling. C44 and C45 are balun decoupling capacitors. R69 to R76 are provided for generic placement of matching components. By removing R79 and R80 and installing 0 Ω at R81 and R82, the output is converted to a differential output. L1 to L4 provide dc bias to the output stages. R67 and R68 provide a connection to the 5 V power plane. Optionally, R67 and R68 can be removed and the output stage biased through the VXA and VXB terminals. Power-up interface. The ADL5202 is powered up by applying a logic high (1.4 V ≤ PWUPA/PWUPB ≤ 3.3 V) to PWUPA and PWUPB from an external source or by installing a shunt between Pin1 and Pin 2 of P1 andP2.
Gain control interface. All of the gain control functions are fully controlled via the USB microcontroller by using the supplied software. Three-pin headers allow for manual operation of the gain control, if desired. The R31 to R34, R45, R46, R53, R54, and R84 to R87 resistors and the C28 to C35 and C47 to C50 capacitors allow for the generic placement of filter components. The R10 to R19, R31 to R62, and R84 to R87 resistors isolate the gain control pins from the microcontroller and provide current limiting.
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Default Conditions C24 to C27, C51 = 0.1 µF (Size 0603) VPOS, 3V3 (test loop red) installed GND (test loop black) installed Installed INA+ (SMA connector) installed INA− (SMA connector) installed INB+ (SMA connector) installed INB− (SMA connector) installed T1, T2 = TC3-1T+ (Mini-Circuits) C18 to C23 = 0.1 µF (Size 0603) R8, R9, R26 to R29 = 0 Ω (Size 0402) R20 to R25, R88, R89 = open
OUTA+ (SMA connector) installed OUTA− (SMA connector) installed OUTB+ (SMA connector) installed OUTB− (SMA connector) installed T3, T4 = TC3-1T+ (mini-circuits) C36 to C45 = 0.1 µF (Size 0603) R63 to R72, R77 to R80 = 0 Ω (Size 0402) R73 to R76, R81, R82 = open L1, L2, L3, L4 = 1 µH (Size 0805) VXA, VXB (test loop) installed
P1 installed for enable P2 installed for enable PWUPA (SMA connector) installed PWUPB (SMA connector) installed R30 = open A0 to A5 (3-pin header) installed B0 to B5 (3-pin header) installed LATCHA (3-pin header) installed LATCHB (3-pin header) installed MODE0 (3-pin header) installed MODE1 (3-pin header) installed PM (3-pin header) installed R10 to R19 = 1 kΩ (Size 0603) R35 to R44 = 1 kΩ (Size 0603) R47 to R52 1 kΩ (Size 0603) R55 to R62 1 kΩ (Size 0603) R31 to R34 = open R45, R46 = open R53, R54 = open R84 to R87 = open C28 to C35 = open C47 to C50 = open
ADL5202
Data Sheet
Configuration Options for the USB Section Table 10. Bill of Materials for USB Section Components C7, C8 C13 C2, C3, C4, C6, C10, C11, C12, C14, C16, C46 C9, C15 C1, C5 CR1 P3 R1, R2, R5 R6, R7 R3, R4 R83 U2 U1 U3 Y1
Default Conditions 22 pF (Size 0603) 1000 pF (Size 0603) 0.1 µF (Size 0402) 1 µF (Size 0402) 10 pF (Size 0402) Green LED ( Panasonic LNJ308G8TRA) USB SMT connector (Hirose Electric UX60A-MB-5ST 240-0003-4) 2 kΩ (Size 0603) 78.7 kΩ (Size 0603) 140 kΩ (Size 0603) 100 kΩ (Size 0603) 0 Ω (Size 0603) USB microcontroller (Cypress CY7C68013A-56LFXC) 64 kB EEPROM (Microchip 24LC64-I/SN) Low dropout regulator (Analog Devices ADP3334ACPZ) 24 MHz crystal oscillator (AEL Crystals X24M000000S244)
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Data Sheet
ADL5202
OUTLINE DIMENSIONS 0.30 0.23 0.18 31
40
30
0.50 BSC
1
TOP VIEW 0.80 0.75 0.70
10 11
20
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
SEATING PLANE
4.45 4.30 SQ 4.25
EXPOSED PAD
21
0.45 0.40 0.35
PIN 1 INDICATOR
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
05-06-2011-A
PIN 1 INDICATOR
6.10 6.00 SQ 5.90
Figure 66. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 6 mm × 6 mm Body, Very Very Thin Quad (CP-40-10) Dimensions shown in millimeters
ORDERING GUIDE Model 1 ADL5202ACPZ-R7 ADL5202-EVALZ 1
Temperature Range −40°C to +85°C
Package Description 40 Lead LFCSP_WQ, 7” Tape and Reel Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 29 of 32
Package Option CP-40-10
ADL5202
Data Sheet
NOTES
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Data Sheet
ADL5202
NOTES
Rev. 0 | Page 31 of 32
ADL5202
Data Sheet
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09387-0-10/11(0)
Rev. 0 | Page 32 of 32
