Transcript
1200 MHz to 2500 MHz Balanced Mixer, LO Buffer, IF Amplifier, and RF Balun ADL5355 FUNCTIONAL BLOCK DIAGRAM
FEATURES
APPLICATIONS Cellular base station receivers Transmit observation receivers Radio link downconverters
IFGM
IFOP
IFON
PWDN
LEXT
20
19
18
17
16
ADL5355 VPIF 1
15
LOI2
RFIN 2
14
VPSW
RFCT 3
13
VGS1
COMM 4
12
VGS0
COMM 5
11
LOI1
BIAS GENERATOR
6
7
8
9
10
VLO3
LGM3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 1.
GENERAL DESCRIPTION The ADL5355 uses a highly linear, doubly balanced passive mixer core along with integrated RF and LO balancing circuitry to allow for single-ended operation. The ADL5355 incorporates an RF balun, allowing for optimal performance over a 1200 MHz to 2500 MHz RF input frequency range using low-side LO injection for RF frequencies from 1700 MHz to 2500 MHz and high-side LO injection for RF frequencies from 1200 MHz to 1700 MHz. The balanced passive mixer arrangement provides good LO-to-RF leakage, typically better than −39 dBm, and excellent intermodulation performance. The balanced mixer core also provides extremely high input linearity, allowing the device to be used in demanding cellular applications where inband blocking signals may otherwise result in the degradation of dynamic performance. A high linearity IF buffer amplifier follows the passive mixer core to yield a typical power conversion gain of 8.4 dB and can be used with a wide range of output impedances.
The ADL5355 provides two switched LO paths that can be used in TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5355 is capable of operation at voltages down to 3.3 V with substantially reduced current. Under low voltage operation, an additional logic pin is provided to power down (<200 µA) the circuit when desired. The ADL5355 is fabricated using a BiCMOS high performance IC process. The device is available in a 5 mm × 5 mm, 20-lead LFCSP and operates over a −40°C to +85°C temperature range. An evaluation board is also available.
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
08080-001
RF frequency range of 1200 MHz to 2500 MHz IF frequency range of 30 MHz to 450 MHz Power conversion gain: 8.4 dB SSB noise figure of 9.2 dB SSB noise figure with 5 dBm blocker of 20 dB Input IP3 of 27 dBm Input P1dB of 10.4 dBm Typical LO drive of 0 dBm Single-ended, 50 Ω RF and LO input ports High isolation SPDT LO input switch Single-supply operation: 3.3 V to 5 V Exposed paddle 5 mm × 5 mm, 20-lead LFCSP 1500 V HBM/500 V FICDM ESD performance
ADL5355 TABLE OF CONTENTS
Features .............................................................................................. 1
3.3 V Performance ...................................................................... 15
Applications ....................................................................................... 1
Circuit Description......................................................................... 16
General Description ......................................................................... 1
RF Subsystem .............................................................................. 16
Functional Block Diagram .............................................................. 1
LO Subsystem ............................................................................. 17
Revision History ............................................................................... 2
Applications Information .............................................................. 18
Specifications..................................................................................... 3
Basic Connections ...................................................................... 18
5 V Performance ........................................................................... 4
IF Port .......................................................................................... 18
3.3 V Performance ........................................................................ 4
Bias Resistor Selection ............................................................... 18
Spur Tables .................................................................................... 5
Mixer VGS Control DAC .......................................................... 18
Absolute Maximum Ratings............................................................ 6
Evaluation Board ............................................................................ 20
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 23
Pin Configuration and Function Descriptions ............................. 7
Ordering Guide .......................................................................... 23
Typical Performance Characteristics ............................................. 8 5 V Performance ........................................................................... 8
REVISION HISTORY 7/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5355 SPECIFICATIONS VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage 1 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER-DOWN (PWDN) INTERFACE 2 PWDN Threshold Logic 0 Level Logic 1 Level PWDN Response Time PWDN Input Bias Current
1 2
Conditions
Min
Tunable to >20 dB over a limited bandwidth
Typ
Unit
2500
dB Ω MHz
450 5.5
Ω||pF MHz V
20 50 1200
Differential impedance, f = 200 MHz Externally generated
Max
230||0.75 30 3.3 −6
5.0 0 15 50
1230
+10
2470 1.0 0.4
1.4 Device enabled, IF output to 90% of its final level Device disabled, supply current < 5 mA Device enabled Device disabled
Apply the supply voltage from the external circuit through the choke inductors. PWDN function is intended for use with VS ≤ 3.6 V only.
Rev. 0 | Page 3 of 24
160 220 0.0 70
dBm dB Ω MHz V V V ns ns µA µA
ADL5355 5 V PERFORMANCE VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under Blocking Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious IF/3 Spurious POWER SUPPLY Positive Supply Voltage Quiescent Current Total Quiescent Current
Conditions
Min
Typ
Max
Unit
Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
7
8.4 14.7 9.2 20
9.5
dB dB dB dB
22
27
dBm
50
dBm
10.4 −12.6 −39 −33 −69 −73
dBm dBm dBm dBc dBc dBc
5 dBm blocker present ±10 MHz from wanted RF input, LO source filtered fRF1 = 1949.5 MHz, fRF2 = 1950.5 MHz, fLO = 1750 MHz, each RF tone at −10 dBm fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1750 MHz, each RF tone at −10 dBm Unfiltered IF output
−10 dBm input power −10 dBm input power 4.5 LO supply, resistor programmable IF supply, resistor programmable VS = 5 V
5 100 90 190
5.5
V mA mA mA
3.3 V PERFORMANCE VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) POWER INTERFACE Supply Voltage Quiescent Current Power-Down Current
Conditions
Min
Including 4:1 IF port transformer and PCB loss ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential fRF1 = 1949.5 MHz, fRF2 = 1950.5 MHz, fLO = 1750 MHz, each RF tone at −10 dBm fRF1 = 1950 MHz, fRF2 = 1900 MHz, fLO = 1750 MHz, each RF tone at −10 dBm
3.0 Resistor programmable Device disabled
Rev. 0 | Page 4 of 24
Typ
Max
Unit
9 15.3 8.75 22
dB dB dB dBm
52
dBm
7
dBm
3.3 125 150
3.6
V mA µA
ADL5355 SPUR TABLES All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured in dBc from the IF output power level. Data was only measured for frequencies less than 6 GHz. Typical noise floor of the measurement system = −100 dBm.
5 V Performance VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 4. M 0
N
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
−42.3 −66.7 <−100
1 −10.0 0.0 −65.3 <−100 <−100
2 −21.1 −57.1 −57.0 −97.6 <−100
3 −53.8 −51.4 −67.0 −61.6 <−100 <−100
4 −75.9 −88.4 <−100 −97.9 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 <−100
6
<−100 <−100 <−100 <−100 <−100 <−100
7
8
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
9
<−100 <−100 <−100 <−100 <−100 <−100 <−100
10
11
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
12
<−100 <−100 <−100 <−100 <−100 <−100
13
<−100 <−100 <−100 <−100 <−100 <−100
14
<−100 <−100 <−100 <−100 <−100 <−100
3.3 V Performance VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1900 MHz, fLO = 1697 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. Table 5. M 0
N
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
−42.9 −64.4 <−100
1 −15.3 0.0 −67.3 <−100 <−100
2 −27.3 −58.3 −56.6 −95.5 <−100
3 −65.5 −52.2 −73.6 −60.4 <−100 <−100
4 −78.0 −75.7 <−100 −97.0 <−100 <−100
5
<−100 <−100 <−100 <−100 <−100 <−100
6
<−100 <−100 <−100 <−100 <−100 <−100
7
8
<−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100 <−100
Rev. 0 | Page 5 of 24
9
<−100 <−100 <−100 <−100 <−100 <−100 <−100
10
11
<−100 <−100 <−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100 <−100
12
<−100 <−100 <−100 <−100 <−100 <−100
13
<−100 <−100 <−100 <−100 <−100 <−100
14
<−100 <−100 <−100 <−100 <−100 <−100
ADL5355 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage, VS RF Input Level LO Input Level IFOP, IFON Bias Voltage VGS0, VGS1, LOSW, PWDN Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, 60 sec)
Rating 5.5 V 20 dBm 13 dBm 6.0 V 5.5 V 1.2 W 25°C/W 150°C −40°C to +85°C −65°C to +150°C 260°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 24
ADL5355
20 19 18 17 16
IFGM IFOP IFON PWDN LEXT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1 2 3 4 5
PIN 1 INDICATOR
ADL5355 TOP VIEW (Not to Scale)
15 LOI2 14 VPSW 13 VGS1 12 VGS0 11 LOI1
NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD. MUST BE SOLDERED TO GROUND.
08080-002
VLO3 6 LGM3 7 VLO2 8 LOSW 9 NC 10
VPIF RFIN RFCT COMM COMM
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions Pin No. 1 2 3 4, 5 6, 8 7 9 10 11, 15 12, 13 14 16 17 18, 19 20
Mnemonic VPIF RFIN RFCT COMM VLO3, VLO2 LGM3 LOSW NC LOI1, LOI2 VGS0, VGS1 VPSW LEXT PWDN IFON, IFOP IFGM EPAD (EP)
Description Positive Supply Voltage for IF Amplifier. RF Input. Must be ac-coupled. RF Balun Center Tap (AC Ground). Device Common (DC Ground). Positive Supply Voltages for LO Amplifier. LO Amplifier Bias Control. LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V. No Connect. LO Inputs. Must be ac-coupled. Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting. Positive Supply Voltage for LO Switch. IF Return. This pin must be grounded. Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode. Differential IF Outputs (Open Collectors). Each requires an external dc bias. IF Amplifier Bias Control. Exposed pad. Must be soldered to ground.
Rev. 0 | Page 7 of 24
ADL5355 TYPICAL PERFORMANCE CHARACTERISTICS 5 V PERFORMANCE VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. 70 240
TA = –40°C
220
TA = +85°C
160
TA = +85°C 40 30
140
20
120
10
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
2.20
0 1.70
1.75
15
18
14
16
13
14
12
INPUT P1dB (dBm)
20
12 TA = –40°C
TA = +25°C
10 8 6
1.95
2.00
TA = +25°C
TA = –40°C
6
1.90
TA = +85°C
9
2
1.85
2.20
10
7
1.80
2.15
11
4
1.75
2.10
8
TA = +85°C
0 1.70
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
Figure 6. Input IP2 vs. RF Frequency
2.05
2.10
2.15
2.20
RF FREQUENCY (GHz)
5 1.70
08080-011
CONVERSION GAIN (dB)
Figure 3. Supply Current vs. RF Frequency
1.80
1.75
Figure 4. Power Conversion Gain vs. RF Frequency
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
2.20
2.15
2.20
08080-023
100 1.70
08080-015
INPUT IP2 (dBm)
180
50
TA = +25°C
TA = –40°C
200
08080-007
SUPPLY CURRENT (mA)
TA = +25°C
60
Figure 7. Input P1dB vs. RF Frequency
35
20 TA = –40°C
TA = +25°C
18
30
SSB NOISE FIGURE (dB)
16
TA = +85°C
20 15 10
14 TA = +85°C
12
TA = +25°C
10 8 6
TA = –40°C
4 5
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
2.20
0 1.70
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
Figure 8. SSB Noise Figure vs. RF Frequency
Figure 5. Input IP3 vs. RF Frequency
Rev. 0 | Page 8 of 24
08080-033
0 1.70
2 08080-019
INPUT IP3 (dBm)
25
ADL5355 250
60 VPOS = 5.25V
55
VPOS = 5.25V
VPOS = 5.0V 50 VPOS = 4.75V
45
VPOS = 4.75V
INPUT IP2 (dBm)
SUPPLY CURRENT (mA)
200
150
100
VPOS = 5.0V
40 35 30 25 20
50
0
20 40 TEMPERATURE (°C)
60
80
10 –40
08080-008
–20
20 40 TEMPERATURE (°C)
60
80
12
12 VPOS = 4.75V VPOS = 5.0V VPOS = 5.25V
VPOS = 5.25V 10 VPOS = 4.75V
10
INPUT P1dB (dBm)
9 8
VPOS = 5.0V
8
6
4
7 2
6
–20
0
20 40 TEMPERATURE (°C)
60
80
0 –40
08080-012
5 –40
Figure 10. Power Conversion Gain vs. Temperature
–20
0
20 40 TEMPERATURE (°C)
60
80
08080-024
CONVERSION GAIN (dB)
0
Figure 12. Input IP2 vs. Temperature
Figure 9. Supply Current vs. Temperature
11
–20
08080-016
15
0 –40
Figure 13. Input P1dB vs. Temperature 12
35 VPOS = 5.25V 30
SSB NOISE FIGURE (dB)
VPOS = 4.75V VPOS = 5.0V
20 15 10
VPOS = 5.25V VPOS = 5.0V
9 VPOS = 4.75V 8
–20
0
20 40 TEMPERATURE (°C)
60
80
6 –40
–20
0
20 40 TEMPERATURE (°C)
60
Figure 14. SSB Noise Figure vs. Temperature
Figure 11. Input IP3 vs. Temperature
Rev. 0 | Page 9 of 24
80
08080-034
0 –40
10
7
5
08080-020
INPUT IP3 (dBm)
25
11
ADL5355 230
70
220
60
210
50 INPUT IP2 (dBm)
200 TA = +25°C
TA = –40°C 190 180
TA = +85°C
30 20
170
80
130
180 230 280 330 IF FREQUENCY (MHz)
380
430
0
08080-006
30
30
80
Figure 15. Supply Current vs. IF Frequency 12
430
TA = +85°C
TA = +25°C
TA = –40°C INPUT P1dB (dBm)
8 TA = +85°C
6
4
TA = +25°C
8
6
4
2
80
130
180
230
280
330
380
430
IF FREQUENCY (MHz)
0
08080-009
0 30
30
80
130
180 230 280 330 IF FREQUENCY (MHz)
380
430
08080-021
CONVERSION GAIN (dB)
380
10
TA = –40°C
2
Figure 19. Input P1dB vs. IF Frequency
Figure 16. Power Conversion Gain vs. IF Frequency 15
40 TA = –40°C
35
14 TA = +25°C
13 SSB NOISE FIGURE (dB)
30 25 TA = +85°C 20 15 10
12 11 10 9 8 7
5
6
0 30
80
130
180 230 280 330 IF FREQUENCY (MHz)
380
430
5 30
08080-017
INPUT IP3 (dBm)
180 230 280 330 IF FREQUENCY (MHz)
Figure 18. Input IP2 vs. IF Frequency
12
10
130
08080-013
10
160 150
TA = +85°C 40
Figure 17. Input IP3 vs. IF Frequency
80
130
180 230 280 330 IF FREQUENCY (MHz)
380
Figure 20. SSB Noise Figure vs. IF Frequency
Rev. 0 | Page 10 of 24
430
08080-035
SUPPLY CURRENT (mA)
TA = –40°C TA = +25°C
ADL5355 10 14
TA = +25°C
TA = –40°C
9
TA = +85°C
7
INPUT P1dB (dBm)
CONVERSION GAIN (dB)
TA = +85°C
12
8
6 5 4 3
10 TA = +25°C
TA = –40°C
8 6 4
2 2 0 –4
–2
0
2
4
6
8
08080-010
0 –6
10
LO POWER (dBm)
–6
–4
Figure 21. Power Conversion Gain vs. LO Power
–2
0 2 4 LO POWER (dBm)
6
8
10
2.15
2.20
2.15
2.20
08080-022
1
Figure 24. Input P1dB vs. LO Power
35
–50 TA = –40°C
30
TA = +25°C
–55
TA = +85°C
IF/2 SPURIOUS (dBc)
INPUT IP3 (dBm)
25 20 15 10
–60
–65
TA = –40°C
TA = +25°C
–70
5
–6
–4
–2
0 2 4 LO POWER (dBm)
6
8
10
–75 1.70
08080-018
0
Figure 22. Input IP3 vs. LO Power
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
–50
60
–55
TA = +25°C
IF/3 SPURIOUS (dBc)
TA = –40°C
55 50
TA = +85°C
40
–60
–65 TA = –40°C
–70
TA = +25°C
–75
35
–4
–2
0 2 4 LO POWER (dBm)
6
8
10
–80 1.70
Figure 23. Input IP2 vs. LO Power
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
Figure 26. IF/3 Spurious vs. RF Frequency
Rev. 0 | Page 11 of 24
08080-027
TA = +85°C
30 –6
08080-014
INPUT IP2 (dBm)
1.80
Figure 25. IF/2 Spurious vs. RF Frequency
65
45
1.75
08080-025
TA = +85°C
ADL5355 100
500
10
400
8
300
6
200
4
100
2
70 60 50 40 30 20
CAPACITANCE (pF)
80
RESISTANCE (Ω)
DISTRIBUTION PERCENTAGE (%)
90
10 7.5
8.0
8.5
9.0
9.5
10.0
CONVERSION GAIN (dB)
0
0 30
80
130
180
230
280
330
380
08080-043
7.0
08080-046
0
430
IF FREQUENCY (MHz)
Figure 27. Conversion Gain Distribution
Figure 30. IF Port Return Loss 0
100
5
80
RF RETURN LOSS (dB)
DISTRIBUTION PERCENTAGE (%)
90
70 60 50 40 30 20
10
15
20
25
24
26
28
30
32
30 1.70
08080-047
0 22
34
INPUT IP3 (dBm)
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
2.20
08080-036
10
Figure 31. RF Port Return Loss, Fixed IF
Figure 28. Input IP3 Distribution 0
100
5
LO RETURN LOSS (dB)
80 70 60 50 40 30 20
10 SELECTED 15
20 UNSELECTED 25
0 8
9
10
11
12
INPUT P1dB (dBm)
13
14
30 1.50
1.55
1.60
1.65 1.70 1.75 1.80 1.85 LO FREQUENCY (GHz)
1.90
1.95
Figure 32. LO Return Loss, Selected and Unselected
Figure 29. Input P1dB Distribution
Rev. 0 | Page 12 of 24
2.00
08080-037
10 08080-048
DISTRIBUTION PERCENTAGE (%)
90
ADL5355 70
0 –5
60
LO-TO-RF LEAKAGE (dBm)
LO SWITCH ISOLATION (dB)
65
TA = +25°C
TA = –40°C 55 TA = +85°C 50
–10 –15 –20 –25 –30
TA = +25°C
TA = +85°C
–35
45
–40
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
LO FREQUENCY (GHz)
08080-041
1.55
–45 1.50
1.55
1.60
1.65 1.70 1.75 1.80 1.85 LO FREQUENCY (GHz)
1.90
1.95
2.00
08080-030
TA = –40°C 40 1.50
Figure 36. LO-to-RF Leakage vs. LO Frequency
Figure 33. LO Switch Isolation vs. LO Frequency 0
0 –5 –10 2LO LEAKAGE (dBm)
RF-TO-IF ISOLATION (dBc)
–10
–20 TA = +25°C –30
TA = +85°C
–40 TA = –40°C
–15 –20
2LO TO IF
–25 2LO TO RF
–30
–50
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
2.20
–40 1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
1.95
2.00
08080-026
1.75
08080-032
–60 1.70
1.95
2.00
08080-028
–35
LO FREQUENCY (GHz)
Figure 37. 2LO Leakage vs. LO Frequency
Figure 34. RF-to-IF Isolation vs. RF Frequency 0
0
3LO LEAKAGE (dBm)
TA = –40°C –10 TA = +25°C –15
TA = +85°C
–20 –30 3LO TO RF
–40 –50
–20
3LO TO IF
–60
–25 1.50
1.55
1.60
1.65 1.70 1.75 1.80 1.85 LO FREQUENCY (GHz)
1.90
1.95
2.00
08080-029
LO-TO-IF LEAKAGE (dBm)
–10 –5
–70 1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.90
LO FREQUENCY (GHz)
Figure 38. 3LO Leakage vs. LO Frequency
Figure 35. LO-to-IF Leakage vs. LO Frequency
Rev. 0 | Page 13 of 24
ADL5355 14
8
13 CONVERSION GAIN
12
6
11
5
10 9
4 SSB NOISE FIGURE
8
3
7
VGS = 00 VGS = 01 VGS = 10 VGS = 11
1 0 1.70
1.75
1.80
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
15
10
5
6
5 2.20
2.15
20
0 –30
30
18
28
16
26
–20
–15 –10 –5 BLOCKER POWER (dBm)
0
5
10
Figure 42. SSB Noise Figure vs.10 MHz Offset Blocker Level
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency 20
–25
08080-031
2
08080-039
7
25 SSB NOISE FIGURE (dB)
9
30
SSB NOISE FIGURE (dB)
15
CONVERSION GAIN (dB)
10
160 150
24
12
22
10
1.85 1.90 1.95 2.00 2.05 RF FREQUENCY (GHz)
2.10
2.15
16 2.20
60 600
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
20
10 SSB NOISE FIGURE
15
9 CONVERSION GAIN 8
10
7
5
6
0 1.0
1.2
1.4
1.6
1.8
LO BIAS RESISTOR VALUE (kΩ)
INPUT IP3 (dBm)
25
11
1000
1200
1400
1600
1800
Figure 43. LO and IF Supply Current vs. IF and LO Bias Resistor Value 30
INPUT IP3
800
BIAS RESISTOR VALUE (Ω)
08080-044
CONVERSION GAIN AND SSB NOISE FIGURE (dB)
R14 IF SET RESISTOR
70
12
0.8
90
18
Figure 40. Input IP3 and Input P1dB vs. RF Frequency
0.6
R9 LO SET RESISTOR
100
08080-040
1.80
110
80
VGS = 00 VGS = 01 VGS = 10 VGS = 11 1.75
120
12
30 INPUT IP3
11
25
10
20 SSB NOISE FIGURE
9
15 CONVERSION GAIN
8
10
7
5
6 0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0 1.5
IF BIAS RESISTOR VALUE (kΩ)
Figure 44. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias Resistor Value
Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias Resistor Value
Rev. 0 | Page 14 of 24
INPUT IP3 (dBm)
6 1.70
20
INPUT P1dB
130
08080-045
8
SUPPLY CURRENT (mA)
14
INPUT IP3 (dBm)
INPUT IP3
08080-038
INPUT P1dB (dBm)
140
ADL5355 3.3 V PERFORMANCE VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 1950 MHz, fLO = 1750 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless otherwise noted. 150
70
145
TA = +25°C
60
TA = –40°C
135
50
TA = –40°C
INPUT IP2 (dBm)
SUPPLY CURRENT (mA)
140
130 TA = +25°C
125 120
TA = +85°C
115
TA = +85°C 40 30 20
110
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
RF FREQUENCY (GHz)
0 1.70
08080-053
100 1.70
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.15
2.20
RF FREQUENCY (GHz)
Figure 45. Supply Current vs. RF Frequency at 3.3 V
Figure 48. Input IP2 vs. RF Frequency at 3.3 V
12
14 TA = –40°C
TA = +25°C
10
12 10
8
INPUT P1dB (dBm)
TA = +85°C
6
4
TA = +85°C
TA = +25°C
8 6
TA = –40°C 4
2
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
RF FREQUENCY (GHz)
0 1.70
08080-049
0 1.70
2
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
RF FREQUENCY (GHz)
Figure 46. Power Conversion Gain vs. RF Frequency at 3.3 V
08080-052
CONVERSION GAIN (dB)
1.75
08080-050
10
105
Figure 49. Input P1dB vs. RF Frequency at 3.3 V
30
14 TA = –40°C
12 SSB NOISE FIGURE (dB)
TA = +25°C
20 TA = +85°C 15
10
5
TA = +25°C 8 TA = –40°C
6
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
RF FREQUENCY (GHz)
2.15
2.20
Figure 47. Input IP3 vs. RF Frequency at 3.3 V
2 1.70
1.75
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
RF FREQUENCY (GHz)
Figure 50. SSB Noise Figure vs. RF Frequency at 3.3 V
Rev. 0 | Page 15 of 24
2.20
08080-054
0 1.70
TA = +85°C 10
4
08080-051
INPUT IP3 (dBm)
25
ADL5355 CIRCUIT DESCRIPTION RF SUBSYSTEM
The ADL5355 consists of two primary components: the radio frequency (RF) subsystem and the local oscillator (LO) subsystem. The combination of design, process, and packaging technology allows the functions of these subsystems to be integrated into a single die, using mature packaging and interconnection technologies to provide a high performance, low cost design with excellent electrical, mechanical, and thermal properties. In addition, the need for external components is minimized, optimizing cost and size.
The single-ended, 50 Ω RF input is internally transformed to a balanced signal using a low loss (<1 dB) unbalanced-to-balanced (balun) transformer. This transformer is made possible by an extremely low loss metal stack, which provides both excellent balance and dc isolation for the RF port. Although the port can be dc connected, it is recommended that a blocking capacitor be used to avoid running excessive dc current through the part. The RF balun can easily support an RF input frequency range of 1200 MHz to 2500 MHz.
The RF subsystem consists of an integrated, low loss RF balun, passive MOSFET mixer, sum termination network, and IF amplifier.
The resulting balanced RF signal is applied to a passive mixer that commutates the RF input with the output of the LO subsystem. The passive mixer is essentially a balanced, low loss switch that adds minimum noise to the frequency translation. The only noise contribution from the mixer is due to the resistive loss of the switches, which is in the order of a few ohms.
The LO subsystem consists of an SPDT-terminated FET switch and a three-stage limiting LO amplifier. The purpose of the LO subsystem is to provide a large, fixed amplitude, balanced signal to drive the mixer independent of the level of the LO input. A block diagram of the device is shown in Figure 51. IFGM
IFOP
IFON
PWDN
LEXT
20
19
18
17
16
As the mixer is inherently broadband and bidirectional, it is necessary to properly terminate all the idler (M × N product) frequencies generated by the mixing process. Terminating the mixer avoids the generation of unwanted intermodulation products and reduces the level of unwanted signals at the input of the IF amplifier, where high peak signal levels can compromise the compression and intermodulation performance of the system. This termination is accomplished by the addition of a sum network between the IF amplifier and the mixer and also in the feedback elements in the IF amplifier.
ADL5355 VPIF 1
15 LOI2
RFIN 2
14 VPSW
RFCT 3
13 VGS1
BIAS GENERATOR 12 VGS0
COMM 5
11 LOI1 6
7
8
9
10
VLO3
LGM3
VLO2
LOSW
NC
NC = NO CONNECT
Figure 51. Simplified Schematic
08080-001
COMM 4
The IF amplifier is a balanced feedback design that simultaneously provides the desired gain, noise figure, and input impedance that is required to achieve the overall performance. The balanced opencollector output of the IF amplifier, with impedance modified by the feedback within the amplifier, permits the output to be connected directly to a high impedance filter, differential amplifier, or an analog-to-digital input while providing optimum secondorder intermodulation suppression. The differential output impedance of the IF amplifier is approximately 200 Ω. If operation in a 50 Ω system is desired, the output can be transformed to 50 Ω by using a 4:1 transformer. The intermodulation performance of the design is generally limited by the IF amplifier. The IP3 performance can be optimized by adjusting the IF current with an external resistor. Figure 41, Figure 43, and Figure 44 illustrate how various IF and LO bias resistors affect the performance with a 5 V supply. Additionally, dc current can be saved by increasing either or both resistors. It is permissible to reduce the dc supply voltage to as low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power dissipation may result.)
Rev. 0 | Page 16 of 24
ADL5355 LO SUBSYSTEM The LO amplifier is designed to provide a large signal level to the mixer to obtain optimum intermodulation performance. The resulting amplifier provides extremely high performance centered on an operating frequency of 1700 MHz. The best operation is achieved with either low-side LO injection for RF signals in the 1700 MHz to 2500 MHz range or high-side injection for RF signals in the 1200 MHz to 1700 MHz range. Operation outside these ranges is permissible, and conversion gain is extremely wideband, easily spanning 1200 MHz to 2500 MHz, but intermodulation is optimal over the aforementioned ranges. The ADL5355 has two LO inputs permitting multiple synthesizers to be rapidly switched with extremely short switching times (<40 ns) for frequency agile applications. The two inputs are applied to a high isolation SPDT switch that provides a constant input impedance, regardless of whether the port is selected, to avoid pulling the LO sources. This multiple section switch also ensures high isolation to the off input, minimizing any leakage from the unwanted LO input that may result in undesired IF responses. The single-ended LO input is converted to a fixed amplitude differential signal using a multistage, limiting LO amplifier. This results in consistent performance over a range of LO input power. Optimum performance is achieved from −6 dBm to +10 dBm, but the circuit continues to function at considerably lower levels of LO input power.
The performance of this amplifier is critical in achieving a high intercept passive mixer without degrading the noise floor of the system. This is a critical requirement in an interferer rich environment, such as cellular infrastructure, where blocking interferers can limit mixer performance. The bandwidth of the intermodulation performance is somewhat influenced by the current in the LO amplifier chain. For dc current sensitive applications, it is permissible to reduce the current in the LO amplifier by raising the value of the external bias control resistor. For dc current critical applications, the LO chain can operate with a supply voltage as low as 3.3 V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5355 has a power-down mode that permits the dc current to drop to <200 µA. All of the logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0.4 V and a Logic 1 input level that exceeds 1.4 V. All logic inputs are high impedance up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection circuitry permits operation up to 5.5 V, although a small bias current is drawn. All pins, including the RF pins, are ESD protected and have been tested up to a level of 1500 V HBM and 500 V CDM.
Rev. 0 | Page 17 of 24
ADL5355 APPLICATIONS INFORMATION BASIC CONNECTIONS
BIAS RESISTOR SELECTION
The ADL5355 mixer is designed to downconvert radio frequencies (RF) primarily between 1200 MHz and 2500 MHz to lower intermediate frequencies (IF) between 30 MHz and 450 MHz. Figure 52 depicts the basic connections of the mixer. It is recommended to ac-couple RF and LO input ports to prevent non-zero dc voltages from damaging the RF balun or LO input circuit. The RFIN capacitor value of 3 pF is recommended to provide the optimized RF input return loss for the desired frequency band.
Two external resistors, RBIAS IF and RBIAS LO, are used to adjust the bias current of the integrated amplifiers at the IF and LO terminals. It is necessary to have a sufficient amount of current to bias both the internal IF and LO amplifiers to optimize dc current vs. optimum IIP3 performance. Figure 41, Figure 43, and Figure 44 provide the reference for the bias resistor selection when lower power consumption is considered at the expense of conversion gain and IP3 performance.
IF PORT
The ADL5355 features two logic control pins, VGS0 (Pin 12) and VGS1 (Pin 13), that allow programmability for internal gate-tosource voltages for optimizing mixer performance over desired frequency bands. The evaluation board defaults both VGS0 and VGS1 to ground. Power conversion gain, IIP3, NF, and IP1dB can be optimized, as is shown in Figure 39 and Figure 40.
The mixer differential IF interface requires pull-up choke inductors to bias the open-collector outputs and to set the output match. The shunting impedance of the choke inductors used to couple dc current into the IF amplifier should be selected to provide the desired output return loss.
MIXER VGS CONTROL DAC
The real part of the output impedance is approximately 200 Ω, as seen in Figure 30, which matches many commonly used SAW filters without the need for a transformer. This results in a voltage conversion gain that is approximately 6 dB higher than the power conversion gain, as shown in Table 2. When a 50 Ω output impedance is needed, use a 4:1 impedance transformer, as shown in Figure 52.
Rev. 0 | Page 18 of 24
ADL5355 +5V
100pF 150pF 470nH
470nH 4:1
RBIAS IF +5V
20
IF OUT
10kΩ 19
18
17
16
10pF
4.7µF
ADL5355 +5V
22pF
1
15
2
14
LO2 IN
3pF RF IN
+5V 10pF
3
13
0.1µF
BIAS GENERATOR 4
12
5
11
22pF
6
7
8
9
RBIAS LO
LO1 IN
10
10kΩ
+5V 10pF
10pF
Figure 52. Typical Application Circuit
Rev. 0 | Page 19 of 24
08080-005
10pF
ADL5355 EVALUATION BOARD An evaluation board is available for the family of double balanced mixers. The standard evaluation board schematic is shown in Figure 53. The evaluation board is fabricated using Rogers® RO3003 material. Table 8 describes the various configuration options of the evaluation board. Evaluation board layout is shown in Figure 54 to Figure 57.
L5 470nH
T1
IF1-OUT
C18 100pF C19 100pF
L4 470nH R24 0Ω
R25 0Ω
PWR_UP
R14 910Ω
C21 10pF
RF-IN C1 3pF C4 10pF
LEXT
PWDN
IFON
IFOP
LO2_IN LOI2
RFIN
VPSW
ADL5355
RFCT
VGS0
COMM
LOI1
VPOS
C20 10pF C22 1nF
VGS1
COMM
R22 10kΩ R23 15kΩ
VGS1
LO1_IN
NC
LOSW
VLO2
VGS0
VLO3
C5 0.01µF
C12 22pF
VPIF
LGM3
C2 10µF
R21 10kΩ
L3 0Ω
IFGM
VPOS
R1 0Ω
C17 150pF
C10 22nF
LOSEL
VPOS C6 10pF
R9 1.1kΩ
VPOS C8 10pF
Figure 53. Evaluation Board Schematic
Rev. 0 | Page 20 of 24
R4 10kΩ 08080-042
VPOS
ADL5355 Table 8. Evaluation Board Configuration Components C2, C6, C8, C18, C19, C20, C21 C1, C4, C5 T1, C17, L4, L5, R1, R24, R25
C10, C12, R4
R21
C22, L3, R9, R14, R22, R23, VGS0, VGS1
Description Power Supply Decoupling. Nominal supply decoupling consists of a 10 µF capacitor to ground in parallel with a 10 pF capacitor to ground positioned as close to the device as possible. RF Input Interface. The input channels are ac-coupled through C1. C4 and C5 provide bypassing for the center taps of the RF input baluns. IF Output Interface. The open-collector IF output interfaces are biased through pull-up choke inductors L4 and L5. T1is a 4:1 impedance transformer used to provide a single-ended IF output interface, with C17 providing center-tap bypassing. Remove R1 for balanced output operation. LO Interface. C10 and C12 provide ac coupling for the LO1_IN and LO2_IN local oscillator inputs. LOSEL selects the appropriate LO input for both mixer cores. R4 provides a pull-down to ensure that LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN is enabled when LOSEL is pulled to logic high. PWDN Interface. R21 pulls the PWDN logic low and enables the device. The PWR_UP test point allows the PWDN interface to be exercised using the external logic generator. Grounding the PWDN pin for nominal operation is allowed. Using the PWDN pin when supply voltages exceed 3.3 V is not allowed. Bias Control. R22 and R23 form a voltage divider to provide 3 V for logic control, bypassed to ground through C22. VGS0 and VGS1 jumpers provide programmability at the VGS0 and VGS1 pins. It is recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. R14 sets the bias point for the internal IF amplifier.
Rev. 0 | Page 21 of 24
Default Conditions C2 = 10 µF (size 0603), C6, C8, C20, C21 = 10 pF (size 0402), C18, C19 = 100 pF (size 0402) C1 = 3 pF (size 0402), C4 = 10 pF (size 0402), C5 = 0.01 µF (size 0402) T1 = TC4-1W+ (Mini-Circuits), C17 = 150 pF (size 0402), L4, L5 = 470 nH (size 1008), R1, R24, R25 = 0 Ω (size 0402) C10, C12 = 22 pF (size 0402), R4 = 10 kΩ (size 0402)
R21 = 10 kΩ (size 0402)
C22 = 1 nF (size 0402), L3 = 0 Ω (size 0603), R9 = 1.1 kΩ (size 0402), R14 = 910 Ω (size 0402), R22 = 10 kΩ (size 0402), R23 = 15 kΩ (size 0402), VGS0 = VGS1 = 3-pin shunt
08080-055
08080-057
ADL5355
Figure 56. Evaluation Board Power Plane, Internal Layer 2
Figure 55. Evaluation Board Ground Plane, Internal Layer 1
08080-058
08080-056
Figure 54. Evaluation Board Top Layer
Figure 57. Evaluation Board Bottom Layer
Rev. 0 | Page 22 of 24
ADL5355 OUTLINE DIMENSIONS 0.60 MAX
5.00 BSC SQ 0.60 MAX
15
PIN 1 INDICATOR
20
16
1
PIN 1 INDICATOR
4.75 BSC SQ
0.65 BSC
3.20 3.10 SQ 3.00
EXPOSED PAD (BOTTOM VIEW) 5 10
0.90 0.85 0.80
12° MAX
SEATING PLANE
0.70 0.65 0.60
0.35 0.28 0.23
0.75 0.60 0.50
0.05 MAX 0.01 NOM COPLANARITY 0.05 0.20 REF
2.60 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
042209-B
TOP VIEW
6
11
Figure 58. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-20-5) Dimensions shown in millimeters
ORDERING GUIDE Model ADL5355ACPZ-R7 1 ADL5355ACPZ-WP1 ADL5355-EVALZ1 1
Temperature Range −40°C to +85°C −40°C to +85°C
Package Description 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
Package Option CP-20-5 CP-20-5
Ordering Quantity 1,500, 7” Tape and Reel 36, Waffle Pack 1
ADL5355 NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08080-0-7/09(0)
Rev. 0 | Page 24 of 24
