Transcript
Dual, Low Noise, Single-Supply Variable Gain Amplifier AD605 FUNCTIONAL BLOCK DIAGRAM
FEATURES VGN
VREF
GAIN CONTROL AND SCALING
PRECISION PASSIVE INPUT ATTENUATOR
FIXED GAIN AMPLIFIER +34.4dB OUT FBK
VOCM +IN –IN
DIFFERENTIAL ATTENUATOR 0 TO –48.4dB
AD605
00541-001
2 independent linear-in-dB channels Input noise at maximum gain: 1.8 nV/√Hz, 2.7 pA/√Hz Bandwidth: 40 MHz (−3 dB) Differential input Absolute gain range programmable −14 dB to +34 dB (FBK shorted to OUT) through 0 dB to 48 dB (FBK open) Variable gain scaling: 20 dB/V through 40 dB/V Stable gain with temperature and supply variations Single-ended unipolar gain control Output common mode independently set Power shutdown at lower end of gain control Single 5 V supply Low power: 90 mW/channel Drives ADCs directly
Figure 1.
APPLICATIONS Ultrasound and sonar time-gain controls High performance AGC systems Signal measurement
GENERAL DESCRIPTION The AD605 is a low noise, accurate, dual-channel, linear-in-dB variable gain amplifier (VGA), optimized for any application requiring high performance, wide bandwidth variable gain control. Operating from a single 5 V supply, the AD605 provides differential inputs and unipolar gain control for ease of use. Added flexibility is achieved with a user-determined gain range and an external reference input that provide user-determined gain scaling (dB/V).
Each independent channel of the AD605 provides a gain range of 48 dB that can be optimized for the application. Gain ranges between −14 dB to +34 dB and 0 dB to +48 dB can be selected by a single resistor between Pin FBK and Pin OUT. The lower and upper gain ranges are determined by shorting Pin FBK to Pin OUT or leaving Pin FBK unconnected, respectively. The two channels of the AD605 can be cascaded to provide 96 dB of very accurate gain range in a monolithic package.
The high performance linear-in-dB response of the AD605 is achieved with the differential input, single-supply, exponential amplifier (DSX-AMP) architecture. Each of the DSX-AMPs comprises a variable attenuator of 0 dB to −48.4 dB followed by a high speed, fixed-gain amplifier. The attenuator is based on a 7-stage R-1.5R ladder network. The attenuation between tap points is 6.908 dB, and 48.360 dB for the entire ladder network. The DSX-AMP architecture results in 1.8 nV/√Hz input noise spectral density and accepts a ±2.0 V input signal when VOCM is biased at VP/2.
The gain control interface provides an input resistance of approximately 2 MΩ and scale factors from 20 dB/V to 30 dB/V for a VREF input voltage of 2.5 V to 1.67 V, respectively. Note that scale factors up to 40 dB/V are achievable with reduced accuracy for scales above 30 dB/V. The gain scales linearly in dB with control voltages (VGN) of 0.4 V to 2.4 V for the 20 dB/V scale and 0.20 V to 1.20 V for the 40 dB/V scale. When VGN is <50 mV, the amplifier is powered down to draw 1.9 mA. Under normal operation, the quiescent supply current of each amplifier channel is only 18 mA. The AD605 is available in a 16-lead PDIP and a 16-lead SOIC_N package and is guaranteed for operation over the −40°C to +85°C temperature range.
Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.
AD605 TABLE OF CONTENTS Features .............................................................................................. 1
Gain Control Interface............................................................... 14
Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1
Fixed Gain Amplifier and Interpolator Circuits—Applying an Active Feedback Amplifier ........................................................ 15
General Description ......................................................................... 1
Applications Information .............................................................. 16
Revision History ............................................................................... 2
Connecting Two Amplifiers to Double the Gain Range ....... 16
Specifications..................................................................................... 3
Evaluation Board ............................................................................ 18
Absolute Maximum Ratings............................................................ 5
Input Connections ..................................................................... 18
ESD Caution .................................................................................. 5
Adjusting Gain, Common-Mode, and Reference Levels ...... 18
Pin Configuration and Function Descriptions ............................. 6
Output Connections .................................................................. 18
Typical Performance Characteristics (per Channel) ................... 7
Outline Dimensions ....................................................................... 21
Theory of Operation ...................................................................... 13
Ordering Guide .......................................................................... 22
Differential Ladder (Attenuator) .............................................. 14 AC Coupling ............................................................................... 14
REVISION HISTORY 6/08—Rev. E to Rev. F Added Evaluation Board Section ................................................. 18 Added Figure 42 and Table 4......................................................... 18 Added Figure 43 and Figure 44..................................................... 19 Added Figure 45 to Figure 50........................................................ 20
7/04—Rev. B to Rev. C Edits to General Description ...........................................................1 Edits to Specifications .......................................................................2 Edits to Ordering Guide ...................................................................3 Change to TPC 22 .............................................................................6 Updated Outline Dimensions ....................................................... 12
5/07—Rev. D to Rev. E Changes to Table 1 ............................................................................ 5 Changes to Fixed Gain Amplifier and Interpolator Circuits— Applying an Active Feedback Amplifier Section........................ 15 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 1/06—Rev. C to Rev. D Updated Format .................................................................. Universal Changes to Table 2 ............................................................................ 5 Changes to Differential Ladder (Attenuator) Section ............... 14 Updated the Outline Dimensions ................................................ 18 Changes to the Ordering Guide.................................................... 19
Rev. F | Page 2 of 24
AD605 SPECIFICATIONS Each channel @ TA = 25°C, VS = 5 V, RS = 50 Ω, RL = 500 Ω, CL = 5 pF, VREF = 2.5 V (scaling = 20 dB/V), −14 dB to +34 dB gain range, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Input Resistance Input Capacitance Peak Input Voltage Input Voltage Noise Input Current Noise Noise Figure Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS −3 dB Bandwidth Slew Rate Output Signal Range Output Impedance Output Short-Circuit Current Harmonic Distortion HD2 HD3 HD2 HD3 Two-Tone Intermodulation Distortion (IMD)
1 dB Compression Point Third-Order Intercept Channel-to-Channel Crosstalk
Group Delay Variation VOCM Input Resistance ACCURACY Absolute Gain Error −14 dB to −11 dB −11 dB to +29 dB +29 dB to +34 dB Gain Scaling Error Output Offset Voltage Output Offset Variation
Conditions
Min
At minimum gain VGN = 2.9 V VGN = 2.9 V RS = 50 Ω, f = 10 MHz, VGN = 2.9 V RS = 200 Ω, f = 10 MHz, VGN = 2.9 V f = 1 MHz, VGN = 2.65 V Constant with gain VGN = 1.5 V, output = 1 V step RL ≥ 500 Ω f = 10 MHz VGN = 1 V, VOUT = 1 V p-p f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz RS = 0 Ω, VGN = 2.9 V, VOUT = 1 V p-p f = 1 MHz f = 10 MHz f = 10 MHz, VGN = 2.9 V, output referred f = 10 MHz, VGN = 2.9 V, VOUT = 1 V p-p, input referred Ch1: VGN = 2.65 V, inputs shorted, Ch2: VGN = 1.5 V (mid gain), f = 1 MHz, VOUT = 1 V p-p 1 MHz < f < 10 MHz, full gain range
0.25 V < VGN < 0.40 V 0.40 V < VGN < 2.40 V 2.40 V < VGN < 2.65 V 0.4 V < VGN < 2.4 V VREF = 2.500 V, VOCM = 2.500 V VREF = 2.500 V, VOCM = 2.500 V
−1.2 −1.0 −3.5 −30
Rev. F | Page 3 of 24
AD605A Typ
Max
Min
AD605B Typ
Max
Unit
175 ± 40 3.0 2.5 ± 2.5 1.8 2.7 8.4 12 −20
175 ± 40 3.0 2.5 ± 2.5 1.8 2.7 8.4 12 −20
Ω pF V nV/√Hz pA/√Hz dB dB dB
40 170 2.5 ± 1.5 2 ±40
40 170 2.5 ± 1.5 2 ±40
MHz V/μs V Ω mA
−64 −68 −51 −53
−64 −68 −51 −53
dBc dBc dBc dBc
−72 −60 15 −1
−72 −60 15 −1
dBc dBc dBm dBm
−70
−70
dB
±2.0 45
±2.0 45
ns kΩ
+1.0 ±0.3 −1.25 ±0.25 ±20 30
+3.0 +1.0 +1.2
–1.2 –1.0 –3.5
+30 57
–30
+0.75 ±0.2 −1.25 ±0.25 ±20 30
+3.0 +1.0 +1.2 +30 50
dB dB dB dB/V mV mV
AD605 Parameter GAIN CONTROL INTERFACE Gain Scaling Factor Gain Range Input Voltage (VGN) Range Input Bias Current Input Resistance Response Time POWER SUPPLY Supply Voltage Power Dissipation VREF Input Resistance Quiescent Supply Current Power-Down Power-Up Response Time Power-Down Response Time
Conditions
Min
VREF = 2.5 V, 0.4 V < VGN < 2.4 V VREF = 1.67 V FBK short to OUT FBK open 20 dB/V, VREF = 2.5 V
19
4.5
48 dB gain change
VPOS VPOS, VGN < 50 mV 48 dB gain, VOUT = 2 V p-p
Rev. F | Page 4 of 24
AD605A Typ
Max
Min
20 30 −14 to +34 0 to 48 0.1 to 2.9 −0.4 2 0.2
21
19
5.0 90 10 18 1.9 0.6 0.4
5.5
4.5
23 3.0
AD605B Typ
Max
Unit
20 30 −14 to +34 0 to 48 0.1 to 2.9 −0.4 2 0.2
21
dB/V dB/V dB dB V μA MΩ μs
5.0 90 10 18 1.9 0.6 0.4
5.5
V mW kΩ mA mA μs μs
23 3.0
AD605 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. Parameter Supply Voltage +VS Pin 12, Pin 13 (with Pin 4, Pin 5 = 0 V) Input Voltage Pin 1 to Pin 3, Pin 6 to Pin 9, Pin 16 Internal Power Dissipation 16-Lead PDIP 16-Lead SOIC_N Operating Temperature Range Storage Temperature Range Lead Temperature, Soldering 60 sec Thermal Resistance θJA 16-Lead PDIP 16-Lead SOIC_N
Rating 6.5 V VPOS, 0 V 1.4 W 1.2 W −40°C to +85°C −65°C to +150°C 300°C
ESD CAUTION
85°C/W 100°C/W
Rev. F | Page 5 of 24
AD605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGN1 1
16 VREF
–IN1 2
15 OUT1
+IN1 3 GND1 4
14 FBK1
AD605
+IN2 6
11 FBK2
–IN2 7
10 OUT2
VGN2 8
9 VOCM
00541-002
13 VPOS TOP VIEW GND2 5 (Not to Scale) 12 VPOS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Mnemonic VGN1 −IN1 +IN1 GND1 GND2 +IN2 −IN2 VGN2 VOCM OUT2 FBK2 VPOS VPOS FBK1 OUT1 VREF
Description CH1 Gain Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. CH1 Negative Input. CH1 Positive Input. Ground. Ground. CH2 Positive Input. CH2 Negative Input. CH2 Gain Control Input and Power-Down Pin. If grounded, device is off; otherwise, positive voltage increases gain. Input to This Pin Defines Common-Mode Voltage for OUT1 and OUT2. CH2 Output. Feedback Pin That Selects Gain Range of CH2. Positive Supply. Positive Supply. Feedback Pin That Selects Gain Range of CH1. CH1 Output. Input to This Pin Sets Gain Scaling for Both Channels: 2.5 V = 20 dB/V and 1.67 V = 30 dB/V.
Rev. F | Page 6 of 24
AD605 TYPICAL PERFORMANCE CHARACTERISTICS (PER CHANNEL) VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, RL = 500 Ω, CL = 5 pF, TA = 25°C, VSS = 5 V. 40.0
40
–40°C, +25°C, +85°C
GAIN SCALING (dBV)
35.0
20
GAIN (dB)
THEORETICAL
37.5
30
10
0
32.5 ACTUAL 30.0 27.5 25.0
–10
0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
20.0 1.25
2.9
00541-006
00541-003
–20
22.5
1.50
1.75
2.00
2.25
2.50
VREF (V)
Figure 3. Gain vs. VGN
Figure 6. Gain Scaling vs. VREF
50
3.0 2.5
40
2.0 1.5 FBK (OPEN)
GAIN ERROR (dB)
20 FBK (SHORT)
10 0
1.0
0 –0.5
+25°C +85°C
–1.0 –1.5
00541-004
–20 0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
00541-007
–2.0
–10
–2.5 –3.0 0.2
2.9
0.7
1.2
1.7
2.2
2.7
VGN (V)
Figure 4. Gain vs. VGN for Different Gain Ranges
Figure 7. Gain Error vs. VGN at Three Temperatures
40
2.0 1.5
30 30dB/V (VREF = 1.67V)
20
ACTUAL
1.0 GAIN ERROR (dB)
ACTUAL
20dB/V (VREF = 2.50V)
10
0
f = 1MHz 0.5 0 f = 5MHz –0.5
f = 10MHz
–1.0 –10
–20
–1.5
00541-005
GAIN (dB)
–40°C
0.5
0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
–2.0
2.9
00541-008
GAIN (dB)
30
0.2
0.7
1.2
1.7
2.2
VGN (V)
Figure 5. Gain vs. VGN for Different Gain Scalings
Figure 8. Gain Error vs. VGN at Three Frequencies
Rev. F | Page 7 of 24
2.7
AD605 2.0
60
VGN = 2.9V (FBK = OPEN) 1.5
40
VGN = 2.9V (FBK = SHORT) VGN = 1.5V (FBK = OPEN)
20
20dB/V VREF = 2.50V
0.5
GAIN (dB)
GAIN ERROR
1.0
0 30dB/V VREF = 1.67V
–0.5
VGN = 1.5V (FBK = SHORT) VGN = 0.1V (FBK = OPEN)
0
VGN = 0.1V (FBK = SHORT) –20
–1.0
VGN = 0.0V
00541-009
–2.0 0.2
0.7
1.2
1.7
2.2
00541-013
–40
–1.5
–60 100k
2.7
1M 10M FREQUENCY (Hz)
VGN (V)
Figure 12. AC Response for Three Values of VGN
Figure 9. Gain Error vs. VGN for Two Gain Scale Values
2.515
14
2.510
12
2.505
VOS (V)
16
10
2.495
6
2.490
4
2.485
2
2.480
–0.8
–0.6
–0.4
–0.2 0 0.2 DELTA GAIN (dB)
0.4
0.6
2.475
0.8
+25°C
+85°C
0
0.5
1.0
1.5
2.0
2.5
3.0
VGN (V)
Figure 10. Gain Match, VGN1 = VGN2 = 1.0 V
Figure 13. Output Offset vs. VGN at Three Temperatures
20 18
–40°C
2.500
8
0
VOCM = 2.50V
2.520
00541-010
PERCENTAGE
18
2.525 N = 50 ΔG(dB) = G(CH1) – G(CH2)
00541-014
20
100M
130
N = 50 ΔG(dB) = G(CH1) – G(CH2)
+85°C
125
16 120
NOISE (nV/ Hz)
+25°C
12 10 8
115 110 –40°C
105
6 100
4
–0.8
–0.6
–0.4
–0.2 0 0.2 DELTA GAIN (dB)
0.4
0.6
90 0
0.8
00541-015
2 0
95
00541-011
PERCENTAGE
14
0.5
1.0
1.5
2.0
2.5
3.0
VGN (V)
Figure 14. Output Referred Noise vs. VGN at Three Temperatures
Figure 11. Gain Match, VGN1 = VGN2 = 2.50 V
Rev. F | Page 8 of 24
AD605 1000
100 VGN = 2.9V
1 0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
10
1.0
RSOURCE ALONE
00541-019
NOISE (nV/ Hz)
10
00541-016
NOISE (nV/ Hz)
100
0.1 1
2.9
10
100
1k
RSOURCE (Ω)
Figure 18. Input Referred Noise vs. RSOURCE
Figure 15. Input Referred Noise vs. VGN 30
2.00
VGN = 2.9V
VGN = 2.9V 1.95 25
NOISE FIGURE (dB)
NOISE (nV/ Hz)
1.90 1.85 1.80 1.75
20
15
1.70 00541-017
1.60 –40 –30 –20 –10
0
10
20
30
40
50
60
70
80
00541-020
10
1.65
5 1
90
10
100
Figure 19. Noise Figure vs. RSOURCE
Figure 16. Input Referred Noise vs. Temperature 60
1.90 VGN = 2.9V
RS = 50Ω 50
NOISE FIGURE (dB)
1.80
1.75
1.70
40
30
20
1M FREQUENCY (Hz)
0 0.1
10M
Figure 17. Input Referred Noise vs. Frequency
00541-021
10
1.65 00541-018
NOISE (nV/ Hz)
1.85
1.60 100k
1k
RSOURCE (Ω)
TEMPERATURE (°C)
0.5
0.9
1.3 1.7 VGN (V)
2.1
Figure 20. Noise Figure vs. VGN
Rev. F | Page 9 of 24
2.5
2.9
AD605 15
–30 VOUT = 1V p-p VGN = 1.0V
10
–40
INPUT GENERATOR LIMIT = 21dBm
5
–45
PIN (dBm)
–50 HD3
–55
HD2
10M FREQUENCY (Hz)
FREQ = 10MHz FREQ = 1MHz
–15
00541-022
–65
1M
–5 –10
–60
–70 100k
0
–20 0.1
100M
Figure 21. Harmonic Distortion vs. Frequency
0.5
0.9
00541-025
HARMONIC DISTORTION (dBc)
–35
1.3 1.7 VGN (V)
2.1
2.5
2.9
Figure 24. 1 dB Compression vs. VGN
–35
35
–40
30
HD3 (10MHz)
25
HD2 (10MHz)
–55 –60
–75 0.5
HD3 (1MHz) 0.8
1.1
1.4
1.7 VGN (V)
2.0
2.3
2.6
–5 0.6
2.9
1.0
1.4
1.8 VGN (V)
2.2
2.6
3.0
Figure 25. Third-Order Intercept vs. VGN at 1 MHz and 10 MHz
–20
–40
10
0
Figure 22. Harmonic Distortion vs. VGN at 1 MHz and 10 MHz
–30
f = 10MHz 15
5
–65 –70
f = 1MHz 20
00541-026
–50
HD2 (1MHz)
INTERCEPT (dBm)
–45
00541-023
HARMONIC DISTORTION (dBc)
VOUT = 1V p-p
2V
f = 10MHz VOUT = 1V p-p VGN = 1.0V
VOUT = 2V p-p VGN = 1.5V
–400mV/DIV
–60 –70 –80 –90
–110 –120 9.92
9.96
10.00 10.02 FREQUENCY (MHz)
10.04
00541-027
TRIG'D
–100 00541-024
POUT (dBm)
–50
2V 253ns
Figure 23. Intermodulation Distortion
100ns/DIV
Figure 26. Large Signal Pulse Response
Rev. F | Page 10 of 24
1.253µs
AD605 –30 VOUT = 200mV p-p VGN = 1.5V
VGN1 = 1V VOUT1 = 1V p-p
40mV (DIV)
CROSSTALK (dB)
–40
VIN2 = GND
–50 VGN2 = 2.9V –60
–70
TRIG'D
VGN2 = 2.5V 00541-028
–80
–200 253ns
Figure 27. Small Signal Pulse Response
VGN2 = 0.1V
–90 100k
1.253µs
100ns/DIV
VGN2 = 2.0V 00541-031
200
1M 10M FREQUENCY (Hz)
100M
Figure 30. Crosstalk (CH1 to CH2) vs. Frequency for Four Values of VGN2 0 VIN = 0dBm
500mV 2.9V
–10 100
VGN = 2.9V
90
VGN (V)
CMRR (dB)
–20 VGN = 2.5V –30
–40
VGN = 2.0V VGN = 0.1V
10
500mV
200ns
00541-029
0.0V
–60 100k
00541-032
–50
0%
1M 10M FREQUENCY (Hz)
100M
Figure 31. CMRR vs. Frequency for Four Values of VGN
Figure 28. Power-Up/Power-Down Response
180 VGN = 2.9V
500mV 2.9V
175
100
VGN (V)
INPUT IMPEDANCE (Ω)
90
170 165 160 155 150
10 0%
100ns
00541-030
500mV
Figure 29. Gain Response
140 100k
00541-033
145
0.1V
1M 10M FREQUENCY (Hz)
Figure 32. Input Impedance vs. Frequency
Rev. F | Page 11 of 24
100M
AD605 25
16 +IS (AD605)
14
GROUP DELAY (ns)
15
10
5
0
10 20 30 40 50 TEMPERATURE (°C)
10
8
VGN = 0.1V
60
70
80
90
VGN = 2.9V 4 100k
1M 10M FREQUENCY (Hz)
Figure 34. Group Delay vs. Frequency
Figure 33. Supply Current (One Channel) vs. Temperature
Rev. F | Page 12 of 24
00541-035
0 –40 –30 –20 –10
12
6
+IS (VGN = 0)
00541-034
SUPPLY CURRENT (mA)
20
100M
AD605 THEORY OF OPERATION The AD605 is a dual-channel, low noise VGA. Figure 35 shows the simplified block diagram of one channel. Each channel consists of a single-supply X-AMP® (hereafter called DSX, differential single-supply X-AMP) comprising the following: • Precision passive attenuator (differential ladder) • Gain control block • VOCM buffer with supply splitting resistors R3 and R4 • Active feedback amplifier 1 (AFA) with gain setting resistors R1 and R2 The linear-in-dB gain response of the AD605 can generally be described by Equation 1. G (dB) = (Gain Scaling (dB/V)) × (Gain Control (V)) − (19 dB − (14 dB) × (FB)) (1) where: FB = 0, if FBK to OUT is shorted. FB = 1, if FBK to OUT is open. Each channel provides between −14 dB to +34.4 dB through 0 dB to +48.4 dB of gain, depending on the value of the resistance connected between Pin FBK and Pin OUT. The center 40 dB of gain is exactly linear-in-dB while the gain error increases at the top and bottom of the range. The gain is set by the gain control voltage (VGN). The VREF input establishes the gain scaling. The useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V, respectively. For example, if FBK to OUT is shorted and VREF is set to 2.50 V (to establish a gain scaling of 20 dB/V), the gain equation simplifies to G (dB) = (20 (dB/V)) × (VGN (V)) – 19 dB
The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control range of 0.1 V to 2.9 V. Maximum gain can be achieved at a VGN of 2.9 V. Because the two channels are identical, only Channel 1 is used to describe their operation. VREF and VOCM are the only inputs that are shared by the two channels, and because they are normally ac grounds, crosstalk between the two channels is minimized. For the highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy 20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode, the gain scaling is determined by the midpoint between +VCC and GND; therefore, care should be taken to control the supply voltage to 5 V. The input resistance looking into the VREF pin is 10 kΩ ± 20%. The AD605 is a single-supply circuit, and the VOCM pin is used to establish the dc level of the midpoint of this portion of the circuit. VOCM needs only an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 V, GND). However, if the dc level of the output is important to the user (see the Applications Information section of the AD9050 data sheet for an example), VOCM can be specifically set. The input resistance looking into the VOCM pin is 45 kΩ ± 20%. 1
To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The AD830 is a practical implementation of the idea.
(2)
VREF VGN
GAIN CONTROL
DIFFERENTIAL ATTENUATOR
EXT
+ G1 + Ao
–IN VPOS R3 200kΩ VOCM
+
C3
OUT
175Ω R2 20Ω
G2 +
3.36kΩ R1 820Ω
R4 200kΩ
EXT
Figure 35. Simplified Block Diagram of a Single Channel of the AD605
Rev. F | Page 13 of 24
FBK
00541-036
C2
DISTRIBUTED g m
175Ω
C1
+IN
AD605 +IN
R
–6.908dB
R
1.5R
–13.82dB
R
1.5R
R
–20.72dB 1.5R
R
–27.63dB 1.5R
R
–34.54dB 1.5R
–41.45dB
R
–48.36dB
1.5R
1.5R
175Ω
1.5R
175Ω
–IN
R
1.5R
R
1.5R
R
1.5R
R
1.5R
R
1.5R
R
1.5R
R
NOTE: R = 96Ω 1.5R = 144Ω
00541-037
MID
Figure 36. R-1.5R Dual Ladder Network
DIFFERENTIAL LADDER (ATTENUATOR)
AC COUPLING
The attenuator before the fixed gain amplifier is realized by a differential, 7-stage, R-1.5R resistive ladder network with an untrimmed input resistance of 175 Ω single ended or 350 Ω differentially. The signal applied at the input of the ladder network is attenuated by 6.908 dB per tap; therefore, the attenuation at the first tap is 6.908 dB, at the second, 13.816 dB, and so on all the way to the last tap where the attenuation is 48.356 dB (see Figure 36). A unique circuit technique is used to interpolate continuously between the tap points, thereby providing continuous attenuation from 0 dB to −48.36 dB. One can think of the ladder network together with the interpolation mechanism as a voltage-controlled potentiometer.
The DSX is a single-supply circuit; therefore, its inputs need to be ac-coupled to accommodate ground-based signals. External Capacitor C1 and Capacitor C2 in Figure 35 level-shift the input signal from ground to the dc value established by VOCM (nominal 2.5 V). C1 and C2, together with the 175 Ω looking into each of DSX inputs (+IN and −IN), act as high-pass filters with corner frequencies depending on the values chosen for C1 and C2. For example, if C1 and C2 are 0.1 μF, together with the 175 Ω input resistance of each side of the differential ladder of the DSX, a −3 dB high-pass corner at 9.1 kHz is formed.
Because the DSX is a single-supply circuit, some means of biasing its inputs must be provided. Node MID together with the VOCM buffer performs this function. Without internal biasing, external biasing is required. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac couple the signal into the DSX. It should be made clear again that the input to the DSX is still fully differential if driven differentially, that is, Pin +IN and Pin −IN see the same signal but with opposite polarity. What changes is the load seen by the driver; it is 175 Ω when each input is driven single ended, but 350 Ω when driven differentially. This can be easily explained when thinking of the ladder network as two 175 Ω resistors connected back-to-back with the middle node, MID, being biased by the VOCM buffer. A differential signal applied between nodes +IN and −IN results in zero current into Node MID, but a single-ended signal applied to either input +IN or −IN, while the other input is ac grounded, causes the current delivered by the source to flow into the VOCM buffer via Node MID. A feature of the X-AMP architecture is that the output-referred noise is constant vs. gain over most of the gain range. Referring to Figure 36, the tap resistance is approximately equal for all taps within the ladder, excluding the end sections. The resistance seen looking into each tap is 54.4 Ω, which makes 0.95 nV/√Hz of Johnson noise spectral density. Because there are two attenuators, the overall noise contribution of the ladder network is √2 times 0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX noise. The rest of the DSX circuit components contribute another 1.20 nV/√Hz, which together with the attenuator produces 1.8 nV/√Hz of total DSX input referred noise.
If the DSX output needs to be ground referenced, another ac coupling capacitor is required for level shifting. This capacitor also eliminates any dc offsets contributed by the DSX. With a nominal load of 500 Ω and a 0.1 μF coupling capacitor, this adds a high-pass filter with −3 dB corner frequency at about 3.2 kHz. The choice for all three of these coupling capacitors depends on the application. They should allow the signals of interest to pass unattenuated, while at the same time, they can be used to limit the low frequency noise in the system.
GAIN CONTROL INTERFACE The gain control interface provides an input resistance of approximately 2 MΩ at Pin VGN1 and gain scaling factors from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V, respectively. The gain varies linearly in decibels for the center 40 dB of gain range, that is, for VGN equal to 0.4 V to 2.4 V for the 20 dB/V scale and 0.25 V to 1.25 V for the 40 dB/V scale. Figure 37 shows the ideal gain curves when the FBK-to-OUT connection is shorted as described by the following equations: G (20 dB/V) = 20 × VGN − 19, VREF = 2.500 V
(3)
G (30 dB/V) = 30 × VGN − 19, VREF = 1.6666 V
(4)
G (40 dB/V) = 40 × VGN − 19, VREF = 1.250 V
(5)
The equations show that all gain curves intercept at the same −19 dB point; this intercept is 14 dB higher (−5 dB) if the FBKto-OUT connection is left open. Outside the central linear range, the gain starts to deviate from the ideal control law but still provides another 8.4 dB of range. For a given gain scaling, one can calculate VREF as
Rev. F | Page 14 of 24
VREF =
2.500 V × 20 dB/V Gain Scale
(6)
AD605 40dB/V
30dB/V
20dB/V
The AFA makes a differential input structure possible because one of its inputs (G1) is fully differential; this input is made up of a distributed gm stage. The second input (G2) is used for feedback. The output of G1 is some function of the voltages sensed on the attenuator taps that is applied to a high gain amplifier (A0). Because of negative feedback, the differential input to the high gain amplifier is zero; this in turn implies that the differential input voltage to G2 times gm2 (the transconductance of G2) is equal to the differential input voltage to G1 times gm1 (the transconductance of G1). Therefore, the overall gain function of the AFA is
35 30 25 20
GAIN (dB)
15
LINEAR-IN-dB RANGE OF AD605
10 5 0 –5
0.5
1.0
1.5
2.0
2.5
3.0
g VOUT R1× R2 = m1 × VATTEN g m 2 R2
GAIN CONTROL VOLTAGE
–10
00541-038
–15 –20
Figure 37. Ideal Gain Curves vs. VREF
Usable gain control voltage ranges are 0.1 V to 2.9 V for the 20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages of less than 0.1 V are not used for gain control because below 50 mV the channel is powered down. This can be used to conserve power and at the same time gate-off the signal. The supply current for a powered-down channel is 1.9 mA, and the response time to power the device on or off is less than 1 μs.
FIXED GAIN AMPLIFIER AND INTERPOLATOR CIRCUITS—APPLYING AN ACTIVE FEEDBACK AMPLIFIER A typical X-amp architecture is powered by a dual polarity power supply. Because the AD605 operates from a single supply, a supply common equal to half the value of the supply voltage is required. An active feedback amplifier (AFA) is used to provide a differential input and to implement the feedback loop. The AFA in the AD605 is an op amp with two gm stages; one is used in the feedback path, and the other is used as a highly linear differential input. A multisection distributed gm stage senses the voltages on the ladder network, one stage for each of the ladder nodes. Only a few of the stages are active at any time and are dependent on the gain control voltage.
(7)
where: VOUT is the output voltage. VATTEN is the effective voltage sensed on the attenuator. (R1 + R2)/R2 = 42. gm1/gm2 = 1.25; the overall gain is therefore 52.5 (34.4 dB). The AFA has additional features that include the following: inverting the output signal by switching the positive and negative input to the ladder network; the possibility of using the −IN input as a second signal input; and independent control of the DSX common-mode voltage. Under normal operating conditions, it is best to connect a decoupling capacitor to Pin VOCM, in which case, the common- mode voltage of the DSX is half of the supply voltage; this allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew rate of the VOCM buffer. If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again, this is done for level shifting and to eliminate any dc offsets contributed by the DSX (see the AC Coupling section). The gain range of the DSX is programmable by a resistor connected between Pin FBK and Pin OUT. The possible ranges are −14 dB to +34.4 dB when the pins are shorted together or 0 dB to +48.4 dB when FBK is left open. For the higher gain range, the bandwidth of the amplifier is reduced by a factor of five to about 8 MHz because the gain increased by 14 dB. This is the case for any constant gain bandwidth product amplifier that includes the active feedback amplifier.
Rev. F | Page 15 of 24
AD605 APPLICATIONS INFORMATION
0.1µF
VIN 0.1µF
1
VGN1
VREF 16
2.500V
2
–IN1
OUT1 15
OUT
3
+IN1
4
GND1
VPOS 13
5
GND2
VPOS 12
AD605
FBK1 14
6
+IN2
FBK2 11
7
–IN2
OUT2 10
8
VGN2
VOCM 9
0.1µF 5V
0.1µF
C1 0.1µF
VIN C2 0.1µF C3 0.1µF
C4 0.1µF
1
VGN1
VREF 16
2
–IN1
OUT1 15
3
+IN1
4
GND1
VPOS 13
5
GND2
VPOS 12
AD605
FBK1 14
6
+IN2
FBK2 11
7
–IN2
OUT2 10
8
VGN2
VOCM 9
2.500V R1
5V
R2
C5 0.1µF OUT C6 0.1µF
Figure 39. Doubling the Gain Range with Two Amplifiers
00541-039
VGN
VGN
00541-040
The basic circuit in Figure 38 shows the connections for one channel of the AD605 with a gain range of −14 dB to +34.4 dB. The signal is applied at +IN1. The ac coupling capacitors before Pin −IN1 and Pin +IN1 should be selected according to the required lower cutoff frequency. In this example, the 0.1 μF capacitors, together with the 175 Ω of each of the DSX input pins, provide a −3 dB high-pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the amplifier and is 40 MHz.
Figure 38. Basic Connections for a Single Channel
As shown in Figure 38, the output is ac-coupled for optimum performance. In the case of connecting to the 10-bit, 40 MSPS ADC, AD9050, ac coupling can be eliminated as long as Pin VOCM is biased by the same 3.3 V common-mode voltage as the AD9050. Pin VREF requires a voltage of 1.25 V to 2.5 V, with gain scaling between 40 dB/V and 20 dB/V, respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to 2.65 V for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V scaling. When this pin is taken to ground, the channel powers down and disables its output.
CONNECTING TWO AMPLIFIERS TO DOUBLE THE GAIN RANGE Figure 39 shows the two channels of the AD605 connected in series to provide a total gain range of 96.8 dB. When R1 and R2 are shorts, the gain range is from −28 dB to +68.8 dB with a slightly reduced bandwidth of about 30 MHz. The reduction in bandwidth is due to two identical low-pass circuits being connected in series; in the case of two identical single-pole, low-pass filters, the bandwidth is reduced by exactly √2. If R1 and R2 are replaced by open circuits, that is, Pin FBK1 and Pin FBK2 are left unconnected, the gain range shifts up by 28 dB to 0 dB to 96.8 dB. As previously noted, the bandwidth of each individual channel is reduced by a factor of 5 to about 8 MHz because the gain increased by 14 dB. In addition, there is still the √2 reduction because the series connection of the two channels results in a final bandwidth of the higher gain version of about 6 MHz.
Two other easy combinations are possible to provide a gain range of −14 dB to +82.8 dB: make R1 a short and R2 an open, or make R1 an open and R2 a short. The bandwidth for both of these cases is dominated by the channel that is set to the higher gain and is about 8 MHz. From a noise standpoint, the second choice is the best because by increasing the gain of the first amplifier, the noise of the second amplifier has less of an impact on the total output noise. One further observation regarding noise is that by increasing the gain, the output noise increases proportionally; therefore, there is no increase in signal-to-noise ratio. It actually stays fixed. It should be noted that by selecting the appropriate values of R1 and R2, any gain range between −28 dB to +68.8 dB and 0 dB to +96.8 dB can be achieved with the circuit in Figure 39. When using any value other than shorts and opens for R1 and R2, the final value of the gain range depends on the external resistors matching the on-chip resistors. Because the internal resistors can vary by as much as ±20%, the actual values for a particular gain have to be determined empirically. Note that the two channels within one part match quite well; therefore, R1 tracks R2 in Figure 39. C3 is not required because the common-mode voltage at Pin OUT1 should be identical to the one at Pin +IN2 and Pin −IN2. However, because only 1 mV of offset at the output of the first DSX introduces an offset of 53 mV when the second DSX is set to the maximum gain of the lowest gain range (34.4 dB), and 263 mV when set to the maximum gain of the highest gain range (48.4 dB), it is important to include ac coupling to get the maximum dynamic range at the output of the cascaded amplifiers. C5 is necessary if the output signal needs to be referenced to any common-mode level other than half of the supply as is provided by Pin OUT2.
Rev. F | Page 16 of 24
AD605 4 f = 1MHz 3 2
GAIN ERROR (dB)
Figure 40 shows the gain vs. VGN for the circuit in Figure 39 at 1 MHz and the lowest gain range (−14 dB to +34.4 dB). Note that the gain scaling is 40 dB/V, double the 20 dB/V of an individual DSX; this is the result of the parallel connection of the gain control inputs, VGN1 and VGN2. The gain can also be sequentially increased by first increasing the gain of Channel 1 and then Channel 2. In this case, VGN1 and VGN2 are driven from separate voltage sources, for instance two separate DACs. Figure 41 shows the gain error of Figure 39. 80 THEORETICAL
–2
–4 0.2
ACTUAL
0.7
1.2
1.7
2.2
VGN (V)
40
Figure 41. Gain Error vs. VGN for the Circuit in Figure 39
30 20 10 0 –10 –20 00541-041
GAIN (dB)
–1
–3
60 50
0
00541-042
f = 1MHz
70
1
–30 –40 0.1
0.5
0.9
1.3 1.7 VGN (V)
2.1
2.5
2.9
Figure 40. Gain vs. VGN for the Circuit in Figure 39
Rev. F | Page 17 of 24
2.7
AD605 EVALUATION BOARD The AD605-EVALZ provides a platform for the circuit designer to become familiar with the many operating and performance features of the AD605 variable gain amplifier. It is a factorydesigned, surface-mount assembly fully tested and ready for service. Figure 42 is a photograph of the AD605-EVALZ. Multiple inputs, test points, and jumpers provide circuit configurations that support any of the operating options of the device. Figure 43 is a schematic of the board. Power is required from only a single 5 V supply capable of supplying 55 mA to 60 mA quiescent current.
INPUT CONNECTIONS The AD605 VGA accepts differential or single-ended input signals and provides single-ended outputs. The SMA connectors enable either configuration to be used, as well as the output and gain control signals. Each of the I/O ports is also available at a test-loop labeled for easy identification. The input resistance at each of the four input SMA connectors is 50 Ω, consisting of the 175 Ω, ±40 Ω resistance of the attenuator ladder network in parallel with the external 69.8 Ω resistors. For single-ended operation, unused inputs can be left disconnected or optional jumpers installed. Either VGA input is usable; for noninverting operation, the INPx is used, and for signal inversion, the INMx is used.
ADJUSTING GAIN, COMMON-MODE, AND REFERENCE LEVELS The gain of each channel is adjusted with trimmers, GN1ADJ and GN2ADJ. Trimmer VREF ADJ adjusts the gain scaling in dB/V (or gain slope), and VOCM ADJ adjusts the output common-mode voltage for both channels. For dynamic gain control, JP1 and JP4 can be removed and the signal applied at the SMA connectors, GN1 and GN2.
00541-043
OUTPUT CONNECTIONS
Figure 42. AD605–EVALZ Evaluation Board
SMA connectors, OUT1 and OUT2, are the output connectors. Series resistors and capacitors are included for termination and dc blocking purposes. The output of the AD605 has a commonmode value of one-half the supply (unless amended by a voltage applied to the VCM pin). Table 4 lists jumpers and their functions, and Figure 44 shows the evaluation board in a typical test configuration.
Table 4. Table of Jumpers Jumper JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8
Function Connects trimmer GN1ADJ to pin VGN1. This jumper can be removed for an ac signal at VGN1. Grounds the IN1 pin via C2. Grounds the IN2 pin via C5. Connects trimmer GN2ADJ to Pin VGN2. This jumper can be removed for an ac signal at VGN2. Connects trimmer VOCMADJ to the VOCM pin. This jumper can be removed for the half supply default VOCM. Shifts the gain of Channel 2 up or down by 14 dB. Shifts the gain of Channel 1 up or down by 14 dB. Connects trimmer VREFADJ to the VREF pin to change the gain slope.
Rev. F | Page 18 of 24
Default Configuration Installed User supplied User supplied Installed Installed Installed Installed Installed
AD605 +5V
CH1_GN
R1 DNI
JP1 C1 1nF VGA1_NEG
J2 INM1
R4 69.8Ω JP2 VGA1_POS
J3 INP1
AD605
C2 0.1µF
1 2
C3 0.1µF
3
R3 69.8Ω
4
VGA2_POS J4 INP2
R6 69.8Ω VGA2_NEG
J5 INM2
5
C4 0.1µF
6 7
C5 0.1µF
8
R5 JP3 69.8Ω CH2_GN
VGN1
VREF
–IN1
OUT1
+IN1
FBK1
GND1
VPOS
GND2
VPOS
+IN2
FBK2
–IN2
OUT2
VGN2
JP4
J6 GN2
C6 1nF
R7 DNI
VOCM
VREF ADJ R14 10kΩ
+5V
R2 10kΩ GN1 ADJ
C14 0.1µF
JP8
VREF 16
C13 OUT1 R13 0.1µF 49.9Ω
15 14
R12 DNI
JP7
+5V
C12 C11 13 0.1µF 0.1µF
+ C8 10µF 10V
12
J8 OUT1
C7 0.1µF
+5V GND1
11 10
C10 0.1µF
VOCM
9
+5V R8 10kΩ GN2 ADJ
R11 R10 DNI 49.9Ω
JP6
J7 OUT2
OUT2 +5V VOCM ADJ
JP5 C9 0.1µF
R9 10kΩ GND2 GND3 GND4
00541-044
J1 GN1
NOTES 1. PARTS IN GRAY ARE NOT INSTALLED.
Figure 43. Schematic Diagram of the AD605-EVALZ Evaluation Board OSCILLOSCOPE
POWER SUPPLY
+5 V GND 5V
FUNCTION GENERATOR
VGA OUTPUT (TO SCOPE)
00541-045
SINGLE-ENDED INPUT
Figure 44. Typical Test Configuration of the AD605-EVALZ
Rev. F | Page 19 of 24
00541-046
00541-049
AD605
Figure 48. AD605-EVALZ Internal Ground Plane
00541-047
00541-050
Figure 45. AD605-EVALZ Assembly
Figure 49. AD605-EVALZ Internal Power Plane
00541-051
00541-048
Figure 46. AD605-EVALZ Primary Side Copper
Figure 47. AD605-EVALZ Secondary Side Copper
Figure 50. AD605-EVALZ Primary Side Silkscreen
Rev. F | Page 20 of 24
AD605 OUTLINE DIMENSIONS 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 16
9
1
8
0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62)
0.100 (2.54) BSC
0.060 (1.52) MAX
0.210 (5.33) MAX
0.195 (4.95) 0.130 (3.30) 0.115 (2.92)
0.015 (0.38) MIN
0.150 (3.81) 0.130 (3.30) 0.115 (2.92)
0.015 (0.38) GAUGE PLANE SEATING PLANE
0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.430 (10.92) MAX
0.005 (0.13) MIN
0.014 (0.36) 0.010 (0.25) 0.008 (0.20)
0.070 (1.78) 0.060 (1.52) 0.045 (1.14)
073106-B
COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 51. 16-Lead Plastic Dual In-Line Package [PDIP] (N-16) Dimensions shown in inches and (millimeters)
10.00 (0.3937) 9.80 (0.3858)
4.00 (0.1575) 3.80 (0.1496)
9
16 1
8
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10
0.51 (0.0201) 0.31 (0.0122)
6.20 (0.2441) 5.80 (0.2283)
1.75 (0.0689) 1.35 (0.0531) SEATING PLANE
0.50 (0.0197) 0.25 (0.0098)
45°
8° 0°
0.25 (0.0098) 0.17 (0.0067)
1.27 (0.0500) 0.40 (0.0157)
Figure 52. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches)
Rev. F | Page 21 of 24
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
AD605 ORDERING GUIDE Model AD605AN AD605ANZ 1 AD605AR AD605AR-REEL AD605AR-REEL7 AD605ARZ1 AD605ARZ-RL1 AD605ARZ-R71 AD605BN AD605BR AD605BR-REEL AD605BR-REEL7 AD605BRZ1 AD605BRZ-RL1 AD605BRZ-R71 AD605-EVALZ1 AD605ACHIPS 1
Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C
Package Description 16-Lead PDIP 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N, 13" Tape and Reel 16-Lead SOIC_N, 7" Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 13" Tape and Reel 16-Lead SOIC_N, 7" Tape and Reel 16-Lead PDIP 16-Lead SOIC_N 16-Lead SOIC_N, 13" Tape and Reel 16-Lead SOIC_N, 7" Tape and Reel 16-Lead SOIC_N 16-Lead SOIC_N, 13" Tape and Reel 16-Lead SOIC_N, 7" Tape and Reel Evaluation Board DIE
Z = RoHS Compliant Part.
Rev. F | Page 22 of 24
Package Option N-16 N-16 R-16 R-16 R-16 R-16 R-16 R-16 N-16 R-16 R-16 R-16 R-16 R-16 R-16
AD605 NOTES
Rev. F | Page 23 of 24
AD605 NOTES
©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00541-0-6/08(F)
Rev. F | Page 24 of 24
