Enee 759h, Spring 2005 Memory Systems: Architecture And Performance Analysis

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Memory Systems Architecture and Performance Analysis Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. ENEE 759H, Spring 2005 Memory Systems: Architecture and Performance Analysis Memory System Organization SLIDE 1 Credit where credit is due: Slides contain original artwork (© Jacob, Wang 2005) UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Memory System Organization Spring 2005 Dimm1 Dimm2 ENEE 759H Lecture3.fm Dimm3 Dimm4 Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 2 Single Channel SDRAM Controller “Mesh Topology” UNIVERSITY OF MARYLAND Addr & Cmd Data Bus Chip (DIMM) Select Memory Systems Architecture and Performance Analysis Where is the data? Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang CPU Request (Read) (Physical Address) (Cachline length = 64B) Data University of Maryland ECE Dept. SLIDE 3 Rank? Bank? Row? Column? Data Magic Memory Controller Command Sequence Rank Address = ? Bank Address = ? Row address = ? Column Address ? UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Channel I Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang 64 “Typical” system controller DMC “PC Class” memory system. 1 physical channel of DDR SDRAM University of Maryland ECE Dept. SLIDE 4 DDR Intel i850 system controller DMC 32 16 D-RDRAM 16 D-RDRAM Intel i850 DRDRAM memory system. 2 physical channel. 1 logical channel Intel i875P system controller DMC 128 64 DDR 64 DDR Intel 875P DDR SDRAM memory system. 2 physical channel. 1 logical channel UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Channel II Spring 2005 Bruce Jacob David Wang University of Maryland ECE Dept. 64 Compaq Alpha EV7 processor ENEE 759H Lecture3.fm 16 D-RDRAM DMC DMC D-RDRAM 16 16 64 D-RDRAM D-RDRAM D-RDRAM D-RDRAM 16 SLIDE 5 D-RDRAM D-RDRAM Intel i925X system controller Two Channels: 64 bit wide per channel DMC 64 DDR2 64 DMC DDR2 Two Channels: 64 bit wide per channel UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Rank I address and command Spring 2005 ENEE 759H Lecture3.fm data bus 16 Bruce Jacob David Wang DMC University of Maryland ECE Dept. Bank data bus 16 data bus 16 SLIDE 6 chip select 0 chip select 1 data bus 16 Rank It’s a “bank” of chips that responds to a single command and returns data. “Bank” terminology already used. UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Rank II Spring 2005 ENEE 759H Lecture3.fm Rambus RIMM Rank Count is Number of Devices Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 7 SDRAM Double Sided Dimm Two Ranks SDRAM Single Sided Dimm One Rank SDRAM/DDR SDRAM system: 1~6 ranks RDRAM system: <= 32 ranks UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Spring 2005 Bank CKE control ENEE 759H Lecture3.fm CLK logic row addr mux WE# CAS# RAS# University of Maryland ECE Dept. SLIDE 8 decode Bruce Jacob David Wang command CS# mode row row address row address latch & row address latch & decoder address latch & decoder latch & decoder decoder DRAM Array Bank 0 Bank 1 Bank 2 Bank 3 sense amp array sense amp array sense amp array sense amp array refresh counter register data out register addr bus address register bank control column address counter I/O gating / read data latch write drivers column column column decoder column decoder decoder decoder data I/O data in register “Banks” of indepedent memory arrays inside of a DRAM Chip SDRAM/DDR SDRAM system: 4 banks RDRAM system: “32” split or 16 full banks UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Spring 2005 Row DRAM devices arranged in parallel in a given rank ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 9 DRAM Array DRAM Array DRAM Array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array one row spanning multiple DRAM devices UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Spring 2005 Column DRAM devices arranged in parallel in a given rank ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. DRAM Array DRAM Array DRAM Array DRAM Array DRAM Array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array sense amp array SDRAM memory systems: width of data bus = column size SLIDE 10 Column = Smallest unit of data moved in memory system UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Where’s the data? Part 1 Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang Read Request Physical Address: 0x0AC75C38 University of Maryland ECE Dept. SLIDE 11 Rank id = 1 Bank id = 1 Row id = 0x0B1D Column id = 0x187 Magic Memory Controller 32 bit physical address (byte addressable) no rank memory id UNIVERSITY OF MARYLAND 32 1413 12 11 31 29 28 27 26 row id bank id column id 0 not used Memory Systems Architecture and Performance Analysis Where’s the data? Part 2 Spring 2005 Bank id = 1 ENEE 759H Lecture3.fm Rank id = 1 Bruce Jacob David Wang Column id = 0x187 Row id = 0x0B1D University of Maryland ECE Dept. SLIDE 12 FPM / EDO / SDRAM / etc. UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 13 UNIVERSITY OF MARYLAND Bare Chips Bare DIP’s shoved into sockets 18 Chips, each x1, 18 bit wide data bus Memory Systems Architecture and Performance Analysis Memory Modules I Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang Organizing chips into modules University of Maryland ECE Dept. SLIDE 14 Put chips on PCB, make a module Data Address FPM / EDO / SDRAM / etc. UNIVERSITY OF MARYLAND Data Memory Systems Architecture and Performance Analysis Memory Modules II Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. same electrical contact front side of 30 pin SIMM SLIDE 15 back side of 30 pin SIMM Single Inline Memory Module UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Memory Modules III Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. electrically different contact front side of DIMM SLIDE 16 back side of DIMM Dual Inline Memory Module UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Memory Modules IV Spring 2005 Registered DIMM ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 17 Latch Data Data Address One extra cycle to buffer and distribute address. More chips (load) can be placed on module UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis Memory Modules V Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 18 Capacity 128 MB 128 MB 128 MB 128 MB device density 64 Mbit 64 Mbit 128 Mbit 256 Mbit number of ranks devices per rank device width number of banks number of rows number of columns 1 16 x4 4 4096 1024 2 8 x8 4 4096 512 1 8 x8 4 4096 1024 1 4 x16 4 8192 512 Four different configurations for a 128 MB SDRAM DIMM UNIVERSITY OF MARYLAND Memory Systems Architecture and Performance Analysis SPD: Serial Presence Detect Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang University of Maryland ECE Dept. SLIDE 19 UNIVERSITY OF MARYLAND SPD: Tiny EEPROM Contains Parameters - Speed settings - Configurations - Programmed by module maker Memory Systems Architecture and Performance Analysis Kingston SDRAM DIMM Spring 2005 ENEE 759H Lecture3.fm Bruce Jacob David Wang 8 Chips. 128 Mbit each. (Infineon) SPD University of Maryland ECE Dept. SLIDE 20 PC133 CAS 3 Dual Inline Memory Module UNIVERSITY OF MARYLAND