Transcript
1230 Midas way, Suite 100 Sunnyvale, CA 94085-4020 (408) 789-2400 Fax: (408) 884-2248 http://www.AriraDesign.com
Engineering Design Specification Arira Design - MX27 Reference Platform
Document #: 800-00355-10SPEC Revision: 0.5 Date: June 10, 2009
1 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Revision History Revision
Changes
Author/Editor
0.1
Initial authoring
BFD
0.2
Review updates
BFD
0.3
Block diagram and connectivity updates
BFD
0.4
Added IRQ and GPIO mapping, Block diagrams updated
ATN
0.5
Battery charging details added, section 7 modified
ATN
2 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Table of Contents 1
2
Introduction ................................................................................................ 6 1.1
Purpose ........................................................................................... 6
1.2
Scope .............................................................................................. 6
1.3
Reference Documents.................................................................... 6
Functional Description ............................................................................... 7 2.1
Functional Block Diagram .............................................................. 7
2.2
MC13783 ......................................................................................... 8
2.3
Memory............................................................................................ 8
2.4
LCD Interface .................................................................................. 9
2.5
USB Interfaces ................................................................................ 9
2.6
I2C Interface .................................................................................. 10
2.7
Expansion board ........................................................................... 11
3
Clock Tree................................................................................................ 12
4
Reset Control ........................................................................................... 13
5
Power ....................................................................................................... 14 5.1
6
Board IO ................................................................................................... 18 6.1
7
Connectors .................................................................................... 18
Firmware/Software Dependencies & Component Configuration Settings27 7.1
8
Power Consumption ..................................................................... 14
Hardware Configuration Settings ................................................. 27
Manufacturing and Testability ................................................................. 30 8.1
Design for Manufacturing (DFM).................................................. 30
8.2
Design for Compliance (DFC) ...................................................... 30
8.3
Design for Testability (DFT).......................................................... 30 3 OF 30
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Table of Figures Figure 1 - Block Diagram .............................................................. 7 Figure 2 - Expansion Board Block Diagram .............................. 11 Figure 3 - Clock Tree .................................................................. 12 Figure 4 - Reset Control.............................................................. 13 Figure 5 – Power Scheme .......................................................... 15 Figure 6 – Battery Charging........................................................ 17 Figure 7: Micro USB OTG AB Connector .................................. 18 Figure 8: USB Type A Connector............................................... 19 Figure 9: Microphone ................................................................. 23 Figure 10: Speaker...................................................................... 23 Figure 11: Stereo Audio Jack ..................................................... 24
4 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
List of Tables Table 1: Power Consumption ..................................................... 14 Table 2: Micro USB OTG AB Connector Pinout........................ 18 Table 3: USB Type A Connector Pinout .................................... 19 Table 4: LCD Connector Pinout ................................................. 20 Table 5: Acoustic touch screen Connector Pinout .................... 21 Table 6: Back Gammon Capacitive Touch Screen Connector Pinout
22
Table 7: Stereo Audio Jack Pinout ............................................. 24 Table 8: 3 Pin Serial Port Header Pinout ................................... 24 Table 9: Expansion Connector Pinout ....................................... 26 Table 10: IMX27- Config Strapping ............................................ 27 Table 11: IMX27- GPIO Mapping ............................................... 28 Table 12: ATLAS – Config Strapping ......................................... 28 Table 13: ATLAS - GPIO Mapping............................................. 29 Table 14: STM32F103 – Config Strapping ................................ 29 Table 15: STM32F103 - GPIO Mapping .................................... 29
5 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
1 1.1
Introduction Purpose This document is intended to define the hardware components of the Arira Design MX27 reference platform, and how the components are interconnected. This document is not intended to act as or replace a theory of operations document or marketing requirements document (MRD), rather it is intended to provide detailed insight as to the specific components used on the board, their interconnectivity, and configuration.
1.2
Scope The intended audience of this document is hardware and firmware/software developers. The contents of this document range from expected power dissipation on the board to addressable contents.
1.3
Reference Documents ¾
MCIMX27 Datasheet Rev 1.2, 07/2008
¾
MCIMX27 Reference manual rev 0.2 & Addendum
¾
MC13783 Power Management and Audio Circuit, User’s Guide, MC13783UG Rev 3.6, 9/2007
¾
MC13783 Technical Data, MC13783/D Rev 3.4, 3/2007
¾
MC13783 Information for GPL Drivers, Reference Manual, MC13783GPLDRM Rev 1.1, 4/2008
¾
External Component Recommendations for the MC13783 Reference Design Application Note, AN3295
¾
MC13783 Buck and Boost Inductor Sizing Application Note, AN3294
¾
Interfacing the MC13783 Power Management IC with i.MX31 Application Note, AN3276
¾
MC13783 Recommended Audio Output SPI Sequences Application Note, AN3261
¾
Voltage Drop Compensation on the MC13783 Switchers Application Note, AN3249
¾
Battery Management for the MC13783 Application Note, AN3155
6 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
2
Functional Description The following sections are intended to provide basic functionality and interconnects used in areas critical to the hardware development of the Arira Design MX27 Reference Platform hardware design.
2.1
Functional Block Diagram
3.5mm STEREO JACK
USB OTG SSI1
EXPANSION CONN
UART 1
SSI2 CSPI3
UART 3 CSI
MICROPHONE (MONO)
MC13783 FEC SD2 I2C2
SPEAKER (MONO)
JTAG
32 Bits
WEIM
CPU SSI4
64M BYTE
NAND FLASH 128M BYTE
USB H2
USB TRANSCEIVER HIGH SPEED
RESISTIVE TOUCH CTRL
USB CONN TYPE A
CSPI1
ADDR:b1010000;0X50
ADDR:b1000100;0X44
MICRO USB OTG CONN
DDR SDRAM
i.MX27
256BYTE ID PROM
LIGHT SENSOR
Li-Ion BATTERY
KEYPAD ESDRAMC
APR TOUCH SCREEN CONNECTOR
SD CARD CONN
LCD CONNECTOR
LCDC
I2C UART 2
STM32F103CB MCU
SPI
ACCELEROMETER
ADC
ANALOG LINES
CAPACITIVE TOUCH CONN
ADDR:b0011100;0X1D
Figure 1 - Block Diagram
7 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
1230 Midas way, Suite 100 Sunnyvale, CA 94085-4020 (408) 789-2400 Fax: (408) 884-2248 http://www.AriraDesign.com
2.2
MC13783 The Freescale MC13783 Atlas chip provides power management, audio interfaces, and user interface components to the MX27 reference platform. Connectivity to the i.MX27 chip is provided through 3 interfaces. One of two available SPI interfaces is used as the control/status interface to/from the i.MX27, and two SSI interfaces are used for the audio interfaces to/from the i.MX27. The interface to the outside world is through a mini USB AB connector. The Atlas chip provides on chip Full Speed USB OTG transceiver and functionality to be both a host (OTG A device) or slave (OTG B device). Power management includes integrated battery charger control, through the USBOTG connector. Current and voltage monitoring of the battery is provided by an on chip ADC. The Atlas chip includes 5 switching power supplies (4 buck and 1 boost) and 18 linear regulators, which are used to power the MX27. Power sequencing is controlled through strapping options on the chip. This is important as the core voltage of the i.MX27 is required to come on before IO voltages. The audio interfaces to the i.MX27 are two interchangeable SSI buses, both with master/slave support. One of 3 available audio inputs (MC1RIN) will be used for the mono microphone input. A handset speaker will be driven by the ASP integrated amplifier, and a stereo headphone jack will be driven by the AHS amplifiers. A touch screen interface provides the circuitry required for a 4-wire resistive touch screen.
2.3
Memory The Arira Design MX27 Reference Platform will have a single chip of mobile 64 MB of DDR SDRAM, upgradable to 128 MB, 128 MB of NAND Flash, upgradable to 4GB, and a Micro SD card interface.
2.3.1
DDR SDRAM The DDR SDRAM will be implemented with Micron MT46H16M32LFCM-7:B or similar part. This is a Mobile DDR SDRAM arranged in 4 Banks x 4Mb x 32, for a total of 64 MB. The i.MX27 incorporates a DDR SRAM controller that runs up to 133MHz. The controller supports 64Mb to 2Gb synchronous DRAM devices with 4 banks, and has two independent chip selects if multiple chips are used.
2.3.2
NAND Flash The Flash will be implemented using a Micron MT29F1G08ABCHC-ET or similar part (100-01597-00). This is a 1.8V IO and core voltage part, 128Mx8 in a 63 ball VFBGA package. The i.MX27 incorporates a NAND Flash controller that supports 8-bit and 16-bit parts, with page sizes of 512 B, 2KB or 4KB.
2.3.3
Micro SD Card Interface An SD card slot connector will be placed on the Arira Design MX27 Reference Platform. The connector used will be a Yamaichi FPS009-2700-0 or similar part (200-01126-00). The i.MX27 has two dedicated Secure Digital Host Controller interfaces, one of which will be connected on board, the other will go off 8 OF 30
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
board through the expansion connector. Micro SD cards may be plugged into this connector for memory expansion, etc.
2.4
LCD Interface The MX27 reference platform will interface to an 4.3” Liquid Crystal Display, with integrated white LED back light, and resistive touch screen.
2.4.1
LCD Data Interface The i.MX27 chip has an integrated LCD controller. This will interface to an LCD through a 40 pin FPC connector.
2.4.2
LCD Back Light Interface The back light on the LCD panel will be controlled through an i.MX27 GPIO output. A PWM circuit implemented with a TI TPS61161 (100-01521-00) LED Driver with PWM brightness control.
2.4.3
Touch Screen Interface The Atlas chip provides the a touch screen interface - the circuitry required for a 4-wire resistive touch screen. A four pin FPC connector is used to connect to the LCD/touch screen assembly.
2.5
USB Interfaces The i.MX27 chip has 3 available USB interfaces: one “On The Go” High Speed interface, one High Speed Host Interface, and one Full Speed Host interface.
2.5.1
USB OTG Full Speed Interface The USB OTG interface from the i.MX27 is connected to the Atlas chip. The Atlas chip provides an on board Full Speed USG OTG transceiver. Note that the i.MX27 supports High speed, but the Atlas chip only has a Full speed transceiver. A mini USB AB connector will be used to connect to the outside world. The ID pin from this connector is used to determine who is to drive the power on the USB OTG interface. The Atlas chip provides on chip USB OTG functionality, and will control power input or output to the connector. When the board is in USB slave mode, the 5V from the host will be used to charge LI battery.
2.5.2
USB Host High Speed Interface (WIFI) The USB Host HS interface from the i.MX27 will be connected to an NXP ISP1504A (100-01407-00). This tranciever will be used to connect to a HS USB WIFI device – TBD.
2.5.3
USB Host Full Speed Interface The USB Host FS interface from the i.MX27 is not used on baord.
9 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
2.6
I2C Interface The I2C interface will have a 3-axis accelerometer, light sensor and a 256 byte IDPROM.
2.6.1
3-axis I2C accelerometer The accelerometer will be implemented using an STMicro LIS302DL (100-01637-00). This device has two programmable interrupt outputs which can be configured for thresholds and timings.
2.6.2
Light sensor Intersil ISL29003IROZ is used as light sensor. This device has one interrupt line to CPU besides the I2C interafce
2.6.3
ID PROM The ID PROM will be implemented using an Atmel AT24C02A 2-wire serial EEPROM (100-01275-00). This device can be used to store manufacturing information such as fab and assembly part numbers and revisions, and board configuration information.
10 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
2.7
Expansion board Expansion board connector on the Arira Design MX27 Reference Platform board will be an 80 pin .8mm pitch double row connector from Samtec, QSE-040-01-F-D-A (200-00932-00). The mating connector on the Expansion Board will be the Samtec QTE-040-01-F-D-A (200-01194-00). The stack height of these two connectors is 5.0mm. An expansion board will bring unused interfaces on the i.MX27 chip. For bring up of the reference board, an Ethernet PHY and an RS-232 transceiver are required. Other interfaces will be brought to a header for debug/testing purpose. See Figure 2 - Expansion Board Block Diagram below.
EXPANSION CONN
FECMII
SMSC LAN8700C
MDI
RJ45 With Magnetics
UART1
MAX3222 RS-232 Buffer
RS-232-1
DB9
UART3 KEYPAD
100 mil Header CSI I2C
JTAG
JTAG CONNECTOR
Figure 2 - Expansion Board Block Diagram
11 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
32KHz
XTAL
CLIA & B
PRI CLK
CLK32 MCU
MC13783
AUDIO
32KHz
NOT INSTALLED 0Ohm
26MHz
26MHz
1.41MHz
1.41MHz
LCD CLK
SDCLK
CSPI1 CLK
CSI CLKS
USBH2_CLK
i.MX27
CPU
SSI4 CLK
EXPANSION CONNECTOR
FEC CLK
CSPI3 CLK
XTAL32K
EXTAL26M
CLK0
SSI2 CLK
SSI1 CLK
60MHz
133MHz DIFF
26MHz OSC
USB TRANSCEIVER HIGH SPEED
64MB
DDR SDRAM
LCD CONN
APR TOUCH CONN
STM32F103CB
8MHz
SPI CLK
ADC
3 Clock Tree
Figure 3 - Clock Tree
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
12 OF 30
4
Reset Control Power management and reset control is provided by the Atlas chip. See Figure 4 - Reset Control below for a diagram of reset flow.
PM_RESET_MCU
POR POWER_ON_RESET
MC13783 RESET SWITCH
RESET_IN
PM_RESET
RESET_L
EXPANSION CONNECTOR
USB3317
GPIO
CPU i.MX27
RESET_OUT
Figure 4 - Reset Control
13 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
5 5.1
Power Power Consumption
Voltage (V) --> Devices CPU MC13783 DDR SDRAM FLASH WIFI Module LCD USB HS Transceiver IDPROM Light Sensor Accelerometer CAP Touch screen -CPU CAP Touch screen -ADC Resistive touch screen APR touch screen Ethernet PHY chip Serial Transceiver Level shifter Micro SD LED x 7 26MHz Oscillator Total Regulator output power (mW) Regulator efficiency (%) Regulator input power (mW )(TYP) Regulator input power (mW)((MAX) Voltage (V) --> Devices CPU MC13783 DDR SDRAM FLASH WIFI Module LCD USB HS Transceiver IDPROM Light Sensor Accelerometer CAP Touch screen -CPU CAP Touch screen -ADC Resistive touch screen APR touch screen Ethernet PHY chip Serial Transceiver Level shifter Micro SD LED x 7 26MHz Oscillator Total Regulator output power (mW) Regulator efficiency (%) Regulator input power (mW )(TYP) Regulator input power (mW)((MAX)
LCDBL 19.2 TYP (mA)
MAX (mA)
20
VATLAS 2.8 TYP (mA)
MAX (mA)
9.5
12
+2.8V_STBY 2.8 TYP (mA)
MAX (mA)
VIOLO 1.8
VIOHI 2.8
TYP (mA)
MAX (mA)
28
34
2
10
TYP (mA) 10
VGEN 1.5
MAX (mA) 10
TYP (mA) 10
VMMC1 3
MAX (mA) 10
22
0.3
22 422
9.5 26.6
85
12 34
497 VMMC2 3 MAX (mA)
50 0.9
0.4 1.12
1.4
2 0.29
3 0.3
4.1 0.3 0.05
4.7 1 0.1
TYP (mA) 20
10 28
10
37.4
41.3
15 10 69.4 208.2
30 10 91.3 273.9
MAX (mA) 20
3
4
30
45
53 148
69 193
TYP (mA) 300
10 15
10 15 80
35
99.1125 SW1AB 1.45
VRF1 2.8
MAX (mA) 20
10 28 80
67.6125
43
TYP (mA) 20
44.05 79.29 80
1.05
VRF2 2.8
7
0.05
30.05 54.09
80
33.3
TYP (mA)
0.3 0.84
80
451.8
MAX (mA)
0.4
0.05
20 384
TYP (mA)
MAX (mA) 300
80
18.75 35 SW2A 1.8
TYP (mA) 20
MAX (mA) 30
100
120
260.25
18.75 SW2B 1.8 TYP (mA) 10
MAX (mA) 10
10
20
342.375 5V5 5 TYP (mA)
MAX (mA)
200
200
7
10
207 1035
210 1050
50 1
10
20
60.9 182.7
71 214
26.7 74.9
80
29 81 80
228.4
80
93.6 267
300 435
120 216
90
186 102
300 435
20 36
90
483.333 242
150 270
90
240 483.333
30 54
80
40 300
1293.8 60
1312.5
Table 1: Power Consumption
14 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
5.1.1
Board Power scheme
PWR IN (MICRO USB CONN) PWR IN (DC JACK) (On Expansion board)
BATTERY
MC13783 VREG LDO - VIOHI
VREG
CPU RTC (OSC32VDD, RTCVDD)
200mA
DCDC - SW2A
LDO - VRF1
500mA
350mA
LDO - VRF2
1.5V
2.8V
2.8V
350mA 1.8V
DCDC - SW2A 500mA
1.8V
(NVDD1)
3.0V
3.0V
(MPLLVDD, UPLLVDD, FPMVDD) CPU IO (NVDD7, NVDD11, NVDD12, NVDD14, NVDD15) CPU IO (NVDD5, NVDD6, NVDD8, NVDD9, NVDD10, AVDD)
VBKUP2 CPU IO (NVDD13)
DCDC - SW2B
BOOST - SW4
500mA
350mA
VMMC1
BOOST
5V
19.2V
1A
350mA LCD MODULE
LDO - VGEN
500mA
VBKUP1
(NVDD2, NVDD3, NVDD4)
CAP TOUCH CIRCUIT
200mA
DCDC - SWIA
(QVDD)
FLASH
CPU CLK (OSC26VDD) CPU PLL
CPU CORE
DDR
2.8V
VMMC2
LDO - TPS76133
350mA
3.3V
TO USB CONN (WIFI)
LCD BACK LIGHT
ETHERNET PHY
100mA
Figure 5 – Power Scheme The i.MX27/MX27L processor consists of three major sets for power supply voltage named QVDD (core logic supply), FUSEVDD (analog supply for FUSEBOX), and NVDD VDDA (IO supply). The External Voltage Regulators and poweron devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. It is important that the applications processor power supplies be powered-up in a certain order to avoid unintentional fuse blown. QVDD should be powered up before FUSEVDD. The recommended order used in Audio puck is: 1. QVDD(1.5 V) 2. FUSEVDD (1.8 V) NVDD (1.8/2.775 V), and Analog Supplies (2.775 V)
15 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
5.1.1
Power ON & Power states Board can be brought to active RUN mode using the PWR button during development and using the accelerometer afterwards. Connecting the USB power or attaching a fully charged battery can also turn the board ON Keeping the power button pressed for >4sec will turn the board OFF. The board is supposed to stay powered by battery all the time with the following power saving options. LCD back light turned OFF and CPU in a lower core frequency and reduced core voltage Putting CPU in Sleep mode is the largest power saving mode. All the power rails will be active in this mode and the system can be waken up by the accelerometer interrupt activating the PON pin of ATLAS chip. Back up power modes are not supported even though VBKUP1 and VBKUP2 are connected. System is expected to go to an unplanned power-off In case of a battery removal or battery contact bounce. Make the VMMC1 and VMMC2 = 3.0V by setting VMMC1 [2:0] = VMMC2 [2:0] = 111 Also make SW3 = 5.0V . SW3[1:0] = 00.
16 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
5.1.2
Battery charging Battery charging module is configured in dual path charging with an additional DC Jack as shown below for faster battery charging and supplying power when the USB OTG port is a host port.
Figure 6 – Battery Charging
M1 & M2 (Q6 and Q17 in the schematics) are Battery charge path regulator, M4 (Q4) is the external input voltage regulator and M3 (Q3) is the battery voltage switch. Application of a charger can be detected by the CARGDETS, USB4V4S, and SE1S bits. Presence of a DC jack can be detected by the DC_JACK_PRSNT signal connected to CPU GPIO PF16. Board can use more power if DC Jack is present (2.5A from DC jack as opposed to 500mA from USB). Also the battery can be fast charged at 1C rates (1.2A) if DC jack is present. Power source for charging can be either from the Micro USB OTG connector or the DC Jack. Hardware will enable the power source as DC jack if both USB and DC jack are plugged in. Turn the charge path regulator (M1 and M2) off by setting ICHRG[3:0] = 0000’b if both the USB and DC jack connector are absent to prevent possible current loops.
17 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6
Board IO
6.1
Connectors The following is a list of interfaces into / out of the MX27 reference platform. • • • • • • • • • • •
6.1.1
Mini USB connector USB Type A connector (for external modules like a Wi-Fi module) LCD connector Acoustic touch screen connector Capacitive touch screen connector Stereo Headphone Jack Speaker Microphone 3 pin Serial Port Header Expansion Connector
Micro USB OTG AB Connector
Figure 7: Micro USB OTG AB Connector Number 1 2 3 4 5
Function USB OTG Power – In or Out Data Data + ID Ground Table 2: Micro USB OTG AB Connector Pinout
18 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6.1.2
USB Type A Connector
Figure 8: USB Type A Connector Number 1 2 3 4
Function USB Power Out Data Data + Ground Table 3: USB Type A Connector Pinout
6.1.3
LCD connector (LCD with resistive touch panel) Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Function LCD Back light cathode LCD Back light Anode GND RESET_L NC TSRIGHT TSTOP TSLEFT TSBOTTOM NC NC LCD_BLU0 LCD_BLU1 LCD_BLU2 LCD_BLU3 LCD_BLU4 LCD_BLU5 NC
Resistive touch panel signals
19 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Number 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Function NC LCD_GRN0 LCD_GRN1 LCD_GRN2 LCD_GRN3 LCD_GRN4 LCD_GRN5 NC NC LCD_RED0 LCD_RED1 LCD_RED2 LCD_RED3 LCD_RED4 LCD_RED5 LCD_HSYNC LCD_VSYNC LCD_DCLK NC NC LCD power SS0 GND NC GND NC NC SCLK MOSI NC DE GND GND Table 4: LCD Connector Pinout
20 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6.1.4
Acoustic touch screen Connector (APR) Number
Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND NC GND NC GND GND GND GND APR_CONN_SCLK APR_CONN_SERO APR_CONN_SERI APR_CONN_SFR NC POWER POWER POWER Table 5: Acoustic touch screen Connector Pinout
6.1.5
Capacitive touch screen connector (Back Gammon) Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Function GND AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD AC_SHIELD CIN11 CIN10 CIN11 CIN10 CIN9 CIN10 CIN9 CIN8 CIN9 CIN8 21 OF 30
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Function CIN7 CIN8 CIN7 CIN6 CIN7 CIN6 CIN5 CIN6 CIN5 CIN4 CIN5 CIN4 CIN3 CIN4 CIN3 CIN2 CIN3 CIN2 CIN1 CIN2 CIN1 CIN0 CIN1 CIN0 AC_SHIELD AC_SHIELD GND GND
Table 6: Back Gammon Capacitive Touch Screen Connector Pinout
22 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6.1.6
Microphone
Figure 9: Microphone 6.1.7
Speaker
Figure 10: Speaker
23 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6.1.8
Stereo Audio Jack
Figure 11: Stereo Audio Jack
Number 1 2 3
Function GND (Sleeve) Left Out (Tip) Right Out (Ring) Table 7: Stereo Audio Jack Pinout
6.1.9
3 Pin Serial port header Number 1 2 3
Function Receive input GND Transmit Output Table 8: 3 Pin Serial Port Header Pinout
24 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
6.1.10 Expansion Connector Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
Function +5V5 +5V5 +5V5 +5V5 RESET_OUT_L TMS. RTCK TCK TDI NC TRST_B NC TDO NC +2V8-1 +2V8-2 +2V8-1 +2V8-2 CPU_GPIO_1 CPU_GPIO_2 UART1_RTS UART1_CTS UART1_RXD UART1_TXD I2C2_SCL PM_RESETB_MCU I2C2_SDA PM_PON_L UART3_RTS UART3_CTS UART3_RXD UART3_TXD KP_COL5 KP_COL4 KP_COL3 KP_COL2 KP_COL1 KP_COL0 KP_ROW5 KP_ROW4 KP_ROW3 KP_ROW2 KP_ROW1 KP_ROW0 FEC_TXD0 25 OF 30
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Function FEC_TXD1 FEC_TXD2 FEC_TXD3 FEC_TX_CLK FEC_TX_ER FEC_TX_EN FEC_RXD0 FEC_RXD1 FEC_RXD2 FEC_RXD3 FEC_RX_CLK FEC_RX_ER FEC_RX_DV FEC_CRS FEC_COL FEC_MDIO FEC_MDC CSI_HSYNC CSI_VSYNC CSI_PIXCLK CSI_MCLK CSI_D0 CSI_D1 CSI_D2 CSI_D3 CSI_D4 CSI_D5 CSI_D6 CSI_D7 EXP_BRD_DET_L BARREL_PWR_PRSNT 5V Power IN 5V Power IN 5V Power IN 5V Power IN Table 9: Expansion Connector Pinout
26 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
7
Firmware/Software Dependencies & Component Configuration Settings
7.1
Hardware Configuration Settings The following sections provide hardware strapping and GPIO assignments on the MX27 reference platform for i.MX27 CPU, ATLAS Companion chip and the STM32F103 MCU
7.1.1
CPU IMX27
7.1.1.1 Configuration Strapping The following tables list the strapping configuration implemented on the Freescale i.MX27 CPU Signal
Value
Boot [3:0]
0000 0010* 0011 0100 0101 0110 0111
Output Signals Active Device (Boot Internal) iROM (Bootstrap USB/UART) iROM (8-bit 2 Kbyte NAND Flash) iROM (16-bit 2 Kbyte NAND Flash) iROM (16-bit 512 byte NAND Flash) iROM (16-bit CS0 at D[15:0] (NOR Flash)) Reserved iROM (8-bit 512 byte NAND Flash)
Output Signals Active Device (Boot External) iROM Bootstrap USB/UART 8-bit 2 Kbyte NAND Flash 16-bit 2 Kbyte NAND Flash 16-bit 512 Kbyte NAND Flash 16-bit CS0 at D[15:0] (NOR Flash) Reserved 8-bit 512B NAND Flash
Boot Address 0x00000030 0xD8000000 0xD8000000 0xD8000000 0xC0000000 0xC0000000 0xD8000000
Table 10: IMX27- Config Strapping * Default Strapping The Default strapping needs to be change to 0000 to use the iROM boot, for booting through UART to program the BGA NAND Flash initially. Installing shorting jumper on J33 will put CPU in iROM boot mode.
7.1.1.2 GPIO Mapping The table below lists signal names assigned to the muxed GPIO pins, and the function of these signals CPU Pin B3
PA27
Function on Audio Puck CPU_TSTOP
D2
PA26
CPU_TSRIGHT
W18 AC19 Y18
PF20 PF19 PF18
EXP_BRD_DET_L PWRFAIL LOBATB
AD19
PF17
PWRRDY
Y19 AC20
RF16 PF14
DC_JACK_PRSNT USB2_RESET_L
GPIO
Comment Resistive gesture touch screen signals. These signals can be driven by the MC13783 signals LEDG1& LEDR1 (pin E11& B10) or the CPU GPIOs PA26 & PA27. Configure the 2 CPU GPIOs as inputs or High Z outputs when ATLAS chip is used to control the resistive gesture touch screen. Make the ATLAS LEDG1 & LEDR1 low when CPU is controlling the resistive gesture touch screen control lines. Expansion board detect signals. Low = Expansion board present High = Voltage at BP (pin B13 of ATLAS) is below UVDET High = Voltage at BP (pin B13 of ATLAS) is below LOWBATL To indicate the Switcher outputs are reached their new set value Normally high, goes low when a new voltage is set on DVS, comes back high again once the voltage reaches the new set point. High = DC Jack plugged in to the expansion board Reset to the USB PHY chip USB3317. CPU must reset the PHY chip once 27 OF 30
THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
CPU Pin
GPIO
Function on Audio Puck
W19
PF13
CSP3_INT
AD20
PF12
ACC_INT1
W20 AC21
PF11 PF10
LS_INT CPU_GPIO_1
U20
PF9
CPU_GPIO_2
AD21 V20 B11
PF8 PF7 PC31
LED_RED LED_GREEN PWROFF
C9
PC30
WDI
A11
PC29
ST_BOOT0
E10
PC28
ST_RESET_L
Comment the GPIOs are stable in order for the PHY to sample the CLKOUT pin as an output. (if the CPU GPIOs drives CLKOUT high during power up, then CLKOUT will become an input on the PHY chip) Primary SPI interrupt from MC13783. Active high Interrupt from Accelerometer. Accelerometer has two configurable interrupt lines. INT2 must be configured as active low in order for this signal to act as the power ON signal. Active low Interrupt from light sensor Used as LCD_RESET signal. GPIO to expansion board for future use. Terminated on the breakout headers on expansion board High = LED ON High = LED ON Signal from CPU for power off after a power fail (Not used) Watch dog to MC13783. Not used by default. Install R228 and R230 to connect WDI to MC13783. WDI on MC13783 is just pulled high by default. (Not used) These signals are used to program the ST chip during every power cycle. Make BOOT0 =1 and pulse ST_RESET_L to program the ST chip through UART2. Make BOOT0= Z and pulse ST_RESET_L to Boot the ST chip in normal mode. Make both signals High Z if not used. Table 11: IMX27- GPIO Mapping
7.1.2
Companion chip-ATLAS-MC13783
7.1.2.1 Configuration strapping Signal
CHRGMOD[1:0]
UMOD[1:0]
Value 00 Z0 10 0Z ZZ 1Z 01 Z1 11 00 0Z 1X 01
Output Signals Active Device (Boot Internal) RESERVED DUAL PATH (Default) SEPERATE INPUT DUAL PATH RESERVED SINGLE PATH SEPERATE INPUT SINGLE PATH
Remarks
Battery charge mode configuration
RESERVED SERIAL PATH SEPERATE INPUT SERIAL PATH SE unidirectional 6-wire SE bidirectional 4-wire Diff unidirectional 6-wire (Default) Diff bidirectional 4-wire
USB OTG input to PHY mode configuration
Table 12: ATLAS – Config Strapping
28 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
7.1.2.2 GPIO Mapping ATLAS Pin G8 F6 E5 G9 E11
GPIO1 GPIO1 GPIO1 GPIO1 LEDG1
B10
LEDR1
GPIO
Function on Audio Puck No Connect No Connect No Connect No Connect Driver for resistive gesture touch panel
Comment This pin is not used. It’s floating. This pin is not used. It’s floating. This pin is not used. It’s floating. This pin is not used. It’s floating. These pins control the FETs used for resistive gesture touch panel. Make these pins low when CPU GPIOs are used for resistive gesture touch panel control
Table 13: ATLAS - GPIO Mapping
7.1.3
Capacitive touch screen micro controller - STM32F103CB
7.1.3.1 Configuration strapping Signal
Value X0 01 11
BOOT[1:0]
Output Signals Active Device (Boot Internal) MAIN FLASH (DEFAULT) SYSTEM MEMORY EMBEDDED SRAM
Remarks STM32F103CB boot mode configuration
Table 14: STM32F103 – Config Strapping
7.1.3.2 GPIO Mapping MCU Pin 43 10
PB7 PA0
Function on Audio Puck ADC_CS_L ADC_INT_L
46
PB9
GPIO_PB9
41
PB5
GPIO_PB5
GPIO
Comment ADC Chip select . Active low Active low interrupt from ADC Connected to GPIO pin of ADC Also drives Red LED, 1 = LED ON Drives GREEN LED, 1 = LED ON Table 15: STM32F103 - GPIO Mapping
7.1.4
Power supply and board specific settings. Set VMMC1 & VMMC2 voltages to 3.0V. (Register 31 and Register 33) Set VSW3 voltage to 5.0V. It defaults to 5.5V (Register 29) Use CPU GPIO PF10 as LCD reset signal.
29 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
8
Manufacturing and Testability
8.1
Design for Manufacturing (DFM) Since the board is not necessarily targeted for manufacturing at a particular contract manufacturer, industry standard DFM guidelines will be used.
8.2
Design for Compliance (DFC) The board will be designed with the following compliance requirements in mind: • • •
8.3 8.3.1
FCC Part 15 (Class B) UL1950 TBD
Design for Testability (DFT) JTAG There are 20 pin standard ARM JTAG connectors for the i.MX27 CPU (Connector on expansion board) and the ST micro controller (Connector on Main board)
8.3.2
In Circuit Testing TBD
30 OF 30 THIS DOCUMENT AND THE INFORMATION CONTAINED HEREIN ARE THE CONFIDENTIAL AND PROPRIETARY PROPERTY OF ARIRA DESIGN, INC. AND ITS CLIENT. DUPLICATION OR DISTRIBUTION PROHIBITED WITHOUT THE PRIOR WRITTEN CONSENT OF ARIRA DESIGN, INC.
