Transcript
EVB-LAN9353 Evaluation Board User’s Guide
2015 Microchip Technology Inc.
DS50002393A
Note the following details of the code protection feature on Microchip devices: •
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-587-0
QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 == DS50002393A-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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EVB-LAN9353 Evaluation Board User’s Guide
Object of Declaration: EVB-LAN9353
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DS50002393A-page 3
EVB-LAN9353 Evaluation Board User’s Guide NOTES:
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EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Table of Contents Preface ........................................................................................................................... 7 Introduction............................................................................................................ 7 Document Layout .................................................................................................. 7 Conventions Used in this Guide ............................................................................ 8 The Microchip Web Site ........................................................................................ 9 Development Systems Customer Change Notification Service ............................ 9 Customer Support ................................................................................................. 9 Document Revision History ................................................................................. 10
Chapter 1. Overview 1.1 Introduction ................................................................................................... 11 1.1.1 References ................................................................................................ 13 1.1.2 Terms and Abbreviations .......................................................................... 14
Chapter 2. Board Details 2.1 Board Details ................................................................................................ 15 2.1.1 Power ........................................................................................................ 15 2.1.2 Power-on Reset ......................................................................................... 15 2.1.3 Clock .......................................................................................................... 16
Chapter 3. Board Configuration 3.1 Strap Options ............................................................................................... 17 3.1.1 Jumpers J4:J15 ......................................................................................... 17 3.1.1.1 GPIO/LED POL/LED Configurations ......................................... 18 3.1.1.2 Serial Management Mode Configuration ................................... 19 3.1.1.3 EEPROM Size Configuration ..................................................... 19 3.1.1.4 Energy-Efficient Ethernet Configuration .................................... 19 3.1.1.5 1588 Enable Configuration ........................................................ 20 3.1.1.6 PHY Address Configuration ....................................................... 20 3.1.2 GPIO 6 & GPIO 7 Input and Output Configurations .................................. 20 3.1.3 Jumper Settings for CONFIG 9 or CONFIG 10 ......................................... 21 3.1.4 Link Partner Duplex/Speed Configurations ............................................... 21 3.1.5 P0/P1 Configurations ................................................................................ 22 3.1.6 RMII RX Clock Configurations ................................................................... 24 3.1.7 GPIO Header ............................................................................................. 24 3.1.8 I2C Aardvark Header ................................................................................. 25 3.1.9 Copper and Fiber Mode Selections ........................................................... 25 3.1.9.1 Copper Mode ............................................................................. 25 3.1.9.2 Fiber Mode ................................................................................ 25 3.1.9.3 FX-LOS Fiber Mode Strap ......................................................... 26
3.2 LEDs ............................................................................................................. 26 3.3 Test Points ................................................................................................... 27
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EVB-LAN9353 Evaluation Board User’s Guide 3.4 Mechanicals ................................................................................................. 27
Appendix A. EVB-LAN9353 Evaluation Board A.1 Introduction .................................................................................................. 28
Appendix B. EVB-LAN9353 Evaluation Board Schematics B.1 Introduction .................................................................................................. 29
Appendix C. Bill of Materials (BOM) C.1 Introduction .................................................................................................. 39
Wordwide Sales and Service ......................................................................................43
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EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Preface NOTICE TO CUSTOMERS All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available. Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document. For the most up-to-date information on development tools, see the MPLAB® IDE online help. Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION This chapter contains general information that will be useful to know before using the EVB-LAN9353. Items discussed in this chapter include: • • • • • •
Document Layout Conventions Used in this Guide The Microchip Web Site Development Systems Customer Change Notification Service Customer Support Document Revision History
DOCUMENT LAYOUT This document describes how to use the EVB-LAN9353 Evaluation Board as a development tool for the LAN9353 three-port 10/100 managed Ethernet switch. The manual layout is as follows: • Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9353 Evaluation Board. • Chapter 2. “Getting Started” – Includes instructions on how to get started with the EVB-LAN9353 Evaluation Board. • Chapter 3. “Board Configuration” – Provides information about the EVB-LAN9353 Evaluation Board battery charging features. • Appendix A. “EVB-LAN9353 Evaluation Board” – This appendix shows the EVB-LAN9353 Evaluation Board. • Appendix B. “EVB-LAN9353 Evaluation Board Schematics” – This appendix shows the EVB-LAN9353 Evaluation Board schematics. • Appendix C. “Bill of Materials (BOM)” – This appendix includes the EVB-LAN9353 Evaluation Board Bill of Materials (BOM).
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EVB-LAN9353 Evaluation Board User’s Guide CONVENTIONS USED IN THIS GUIDE This manual uses the following documentation conventions: DOCUMENTATION CONVENTIONS Description Arial font: Italic characters
Represents Referenced books Emphasized text A window A dialog A menu selection A field name in a window or dialog A menu path
MPLAB® IDE User’s Guide ...is the only compiler... the Output window the Settings dialog select Enable Programmer “Save project before build”
A dialog button A tab A number in verilog format, where N is the total number of digits, R is the radix and n is a digit. A key on the keyboard
Click OK Click the Power tab 4‘b0010, 2‘hF1
Italic Courier New
Sample source code Filenames File paths Keywords Command-line options Bit values Constants A variable argument
Square brackets [ ]
Optional arguments
Curly brackets and pipe character: { | } Ellipses...
Choice of mutually exclusive arguments; an OR selection Replaces repeated text
#define START autoexec.bat c:\mcc18\h _asm, _endasm, static -Opa+, -Opa0, 1 0xFF, ‘A’ file.o, where file can be any valid filename mcc18 [options] file [options] errorlevel {0|1}
Initial caps
Quotes Underlined, italic text with right angle bracket Bold characters N‘Rnnnn
Text in angle brackets < > Courier New font: Plain Courier New
Represents code supplied by user
DS50002393A-page 8
Examples
File>Save
Press ,
var_name [, var_name...] void main (void) { ... }
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Preface THE MICROCHIP WEB SITE Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. The Development Systems product group categories are: • Compilers – The latest information on Microchip C compilers, assemblers, linkers and other language tools. These include all MPLAB C compilers; all MPLAB assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all MPLAB librarians (including MPLIB object librarian). • Emulators – The latest information on Microchip in-circuit emulators.This includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators. • In-Circuit Debuggers – The latest information on the Microchip in-circuit debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express. • MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as well as general editing and debugging features. • Programmers – The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3.
CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • •
Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support
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EVB-LAN9353 Evaluation Board User’s Guide Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support
DOCUMENT REVISION HISTORY Revision A (July 2015) • Initial Release of this Document.
DS50002393A-page 10
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EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Chapter 1. Overview 1.1
INTRODUCTION The LAN9353 is a fully featured, three-port 10/100 managed Ethernet switch designed for industrial and embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9353 combines all the functions of a 10/100 switch system, including the switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY transceivers, and serial management. IEEE 1588v2 is supported via the integrated IEEE 1588v2 hard-ware time stamp unit, which supports end-to-end and peer-to-peer transparent clocks. The LAN9353 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and 100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE) (100Mbps only), and 802.1D/802.1Q management protocol specifications, enabling compatibility with industry standard Ethernet and Fast Ethernet applications. 100BASE-FX is supported via an external fiber transceiver and cable diagnostics (short, open and length) is included on the internal twisted pair copper interface. The EVB-LAN9353 is an Evaluation Board (EVB) that utilizes the LAN9353 to provide a fully-functional three-port Ethernet switch with Single MII/RMII/Turbo MII or Dual RMII. The EVB-LAN9353 provides one fully integrated MAC/PHY internet port (Port 2) via on-board RJ45 connectors. Port 0 and Port 1 provides two MII port connectors which support the following: • An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable MAC (with LAN9353 in PHY mode), via the on-board 40-pin male MII connector • An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable PHY (with LAN9353 in MAC mode), via the on-board 40-pin female MII connector Power is supplied to the board via a +5V external wall mount power supply. The EVB-LAN9353 includes a 64K x 8 I2C EEPROM that may be used to automatically load configuration settings from the EEPROM into the device at reset. An I2C host adapter interface header (10-pin, 2x5) is provided to simplify I2C based configuration. A simplified block diagram of the EVB LAN9353 can be seen in Error! Reference source not found and LAN9353 supports for CONFIG 9 or CONFIG 10. CONFIG 9: used to configure the LAN9353 in Dual RMII mode for external ports. CONFIG 10: used to configure the LAN9353 in Single MII/RMII/TMII mode for external port.
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EVB-LAN9353 Evaluation Board User’s Guide FIGURE 1-1:
EVB-LAN9353 BLOCK DIAGRAM (CONFIG 9) To External MAC
To External PHY
To External PHY
To External MAC
40 pin MII Connector (Male)
40 pin MII Connector (Female)
40 pin MII Connector (Female)
40 pin MII Connector (Male)
RMII Mode Switch
I2C EEPROM
Straps Jumpers
RMII Port 1
Port 0
Power Supply Module
Microchip LAN9353
5V
Reset
Crystal Port 2
10/100 Ethernet Magnetics & RJ45
Fiber Transceiver (SFP)
Ethernet
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FIGURE 1-2:
EVB-LAN9353 BLOCK DIAGRAM (CONFIG 10) To External PHY
To External MAC
40 pin MII Connector (Female)
40 pin MII Connector (Male)
MII/RMII/TMII Port 0
Mode Switch
Microchip LAN9353
I2C EEPROM
Straps Jumpers
Fiber Transceiver (SFP)
5V
Reset
Crystal Port 1
Port 2
10/100 Ethernet Magnetics & RJ45
10/100 Ethernet Magnetics & RJ45
Ethernet
1.1.1
Power Supply Module
Fiber Transceiver (SFP)
Ethernet
References
Concepts and material available in the following documents may be helpful when reading this document. Visit www.microchip.com for the latest documentation. Document LAN9353 datasheet
Location Visit www.microchip.com
AN8-13 Suggested Mag- http://www.microchip.com/wwwApnetics pNotes/AppNotes.aspx?appnote=en562793 EVB-LAN9353 Evaluation Board Schematic
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EVB-LAN9353 Evaluation Board User’s Guide 1.1.2 • • • • • • • • • •
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Terms and Abbreviations
EVB - Evaluation Board DNP - Do Not Populate 100BASE-TX - 100 Mbps Fast Ethernet, IEEE802.3u Compliant GPIO - General Purpose I/O MII - Media Independent Interface RMII - Reduced Media Independent Interface EEE - Energy-Efficient Ethernet SFP - Small Form-factor Pluggable SFF - Small Form Factor SMI - Serial Management Interface
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EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Chapter 2. Board Details 2.1
BOARD DETAILS The following sections describe the various board features, including jumpers, LEDs, test points, system connections, and switches. A top view of the EVB-LAN9353 is shown in Figure 2-1. FIGURE 2-1:
LAN9353 BOARD REV-A EEPROM
Strap
Mode Switch
Power
Reset
Port 1** (Female) MII Connector
Port 0 (Female) MII Connector
Port 1** (Male) MII Connector
Port 0 (Male) MII Connector
Microchip LAN9353
Port 1** (with integrated magnetics & LEDs)
Note:
2.1.1
Port 2 (with integrated magnetics & LEDs)
Config 10: Port 1 and Port 2 both are Internal, Port 0 External. Config 9: Only Port 2 Internal, Port 0 and Port 1 are External.
Power
DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter. switch (SW1) need to be ON position for the 5V to reach the 3.3V regulator. Glowing of Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to the LAN9353 and it has internal 1.2 V regulator which supplies power to the internal core logic.
2.1.2
Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9353 or if the power is removed and reapplied to the LAN9353. This event resets all circuitry within the LAN9353. After initial power-on, the LAN9353 can be reset by pressing the reset switch (SW2). The reset LED D2 will assert (red) when the LAN9353 is in reset condition.
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EVB-LAN9353 Evaluation Board User’s Guide For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset release.
2.1.3
Clock
The LAN9353 requires a fixed-frequency 25 MHz clock (±50 ppm) source for use by the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz crystal to the OSCI and OSCO pins. Optionally, this clock can be provided by driving the OSCI input pin with a single-ended 25 MHz clock source.
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EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Chapter 3. Board Configuration 3.1
STRAP OPTIONS The following tables describe the default settings and jumper descriptions for the EVB-LAN9353. These defaults are the recommended configurations for evaluation of the LAN9353. These settings may be changed as needed, however, any deviation from the defaults settings should be approached with care and knowledge of the schematics and datasheet. An incorrect jumper setting may disable the board.
3.1.1
Jumpers J4:J15
Jumpers J4 through J15 set various functions of the LAN9353. They can also be used as GPIOs, LED drivers. When used as LED drivers, as they are on the EVB-LAN9353, they are connected a specific way to set the strap value to a “1”, and another way to set the strap value to a “0” Figure 3-1 illustrates the schematics connections with the D3 circuit as a pull-up, and the D4 circuit as a pull-down. To illuminate D3, the LAN9353 will drive the cathode of the D3 low. To illuminate D4, the LAN9353 will drive the cathode of the D4 high. The J4 - J15 jumpers must be configured in pairs to identical settings in order to realize the D3 circuit or the D4 circuit. The pairings are as follows: -
J4 & J7 J6 & J9 J5 & J8 J11 & J14 J10 & J13 J12 & J15
The following subsections detail the jumper pair settings, their associated strap settings, and the functional effects of setting the straps. All strap values are read during power-up and on the rising edge of nRST signal. Once the strap value is set, the LAN9353 will drive the LED’s high or low for illumination according the strap value. For other designs which may use these pins as GPIOs refer to LAN9353 datasheet for additional information. In those cases, internal default straps must be changed by an I2C or SMI master or through EEPROM fields.
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EVB-LAN9353 Evaluation Board User’s Guide FIGURE 3-1:
3.1.1.1
LED STRAP CIRCUIT
GPIO/LED POL/LED CONFIGURATIONS:
GPIO/LED POL/LED configuration straps are used to configure the default polarity of LEDs, GPIOs through jumpers as shown below in Table 3-1. TABLE 3-1:
GPIO/LED POL/LED CONFIGURATIONS
Header
Pin Settings
Signal Name
Strap Value
Description
J4 & J7
1-2(default)
LEDPOL0 /GPIO0 /LED0
1
The LED (D3) is set as active LOW.
0
The LED (D3) is set as active HIGH.
1
The LED (D4) is set as active LOW.
0
The LED (D4) is set as active HIGH.
1
The LED (D5) is set as active LOW.
0
The LED (D5) is set as active HIGH.
1
The LED (D6) is set as active LOW.
0
The LED (D6) is set as active HIGH.
2 -3
J5 & J8
1-2(default)
LEDPOL1 /GPIO1 /LED1
2 -3
J6 & J9
1-2(default)
LEDPOL2 /GPIO2 /LED2
2 -3
J10 & J13
1-2(default)
2 -3
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LEDPOL3 /GPIO3 /LED3
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TABLE 3-1:
GPIO/LED POL/LED CONFIGURATIONS (CONTINUED)
Header
Pin Settings
Signal Name
Strap Value
Description
J11 & J14
1-2(default)
LEDPOL4 /GPIO4 /LED4
1
The LED (D7) is set as active LOW.
0
The LED (D7) is set as active HIGH.
1
The LED (D8) is set as active LOW.
0
The LED (D8) is set as active HIGH.
2 -3
J12 & J15
1-2(default)
LEDPOL5 /GPIO5 /LED5
2 -3
3.1.1.2
SERIAL MANAGEMENT MODE CONFIGURATION
Serial Management Mode selection strap (MNGT0) is used to configure the default value of the Serial Management Mode Strap hard-strap (serial_mngt_mode_strap) through jumpers as shown below in Table 3-2. TABLE 3-2: Header
SERIAL MANAGEMENT MODE CONFIGURATION Pin Settings
serial_mngt_mode_ strap
Description
J4 & J7
2-3
0
SMI Managed Mode
J4 & J7
1-2 (default)
1
I2C Managed Mode
3.1.1.3
EEPROM SIZE CONFIGURATION:
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512 as shown below in Table 3-3. TABLE 3-3:
EEPROM SIZE CONFIGURATION
Header
Pin Settings
eeprom_size_strap Value
J6 & J9
1-2 (default)
1
EEPROM size = 32K bits (4k x 8) through 512K bits (64K x 8)
2 -3
0
EEPROM size = 1K bits (128 x 8) through 16K bits (2K x 8)
3.1.1.4
Description
ENERGY-EFFICIENT ETHERNET CONFIGURATION
EEE_EN configuration strap is used to configure the default value of the EEE Enable 2-1 soft-straps (EEE_enable_strap_[2:1]) through jumpers as shown below in Table 3-4. Note:
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“EEE_enable_strap_1” strap is used for the LAN9353 when in Port 1 internal PHY mode.
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EVB-LAN9353 Evaluation Board User’s Guide TABLE 3-4:
EEE_EN CONFIGURATION
Header
Pin Settings
EEE_enable_strap_[ 2:1] Value
J10 & J13
1-2(default)
1
EEE Enable
2 -3
0
EEE Disable
3.1.1.5
Description
1588 ENABLE CONFIGURATION
Energy Efficient Ethernet configuration strap is used to configure the default value of the 1588 Enable soft-strap (1588_enable_strap) through jumpers as shown below in Table 3-5. TABLE 3-5:
1588 ENABLE CONFIGURATION
Header
Pin Settings
1588_enable_strap Value
J11 & J14
1-2 (default)
1
1588 Enable
2 -3
0
1588 Disable
3.1.1.6
Description
PHY ADDRESS CONFIGURATION
PHY Address selection strap is used to configure the default value of the Switch PHY Address Select soft-strap (phy_addr_sel_strap) through jumpers as shown below in Table 3-6. TABLE 3-6:
PHY ADDRESSING VIRTUAL PHY 0 AND 1 PHY_ADDR_SEL DEFAULT _STRAP Value ADDRESS VALUE
PHY A DEFAULT ADDRESS VALUE
PHY B DEFAULT ADDRESS VALUE
Header
Pin Settings
J12 & J15
1-2
1
1
2
3
2-3 (default)
0
0
1
2
3.1.2
GPIO 6 & GPIO 7 Input and Output Configurations
GPIO 6 & 7 configuration straps are used to configure the default input value of the GPIO 6 and 7 through jumpers as shown below in Table 3-7 and Table 3-8. TABLE 3-7: Header
Pin Settings
Input
J20
1-2
1
J21
TABLE 3-8:
2-3
0
1-2
1
2-3
0
Signal Name GPIO6 GPIO7
GPIO 6 & 7 OUTPUT CONFIGURATION
Header
Pin
Output
J20
2
Push Pull
GPIO6
J21
2
Push Pull
GPIO7
Note:
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GPIO 6 & 7 INPUT CONFIGURATION
Signal Name
By default, the jumpers settings for J20 & J21 will be OPEN.
2015 Microchip Technology Inc.
3.1.3
Jumper Settings for CONFIG 9 or CONFIG 10
CONFIG 9: Used to configure the LAN9353 in Dual RMII mode by using jumpers as shown below in Table 3-9. Port 0: RMII PHY, RMII MAC modes Port 1: RMII MAC, RMII PHY modes Port 2: Internal PHY CONFIG 10: Used to configure the LAN9353 in Single MII/RMII/TMII mode by using jumpers as shown below in Table 8 Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC, TMII MAC, TMII PHY modes Port 1: Internal PHY Port 2: Internal PHY TABLE 3-9:
CONFIG 9 OR CONFIG 10 SETTINGS
SW11 SW12 SW13 SW14 SW15 SW16 SW17 SW18
Mode
Configurations
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
2 RMII
CONFIG 9
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1xMII/RMII/T MII (DEFAULT)
CONFIG 10
Note:
3.1.4
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Link Partner Duplex/Speed Configurations
CONFIG 9 or CONFIG 10 must be configured before Link partner Duplex/Speed configurations. For a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section 3.1.3. The “duplex_strap_0” strap from J28 is used to determine the link partners duplex ability when in Port 0 MII MAC and RMII MAC modes as shown below in Table 3-10. The “speed_strap_0” strap from J29 is used to determine the link partners speed ability and to determine the parallel detect speed when in Port 0 “MII MAC and RMII MAC” modes as shown below in Table 3-10. TABLE 3-10: J28 (P0_DUPLEX)
EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY FOR PORT 0 J29 (P0_SPEED) duplex_strap_0
speed_strap_0
ADVERTISED LINK PARTNER ABILITY
1-2
2-3
1
0
10BASE-T full-duplex (0010)
1-2
1-2
1
1
100BASE-X full-duplex (1000)
2-3
2-3
0
0
10BASE-T half-duplex (0001)
2-3
1-2
0
1
100BASE-X half-duplex (0100)
Note:
2015 Microchip Technology Inc.
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
DS50002393A-page 21
EVB-LAN9353 Evaluation Board User’s Guide The “duplex_strap_1” strap from J30 is used to determine the link partners duplex ability when in Port 1 RMII MAC mode as shown below in Table 10. The “speed_strap_1” strap from J31 is used to determine the link partners speed ability and to determine the parallel detect speed when in Port 1 “RMII MAC” mode as shown below in Table 3-11. TABLE 3-11: J30 (P1_DUPLEX)
EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY FOR PORT 1 J31 (P1_SPEED) duplex_strap_1
ADVERTISED LINK PARTNER ABILITY
speed_strap_1
1-2
2-3
1
0
10BASE-T full-duplex (0010)
1-2
1-2
1
1
100BASE-X full-duplex (1000)
2-3
2-3
0
0
10BASE-T half-duplex (0001)
2-3
1-2
0
1
100BASE-X half-duplex (0100)
Note:
3.1.5
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Port 0/Port 1 Mode Configurations
CONFIG 9 or CONFIG 10 must be configured before P0/P1 mode configurations. For a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section 3.1.3 P0 Mode configuration straps (SW5, SW6, SW7 & SW8) are used to configure the hard-straps such as Switch Port 0 Mode Strap (P0_mode_strap[1:0]), Switch Port 0 RMII Clock Direction Strap (P0_rmii_clock_dir_strap) and Switch Port 0 Clock Strength Strap (P0_clock_strength_strap) as shown below in Table 3-12. TABLE 3-12: P1_ INTPHY (J5 & J8)
DS50002393A-page 22
PORT 0 MODE STRAP MAPPING
P0_MODE3 P0_MODE2 P0_MODE1 P0_MODE0 (SW8) (SW9) (SW7) (SW5)
MODE
1-2
1-3
1-3
X
X
MII MAC
1-2
1-3
1-2
1-3
X
MII PHY
1-2
1-3
1-2
1-2
1-3
Turbo MII PHY 12 ma
1-2
1-3
1-2
1-2
1-2
Turbo MII PHY 16 ma
2-3
X
1-3
1-3
X
1-2
1-2 1-3
1-2
1-3
RMII MAC clock out 12ma
1-3
1-2
1-2
RMII MAC clock out 16ma
1-2
1-3
X
2-3
X
1-2
1-2
2-3
X
1-2
1-2
2-3
X
1-2
1-2
RMII MAC clock in (default)
RMII PHY clock in
2015 Microchip Technology Inc.
TABLE 3-12: P1_ INTPHY (J5 & J8)
PORT 0 MODE STRAP MAPPING (CONTINUED)
P0_MODE3 P0_MODE2 P0_MODE1 P0_MODE0 (SW8) (SW9) (SW7) (SW5)
2-3
X
1-2
1-2
2-3
X
1-2
1-2
MODE
1-2
1-2
1-3
RMII PHY clock out 12ma
1-2
1-2
1-2
RMII PHY clock out 16ma
Note:
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Note:
SW8 will be used for Port 0 when LAN9353 is configured in Single MII/TMII/RMII Mode and SW8 will be ignored when LAN9353 is in Dual RMII mode.
P1 Mode configuration straps (SW10, SW8, SW6 & J5/J8) are used to configure the hard-straps such as Switch Port 1 Mode Strap (P1_mode_strap[1:0]), Switch Port 1 RMII Clock Direction Strap (P1_rmii_clock_dir_strap) and Switch Port 1 Clock Strength Strap (P1_clock_strength_strap) as shown below in Table 3-13. TABLE 3-13:
PORT 1 MODE STRAP MAPPING
P1_INTPHY (J5 & J8)
P1_MODE2 (SW10)
P1_MODE1 (SW8)
P1_MODE0 (SW6)
2-3
1-3
1-3
X
2-3
1-3
1-2
1-3
RMII MAC clock out 12ma
2-3
1-3
1-2
1-2
RMII MAC clock out 16ma
2-3
1-2
1-3
X
2-3
1-2
1-2
1-3
RMII PHY clock out 12ma
2-3
1-2
1-2
1-2
RMII PHY clock out 16ma
1-2
X
X
X
MODE RMII MAC clock in (default)
RMII PHY clock in
Internal PHY
Note:
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
Note:
SW8 will be used for Port 1 when LAN9353 is configured in Dual RMII Mode and SW8 will be ignored when LAN9353 is in Single MII/TMII/RMII mode.
2015 Microchip Technology Inc.
DS50002393A-page 23
EVB-LAN9353 Evaluation Board User’s Guide 3.1.6
RMII RX Clock Configurations
When LAN9353 is in MAC/PHY mode the reference clock routed either through TX or RX Clock as shown in Table 3-14 for Port 0 and Table 3-15 for Port 1. TABLE 3-14:
RX CLOCK CONFIGURATIONS FOR PORT 0
Switch Settings
DESCRIPTION
Mode
SW23 (1-3) (Default)
TX Clock used as a Reference Clock
RMII MAC
SW23 (1-2)
RX Clock used as a Reference Clock
RMII MAC
SW24 (1-3) (Default)
Reference clock used as a TX RMII PHY clock
SW24 (1-2)
Reference clock used as a RX RMII PHY clock
Note:
When Port 0 configured in RMII mode, short Jumper J25 (1-2).
TABLE 3-15:
RMII RX CLOCK CONFIGURATIONS FOR PORT 1
Switch Settings
DESCRIPTION
Mode
SW25 (1-3) (Default)
TX Clock used as a Reference Clock
RMII MAC
SW25 (1-2)
RX Clock used as a Reference Clock
RMII MAC
SW26 (1-3) (Default)
Reference clock used as a TX RMII PHY clock
SW26 (1-2)
Reference clock used as a RX RMII PHY clock
Note:
External PHY considered LAN8742.
Note:
For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.
3.1.7
GPIO Header
J27 header is used for GPIO. Pin details are given below in Table 3-16. TABLE 3-16:
DS50002393A-page 24
PIN NAMES FOR GPIO HEADER Signal Name
Pin Number
GPIO0
J27.1
GPIO1
J27.2
GPIO2
J27.3
GPIO3
J27.4
GPIO4
J27.5
GPIO5
J27.6
GPIO6
J27.7
GPIO7
J27.8
2015 Microchip Technology Inc.
3.1.8
I2C Aardvark® Header
J16 connector is used for I2C Aardvark header. Respective pin details are given below in Table 3-17. TABLE 3-17:
3.1.9
PIN NAMES FOR I2C AARDVARK HEADER Signal Name
Pin Number
I2C2_SCL
J16.1
I2C2_SDA
J16.3
GND
J16.2 & J16.10
Copper and Fiber Mode Selections
The LAN9353 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In 100BASE-FX operation, the presence of the receive signal is indicated by the external transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL Signal Detect (SFF). This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By default Copper Mode is active. Fiber Mode is supported as an assembly option. To select the Copper or Fiber Mode, the respective strap and signal routing resister assembly options must to be configured. Note: 3.1.9.1
Vendor part number for SFP Transceiver: Finisar/FTLF1217P2. COPPER MODE
The EVB-LAN9353 is set to Copper Mode by default. Table 3-18 details the required strap resistors settings for Copper Mode operation. TABLE 3-18: Resistors R79 (10K)
COPPER MODE STRAP RESISTORS Signal Names FXLOSEN
Description Copper twisted pair for ports A and B further determined by FXSDENA and FXSDENB
R76, R80 (10K) FXSDA/FXSDB Configures Port 0 and Port 1 to Copper Mode
Note:
R75, R77, and R78 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 3-19 must be assembled for Copper Mode operation. TABLE 3-19:
COPPER MODE SIGNAL ROUTING RESISTORS Resistors
Description
R17, R19, R21, R23
Port 0 Copper mode is Enabled
R31, R33, R35, R37
Port 1 Copper mode is Enabled
Note:
3.1.9.2
R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be populated (DNP). FIBER MODE
The LAN9353 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the respective strap and signal routing resisters must be configured. Note:
2015 Microchip Technology Inc.
Copper Mode related resistors must be DNP while Fiber Mode is active (See Section 3.1.9.1 “Copper Mode”).
DS50002393A-page 25
EVB-LAN9353 Evaluation Board User’s Guide Table 3-20 details the required strap resistor settings for Fiber Mode operation. TABLE 3-20:
FIBER MODE STRAP RESISTORS Resistors
Description
R77 (10K)
Configures Port 0 & 1 to FX_LOS Mode
R75, R78 (10K)
Configures Port 0 & 1 to Fiber mode, respectively
Note:
R76, R79, and R80 must not be populated (DNP).
Additionally, the signal routing resistors detailed in Table 3-21 must be assembled for Fiber Mode operation. TABLE 3-21:
FIBER MODE SIGNAL ROUTING RESISTORS Resistors
Description
R16, R18, R20, R22
Port 0 Fiber mode Enabled
R30, R32, R34, R36
Port 1 Fiber mode Enabled
Note:
3.1.9.3
R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be populated (DNP). FX-LOS FIBER MODE STRAP
FX-LOS strap details are shown in Table 3-22. These strap settings determine if the ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode. TABLE 3-22:
FX-LOS MODE STRAP SETTINGS Reference Voltage (v)
R77 (10K) R79 (10K) Populate
DNP
3.3
A level above 2V selects FX-LOS for Port 0 and Port 1
Populate
Populate
1.5
A level of 1.5V selects FX-LOS for Port 0 and FX-SD / Copper twisted pair for Port 1, further determined by FXSDB
DNP
Populate
0 (Default)
A level of 0V selects FX-SD / Copper twisted pair for Ports 0 and 1, further determined by FXSDA, FXSDB
Note:
3.2
Function
The above strap details describe the LAN9353 function. This EVB does not support SFF Fiber Mode. Therefore, FX-SD related straps are not applicable.
LEDS Table 3-23 describes the different LED references and their corresponding colors and indications TABLE 3-23:
LEDS
Reference
Indication
D1
Green
3.3V Power active
D2
Red
LAN9353 is in reset condition
D4
Green
Full-duplex / Collision Port 1
D7
Green
Full-duplex / Collision Port 2
Note:
DS50002393A-page 26
Color
Assumes the LED_FUN field of the LED_CFG register is 00b.
2015 Microchip Technology Inc.
3.3
TEST POINTS Table 3-24 describes the different test points and their corresponding connections. TABLE 3-24: Test Points
3.4
TEST POINTS Description
Connection
TP1
Single pin populated 5V
5V_EXT
TP2
Single pin populated 3V3
3V3
TP3
Single pin unpopulated VDDCR
VDDCR
TP4
Single pin unpopulated IRQ
IRQ
TP5
Single pin unpopulated P0_MDC
P0_MDC
TP6
Single pin unpopulated P0_MDIO
P0_MDIO
TP7
Single pin unpopulated P1_MDC
P1_MDC
TP8
Single pin unpopulated P1_MDIO
P1_MDIO
TP9
Single pin populated GND
GND
TP10
Single pin populated GND
GND
MECHANICALS Figure 3-2 displays details for EVB-LAN9353 mechanical dimensions. Dimension are in mm. FIGURE 3-2:
2015 Microchip Technology Inc.
LAN9353 EVB MECHANICAL DIMENSIONS
DS50002393A-page 27
EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Appendix A. EVB-LAN9353 Evaluation Board A.1
INTRODUCTION
This appendix shows the EVB-LAN9353 Evaluation Board. FIGURE A-1:
EVB-LAN9353 EVALUATION BOARD
2015 Microchip Technology Inc.
DS50002393A-page 28
EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Appendix B. EVB-LAN9353 Evaluation Board Schematics B.1
INTRODUCTION
This appendix shows the EVB-LAN9353 Evaluation Board Schematics.
2015 Microchip Technology Inc.
DS50002393A-page 29
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 1
EVB-LAN9353 Block Diagram (Config 10) 40 Pin MII Connector (Male)
40 Pin MII Connector (Female)
EVB-LAN9353 Block Diagram (Config 9) 40 Pin MII Connector (Male)
MII/RMII/TMII Mode Switch I2C EEPROM/ Header
Microchip LAN9353
Straps Jumpers Port 1
Fiber Trasnceiver(SFP) Port 1
10/100 Ethernet Magnetics & RJ45
Mode Switch
Reset Switch
I2C EEPROM/ Header
Crystal
Straps Jumpers
Port 2
10/100 Ethernet Magnetics & RJ45
40 Pin MII Connector (Female)
40 Pin MII Connector (Male) RMII
RMII Power Supply Module
Port 0
40 Pin MII Connector (Female)
Port 1
Port 0
Power Supply Module
Microchip LAN9353
Reset Switch
Crystal Port 2
Fiber Trasnceiver(SFP) Port 2
10/100 Ethernet Magnetics & RJ45
Fiber Trasnceiver(SFP) Port 2
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 30
FIGURE B-1:
2015 Microchip Technology Inc.
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 2 POWER SUPPLY
FB1
2
5V_SW
3
R1 0
2A/0.05DCR
2 J1
Switch, SPDT, Slide P/N:1101M2S3CQE2
C2 10uF 25V
3-$+
EN12_1
2 1
VIN ENABLE
VOUT TRIM
3_Amp
GND
C3 0.1uF
4 5
R2 1K
VOUT_3V3 C1
3
OKR-T/3-W12-C
R3 3.30K 1%
(Ra)
R4 470E 1%
(Rb)
R4A 33E 1%
C4
C5
10uF
4.7uF DNP
1
1
A
5V_EXT
3
3V3 3V3
0.1uF
D1 GRN
C
1
TP2 ORANGE
3 .3V REGULATOR, 3A ( 3V3 fixed when Rb=503e) U1
2
TP1 RED 5V
SW1
"3V3 Present"
2015 Microchip Technology Inc.
FIGURE B-2:
3V3 3V3 3V3
RESET
3
R8
1K
2
NDS355AN_NMOS
1
D
RST# Q1
1 G
5
RESET#
3
VDD
3V3
MR#
2
4
5
U2 2 1/10W 1%
S
74LVC1G14
1 3
Reset Generator
TP10 BLACK
4
TPS3125 SOT23_5 Threshold = 2.64V Delay = 180ms
TP9 BLACK
RED U3
2
R9 2.2K
1
A D2 "Reset"
C
2
DS50002393A-page 31
EVB-LAN9353 Evaluation Board User’s Guide
sw_pb_2P
1 R7 100
GND
SW2
R5 4.75K 1%
0.1uF
2
1
C6 R6 10.0K 1/10W 1%
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 3 3V3
Power Supply Filtering
VDD33TXRX1 FB2
3V3
2A/0.05DCR
VDDCR
VDD12TX1 VDD12TX2
0.1uF
VDD33TXRX1 VDD33TXRX2
BLM18EG221SN1D
FB5 2A/0.05DCR
12.1K 1%
RBIAS RST#
TP4 WHITE DNP
IRQ ATEST/FXLOSEN
7 57 11 44 8 41
I2C2_SCL I2C2_SDA
43 42
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
48 46 45 34 18 17 13 12
RBIAS RST# IRQ ATEST/FXLOSEN TESTMODE
I2CSCL/EESCL/TCK I2CSDA/EESDA/TMS
56 59 VDD12TX1 VDD12TX2
6 24 38
TXNA TXPA RXNA RXPA
TXNB TXPB RXNB RXPB
FXSDENB/FXSDB/FXLOSB
GPIO0/LED0/TDO/LEDPOL0/MNGT0 GPIO1/LED1/TDI/LEDPOL1/P1_INTPHY GPIO2/LED2/LEDPOL2/E2PSIZE GPIO3/LED3/LEDPOL3/EEEEN GPIO4/LED4/LEDPOL4/1588EN GPIO5/LED5/LEDPOL5/PHYADD GPIO6 GPIO7 LAN9353
VDDCR_1 VDDCR_2 VDDCR_3
14 20 32 37 47 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5
58 5
REG_EN
GND
REG_EN R10
2015 Microchip Technology Inc.
65
18pF
FXSDENA/FXSDA/FXLOSA
INT PORT0
C27
OSCVDD12 OSCI OSCO OSCVSS
INT PORT1
1
3 1 2 4
OTHER SIGNALS
OSCI OSCO 3V3
OSC
POWER
25.000MHz 25ppm
Y1
I2C
18pF
2
C26
VDD33BIAS VDD33
U4A
Note: OSCVSS need to connect to Chip gnd.
VDD33TXRX1 VDD33TXRX2
51 64
VDD12TX1 VDD12TX2
0.1uF
C25
9
FXSDA/FXLOSA
52 53 54 55
TXNA TXPA RXNA RXPA
63 62 61 60
TXNB TXPB RXNB RXPB
10
FXSDB/FXLOSB
C20
C21
C22
0.1uF
0.1uF
1uF
C18 0.1uF
C16
C14
C15
C13
C12 DNP
C11
C17 0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
TP3 SMT
VDDCR
470pF
3V3
Low ESR C19
3V3 2A/0.05DCR
C24
1.0uF
3V3 FB4
C23 1.0uF DNP
0.1uF
C9
2A/0.05DCR
C10
0.1uF VDD33TXRX2
0.1uF
FB3
C8
DNP 1.0uF
C7 1.0uF DNP
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 32
FIGURE B-3:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 4 /,1.$&7
330E LED2_ANODE
0E
DNP R16 R17
0 0
FX_SFP-TXPA
TXNA
DNP R18 R19
0 0
FX_SFP-TXNA
RXPA
DNP R20 R21
0 0
RXNA
DNP R22 R23
0 0
R12 49.9 1/10W 1%
R13 49.9 1/10W 1%
R14 49.9 1/10W 1%
9
C
R11 49.9 1/10W 1%
10
T1 Pulse J0011D01BNL R15 0
GRN 1
COP-TXPA
4 2
COP-TXNA
A
FB6
3257
TXPA
R61
LED2_CATHODE
VDD33TXRX1
RJ45
XMIT TD+
75
75
1
TXCT
4&5
TD-
2
'HIDXOWDVVHPEO\ LED1 (Green) = LINK/ACT
8
50V 10%
6
RD-
1000 pF
NC
2 kV
CHS GND
R62 R24
330E
LED0_CATHODE
0
LED0_ANODE
63(('
RES1210
/,1.$&7
VDD33TXRX2
R102
330E LED5_ANODE
LED5_CATHODE
0 0
DNP R32 R33
0 0
FX_SFP-TXNB
RXPB
DNP R34 R35
0 0
FX_SFP-RXPB
RXNB
DNP R36 R37
0 0
TXNB
FX_SFP-TXPB
R26 49.9 1/10W 1%
R27 49.9 1/10W 1%
R28 49.9 1/10W 1%
9
C
R25 49.9 1/10W 1%
10
T2 Pulse J0011D01BNL
DNP R30 R31
TXPB
0E
R29 0
GRN 1
COP-TXPB
4 2
COP-TXNB
A
3257
FB7
RJ45
XMIT TD+
75
75
1
TXCT
4&5
TD-
2 LED1 (Green) = LINK/ACT
Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment.
2 kV
CHS GND
A1
YEL C1
8
6 1000 pF
NC
12
DS50002393A-page 33
1RWH )%DQG)%WREH]HURRKPV
50V 10%
7
11
C36 10pF 50V 5% DNP
MTG1
C35 10pF 50V 5% DNP
MTG
C34 10pF 50V 5% DNP
3 7&8
RD-
16
C33 10pF 50V 5% DNP
75
RXCT
15
6 C37 0.022uF
GND1
COP-RXNB
75
GND
FX_SFP-RXNB
LED2 (Yellow) = SPEED
RD+
14
5
13
3
COP-RXPB
RCV
R103 R38
0 RES1210
LED3_CATHODE
63(('
330E LED3_ANODE
EVB-LAN9353 Evaluation Board User’s Guide
Note: Capacitors C10 through C13 are optional for EMI purposes and are not populated on the LAN8740/41 evaluation board. These capacitors are required for operation in an EMI constrained environment.
YEL A1
7
12
C31 10pF 50V 5% DNP
C1
C30 10pF 50V 5% DNP
GND
C29 10pF 50V 5% DNP
13
C28 10pF 50V 5% DNP
3 7&8
11
6 C32 0.022uF
75
MTG1
COP-RXNA
LED2 (Yellow) = SPEED
75
RXCT
MTG
FX_SFP-RXNA
RCV RD+
16
5
15
3
COP-RXPA
GND1
FX_SFP-RXPA
14
2015 Microchip Technology Inc.
FIGURE B-4:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 5 3V3
R39 82
R40 82
R41 49.9
R42 49.9
Note:Place capacitors, and resistors close to FOT
C38
0.1uF
C40
0.1uF
3V3
Fiber Port 1 :SFP Interface R43 82
R44 82
R45 49.9
R46 49.9
Note:Place capacitors, and resistors close to FOT
Assemble 0E at C38,C40,C42,C44
FX_SFP-RXNA
Fiber Port 2 :SFP Interface
Assemble 0E at C39,C41,C43,C45
C39
0.1uF
C41
0.1uF
C43
0.1uF
C45
R48 100 DNP 0.1uF
FX_SFP-RXNB
FX_SFP-RXPA FX_SFP-RXPB C42 FX_SFP-TXPA 0.1uF
FX_SFP-TXPB
3V3 R47 100 DNP
3V3
SFP_VCCT
C44
L2
SFP_VCCR
FX_SFP-TXNA
1uH C49 0.1uF
R51 130
R52 130
SFP_RD2+ SFP_RD2-
C48 + 10uF 16V
C47 0.1uF
SFP_TD2SFP_TD2+
SFP_RD+ SFP_RD-
SFP_TDSFP_TD+
R50 130
C46 + 10uF 16V DNP
L1
C50 + 10uF 16V DNP
C51 0.1uF
C56 + 31 10uF 30 16V 29 28 27 26 25 24 23 22 21
C57 0.1uF
L3 1uH
R53 4.7K
R54 4.7K
C55 0.1uF
VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3
C54 + 10uF 16V
Note:Place resistors close to ASIC J3 FTLF1217P2 SFP_VCCT2
1 2 3 4 5 6 7 8 9 10
SFP_VCCT
31 30 29 28 27 26 25 24 23 22 21
R55 4.7K
R56 4.7K
R57 4.7K
FXSDA/FXLOSA
VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1
J2 FTLF1217P2
31 30 29 28 27 26 25 24 23 22 21
1 2 3 4 5 6 7 8 9 10
Note:Place resistors close to ASIC
VeeT TXFault TX Disable MOD-DEF(2) MOD-DEF (1) MOD-DEF (0) Rate Select LOS VeeR VeeR1
VeeT1 TDTD+ VeeT2 VccT VccR VeeR2 RD+ RDVeeR3
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
L4
R58 4.7K
R59 4.7K
R60 4.7K
FXSDB/FXLOSB
2015 Microchip Technology Inc.
Note: Fiber mode related components are Not Populated on EVB (Default)
1uH
SFP_VCCR2
FX_SFP-TXNB
0.1uF
R49 130
SFP_VCCT2
31 30 29 28 27 26 25 24 23 22 21
C52 + 10uF 16V
1uH
C53 0.1uF
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 34
FIGURE B-5:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 6 GPIO [0:5] & LED_POL_Strap
3V3
I2C EEPROM GPIO3
GPIO5
1
R82 10.0K
1 2 3
R83 10.0K
7
A0 A1 A2
GPIO2
R86 0E
GPIO4
GPIO3
I2C2_SDA
6
I2C2_SCL
Note: U5: IC DIP Socket. Different sizes can be mounted I2C EEPROM Lower size Below 16K(2K X 8)
3
1
J15
3
3
1
3
1
J13
1
J14
GPIO1
5
I2C EEPROM Higher size Above 16K(2K X 8) [Default-512KBIT]
2
2
2
R85 0E
J8
3
1
J9
3
1
J7
GPIO0
R84 1K
2
R74 1K
2
2
R73 0E
SDA SCL
WP
2
2
2
LED3_CATHODE LED5_CATHODE
2
VCC
4.7K
24FC512-I/P R72 0E
0.1uF
3
1 2
R66
LED3_ANODE LED5_ANODE
1
R81 10.0K
LED1_CATHODE LED4_CATHODE
2
LED0_CATHODE LED2_CATHODE
3
1
1
3
2
J12
2 LED1_ANODE LED4_ANODE
R71 10.0K
1
R70 10.0K
1
1
1
LED0_ANODE LED2_ANODE
R69 10.0K
J10
2
J11
2
J5
2
J6
3
1
3
1
3
1
U5 J4
R68
GPIO4
R67
GPIO1
3V3 C58
3V3
2K
GPIO2
3V3
2K
GPIO0
3V3
8
3V3
GND
3V3
4
3V3
2
2015 Microchip Technology Inc.
FIGURE B-6:
GPIO5
FX_Mode_Strap_1 & 2 3V3
Port 2 LEDs
Port 1 LEDs
LED0_ANODE
LED0_CATHODE
LED1_ANODE LED1_CATHODE
DNP SPEED 2 D3 1 GRN A C
LED3_ANODE LED3_CATHODE
FULL DUPLEX / Collision 2 D4 1 GRN A C
LED3_ANODE LED3_CATHODE
LED4_ANODE LED4_CATHODE
DNP SPEED D6 1 C GRN A
3257 J16
2 I2C2_SCL I2C2_SDA
FULL DUPLEX / Collision 2 D7 1 C GRN A
1 3 5 7 9
2 4 6 8 10
3257
3257 HEADER 5X2
LED2_ANODE LED2_CATHODE
LED2_ANODE LED2_CATHODE
DNP LINK/ACT 2 D5 1 C GRN A
LED5_ANODE LED5_CATHODE
LED5_ANODE LED5_CATHODE
DNP LINK/ACT 2 D8 1 GRN A C
02'( 3RXSXODWH &RSSHU 5 'HIDXOW )LEHU
5
&RSSHU 'HIDXOW
5
)LEHU
5
FXSDA/FXLOSA
R75
DNP 10K
R76
10K
R78
DNP 10K
R80
10K
3V3
FXSDB/FXLOSB
3V3
1 Strap Name
Logic
Connector
LED Polarity Strap
0
J4,J7 (2&3)
The LED is set as active high.
1
J4,J7 (1&2) (Default)
The LED is set as active low,
0
J5,J8 (2&3)
The LED is set as active high.
1
J5,J8 (1&2) (Default)
The LED is set as active low,
0
J6,J9 (2&3)
The LED is set as active high. EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)
1
J6,J9 (1&2) (Default)
The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)
0
J10,J13 (2&3)
The LED is set as active high. EEE Disable
1
J10,J13 (1&2) (Default)
The LED is set as active low, EEE Enable
0
J11,J14 (2&3)
The LED is set as active high. 1588 Disable
1
J11,J14 (1&2) The LED is set as active low, (Default) 1588 Enable
0
J12,J15 (2&3) (Default)
The LED is set as active high. PHYADD=0,1,2
J12,J15 (1&2)
The LED is set as active low, PHYADD =1,2,3
GPIO6 R99
2 3
10K
FX_Los_Strap_1 & 2
J20
LED0/GPIO0/MNGT0
3V3
5
5
3RXSXODWH
'13
5HI9ROWDJH 9
$ERYH9VHOHFWV);/26IRUSRUWVDQG
9
/HYHORI9VHOHFWV);/26IRUSRUWDQG );6'FRSSHUWZLVWHGSDLUIRUSRUW IXUWKHUGHWHUPLQHGE\);6'%
1
LED1/GPIO1
LED2/GPIO2/E2PSIZE
LED3/GPIO3/EEEEN
LED4/GPIO4/1588EN
DS50002393A-page 35
LED5/GPIO5/PHYADD 1
GPIO7 R100
2 3
10K
3RXSXODWH 3RXSXODWH
J21
R77 10K DNP ATEST/FXLOSEN
'13 3RXSXODWH 'HIDXOW 'HIDXOW 'HIDXOW GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
3V3
)XQFWLRQ
1 2 3 4 5 6 7 8 J27 HEADER 8
/HYHORI96HOHFWV);6'FRSSHUWZLVWHGSDLU IRUSRUWV$DQG% IXUWKHUGHWHUPLQHGE\);6'$DQG);6'%
R79 10K
EVB-LAN9353 Evaluation Board User’s Guide
LED0_CATHODE
LED0_ANODE
Aardvark - I2C Connector
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 7 3V3 3V3
P0_OUT/REF_CLK_MODE0 R104
SW5 10.0K 1
2
P0_MODE0
3
SW6
P1_REFCLK_MODE0/P0_INCLK
R105
10.0K
Config 10 Port 0 : External (MII/RMII/TMII) Port 1 and Port 2 : Internal
2
1
P1_MODE0
3 JS102011CQN JS102011CQN 3V3 SW7 P0_OUTD0_MODE1
R106
10.0K
3V3
2
1
P0_MODE1
3
P1_OUTD0_MODE1/P0_OUTD2_MODE3
SW8 R107
10.0K
2
1
P0_MODE3 & P1_MODE1
3 JS102011CQN JS102011CQN 3V3 P0_OUTD1_MODE2
SW9 R108
10.0K
3V3
2
1 3
P0_MODE2
P1_OUTD1_MODE2/P0_OUTD3
SW10 R109
10.0K
2
1 3
JS102011CQN JS102011CQN
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . Note: CONFIG9 or CONFIG 10 must be configured before P0/P1 mode configurations
Config 9 : Port 0 and Port 1 : External (RMII) and Port 2 : Internal WŽƌƚϭ;ZD//ͿDK ^dZWDĂƉƉŝŶŐ
2015 Microchip Technology Inc.
Wϭͺ/EdW,z͗ :ϱĂŶĚ:ϴ Ϭ ^ŚŽƌƚϮͲϯ Ϭ ^ŚŽƌƚϮͲϯ Ϭ ^ŚŽƌƚϮͲϯ Ϭ ^ŚŽƌƚϮͲϯ Ϭ ^ŚŽƌƚϮͲϯ Ϭ ^ŚŽƌƚϮͲϯ ϭ ^ŚŽƌƚϭͲϮ
WϭͺDK Ϯ ^tϭϬ Ϭ ^ŚŽƌƚϭͲϯ Ϭ ^ŚŽƌƚϭͲϯ Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ dž ŽƉĞŶ
WϭͺDK ϭ ^tϴ Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ dž ŽƉĞŶ
WϭͺDK Ϭ ^tϲ dž ŽƉĞŶ Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ dž ŽƉĞŶ Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ dž ŽƉĞŶ
WŽƌƚϭDŽĚĞ ZD//DĐůŽĐŬŝŶ ;ZD//ƉŝŶƌĞŵĂƉŵŽĚĞͿ ZD//DĐůŽĐŬŽƵƚϭϮŵĂ ZD//DĐůŽĐŬŽƵƚϭϲŵĂ ZD//W,zĐůŽĐŬŝŶ
P1_MODE2
WŽƌƚϬDK ^dZWDĂƉƉŝŶŐ Wϭͺ/EdW,z͗ WϬͺDK ϯ WϬͺDK Ϯ WϬͺDK ϭ WϬͺDK Ϭ :ϱĂŶĚ:ϴ ^tϴ ^tϵ ^tϳ ^tϱ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ Ϭ ϭ ^ŚŽƌƚϮͲϯ Ϭ ϭ ^ŚŽƌƚϮͲϯ Ϭ ϭ ^ŚŽƌƚϮͲϯ Ϭ ϭ ^ŚŽƌƚϮͲϯ Ϭ ϭ ^ŚŽƌƚϮͲϯ Ϭ ϭ
Ϭ ^ŚŽƌƚϭͲϯ Ϭ ^ŚŽƌƚϭͲϯ Ϭ ^ŚŽƌƚϭͲϯ Ϭ ^ŚŽƌƚϭͲϯ dž ϭ ^ŚŽƌƚϭͲϮ dž ϭ ^ŚŽƌƚϭͲϮ dž ϭ ^ŚŽƌƚϭͲϮ dž ϭ ^ŚŽƌƚϭͲϮ dž ϭ ^ŚŽƌƚϭͲϮ dž ϭ
ZD//W,zĐůŽĐŬŽƵƚϭϮŵĂ ZD//W,zĐůŽĐŬŽƵƚϭϲŵĂ /ŶƚĞƌŶĂůW,z
P1_REFCLK_MODE0/P0_INCLK P1_OUTD1_MODE2/P0_OUTD3 P1_OUTD0_MODE1/P0_OUTD2_MODE3 P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUT/REF_CLK_MODE0
Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ
dž E Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ ϭ ^ŚŽƌƚϭͲϮ
dž E dž E Ϭ ^ŚŽƌƚϭͲϯ ϭ ^ŚŽƌƚϭͲϮ
Ϭ
Ϭ
dž
^ŚŽƌƚϭͲϯ
^ŚŽƌƚϭͲϯ
E
Ϭ
ϭ
Ϭ
^ŚŽƌƚϭͲϯ
^ŚŽƌƚϭͲϮ
^ŚŽƌƚϭͲϯ
Ϭ
ϭ
ϭ
^ŚŽƌƚϭͲϯ
^ŚŽƌƚϭͲϮ
^ŚŽƌƚϭͲϮ
ϭ
Ϭ
dž
^ŚŽƌƚϭͲϮ
^ŚŽƌƚϭͲϯ
E
ϭ
ϭ
Ϭ
^ŚŽƌƚϭͲϮ
^ŚŽƌƚϭͲϮ
^ŚŽƌƚϭͲϯ
ϭ
ϭ
Ž
DK D//D D//W,z dƵƌďŽD//W,zϭϮŵĂ dƵƌďŽD//W,zϭϲŵĂ ZD//DĐůŽĐŬŝŶ
ZD//DĐůŽĐŬŽƵƚϭϮŵĂ
ZD//DĐůŽĐŬŽƵƚϭϲŵĂ
ZD//W,zĐůŽĐŬŝŶ
ZD//W,zĐůŽĐŬŽƵƚϭϮŵĂ
ZD//W,zĐůŽĐŬŽƵƚϭϲŵĂ
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 36
FIGURE B-7:
2015 Microchip Technology Inc.
FIGURE B-8:
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 8
Jumper settings for CONFIG 9 or CONFIG 10
2
P0_INCLK P1_REFCLK_MODE0
SW11
SW12
SW13
SW14
SW15
SW16
SW17
SW18
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-3
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
Mode
Configuration
2 RMII 1 MII/RMII/TMII (Default)
CONFIG 9 CONFIG 10
8 Jumpers Config9(2RMII) = 2-3 Short (1-2 - open) Config10 = 1-2 Short (2-3 - open) (Default)
SW11 JS102011CQN 1
3 SW12
2
P0_IND3
1
JS102011CQN
3
P1_IND1 P0_IND2 P1_IND0
2
SW13 JS102011CQN 1
P0_REFCLK/P0_MODE0[P0_OUTCLK/P0_REFCLK/P0_MODE0]
SW14
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa .
P0_INER P1_INDV
2 JS102011CQN 3
U4B
LAN9353
3 P1_REFCLK_MODE0/P0_INCLK R117 P1_IND1/P0_IND3 R144 R145 P1_IND0/P0_IND2 P1_INDV/P0_INER
1
R146 P1_OUTD1_MODE2/P0_OUTD3 P1_OUTD0_MODE1/P0_OUTD2_MODE3R147 1 P1_OUTDV
SW15 2 P0_OUTD3 JS102011CQN 1 3 P1_OUTD1_MODE2 SW16 2 P0_OUTD2 1 JS102011CQN 3 P1_OUTD0_MODE1 SW17 2 P0_CRS JS102011CQN 1 3 P1_MDC_DUPLEX SW18 2 P0_COL 1 JS102011CQN 3 P1_MDIO_SPEED
33 33 33
29 31 30 33
33 33 2 J22
15 16 35
P1_MDC_DUPLEX/P0_CRS P1_MDIO_SPEED/P0_COL
49 50
P1_REFCLK/P1_MODE0[P0_INCLK] P1_IND1[P0_IND3] P1_IND0[P0_IND2] P1_INDV[P0_INER] P1_OUTD1/P1_MODE2[P0_OUTD3] P1_OUTD0/P1_MODE1[P0_OUTD2/P0_MODE3] P1_OUTDV[RESERVED] P1_DUPLEX/P1_MDC[P0_CRS] P1_SPEED/P1_MDIO[P0_COL]
CONFIG9[CONFIG10]
P0_IND1 P0_IND0 P0_INDV P0_OUTD1/P0_MODE2 P0_OUTD0/P0_MODE1 P0_OUTDV P0_DUPLEX P0_SPEED[P0_OUTER/P0_SPEED] P0_MDC P0_MDIO
25
R116 33
28 27 26
R122 R123
21 22 23
R124 R125
P0_OUT/REF_CLK_MODE0
33 33
P0_IND1 P0_IND0 P0_INDV
33 P0_OUTD1_MODE2 33 P0_OUTD0_MODE1 P0_OUTDV
36 19
P0_DUPLEX P0_OUTER_SPEED
39 40
P0_MDC P0_MDIO
CONFIG9 = 2RMII CONFIG10 = 1 MII/RMII(Default)
J28
P1_MDC_DUPLEX/P0_CRS R120
2
P0_DUPLEX R118
J30
3V3
1
J29
Default -Open
J31
3V3
1
2
Duplex Strap_0
3
3
10.0K
Emulated Link Partner Default Advertised Ability for Port 0 J29 (P0_SPEED)
3V3
1
2
P1_MDIO_SPEED/P0_COL R121 10.0K
Default -Open
Default (1-2)
J28 (P0_DUPLEX)
3
10.0K
3
10.0K
Default (1-2)
P0_OUTER_SPEED R119
3V3
1
2
Speed ADVERTISED LINK PARTNER ABILITY Strap_0 (Bits 8,7,6,5)
DS50002393A-page 37
1-2
2-3
1
0
10BASE-T full-duplex (0010)
1-2
1-2
1
1
100BASE-X full-duplex (1000) (Default)
2-3
2-3
0
0
10BASE-T half-duplex (0001)
2-3
1-2
0
1
100BASE-X half-duplex (0100)
Emulated Link Partner Default Advertised Ability for Port 1 J30 (P1_DUPLEX)
J31 (P1_SPEED)
Duplex Strap_1
Speed ADVERTISED LINK PARTNER ABILITY Strap_1 (Bits 8,7,6,5)
1-2
2-3
1
0
10BASE-T full-duplex (0010)
1-2
1-2
1
1
100BASE-X full-duplex (1000)
2-3
2-3
0
0
10BASE-T half-duplex (0001)
2-3
1-2
0
1
100BASE-X half-duplex (0100)
P0_INER P0_INCLK P0_INDV P0_IND0 P0_IND1 P0_IND2 P0_IND3 P0_COL P0_CRS P0_MDIO P0_MDC P0_OUTD3 P0_OUTD2 P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUTDV P0_OUT/REF_CLK_MODE0 P0_OUTER_SPEED P1_REFCLK_MODE0/P0_INCLK P1_OUTD1_MODE2/P0_OUTD3 P1_OUTD0_MODE1/P0_OUTD2_MODE3 P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUT/REF_CLK_MODE0
EVB-LAN9353 Evaluation Board User’s Guide
P1_MDIO_SPEED P1_MDC_DUPLEX P1_IND1 P1_IND0 P1_INDV P1_REFCLK_MODE0 P1_OUTDV P1_OUTD0_MODE1 P1_OUTD1_MODE2
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 9 MII Male for External MAC Board AMP - 6-5174218-2 MII_RA 5V
10uF 0.1uF
MII Female for External PHY Board
C59 C61
Port 0 - RMII RX Clock Configurations
5V
FEMALE MII CONN AMP - 749069-4
C60
SW23
10uF 0.1uF
R126 R127
0E 0E
MAC_TXCLK0 MAC_RXCLK0
+5V[3] MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V[4]
+5V[1] COMMON[1] COMMON[2] COMMON[3] COMMON[4] COMMON[5] COMMON[6] COMMON[7] COMMON[8] COMMON[9] COMMON[10] COMMON[11] COMMON[12] COMMON[13] COMMON[14] COMMON[15] COMMON[16] COMMON[17] COMMON[18] +5V[2]
Chassis2 Chassis1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
MAC_RXCLK0
3
Default Short 2-3
JS102011CQN SW24 2 PHY_RXCLK0
J23
P0_MDIO P0_MDC P0_OUTD3 P0_OUTD2 P0_OUTD1_MODE2 P0_OUTD0_MODE1 P0_OUTDV P0_OUT/REF_CLK_MODE0 P0_OUTER_SPEED P0_INER P0_INCLK P0_INDV P0_IND0 P0_IND1 P0_IND2 P0_IND3 P0_COL P0_CRS
2 MAC_TXCLK0 1
C62
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P0_INCLK
P0_MDIO P0_MDC P0_IND3 P0_IND2 P0_IND1 P0_IND0 P0_INDV 0E PHY_RXCLK0 P0_INER 0E TXER0 0E PHY_TXCLK0 P0_OUTDV P0_OUTD0_MODE1 P0_OUTD1_MODE2 P0_OUTD2 P0_OUTD3 P0_COL P0_CRS
R128
P0_OUTER_SPEED DNP P0_OUT/REF_CLK_MODE0
R129 R130
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PHY_TXCLK0 1
3
J24
Default (1-3)
JS102011CQN Switch Settings
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Description
Mode
SW23 (1-3) Default
TX Clock used as a Reference Clock
RMII MAC
SW23 (1-2)
RX Clock used as a Reference Clock
RMII MAC
SW24 (1-3) Default
Reference clock used as a TX clock
RMII PHY
SW24 (1-2)
Reference clock used as a RX clock
RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . 2. External PHY considered LAN8742
PORT 0
MII Male for External MAC Board AMP - 6-5174218-2 MII_RA
PORT 1 5V
10uF 0.1uF
MII Female for External PHY Board
C63
5V
FEMALE MII CONN AMP - 749069-4
C64
C65
Port 1 - RMII RX Clock Configurations
10uF
SW25 C66
0.1uF
2
MAC_RXCLK1
3
Default Short 2-3
MAC_TXCLK1 1
P1_MDIO_SPEED P1_MDC_DUPLEX P1_OUTD1_MODE2 P1_OUTD0_MODE1 P1_OUTDV P1_REFCLK_MODE0
R135
0E MAC_TXCLK1 MAC_RXCLK1
P1_INDV P1_IND0 P1_IND1
P1_CRS
2015 Microchip Technology Inc.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+5V[3] MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS +5V[4]
+5V[1] COMMON[1] COMMON[2] COMMON[3] COMMON[4] COMMON[5] COMMON[6] COMMON[7] COMMON[8] COMMON[9] COMMON[10] COMMON[11] COMMON[12] COMMON[13] COMMON[14] COMMON[15] COMMON[16] COMMON[17] COMMON[18] +5V[2]
Chassis2 Chassis1
J18 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1_MDIO_SPEED P1_MDC_DUPLEX P1_IND1 P1_IND0 P1_INDV PHY_TXCLK1 P1_REFCLK_MODE0
R136 0E PHY_RXCLK1 P1_OUTDV P1_OUTD0_MODE1 P1_OUTD1_MODE2
P1_CRS P1_INDV
P1_CRS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
JS102011CQN SW26 2 PHY_RXCLK1
J19
PHY_TXCLK1 1
3
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Switch Settings
Pullup for MDIO(common for all PHY) signal TP7
TP8
J25 P0_INDV
1
2
Short option for RXDV & CRS for RMII mode
P1_MDIO_SPEED
1.5K
P1_MDC_DUPLEX
10K
R137 R138
3V3
TP6 3V3 P0_MDIO P0_MDC
2
1 J26
R133
10K
P0_OUTDV
R139
10K
P1_OUTDV
3V3
J26 = Default open
P0_CRS
1.5K
R131
10K
R132 DNP
TX Clock used as a Reference Clock
SW25 (1-2)
RX Clock used as a Reference Clock
SW26 (1-3) Default
Reference clock used as a TX clock Reference clock used as a RX clock
Mode RMII MAC RMII MAC RMII PHY RMII PHY
Note: 1. For Switches to short 1-3, Knob Position should be at 1-2 and vice versa . 2. External PHY considered LAN8742
Pullup for MDIO(common for all PHY) signal TP5
3V3
Description
SW25 (1-3) Default
SW26 (1-2)
For RMII
J28 = Default open Short for RMII mode
Default (1-3)
JS102011CQN
R134
49.9K DNP
TXER0
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 38
FIGURE B-9:
EVB-LAN9353 EVALUATION BOARD USER’S GUIDE
Appendix C. Bill of Materials (BOM) C.1
INTRODUCTION
This appendix includes the EVB-LAN9353 Evaluation Board Bill of Materials (BOM).
2015 Microchip Technology Inc.
DS50002393A-page 39
TABLE C-1: Item
EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS
Qty
Reference Designator(s)
Part
PCB Footprint
Manufacturer
Manufacturer Part Number
1
2
C2,C4
10uF
CAP0805
Murata
GRM21BR61E106KA73L
2
21
C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17 0.1uF ,C18,C21,C22,C24,C25,C58,C61,C62,C64,C6 6
CAP0603
Murata
GRM155R61E104KA7D
3
1
C19
1uF
CAP0603
Murata
GRM188R61C105KA93D
4
1
C20
470pF
CAP0603
Murata
GRM033R71E471KA01D
5
2
C26,C27
18pF
CAP0603
Murata
GRM1885C1H180JA01D
6
2
C32,C37
0.022uF
CAP0603
Kemet
C0603C223K5RACTU
7
4
C59,C60,C63,C65
10uF
CAP0603
TDK
C1608X5R0J106K080AB
8
3
D1,D4,D7
GRN
LED0603
Wurth electronics
150 060 GS7 500 0
9
1
D2
RED
LED0603
Wurth electronics
150 060 RS7 500 0
Murata
10
5
FB1,FB2,FB3,FB4,FB5
2A/0.05DCR
RES0603
11
1
J1
SKT_PWR_2R0mm_4A_THRU_R A
th_conn_pwrjack_dc-210_rt Cui Stack
PJ-002AH
BLM18EG221SN1D
12
18
J4,J5,J6,J7,J8,J9,J10,J11,J12,J13,J14,J15,J2 0,J21,J28,J29,J30,J31
HDR_1x3
TH_CONN_1X3P
FCI
68000-103HLF
13
1
J16
HEADER 5X2
th_conn_2x5p_BOX
FCI
67997-210HLF
14
2
J18,J23
MII_RA
TH_CONN_TE-5173278_40P
TE
5173278-2-ND
15
2
J19,J24
FEMALE MII CONN
TH_CONN_MII-749069-4
TE
749069-4-ND
2015 Microchip Technology Inc.
16
3
J22,J25,J26
CONN_2P
th_conn_1x2p
FCI
68000-102HLF
17
1
J27
CONN_8P
th_conn_1x8p
FCI
68000-108HLF
18
1
Q1
NDS355AN_NMOS
sot23-NDS
Fairchild
NDS355AN
19
15
R1,R15,R29,R126,R127,R128,R130,R135,R1 36,FB6,FB7,R72,R73,R85,R86
0E
RES0603
Panasonic
ERJ-3GEY0R00V
20
4
R2,R8,R74,R84
1K
RES0603
Panasonic
ERJ-3GEYJ102V
21
1
R3
3.30K
RES0603
Yageo America
9C06031A3301FKHFT
22
1
R4
470E
RES0603
BOURNS
CR0603-FX-4700ELF
23
1
R4A
33E
RES0603
BOURNS
CR0603-FX-33R0ELF
24
1
R5
4.75K
RES0603
Panasonic
ERJ-3EKF4751V
25
25
R6,R69,R70,R71,R81,R82,R83,R76,R79,R80, 10.0K R99,R100,R133,R138,R139,R104,R105,R106 ,R107,R108,R109,R118,R119,R120,R121
RES0603
Panasonic
ERJ-3EKF1002V
EVB-LAN9353 Evaluation Board User’s Guide
DS50002393A-page 40
Configuration: Config 10: Two internal copper mode with higher size EEPROM (24FC512)
2015 Microchip Technology Inc.
TABLE C-1:
EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS (CONTINUED)
Item
Qty
Reference Designator(s)
Part
PCB Footprint
Manufacturer
Manufacturer Part Number
26
1
R7
100E
RES0603
Panasonic
27
1
R9
2.2K
RES0603
Panasonic
ERJ-3GEYJ222V
28
1
R10
12.1K
RES0603
Rohm
MCR01MZPF1202 9C06031A49R9FKHFT
ERJ-3EKF1000V
29
8
R11,R12,R13,R14,R25,R26,R27,R28
49.9E
RES0603
Yageo America
30
8
R17,R19,R21,R23,R31,R33,R35,R37
0
RES0402
Panasonic
ERJ-2GE0R00X
31
2
R24,R38
0
RES1210
Vishay
CRCW12100000Z0EA
32
4
R61,R62,R102,R103
330E
RES0603
Panasonic
ERJ-3GEYJ331V
33
2
R67,R68
2K
RES0603
Panasonic
ERJ-3GEYJ202V
34
10
R116,R117,R122,R123,R124,R125,R144,R14 5,R146,R147
33E
RES0603
BOURNS
CR0603-FX-33R0ELF
35
2
R131,R137
1.5K
RES0603
Panasonic
ERJ-3GEYJ152V
36
1
SW1
SW-SPDT-SLIDE
sw_ck_1101m2s3cqe2
C&K
1101M2S3CQE2
37
1
SW2
sw_pb_2P
sw_pb_2P
Panasonic
38
18
SW5,SW6,SW7,SW8,SW9,SW10,SW11,SW1 2,SW13,SW14,SW15,SW16,SW17,SW18,SW 23,SW24,SW25,SW26
450301014042
TH_SW_SPST_3P_10x2p5 Wurth electronics
450301014042
39
1
TP1
RED
TH_TP_60D40
Keystone
5000
40
1
TP2
ORANGE
TH_TP_60D40
Keystone
5003
TP9,TP10
BLACK
TH_TP_60D40
Keystone
5001
Pulse Electronics
553-1483-ND
41
EVQ-PJU04K
42
2
T1,T2
Pulse - J0011D01BNL
th_conn_pulse_rj45_j0026
43
1
U1
3_Amp
TH_DC-DC_VERT_5PIN_P Murata 67
OKR-T/3-W12-C
44
1
U2
TPS3125
SOT23_5
TI
TPS3125L30DBVR
DS50002393A-page 41
45
1
U3
74LVC1G14
SOT23_5
TI
SN74LVC1G14DCKR
46
1
U4
LAN9353
IC_QFN64
Microchip
LAN9353
47
1
U5
Round Base
IC_DIP8_300
Assmann
AR08-HZL-TT-R
48
1
U5
24FC512
IC_DIP8_300
Microchip
24FC512-I/P
49
4
D3,D5,D6,D8
GRN
LED0603
Wurth electronics
150 060 GS7 500 0
50
1
Y1
25.000MHz
XTAL_HCM49
Cardinal Components Inc.
CSM1Z-A5B2C5-40-25.0D18-F
EVB-LAN9353 Evaluation Board User’s Guide NOTES:
DS50002393A-page 42
2015 Microchip Technology Inc.
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DS50002393A-page 43
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