Transcript
EX3 DIGITAL ELECTRONICS Right through this exercise and the corresponding didactical units (Unit 1.6) the following concepts will be covered and must be understood by all the students after completing the task: 1) CMOS technology for realizing basic gates and other logic families; 2) electrical characteristics of digital integrated circuits, such as: logic voltage levels, noise margins, propagation delays and transition times, power dissipation; maximum frequency of operation of a digital circuit; 3) three-state gates; 4) evolution of integrated circuits and the obsolescence curve; 5) chronograms or timing diagrams to verify circuit operation; 6) Levels of integration of digital chips. 1
Write the expression of the output function Z1 (as in EX2) of the circuit shown in Fig. 1. Deduce the timing diagram of Z1 (a graphical representation that shows the propagation of the signals as a function of time) when applying the waveforms. Consider the ideal input waveforms shown in Fig. 1. In addition, determine the chip power consumption. VDD
0.1
SC CMOS
BAT1
VDD
1
X3
1
X2
0
X1
1
X0
X3
R1 5V
X2 Z1
0
Z0
1
X1
VSS
X0
CCT001
U4:A X3
1
X2
2
3
4011
X1
PACKAGE=DIL14 MODFILE=40NAND2 VOLTAGE=5V
U1:A 1 2 8
U3:B
U2:B 9
5
5
4 4
6
Z1
6 1
4073
3
X0
2
4071
U3:A 4071
U2:A
4081
U2:C
8
1
10 3
9
Z0
2
4081
4071
Fig. 1 Gate network of the CMOS logic family and inputs signals
2
Design a parity-even generator of 6 bits in LS technology. Using Proteus-VSM, draw the circuit, verify its truth table and calculate the following parameters: Voltage levels, high and low noise margins, power dissipation, maximum frequency of operation.
3
Deduce from a Proteus-VSM simulation the propagation delay and the maximum frequency of operation of: a) CMOS inverter (4069) operating at VDD = 10 V; b) LS inverter (74LS04); c) the network in Fig. 1; d) 4-digit BCD adder designed in section 1f of exercise EX2.
4
Analyse the CMOS circuits represented in Fig. 2 and determine which logic gates represent.
Fig. 2 Logic gates made with CMOS technology
Extra: Example design flow for a digital circuit. A 4-bits parity-odd checker. As shown in Fig. 3, only one entity of 4 inputs and 1 output has to be designed. SPECIFICATIONS
BLOCK DIAGRAM (ENTITY)
INDEPENDENT DESIGN OF EACH ENTITY
X3 X2
4-BIT PARITY-ODD CHECKER
E
X1 SIMULATION
NO
X0
DOES IT WORK?
YES IMPLEMENTATION OF THE LABORATORY PROTOTYPE
Fig. 3 Design process of a digital circuit
After the design process (specification, block diagram, truth table, canonical expression and Karnaugh minimization), we can demonstrate that the output error signal E generated by a parity odd checker can be represented by: E = (X0⊕ X1⊕ X2⊕ X3)′ Logic diagram in Fig. 4 produced in DEEDS can be interactively simulated applying vectors at the inputs. For instance, output E for the input vector (0 1 1 0)
Fig. 4 Schematic for the 4-bit parity checker
In the time diagram shown in Fig. 5 output E is simulated for several input combinations
Fig. 5 Time diagram for several input combinations
