Transcript
Fast Interlocks Detection System for switch and machine protection (FIDS) Fellowship: current status S. Uyttenhove Under supervision of Pieter Van Trappen
5/3/2016
FIDS
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Fellowship’s overview 1. 2.
3. 4. 5. 6.
Initial conditions: functional specification and prototype Prototype improvement and testing Design of the new solution Hardware development Hardware tests Milestones
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1) Initial conditions: functional specification and prototype • •
Fast Interlocks Detection System for switch and machine protection (FIDS) Scope:
Currently existing:
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PSB, PS, SPS, LHC (excluding LHC beam dump) Missing/faulty/erratic shots Short-circuits, no dump switch forward current, reverse overvoltage, magnet overvoltage Thyratron Protection Unit (TPU) NI PXI Platform SPS & LHC cards: FPS, FSD-B, KFMD-B, MOVD
Following the initial functional specification: • Same system for PSB, PS, SPS and LHC • Advantages: More flexibility Easier calibration Homogenous Industrial interface Advanced diagnostics
• Functional Specification currently under approval:
https://edms.cern.ch/document/1502784/0.4
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2) Prototype improvement and testing •
Features tested in 867 • • • • • •
Missing/erratic(/faulty) shots Range 0V -> 40kV Running fine for ~95000 pulses MKDV (SAL.2): terminated magnets EK (SAL.5): resonant charging, S/C magnets, pulse length min:100ns Retriggering
https://espace.cern.ch/te-dep-abt/Projects/FIDS/Shared%20Documents/FIDS%20867%20tests.docx
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3) Design of the new solution •
Choice between three main options: • Entire homemade design • National Instruments PCI eXtensions for Instrumentions (PXI) • LAN eXtensions for Instrumentation (LXI)
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Uncertainties regarding the bus communication (waiting BE-CO decision)
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Homemade FPGA Mezzanine Carrier (FMC) and Carrier • FMC Advantages:
Allows reuse of hardware cards/carriers Allows flexibility given the heterogeneous environment Card usable in other projects (BI.DIS LIU …) Back-up/Help from the BE-CO department
• FMC Drawbacks:
Fixed mechanical/electrical format Fixed set of user defined pins Fixed set of voltages
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3) Design of the new solution – example with SBDS Carrier 1 (MKDV): • FMC1: GTO1A, GTO1B, GTO2A, GTO2B, GTO3A, GTO3B, Trigger1, Trigger2, Trigger3 • FMC2: TMR1, TMR2, TMR3; KTHT output for MKDH • AI: Vpfn1, Vpfn2, Vpfn3, Ip1, Ip2, Ip3 • Out: Retrigger output, PLC fail-safe interlock Carrier 2 (MKDH): • FMC1: GTO1A, GTO1B, GTO2A, GTO2B, GTO3A, GTO3B, Trigger1, Trigger2, Trigger3 • FMC2: Im1, Im2, Im3, Icb1, Icb2, Icb3 • AI: Vcb1a, Vcb1b, Vcb2a, Vcb2b, Vcb3a, Vcb3b • Out: retrigger output, PLC fail-safe interlock Carrier 3 (MKDH): • FMC1: Vcrossbar1A, Vcrossbar1B, Vcrossbar2A, Vcrossbar2B, Vcrossbar3A, Vcrossbar3B, Trigger1, Trigger2, Trigger3 • FMC2: • AI: Vcb1a, Vcb1b, Vcb2a, Vcb2b, Vcb3a, Vcb3b • Out: PLC fail-safe interlock https://indico.cern.ch/event/467041/ s.10
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4) Hardware development: FMC •
FMC is an ANSI/VITA standardized format for mezzanine module with connection to an FPGA
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Main specifications:
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10 high speed inputs and comparators 8 LVTTL outputs Comparators inputs levels: ±5V Programmable threshold: from 5V to -5 using DAC with 5mV precision (12bits) FMC to carrier interface: Low Pint Count (LPC) Output isolated contact for failsafe check by PLC
http://www.ohwr.org/projects/fmc-dio-10i-8o/wiki
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4) Hardware development: FMC •
Simulated • Hysteresis: http://www.ohwr.org/projects/fmc-dio-10i-8o/wiki/Hysteresis • Comparators tested using evaluation board: http://www.ti.com/lit/ug/snoa494a/snoa494a.pdf
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Schematics reviewed inside ABT/EC and BE/CO • First Draw: http://www.ohwr.org/documents/441 • •
Review with BE-CO: http://www.ohwr.org/projects/fmc-dio-10i-8o/wiki/Review_first_draw Corrections after review: http://www.ohwr.org/projects/fmc-dio-10i-8o/wiki/Corrections_after_Review_first_draw
• Second Draw: http://www.ohwr.org/documents/445
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4) Hardware development: Connector breakout board •
Small breakout board allowing the use of the FMC
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It has 9 double LEMO to handle 10 inputs and 8 outputs 2 phoenix contacts allow communication with PLC Connector FCS8: https://www.samtec.com/products/fcs8 Mating cable FCF8: https://www.samtec.com/products/fcf8
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4) Hardware development: Gateware and FMC tests •
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The VHDL code is currently being written in parallel with the FMC tests Compatibility with BE-CO equipment using wishbone bus (SVEC, IP cores,…) Easy implementation with the new Xilinx family used in the new carrier The code takes care of: I/O, I2C, SPI, fail-safe…
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Example outputs: “01010101” is displayed using VME command
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4) Hardware development : Patch panel •
To allow easy integration of I/O with the FMC boards, a patch panel is required • Connection I2C either PP <-> FMC or PP <-> FASEC (Carrier), local low level interface • LCD and buttons interaction •
Mechanics and electronics are ready • Routed by design office, requires only one last review
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5) Milestones •
Q1 & Q2 2016: production and tests FMC DIO 10I8O including BIDIS
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Q2 & Q3 2016: carrier production and tests + VHDL development
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Q3 2016: Final redesign of the FMC
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Mid-September: foreseen installation (MKP?) during the technical stop (S37). Being in parallel with former fast-interlock systems
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Q4 2016 & Q1 2017: Creation of a test procedure and a test bench for the FMC
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Q2 2017: Installation ready
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