Transcript
2nd International Conference on Power Electronics, Systems and Applications (ICPESA'2013) Sept. 25-26, 2013 Phnom Penh ( Cambodia)
FPGA Implementation of USB 3.0 (Super-Speed Bus) Function IP Protocol using Verilog HDL A B M Najmul. Karim, Mohammad. Anas, Tashfia. Afreen, and Iqbalur. Rahman Rokon
• USB 1.0: Released in November 1995. • USB 1.1: Released in August 1998. • USB 2.0: Released in April 2000. • USB 3.0: Released in November 2008. Basic differences among the major versions are as: [3]
Abstract—At present, Universal serial bus (USB) is been supposed as a popular term which is designed to standardize the connection of computer peripherals to perform communication as well as power supply. Thus, in this paper an efficient implementation of USB3.0 interface design is been proposed which includes two layer; named as Link layer and Physical layer. For transferring data on parallel layer, two different frequency clocks of 125MHz and 250MHz generation is presented in this design. Also, lock down the receiver clock is done by using incoming asynchronous serial data. The design is implemented in Cyclone II FPGA using the Altera DE1 board and performed coding in Verilog hardware description language at Register Transfer Level (RTL), simulating in ModelSim, synthesizing in Quartus II software.
TABLE I DIFFERENCES OF USB VERSIONS Version USB 1.0 USB 2.0 USB 3.0
Keywords—FPGA, RTL, USB3.0, Verilog.
Data rate type
Maximum data transfer rate
low speed and full speed enabled high speed and usb 1.0 feature enabled super speed and usb 2.0 mode enabled
12 Mbit/s 180 Mbit/s
5 Gbit/s
I. INTRODUCTION
II. USB 3.0: INTERFACE DESCRIPTION
NIVERSAL Serial Bus (USB) is an industry standard developed in the mid-1990s that defines the cables, connectors and communications protocols used in a bus for connection, communication, and power supply between computers and electronic devices which is developed and invented by Ajay bhatt [1]. It is a fast, bidirectional, low-cost, dynamically attachable interface that is consistent with the requirements of the PC platforms of today and tomorrow [2]. In 1995, Intel produced the first integrated circuits supporting USB. However, in January 1996 the original USB 1.0 specification was introduced. The USB standard evolved through several versions before and after its official release in 1996: • USB 0.7: Released in November 1994. • USB 0.8: Released in December 1994. • USB 0.9: Released in April 1995. • USB 0.99: Released in August 1995.
A. Overview USB 3.0, also known as Super Speed USB, is the next evolutionary phase of the Universal Serial Bus, inarguably the most successful and ubiquitous interface standard ever created. As computer hardware and peripherals continue to expand in capacity, speed, and portability, the interfaces that connect them must also advance in these areas [4]. Thus this Super Speed USB has much more improvements than HiSpeed USB (USB2.0). The following areas indicating the improvement of its features: • Increased transfer speed • Advanced power consumption features • Improved bandwidth • Increased maximum bus utilization • Backward USB 2.0 compatibility
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B. Architectural Description In USB 3.0, dual-bus architecture is used to allow both USB 2.0 (Full Speed, Low Speed, or High Speed) and USB 3.0 (Super Speed) operations to take place simultaneously, thus providing backward compatibility [5]. The following Fig. 1 indicates an architectural diagram of Super speed interconnect represented as communication layers through a topology of host, five layers of hubs and devices.
A B M Najmul Karim is a graduate student from Department of Electrical Engineering and Computer Science, North South University, Dhaka, Bangladesh (e-mail:
[email protected]). Mohammad Anas is a graduate student from Department of Electrical Engineering and Computer Science, North South University, Dhaka, Bangladesh (e-mail:
[email protected]). Tashfia Afreen is a graduate student from Department of Electrical Engineering and Computer Science, North South University, Dhaka, Bangladesh (e-mail:
[email protected]). Iqbalur Rahman Rokon is a Faculty member in North South University, Dhaka, Bangladesh. Former Sr. Engineer, VLSI Chip Research and Development (R&D), Emulex Corporation, California, USA. (Phone: +8801726246189 ; e-mail:
[email protected] ). 51
2nd International Conference on Power Electronics, Systems and Applications (ICPESA'2013) Sept. 25-26, 2013 Phnom Penh ( Cambodia)
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Buffering for data and protocol layer information elements. • State machines and buffering for managing information exchanges. It implements protocol for flow control, reliable delivery of packet headers, and link power management. Besides, physical portion include, • Transmit and receive byte streams. • Managing state of its PHY including power management and events. E. Protocol Layer Protocol layer provides data information exchange between host and device endpoint and thus it points end to end communication rules; this communication relationship is known as PIPE.As it is a host directed protocol; timing of application data transfer depends on host. All protocol layers are accomplished via the exchange of packets. These packets are sequence of data bytes with specific control sequence. Host transmitted protocol packets are transmitted through intervening hubs directly to a peripheral device. Device transmitted protocol packets simply flow upstream through hubs to the host [6]. The building block of protocol layer, named as packet headers, are fixed in size packets with a type and subtype. These are delivered through port to port communication layer and the rest of the field is utilized by end to end protocol. To synchronize devices with the host, a host delivers a packet which includes its timestamp. Host determines a certain period to transmit this special packet.
Fig. 1 Super speed bus communication layers and power management layers
The physical layer implements support functions required to talk to a USB 3.0 PIPE complaint PHY interface while implementation of the USB 3.0 link management, transaction management and data transfers is performed by link and protocol layers. C. Physical Layer The physical layer defines the PHY portion of a port and the physical connection between a downstream facing port (on a host or hub) and the upstream facing port on a device. The Super Speed physical connection is comprised of two differential data pairs, one transmit path and one receive path. The electrical aspects of each path are characterized as a transmitter, channel and receiver. These are unidirectional differential link [6]. By enabling receiver termination, initialization of each differential links took place at an electrical level. The transmitter performs detecting receiver termination and informing link layer. In an electrical idle state, there will be no signaling on the differential ink and low frequency periodic signal will be generated which is simple to generate and consume very little power. Each PHY has its own clock domain. After receiving 8 bit data from link layer, physical layer scrambles these data to decrease EMI emission. To transmit over the physical connection, it encodes the 8 bit scrambled data in to 10 bit symbols. These data, then, sent at a speed to keep EMI emission low. The bit stream is recovered by the receiver and then descrambled and decoded from 10 bit data to 8 bit data and for further processing, it is been sent to the Link layer.
F. Power Management Super speed provides power management in bus architecture, link, device and function. These areas are in coupled with each other based on allowable power state transitions. Link power management occurs asynchronously on every link in the connected hierarchy. It depends upon host, device or combination of both. Link power state may be driven by host or downstream port. The host does not directly control visibility of individual link power state that indicates one or more link in the path between host and device can be in reduced power state. Super speed power-management has the ability to define the needs of battery-powered portable applications. Two “Idle” modes (denoted as U1 and U2) are defined in addition to the “Suspend” mode (denoted as U3) of the USB 2.0 standard. The Idle modes are activated when it notices inactivity on a downstream port for a specific period based on predetermined information received from the host. Such information is indicated by the host to the device using the flags “Packet pending,” “End of burst,” and “Last packet” [7]. By allowing more circuitry, U2 state provides higher power savings than U1. That is why U2 to active state transition period is longer. The U3 state consumes the minimum power and also it requires a longer time to wake up the system.
D. Link Layer A super speed link logical and physical connection of the two ports, called as link partners. The link layer is responsible for logical connection of the port and communication of the link partners. Logical portion include, • Initialization of physical layer and event management i.e. connect, removal and power management • Detect receive packets and error checks for received header packets. • Provide an appropriate interface to the protocol layer for information exchanges. 52
2nd International Conference on Power Electronics, Systems and Applications (ICPESA'2013) Sept. 25-26, 2013 Phnom Penh ( Cambodia)
power on state for both downstream and upstream port.
III. DESIGN BLOCK DIAGRAM The following figures indicate the functions of PHY layer.
Fig. 4 Simulation result of the design
Fig. 2 Transmitter block diagram [6]
Fig. 5 Synthesis result of the design
Receiving of SS_INACT determines whether it will be enabled in downstream port or not. Polling is the state for link training. In this state SS_IN_LFPS handshake shall take place between two ports. LOCK_BIT, LOCK_SYM, and DATA_EQL are achieved in this state. Recovery is the state for retraining the link or to perform Hot Reset or to switch to Loop Back mode.. Hot Reset is state defined to allow downstream port to reset upstream port. Another two states, Loop Back and Compliance mode are introduced for bit error test and transmitter compliance test. SS_inactive is the link error state where a link is in non-operable state and software intervention is needed. SS_Disable is the state where super speed connectivity is disabled. In this state BUS will be present but receiving and transmitting of SS_IN_LFPS and S_SPD will be inactive [6].
Fig. 3 Receiver block diagram [6]
IV. DESIGN DESCRIPTION Link training and status state machine is the state machine defined for link connectivity and link power management. It consists of 12 different link states that can be characterized based on their functionalities. U0, U1, U2 and U3 are the four operational link states. In the design there are declare as parameter. U0 is the state where Super speed link is enabled. Packet transfers are in progress or in idle state. U1 is low power link state where no packet transfer is carried out and Super speed link connectivity can be disabled to save power. U2 is also low power state but allow more power saving opportunities. U3 is the link suspended state where aggressive power saving is carried out. Rx_Detect, Polling, Recovery and Hot_Reset are four link states, that are introduced for link initialization and training. Rx_Detect is the 53
2nd International Conference on Power Electronics, Systems and Applications (ICPESA'2013) Sept. 25-26, 2013 Phnom Penh ( Cambodia)
application specific integrated circuits (ASICs). No doubt, it is a big advantage to be able to add super speed USB 3.0 interface to an FPGA based embedded system. Thus because of the invariable development in VLSI technology, it can be expected that this effort will add a new dimension in that trend with its efficiency and this work will play an important role in embedded systems.
V. METHODOLOGY AND HARDWARE ARCHITECTURE
ACKNOWLEDGMENT At first the authors would like to thank to the Almighty for giving the opportunity to finish the work properly. Besides, they would express their gratitude especially to their parents for boundless inspiration and support. Also, they are grateful to Dr. Kazi M. A. Salam, Chairman of EECS Department, North South University for providing the facilities for the completion of this work. REFERENCES [1] [2] [3]
Fig. 6 Design implementation flow [8]
[4]
This project involved three phases – simulation, synthesis and implementation of the Verilog codes in the FPGA board. Modelsim ALTERA Edition 6.5b was used for functional simulation and logical verification at each block level and system level. The Quartus II and Xillinx Synthesis Technology of Xillinx ISE tool both were used for the synthesis of unit i.e. analyzing and compiling the HDL designs, performing timing analysis, examining RTL diagrams and simulating the design’s reaction to different stimulus. The FPGA board Cyclone II EP2C20F484C7 and EPCS4 serial configuration was used in order to implement the design.
[5] [6]
VI. RESULT
VII. CONCLUSION For implementation, FPGA technology offers much more significant advantages than general purpose processors and 54
USB (Universal Serial Bus). Wikipedia the free encyclopedia. Retrieved May 20, 2013, from http://en.wikipedia.org/wiki/USB. Super Speed USB from the USB-IF. Retrieved May 28, 2013, from http://www.usb.org/developers/ssusb. USB - Universal Serial Bus. Retrieved June 01, 2013, from http://compnetworking.about.com/cs/cabling/g/bldef_usb.htm. USB 3.0 Explained: A complete, readable guide to the Super Speed USB Specification. Retrieved June 08, 2013, from http://www.datapro.net/techinfo/usb_3_explained.html. USB 3.0 (Super Speed USB). Wikipedia the free encyclopedia. Retrieved June 14, 2013, from http://en.wikipedia.org/wiki/USB3.0 Universal Serial Bus 3.0 Specification, Available at:
