Ftf4052m Datasheet

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IMAGE SENSORS DATA SHEET FTF4052M 22M Full-Frame CCD Image Sensor Preliminary specification DALSA Professional Imaging 2009 April 24 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M • 36mm x 48 mm optical size • 22M active pixels (4008H x 5344V) • Progressive scan • Excellent anti-blooming • Variable electronic shuttering • Square pixel structure • H and V binning • Vertical subsampling • 100% optical fill factor • High linear dynamic range (>72dB) • High sensitivity Description • Low dark current and fixed-pattern noise • Low read-out noise • Data rate up to 27 MHz • Mirrored, split and four quadrant read-out • Perfectly matched to visual spectrum The FTF4052M is a full frame CCD monochrome image sensor designed for medical, scientific, and industrial applications, with very low dark current and a linear dynamic range of over 12 true bits at room temperature. The four lownoise output amplifiers, one at each corner of the chip, make the FTF4052M suitable for a wide range of high-end visual light applications. With one output amplifier, a progressively scanned image can be read out at one frame per second. By using multiple outputs the frame rate increases accordingly. The device structure is shown in figure 1. • RoHS compliant 6 black lines Z Y Device structure Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Timing pixels: Dummy register cells: Optical black lines: 5356 lines 5344 active lines 36.072 mm (H) x 48.096 mm (V) 38.452 mm (H) x 49.796 mm (V) 9 µm x 9 µm 4008 (H) x 5344 (V) 4056 (H) x 5356 (V) Left: 20 Right: 20 Left: 4 Right: 4 Left: 24 Right: 24 Bottom: 6 Top: 6 Image Area 20 4 4008 active pixels W 24 Output amplifier 4 20 6 black lines 4056 cells Output register X 24 4104 cells Figure 1 - Device structure April 24, 2009 2 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Architecture of the FTF4052M The optical centers of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below and above the image section for readout. After the integration time, the image charge is shifted one line at a time to either the upper or lower register or to both simultaneously, depending on the read-out mode. A separate transfer gate (TG) between the image section and output register will enable sub-sampling features. The left and the right half of each register can be controlled independently. This enables either single or multiple readout. During vertical transport, the C3 gates separate the pixels in the register. The central C3 gates of the lower and upper registers are part of the left half of the sensor (W and Z quadrants respectively). Each register can be used for vertical binning. Each register contains a summing gate at both ends that can be used for horizontal binning (see figure 2). IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacitance of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of overscan (timing)pixels per line Number of black reference pixels per line Total number of pixels per line 60.1mm 3:4 36.072 x 48.096mm2 9µm x9µm 100% 16 pins (A1..A4) 38nF per pin 5344 4 (=2x2) 8 (=2x4) 5356 4008 8 (2x4) 40 (2x20) 4056 OUTPUT REGISTERS Output buffers on each corner Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacitance of each C-clock phase Overlap capacity between neighboring C-clocks Output register Summing Gates Capacitance of each SG Reset Gate clock phases Capacitance of each RG April 24, 2009 Three-stage source follower 2 48 (2x24) 4104 (4056+48) 6 pins per register (C1..C3) 200 pF per pin 40pF 4 pins (SG) 15pF 4 pins (RG) 15pF 3 DALSA Professional Imaging 22M Full-Frame CCD Image Sensor April 24, 2009 Preliminary Specification FTF4052M 4 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Specifications ABSOLUTE MAXIMUM RATINGS1 MIN MAX UNIT GENERAL: storage temperature -40 +80 ºC ambient temperature during operation -20 +60 ºC voltage between any two gates -20 +20 V DC current through any clock (absolute value) -0.2 +0.2 µA OUT current (no short circuit protection) 0 +10 mA VPS, SFD, RD -0.5 +30 V VCS, SFS -8 +5 V All other pins -5 +25 V SFD, RD -15 +0.5 V VCS, SFS, VPS -30 +0.5 V All other pins -30 +0.5 V -5 0 VOLTAGES IN RELATION TO VPS: VOLTAGES IN RELATION TO VNS: VOLTAGES IN RELATION TO SFD: RD DC CONDITIONS 2,3 V TYPICAL [V] 24 MAX [V] 28 MAX [mA] N substrate P substrate MIN [V] 20 5.5 6 6.5 15 SFD Source Follower Drain 19.5 20 20.5 4.5 SFS Source Follower Source 0 0 0 1 VCS Current Source 0 0 0 − OG Output Gate 4.75 5.0 5.25 − RD Reset Drain 19.5 20 20.5 − MIN TYPICAL MAX UNIT IMAGE CLOCKS/ TRANSFER GATES : A-clock amplitude during integration and hold 8 8 8.5 V A-clock amplitude during vertical transport (duty cycle=5/8) 6 11 11 11.5 V A-clock low level - 0 - V Charge Reset (CR) level on A-clock7 -5 0 - V C-clock amplitude (duty cycle during hor. transport=3/6) 4.75 5 5.25 V C-clock low level - 3 - V Summing Gate (SG) amplitude 4.75 5 10 V Summing Gate (SG) low level - 4.5 - V Reset Gate (RG) amplitude 5 5 10 V Reset Gate (RG) low level - 17.0 - V Charge Reset (CR) pulse on Nsub7 0 5 5 V VNS VPS 4 AC CLOCK LEVEL CONDITIONS2 15 5 OUTPUT REGISTER CLOCKS: OTHER CLOCKS: 1 During Charge Reset it is allowed to exceed maximum rating levels (see note 7) All voltages in relation to SFS; typical values are according to test conditions Power-up sequence: VNS, SFD, RD, VPS, all others. The difference between SFD and RD should not exceed 5V during power up or down. 4 To set the VNS voltage for optimal Vertical Antiblooming (VAB), it should be adjustable between minimum and maximum values 5 Transfer gate should be clocked as A1 during normal transport or held low during a line shift to sub-sample image 6 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 3V higher than the voltage during integration A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed 7 Charge Reset can be achieved in two ways of which the first method is preferred: A. The typical A-clock low level is applied to all image clocks for proper CR, an additional Charge Reset pulse on VNS is required B. The minimum CR level is applied to all image clocks simultaneously 2 3 April 24, 2009 5 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Timing diagrams (for default operation) AC CHARACTERISTICS 1 Horizontal frequency (1/Tp) Vertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) register clocks (C)2 summing gate (SG) reset gate (RG) 1 2 MIN. 10 10 3 3 - TYPICAL 25 50 Line time 20 5 5 3 MAX. 27 100 1/8 Tp 1/8 Tp 1/8 Tp UNIT MHz kHz µs ns ns ns ns Tp = 1 clock period Duty cycle = 3/6 Frame timing 5356 image lines SSC 1 1 1 1 5356 1 5353 5354 5355 1 1 1 CR 6 black 5348 5349 5350 7 8 9 2 3 4 5 6 5344 active lines H L Trig_in H L H L VA high H L TG/A1 H L A2 H L A3 H L A4 H L NS pulse/CR 1 1 1 1 1 1 6 black integration idle 5351 5352 integration CR REMARKS * CR is applied during the first line after the transition from L to H of Trig_in * CCD is integrating during high period of Trig_in * After read-out sequence the timing will go into idle mode. Figure 3 - Frame timing diagram April 24, 2009 6 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Active Pixels Falling edge of pixel 4763 5us 682 12.4us 7.5us 10us 558 H L 7.5us 496 A4 Active Pixels 434 A3 H L 27.4us 372 A2 H L 7.5us 310 TG/A1 H L 27.4us 248 VA high H L Rising edge of pixel 0 124 SSC H L B 4008 20 24 black 4 overscan dummy 20 4 black overscan 684 4008 Pixel numbers represent the beginning of the pixel concerned B 186 Sensor Output 684 708 728 732 4740 4744 Line timing - single output 7.5us 14.9us REMARKS * Thorizontal = 4764 * 1/25E6 = 190.6us * Vertical transport frequency = 50kHz 684 708 728 732 Line timing - dual output Pixel numbers represent the beginning of the pixels concerned Sensor Output Active Pixels B 7.5us 682 7.5us 558 10us 496 H L 5us 12.4us 434 A4 7.5us 372 A3 H L 27.4us 310 A2 H L 7.5us 248 TG/A1 H L 27.4us 186 VA high H L Rising edge of pixel 0 124 H L 684 Falling edge of pixel 2740 SSC Active Pixels 4008 20 24 black 4 overscan dummy 2004 14.9us REMARKS * Thorizontal = 2740 * 1/25E6 = 109.6us * Vertical transport frequency = 50kHz Figure 4 - Vertical read-out, single and dual modes April 24, 2009 7 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Pixel timing SSC SSC clocked with rising edge of C2 C3 C1 C2 SG RG SINGLE OUTPUT 7 dummy 20 black 4 overscan DUAL OUTPUT 7 dummy 20 black 4 overscan 4008 active 4 overscan 20 black 2004 active SENSOR PIN SINGLE OUTPUT Left SINGLE OUTPUT Right DUAL OUTPUT C1L C2L C3L C1R C2R C3R C1 C2 C3 C1 C2 C3 C2 C1 C3 C2 C1 C3 C1 C2 C3 C2 C1 C3 40ns 20ns C3 C1 C2 SG RG Sensor output H L 13.33ns H L 26.67ns H L PHIC'S @ 25MHz H L 6.67ns H L RG black signal Figure 5 - Start horizontal read-out, single and dual modes April 24, 2009 8 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor Performance The test conditions for the performance characteristics are as follows: • All values are measured using typical operating conditions. • VNS is adjusted as low as possible while maintaining proper Vertical Anti-Blooming. • Sensor temperature =60°C (333K). • Horizontal transport frequency =18MHz. FTF4052M • • • Vertical transport frequency =50kHz. Integration time =100ms. The light source is a lamp of 3200K in conjunction with neutral density filters and a 1.7mm thick BG40 infrared cut-off filter. For Linear Operation measurements, a temperature conversion filter (Melles Griot type no.03FCG261, -120 mired, thickness: 2.5mm) is applied. LINEAR OPERATION 1 3 MAX. UNIT 0.999999 - Image lag - 0 0 % Resolution (MTF) @ 56 lp/mm 65 - - % Light sensitivity 1500 2000 2500 mV/lux·s Block-to-block difference - 0.3 1.0 % Stitching effect - 0.7 3.0 % Low Pass Shading 2 - 2 5 % - 1 5 % Random Non-Uniformity (RNU) 2 TYPICAL - Charge Transfer 1 MIN. 3 Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. Low Pass Shading is defined as the ratio of the one- value of an 8x8 pixels blurred image (low-pass) to the mean signal value. value of the high-pass image to the mean signal value at nominal light. RNU is defined as the ratio of the one- 9216 35°C 8192 Linear Dynamic Range 7168 45°C 6144 5120 4096 55°C 3072 2048 1024 0 0 5 10 15 20 25 30 Horizontal Read-out Frequency (MHz) Linear dynamic range is defined as the ratio of Q lin to read-out noise with the read-out noise reduced by CDS. Figure 6 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature April 24, 2009 9 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M 5.0 4.5 4.0 Images/se c. 3.5 3.0 4 outputs 2.5 2.0 2 outputs 1.5 1.0 1 output 0.5 0.0 0 20 10 30 40 50 60 70 90 80 100 Integration Time (m s) Figure 7 - Maximum number of images/second versus integration time 100% Horizontal 90% Vertical 80% Response (%) 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 25 30 Angle of illumination (degrees) Figure 8 - Angular response versus angle of illumination April 24, 2009 10 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M 30 25 Quantum Efficiency (%) 20 15 10 5 0 380.00 430.00 480.00 530.00 580.00 630.00 680.00 730.00 780.00 830.00 880.00 930.00 980.00 Wavelength (nm) Figure 9 – Quantum efficiency versus wavelength April 24, 2009 11 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M LINEAR/SATURATION MIN. TYPICAL MAX. UNIT Full-well capacity saturation level (Qmax ) 1 2000 3400 - mV Full-well capacity linear operation (Qlin) 2 2000 2500 - mV Charge handling capacity 3 - 6000 - mV Overexposure 4 handling - 200 - x Qmax level Qmax is determined from the low-pass filtered image. The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The test guarantees 97% linearity. Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer. 4 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB) is tested by measuring the dark line along the image section. 1 2 3 3500 Output Signal (mV) 2800 2100 1400 700 0 0 1 2 3 4 5 Exposure (arbitrary units) Figure 10 - Charge handling April 24, 2009 12 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor OUTPUT BUFFERS FTF4052M MIN TYPICAL MAX UNIT Conversion factor 18 20 22 µV/el. Mutual conversion factor matching (∆ACF)1 - 0 2 µV/el. Supply current - 4.5 - mA Bandwidth (Rload=3.3Ω) 90 105 - MHz Output impedance buffer (Rload=3.3Ω, Cload=2pF - 400 - Ω Matching of the four outputs is specified as ∆ACF with respect to reference measured at the operating point (Qlin/2) 1 DARK CONDITION MIN TYPICAL MAX UNIT Dark current level @ 20°C Dark current level @ 60°C - 10 30 pA/cm2 - 0.3 0.6 nA/cm2 Fixed Pattern Noise (FPN) @ 60ºC - 40 60 mV/s Amplifier noise over full bandwidth after CDS - 0.5 - mV 1 1 FPN is one-σ value of the high-pass image and normalized at 1 sec integration time Dark Current (pA/cm2 ) 1000 100 10 1 0 10 20 30 40 50 60 Temp. (oC) Figure 11 - Dark current versus temperature April 24, 2009 13 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor Application information Current handling One of the purposes of VPS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the VRD connection and, if excessive (from over-exposure), free electrons are drained to VNS. No current should flow into any VPS connection of the sensor. During high overexposure a total current of 5 to 10mA through all VPS connections together may be expected. The PNP emitter follower in the circuit diagram (figure 12) serves these current requirements. VNS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure a total current of 5 to 10mA through all VNS connections together may be expected. The clamp circuit, consisting of the diode and electrolytic capacitor, enables the addition of a Charge Reset (CR) pulse on top of an otherwise stable VNS voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance Uncoupling of DC voltages All DC voltages (not VNS, which has additional CR pulses as described above) should be uncoupled with a 22nF uncoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will flow through VRD. Therefore a large series resistor in the VRD connection may be used. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about FTF4052M 400 ) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a too-small quiescent current in the emitter follower; about 10mA should do the job. The collector of the emitter follower should be uncoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3k3 typically results in a bandwidth of 85MHz. Device protection The output buffers of the FTF4052M are likely to be damaged if VPS rises above SFD or RD at any time. This danger is most realistic during power-on or power-off of the camera. The RD voltage should always be lower than the SFD voltage. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 10mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Because of the fact that our CCDs are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 12. Unused sections To reduce power consumption the following steps can be taken. Connect unused output register pins (C1...C4, SG) and unused SFS pins to zero Volts. Device Handling An image sensor is an MOS device which can be destroyed by electro-static discharge (ESD). Therefore, the device should be handled with care. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use fingercots. April 24, 2009 When cleaning the glass we recommend using ethanol (or possibly water). Use of other liquids is strongly discouraged: • if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. • the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Dry rubbing of the window may cause electro-static charges or scratches which can destroy the device. 14 BAT74 22n NS 120K 20K 9K 100K CR 31K5 7K5 22n 0E NS NS VPS VRD NS VPS SFD 22n BAS28 100K BAS28 100K BAS28 100K BAS28 100K 100K CCD OUT BAS28 47K A2 1u TG 100K BC860C BAS28 BAS28 100K VOG BAS28 56K 22K A1 22n A4 BAT74 BAT74 A3 BAT74 BAS28 NS_CR 100E BAS28 B1 B2 A2 A1 C2 A5 B4 A4 A3 B5 B6 A8 A7 B7 A6 A10 C9 A9 B9 B10 VOG OUT SFD VPS VNS VNS TG A4W A3W A2W A1W A1Z A2Z A3Z A4Z TG VNS VNS VPS SFD OUTZ VRD B8 OG NS_CR 22n 22n 22n 22n 22n 2K2 VRD NS BAS28 NS_CR image sensor CCD D10 RD 35V D2 M9 NS NS_CR C2 22n SFS D9 SFS E9 RG C2 F1 C3 G2 OG B3 22n VNS G10 VNS G1 VCS C10 C1 E10 SG D1 VNS M10 VNS M1 BAS28 RD N10 C3 M2 RG F9 E2 N9 C2 C3 22n SG F10 C1 E1 P10 N1 VCS 22n G9 C2 22n P9 C1 C1 N2 C1 C3 F2 R10 SG SG RG RG P2 RD R1 T8 22n 22n 22n VRD T1 T2 U2 U1 S2 U5 T4 U4 U3 T5 T6 U8 U7 T7 U6 U10 S9 U9 T9 T10 VOG OUT SFD VPS VNS VNS TG A4X A3X A2X A1X A1Y A2Y A3Y A4Y TG VNS VNS VPS SFD OUTY VRD NS_CR 22n BAS28 BAS28 H DRIVER 74ACT04 1 74ACT04 H DRIVER 1 H DRIVER 74ACT04 1 NS VSFD VPS NS VPS SFD From PPG 22M Full-Frame CCD Image Sensor 22n 22n 22n 22n 22n 22n 22n 22n 22n 22n RD P1 VCS S10 VCS S1 SFS R9 SFS R2 OG T3 OG 22n NS_CR 22n 22n April 24, 2009 SG RG C1 C2 C3 From V-Driver DALSA Professional Imaging Preliminary Specification FTF4052M NS_CR BFR92 22n 12K Figure 12 – Application diagram for single output operation 15 3K3 VSFD DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Pin configuration The FTF4052M is mounted in a Pin Grid Array (PGA) package with 80 pins in a 20x25 grid of 51.30 x 64.00 mm2. The position of pin A1 (quadrant W) is marked with a gold Symbol VNS TG VNS VNS VPS SFD SFS VCS OG RD A1 A2 A3 A4 C1 C2 C3 SG RG OUT Name N substrate Transfer Gate N substrate N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain Image Clock (Phase 1) Image Clock (Phase 2) Image Clock (Phase 3) Image Clock (Phase 4) Register Clock (Phase 1) Register Clock (Phase 2) Register Clock (Phase 3) Summing Gate Reset Gate Output dot on top of the package. The image clock phases of quadrant W are internally connected to X, and Y is connected to Z. Pin # W A1 A5 C2 G1 A2 B2 D2 C1 B3 D1 B5 A3 A4 B4 F2 F1 G2 E1 E2 B1 Pin # X P1 P5 M2 H1 P2 N2 L2 M1 N3 L1 N5 P3 P4 N4 J2 J1 H2 K1 K2 N1 Pin # Y P10 P6 M9 H10 P9 N9 L9 M10 N8 L10 N6 P8 P7 N7 J9 J10 H9 K10 K9 N10 Pin # Z A10 A6 C9 G10 A9 B9 D9 C10 B8 D10 B6 A8 A7 B7 F9 F10 G9 E10 E9 B10 Figure 13 - Pin configuration (top view) April 24, 2009 16 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M 51.3±0.51 [6.42] Z Y W X [7.12] 32.00±0.15 COVER GLASS EPOXY GLUE 49.76 A 64.00±0.64 SENSOR CHRYSTAL 38.46 INDEX-MARK PIN 1 4.47±0.39 1±0.05 (Cover glass) AR COAT 0.04 1.27±0.15 4.57±0.15 1° 1.68±0.20 (Image area - top cover glass) 25.65±0.15 1.4/100 Ø0.46±0.05 60.96±0.60 A is the center of the image area Position of A: 25.65 ± 0.15 to left edge of package 32.00 ± 0.15 to lower edge of package 2.79 ± 0.15 to bottom of package Angle of rotation: less then ± 1° Sensor flatness: < 40 µm (P-V) (2.54) Cover glass: Hoya CG1 Thickness of cover glass: 1 ± 0.05 Refractive index: nd = 1.506 Double sided AR coating < 1% (430-660nm) reflection Hermetically sealed package All drawing units are in mm (2.54) 48.26±0.27 Figure 14 – Mechanical drawing of the PGA package April 24, 2009 17 DALSA Professional Imaging Preliminary Specification 22M Full-Frame CCD Image Sensor FTF4052M Order codes The sensor can be ordered using the following code: Description FTF4052M sensors Quality Grade Order Code FTF4052M/HG High grade 9922 157 73111 FTF4052M/IG Industrial grade 9922 157 73121 FTF4052M/EG Economy grade 9922 157 73151 FTF4052M/TG Test grade 9922 157 73131 Defect Specifications The CCD image sensor can be ordered in a specific quality grade. The grading is defined with the maximum amount of pixel defects, column defects, row defects and cluster defects, in both illuminated and non-illuminated conditions. For detailed grading information, please contact your local DALSA representative. For More Information For more detailed information on this and other products, contact your local rep or visit our Web site at http://www.dalsa.com/sensors/products/products.asp. DALSA Professional Imaging Sales Department High Tech Campus 27 5656 AE Eindhoven The Netherlands Tel: +31 40 259 9009 Fax: +31 40 259 9015 http://www.dalsa.com/sensors [email protected] This information is subject to change without notice. April 24, 2009 18