Transcript
Specifications GAL22V10
GAL22V10
High Performance E2CMOS PLD Generic Array Logic™ Functional Block Diagram
Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 4 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology
RESET
I/CLK
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I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
10
• ACTIVE PULL-UPS ON ALL PINS
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• COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices • 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR — 90mA Typical Icc on Low Power Device — 45mA Typical Icc on Quarter Power Device
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PROGRAMMABLE AND-ARRAY (132X44)
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• E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention
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• TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability
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16
16
14
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• APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade
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I PRESET
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Pin Configuration
• LEAD-FREE PACKAGE OPTIONS ESCRIPTION
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The GAL22V10, at 4ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V10 to consume much less power when compared to bipolar 22V10 devices. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently.
I
2
I/O/Q
28
I/O/Q
Vcc
I/CLK
NC
I
I
PLCC
Description
DIP
26
5
25
I I
I
7
GAL22V10 Top View
9
23
21
I
I/CLK
11
I/O/Q
I
I/O/Q
I/O/Q
I
I
I/O/Q
I
13
18
I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I
I/O/Q I/O/Q
Vcc 24
12 I I I I I GND
6 I I
1 I/CLK I I I
GND
I/O/Q
6
I/O/Q 18
I
Top View
I/O/Q
GAL 22V10
I
I/O/Q
GAL22V10
1
Vcc
I
SOIC
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
24
NC
I/O/Q
19 18
16 NC
I
14
I
12
1
I/O/Q
I/O/Q
GND
I
I/O/Q I/O/Q
NC
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices.
22v10_12
OLMC
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q 12
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Specifications GAL22V10 GAL22V10 Ordering Information Conventional Packaging Commercial Grade Specifications Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
Ordering #
Package
4
2.5
3. 5
140
GAL22V10D-4LJ
5
3
4
140
GAL22V10D-5LJ
28-Lead PLCC
7.5
4.5
4. 5
140
GAL22V10D-7LP
24-Pin Plastic DIP
4.5
4.5
140
GAL22V10D-7LJ
28-Lead PLCC
7
7
55
GAL22V10D-10QP
24-Pin Plastic DIP
55
GAL22V10D-10QJ
28-Lead PLCC
130
GAL22V10D-10LP
24-Pin Plastic DIP
130
GAL22V10D-10LJ
28-Lead PLCC
30
GAL22V10D-10LS1
24-Pin SOIC
55
GAL22V10D-15QP
24-Pin Plastic DIP
55
GAL22V10D-15QJ
28-Lead PLCC
90
GAL22V10D-15LP
24-Pin Plastic DIP
90
GAL22V10D-15LJ
28-Lead PLCC
90
GAL22V10D-15LS1
24-Pin SOIC
55
GAL22V10D-25QP
24-Pin Plastic DIP
55
GAL22V10D-25QJ
28-Lead PLCC
90
GAL22V10D-25LP
24-Pin Plastic Dip
10
15
25
10
15
8
15
28-Lead PLCC
90
GAL22V10D-25LJ
28-Lead PLCC
90
GAL22V10D-25LS1
24-Pin SOIC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
Industrial Grade Specifications Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
7.5
5
4. 5
160
GAL22V10D-7LPI
24-Pin Plastic DIP
4.5
4. 5
160
GAL22V10D-7LJI
28-Lead PLCC
7
7
160
GAL22V10D-10LPI
24-Pin Plastic DIP
160
GAL22V10D-10LJI
28-Lead PLCC
13 0
GAL22V10D-15LPI
24-Pin Plastic DIP
130
GAL22V10D-15LJI
28-Lead PLCC
130
GAL22V10D-20LPI
24-Pin Plastic DIP
130
GAL22V10D-20LJI
28-Lead PLCC
13 0
GAL22V10D-25LPI
24-Pin Plastic DIP
130
GAL22V10D-25LJI
28-Lead PLCC
10
15
20
25
10
14
15
8
10
15
Ordering #
2
Package
Specifications GAL22V10 Lead-Free Packaging Commercial Grade Specifications Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
4
2. 5
3. 5
140
GAL22V10D-4LJN
Lead-Free 28-Lead PLCC
5
3
4
140
GAL22V10D-5LJN
Lead-Free 28-Lead PLCC
7.5
4. 5
4.5
14 0
GAL22V10D-7LPN
Lead-Free 24-Pin Plastic DIP
4.5
4.5
14 0
GAL22V10D-7LJN
Lead-Free 28-Lead PLCC
7
7
55
GAL22V10D-10QPN
Lead-Free 24-Pin Plastic DIP
10
15
25
10
8
15
15
Ordering #
Package
55
GAL22V10D-10QJN
Lead-Free 28-Lead PLCC
130
GAL22V10D-10LPN
Lead-Free 24-Pin Plastic DIP
130
GAL22V10D-10LJN
Lead-Free 28-Lead PLCC
55
GAL22V10D-15QPN
Lead-Free 24-Pin Plastic DIP
55
GAL22V10D-15QJN
Lead-Free 28-Lead PLCC
90
GAL22V10D-15LPN
Lead-Free 24-Pin Plastic DIP
90
GAL22V10D-15LJN
Lead-Free 28-Lead PLCC
55
GAL22V10D-25QPN
Lead-Free 24-Pin Plastic DIP
55
GAL22V10D-25QJN
Lead-Free 28-Lead PLCC
90
GAL22V10D-25LPN
Lead-Free 24-Pin Plastic Dip
90
GAL22V10D-25LJN
Lead-Free 28-Lead PLCC
Industrial Grade Specifications Tpd (ns) 7.5
10
Tsu (ns)
Tco (ns)
Icc (mA)
Ordering #
Package
5
4. 5
160
GAL22V10D-7LPNI
Lead-Free 24-Pin Plastic DIP
4.5
4. 5
160
GAL22V10D-7LJNI
Lead-Free 28-Lead PLCC
7
7
160
GAL22V10D-10LPNI
Lead-Free 24-Pin Plastic DIP
160
GAL22V10D-10LJNI
Lead-Free 28-Lead PLCC
130
GAL22V10D-15LPNI
Lead-Free 24-Pin Plastic DIP
15
10
8
20
14
10
25
15
15
130
GAL22V10D-15LJNI
Lead-Free 28-Lead PLCC
130
GAL22V10D-20LPNI
Lead-Free 24-Pin Plastic DIP
130
GAL22V10D-20LJNI
Lead-Free 28-Lead PLCC
130
GAL22V10D-25LPNI
Lead-Free 24-Pin Plastic Dip
130
GAL22V10D-25LJNI
Lead-Free 28-Lead PLCC
Part Number Description XXXXXXXX _ XX
X XX X
GAL22V10D Device Name Grade
Speed (ns)
L = Low Power Power Q = Quarter Power
Blank = Commercial I = Industrial
Package P = Plastic DIP PN = Lead-Free Plastic DIP J = PLCC JN = Lead-Free PLCC S = SOIC
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Specifications GAL22V10 Output Logic Macrocell (OLMC) The GAL22V10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 14 and 23, DIP pinout), two have ten product terms (pins 15 and 22), two have twelve product terms (pins 16 and 21), two have fourteen product terms (pins 17 and 20), and two OLMCs have sixteen product terms (pins 18 and 19). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.
The GAL22V10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low.
A R
D
4 TO 1 MUX
Q CLK
Q SP
2 TO 1 MUX
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins.
Each of the Macrocells of the GAL22V10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page.
COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either “on” (dedicated output), “off” (dedicated input), or “product-term driven” (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array.
REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC’s D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array.
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Specifications GAL22V10 Registered Mode
AR
AR
Q
D
CLK
Q
D
Q
CLK
SP
Q SP
ACTIVE LOW
ACTIVE HIGH
S0 = 0 S1 = 0
S0 = 1 S1 = 0
Combinatorial Mode
ACTIVE LOW
ACTIVE HIGH
S0 = 0 S1 = 1
S0 = 1 S1 = 1
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Specifications GAL22V10 GAL22V10 Logic Diagram / JEDEC Fuse Map DIP (PLCC) Package Pinouts 1 (2) 0
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET (TO ALL REGISTERS)
0000 0044 . . . 0396
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OLMC S0 5808 S1 5809
0440 . . . . 0880
10
OLMC S0 5810 S1 5811
2 (3) 0924 . . . . . 1452
12
OLMC S0 5812 S1 5813
3 (4) 1496 . . . . . . 2112
14
OLMC
23 (27)
22 (26)
21 (25)
20 (24)
S0 5814 S1 5815
4 (5) 2156 . . . . . . . 2860
16
OLMC
19 (23)
S0 5816 S1 5817
5 (6) 2904 . . . . . . . 3608
16
OLMC
18 (21)
S0 5818 S1 5819
6 (7) 3652 . . . . . . 4268
14
OLMC
17 (20)
S0 5820 S1 5821
7 (9) 4312 . . . . . 4840
12
OLMC S0 5822 S1 5823
8 (10) 4884 . . . . 5324
10
OLMC S0 5824 S1 5825
9 (11) 5368 . . . 5720
8
OLMC S0 5826 S1 5827
10 (12)
SYNCHRONOUS PRESET (TO ALL REGISTERS)
5764
11 (13) 5828, 5829 ...
Electronic Signature
... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 M S B
L S B
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16 (19)
15 (18)
14 (17)
13 (16)
Specifications SpecificationsGAL22V10D GAL22V10 Absolute Maximum Ratings1
Recommended Operating Conditions Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75°C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied . ......................... -2.5 to VCC +1.0V Off-state output voltage applied........... -2.5 to VCC +1.0V Storage Temperature . ................................ -65 to 150°C Ambient Temperature with Power Applied . ....................................... -55 to 125°C
Industrial Devices: Ambient Temperature (TA) ............................ -40 to 85°C Supply voltage (VCC) with Respect to Ground ..................... +4.50 to +5.50V
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
Vss – 0.5
—
0.8
V
Input High Voltage
2.0
—
Vcc+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
–100
μA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
μA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.4
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–30
—
–130
mA
Output Short Circuit Current
COMMERCIAL ICC Operating Power Supply Current
INDUSTRIAL ICC Operating Power Supply Current
VCC = 5V
VOUT = 0.5V TA = 25°C
VIL = 0.5V VIH = 3.0V
L-4/-5/-7
—
90
140
mA
ftoggle = 15MHz Outputs Open
L-10
—
90
130
mA
L-15/-25
—
75
90
mA
Q-10/-15/-25
—
45
55
mA
VIL = 0.5V VIH = 3.0V
L-7/-10
—
90
160
mA
ftoggle = 15MHz Outputs Open
L-15/-20/-25
—
75
130
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and TA = 25 °C
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Specifications GAL22V10D Specifications GAL22V10 AC Switching Characteristics Over Recommended Operating Conditions
PARAM
TEST COND.1
tpd tco tcf2 tsu th
COM
COM
COM/IND
-4
-5
-7
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
A
Input or I/O to Combinatorial Output
1
4
1
5
1
7.5
ns
A
Clock to Output Delay
1
3.5
1
4
1
4.5
ns
—
Clock to Feedback Delay
—
2.5
—
3
—
3
ns
—
Setup Time, Input or Fdbk before Clk↑
2.5
—
3
—
4.5
—
ns
—
Hold Time, Input or Fdbk after Clk↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with External Feedback, 1/(tsu + tco)
167
—
142.8
—
111
—
MHz
A
Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf)
200
—
166
—
133
—
MHz
A
Maximum Clock Frequency with No Feedback
250
—
200
—
166
—
MHz
—
Clock Pulse Duration, High
2
—
2.5
—
3
—
ns
—
Clock Pulse Duration, Low
2
—
2.5
—
3
—
ns
B
Input or I/O to Output Enabled
1
5
1
6
1
7.5
ns
tdis tar
C
Input or I/O to Output Disabled
1
5
1
5.5
1
7.5
ns
A
Input or I/O to Asynch. Reset of Reg.
1
4.5
1
5.5
1
9
ns
tarw tarr tspr
—
Asynch. Reset Pulse Duration
4.5
—
4.5
—
7
—
ns
—
Asynch. Reset to Clk↑ Recovery Time
3
—
4
—
5
—
ns
—
Synch. Preset to Clk↑ Recovery Time
3
—
4
—
5
—
ns
fmax3
twh twl ten
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. Characterized initially and after any design or process changes that may affect these parameters.
Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
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Specifications SpecificationsGAL22V10D GAL22V10 AC Switching Characteristics Over Recommended Operating Conditions
PARAM.
TEST COND.1
tpd tco tcf2 tsu th
fmax3
COM / IND
COM / IND
IND
COM / IND
-10
-15
-20
-25
DESCRIPTION
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
A
Input or I/O to Comb. Output
1
10
3
15
3
20
3
25
ns
A
Clock to Output Delay
1
7
2
8
2
10
2
15
ns
—
Clock to Feedback Delay
—
2.5
—
2.5
—
8
—
13
ns
—
Setup Time, Input or Fdbk before Clk↑
6
—
10
—
12
—
15
—
ns
—
Hold Time, Input or Fdbk after Clk↑
0
—
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with External Feedback, 1/(tsu + tco)
83.3
—
55.5
—
41.6
—
33.3
—
MHz
A
Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf)
110
—
80
—
45.4
—
35.7
—
MHz
A
Maximum Clock Frequency with No Feedback
125
—
83.3
—
50
—
38.5
—
MHz
—
Clock Pulse Duration, High
4
—
6
—
10
—
13
—
ns
—
Clock Pulse Duration, Low
4
—
6
—
10
—
13
—
ns
B
Input or I/O to Output Enabled
1
10
3
15
3
20
3
25
ns
C
Input or I/O to Output Disabled
1
9
3
15
3
20
3
25
ns
A
Input or I/O to Asynch. Reset of Reg.
1
13
3
20
3
25
3
25
ns
twh twl ten tdis tar tarw tarr
—
Asynch. Reset Pulse Duration
8
—
15
—
20
—
25
—
ns
—
Asynch. Reset to Clk↑ Recovery Time
8
—
10
—
20
—
25
—
ns
tspr
—
Synch. Preset to Clk↑ Recovery Time
8
—
10
—
14
—
15
—
ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
Capacitance (TA = 25°C, f = 1.0 MHz) SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
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Specifications GAL22V10 Switching Waveforms
INPUT or I/O FEEDBACK
INPUT or I/O FEEDBACK
VALID INPUT
VALID INPUT
tsu
th
t pd CLK
COMBINATORIAL OUTPUT
tco REGISTERED OUTPUT
Combinatorial Output
1/ fmax (external fdbk)
Registered Output INPUT or I/O FEEDBACK
t dis
t en
OUTPUT
CLK 1/ f max (internal fdbk)
Input or I/O to Output Enable/Disable
tsu
t cf REGISTERED FEEDBACK
fmax with Feedback tw l
tw h CLK 1 / fm a x
(w/o fdbk)
Clock Width
INPUT or I/O FEEDBACK DRIVING SP
INPUT or I/O FEEDB ACK DRIVI NG AR
tsu
th
t spr
tarw
CLK
CLK
tarr
tco
R E G I S T ER E D OUTPUT
REGISTERED OUTPUT
tar Synchronous Preset
Asynchronous Reset
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Specifications GAL22V10 fmax Descriptions CL K
LOGIC ARR AY
CLK
LOGIC ARRAY
R EG I S T E R
REGISTER
ts u
tc o
fmax with External Feedback 1/(tsu+tco)
t cf t pd
Note: fmax with external feedback is calculated from measured tsu and tco.
fmax with Internal Feedback 1/(tsu+tcf)
CLK
LOGIC ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
REGISTER
tsu + th
fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
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Specifications GAL22V10 Switching Test Conditions Input Pulse Levels
GAL22V10D-4 Output Load Conditions (see figure below)
GND to 3.0V
Input Rise and
D-4/-5/-7
1.5ns 10% – 90%
Fall Times
D-10/-15/-20/-25
2.0ns 10% – 90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
Test Condition A B
See Figure
C
3-state levels are measured 0.5V from steady-state active level.
R1
CL
50Ω
50pF
Z to Active High at 1.9V
50Ω
50pF
Z to Active Low at 1.0V
50Ω
50pF
Active High to Z at 1.9V
50Ω
50pF
Active Low to Z at 1.0V
50Ω
50pF
+1.45V
Output Load Conditions (except D-4) (see figure below) R1
R2
CL
300Ω
390Ω
50pF
Active High
∞
390Ω
50pF
Active Low
300Ω
390Ω
50pF
Active High
∞
390Ω
5pF
Active Low
300Ω
390Ω
5pF
Test Condition A B C
TEST POINT R1 FROM OUTPUT (O/Q) UNDER TEST
+5V
R1
FROM OUTPUT (O/Q) UNDER TEST
TEST POINT
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
12
Z0 = 50Ω, CL*
Specifications GAL22V10 Electronic Signature
Output Register Preload
An electronic signature (ES) is provided in every GAL22V10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell.
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions.
The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically a GAL22V10 and a GAL22V10-UES (UES = User Electronic Signature) or GAL22V10-ES. This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature.
The GAL22V10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
Input Buffers
The JEDEC map for the GAL22V10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the GAL22V10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer.
GAL22V10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
Security Cell
The input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.)
A security cell is provided in every GAL22V10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
Typical Input Current I n p u t C u r r e n t (u A )
Latch-Up Protection GAL22V10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
0
-20
-40 -60 0
1.0
2.0
3.0
In p u t V o lt ag e ( V o lt s)
Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
13
4.0
5.0
Specifications GAL22V10 Power-Up Reset Vcc (min.)
Vcc
t su t wl
CLK
t pr INTERNAL REGISTER Q - OUTPUT
Internal Register Reset to Logic "0"
ACTIVE LOW OUTPUT REGISTER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGISTER
Device Pin Reset to Logic "0"
Circuitry within the GAL22V10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1μs MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Input/Output Equivalent Schematics PIN
PIN Feedback
Vcc Active Pull-up Circuit
Active Pull-up Circuit
(Vref Typical = 3.2V)
Vcc ESD Protection Circuit
Vref
Tri-State Control
Vcc
PIN
Vcc
(Vref Typical = 3.2V)
Vref
Data Output
PIN
ESD Protection Circuit Feedback (To Input Buffer)
Typical Input
Typical Output
14
Specifications GAL22V10 GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc
RISE FALL
1
0.95
RISE FALL
1.05
1
0.95
4.5
4.75
5
5.25
1
0.95
0.9 4.5
5.5
4.75
Supply Voltage (V)
5
5.25
5.5
4.5
Normalized Tpd vs Temp
Normalized Tco vs Temp
1.1
1
1.2
RISE FALL
1.1
1
0.9 -55 50
75
100
1.1
1
0.8 -25
Temperature (deg. C)
25
50
75
125
-55
-25
0
-0.1
RISE FALL
-0.2
-0.1
-0.2
RISE FALL
-0.3
-0.4 1
2
3
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
12
Delta Tco (ns)
RISE FALL
8
4
0
-4 50
100
150
200
250
300
Output Loading (pF)
RISE FALL
8
4
0
-4 0
25
50
75
100
Temperature (deg. C)
Delta Tco vs # of Outputs Switching
0
-0.3
Delta Tpd (ns)
100
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0
Delta Tpd (ns)
0
125
Delta Tco (ns)
25
RISE FALL
0.9
0.8 0
5.5
Normalized Tsu vs Temp
0.9
-25
5.25
1.3
Normalized T
Normalized Tco
RISE FALL
5
Supply Voltage (V)
1.2
-55
4.75
Supply Voltage (V)
1.3
1.2
RISE FALL
1.05
0.9
0.9
Normalized Tpd
1.1
Normalized Tsu
Normalized Tco
Normalized Tpd
1.05
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.1
1.1
0
50
100
150
200
250
Output Loading (pF)
15
300
125
Specifications GAL22V10 GAL22V10D-4/-5/-7/-10L (PLCC): Typical AC and DC Characteristic Diagrams Vol vs Iol
Voh vs Ioh
Voh vs Ioh 3.95
4
0.6
3.85 3.75
Vol (V)
Voh (V)
0.4
Voh (V)
3
2
0.2
3.65 3.55 3.45 3.35
1
3.25 3.15 0.00
0
0 0
5
10
15
20
25
30
35
0
40
5
10 1 5 2 0 2 5 3 0 3 5 4 0 4 5 50 55 60
Normalized Icc vs Vcc
Normalized Icc vs Temp
0.9
5
5.25
1 0.9
0.7 -55
5.5
Supply Voltage (V)
0
25
50
88
100
125
5
20
4
40
3 2
60 80
1 100 0 0
0.5
1
1.5
2
2.5
3
Vin (V)
3.5
4
4.5
5
-3
1.05
1
-2.5
-2
-1.5
Vik (V)
16
-1
-0.5
1
15
25
50
Frequency (MHz)
Input Clamp (Vik) 0
Iik (mA)
Delta Icc (mA)
Delta Icc vs Vin (1 input)
1.1
0.95 -25
Temperature (deg. C)
6
5.00
1.15
1.1
0.8
4.75
4.00
Normalized Icc vs Freq
Normalized Icc
Normalized Icc
Normalized Icc
1
3.00
1.2
1.2 1.1
2.00
Ioh(mA)
1.3
1.2
0.8 4.5
1.00
Ioh(mA)
Iol (mA)
1
75
1 00
Specifications GAL22V10 GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc
1.2
1
0.95
RISE FALL
Normalized Tsu
Normalized Tco
1.05
1
4.75
5
5.25
4.5
5.5
4.75
Normalized Tpd vs Temp
0.9
5
5.25
4.5
5.5
4.75
Normalized Tco
1.1
1
5.25
5.5
Normalized Tsu vs Temp
1.2
RISE FALL
5
Supply Voltage (V)
Normalized Tco vs Temp
1.3
1.3
RISE FALL
1.2
RISE FALL
1.1
1
0.9
0.9
1.1
1
0.9
25
50
75
100
0.8 -55
125
-25
0
25
50
75
100
0.8 -55
125
-25
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 -0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4 -0.5 -0.6 -0.7
RISE FALL
-0.8 -0.9
0
-0.4 -0.5 -0.6 -0.7
RISE FALL
-0.8 -0.9
-1
-1
-1.1
-1.1 1
2
3
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading 12
12
Delta Tco (ns)
RISE FALL
8
4
0
-4
RISE FALL
8
4
0
-4 0
50
100
150
200
250
300
Output Loading (pF)
0
50
100
150
200
250
Output Loading (pF)
17
25
50
75
100
Temperature (deg. C)
Delta Tco vs # of Outputs Switching
0
Delta Tco (ns)
0
Delta Tpd (ns)
-25
Delta Tpd (ns)
0.8 -55
1
Supply Voltage (V)
Supply Voltage (V)
1.2
RISE FALL
1.1
0.8
0.95 4.5
Normalized Tsu
Normalized Tpd
RISE FALL
1.05
0.9
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc 1.1
1.1
300
125
Specifications GAL22V10 GAL22V10D-7/10L (PDIP): Typical AC and DC Characteristic Diagrams Vol vs Iol
Voh vs Ioh
0.5
Voh vs Ioh
4
3.8 3.7
0.4
3.6
3
0.2
Voh (V)
Voh (V)
Vol (V)
3.5 0.3
2
3.4 3.3 3.2 3.1
1 0.1
3 2.9 0
0 0
5
10
15
20
25
0
30
5
10
15
30
35
1.1
1.2
Normalized Icc
1.3
1.05 1 0.95 0.9 0.85 5
5.25
1 0.9
9
10
8
20
7
30
6
40
Iik (mA)
0
5 4
25
100
60 70
2
80
1
90
0 0
0.5
1
1.5
2
2.5
3
Vin (V)
3.5
4
4.5
5
100 -2.5
1.05
-2
-1.5
-1
Vik (V)
18
-0.5
1
15
25
50
Frequency (MHz)
50
3
1.1
0.95 0
Input Clamp (Vik)
Delta Isb vs Vin (1 input)
5.00
1
Temperature (deg. C)
10
4.00
Normalized Icc vs Freq
1.1
Supply Voltage (V)
3.00
1.15
0.7 -55
5.5
2.00
1.2
0.8
4.75
1.00
Ioh (mA)
Normalized Icc vs Temp
1.15
4.5
2.8 0.00
40
Normalized Icc
Normalized Icc vs Vcc
Normalized Icc
25
Ioh (mA)
Iol (mA)
Delta Icc (mA)
20
0
75
100
Specifications GAL22V10 GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc
1
0.95
0.9 4.5
4.75
5
5.25
RISE FALL
1.1
1.05
1
0.95
0.9 4.5
5.5
4.75
Supply Voltage (V)
5
5.25
1
0.9
0.8 4.5
5.5
4.75
1 0.9
5.5
1.45 1.35
RISE FALL
1.2
Normalized Tsu
Normalized Tco
1.1
5.25
Normalized Tsu vs Temp
1.3
RISE FALL
5
Supply Voltage (V)
Normalized Tco vs Temp
Normalized Tpd vs Temp
1.2
RISE FALL
1.1
Supply Voltage (V)
1.3
1.1
1
0.9
RISE FALL
1.25 1.15 1.05 0.95 0.85
25
50
75
100
125
0.8 -55
Temperature (deg. C)
0
25
50
75
100
0.75 -55
1 25
-25
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0
Delta Tpd (ns)
-25
-0.4
RISE FALL -0.8
-1.2 1
2
3
4
5
6
7
8
9
0
-0.4
RISE FALL -0.8
-1.2
10
1
2
Number of Outputs Switching
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading 20
20 16
16
RISE FALL
12 8 4 0
RISE FALL
12 8 4 0
-4
-4
-8 0
50
100
150
200
250
0
3 00
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
19
25
50
75
Temperature (deg. C)
Delta Tco vs # of Outputs Switching
0
Delta Tco (ns)
0
Delta Tco (ns)
-25
Delta Tpd (ns)
Normalized Tpd
Normalized Tsu
RISE FALL
Normalized Tco
Normalized Tpd
1.2
1.15
1.05
0.8 -55
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
1.1
3 00
100
1 25
Specifications GAL22V10 GAL22V10D-10Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Vol vs Iol
Voh vs Ioh
Voh vs Ioh
4.5
0.6
4.5
4 3.5
4
Voh (V)
Vol (V) 0.2
Voh (V)
3
0.4
2.5 2 1.5
3.5
3
1 0.5 0
0 0
5
10
15
20
25
30
35
0
40
20
40
2.5 0.00
60
Normalized Icc vs Vcc
Normalized Icc
Normalized Icc
Normalized Icc
0.9
1.15 1.05 0.95 0.85
4.75
5
5.25
5.5
0.75 -55
Supply Voltage (V)
0
25
50
88
100
1 25
0 10
6
30
Iik (mA)
Delta Icc (mA)
20 5 4 3
40 50 60
2 70 1
80
0 0
0.5
1
1.5
2
2.5
3
Vin (V)
3.5
4
4.5
5
90 -2.5
1.3 1.2 1.1 1
-2
-1.5
-1
Vik (V)
20
-0.5
1
15
25
50
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
5.00
0.9 -25
Temperature (deg. C)
7
4.00
1.4
1.25
1
3.00
Normalized Icc vs Freq
1.35
1.1
2.00
Ioh (mA)
Normalized Icc vs Temp
1.2
0.8 4.5
1.00
Ioh (mA)
Iol (mA)
0
75
1 00
Specifications GAL22V10 Notes Revision History Date
Version
Change Summary
-
22v10_08
Previous Lattice release.
August 2004
22v10_09
Added lead-free package options.
July 2006
22v10_10
Corrected SOIC pin configuration diagram. Pin 13.
August 2006
22v10_11
Updated for lead-free package options.
December 2006
22v10_12
Corrected Icc in the Ordering Part Number section on pages 2-3.
21
