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GS1560 Dual Rate Serial Digital Re-clocking De-serializer PRODUCT BRIEF DESCRIPTION
GS1560 Dual Rate Serial Digital Re-clocking De-serializer
GS1560 Dual Rate Serial Digital Re-clocking De-serializer
• Compliant With SMPTE 292M and SMPTE 259M-C
The GS1560 is a dual-rate re-clocking de-serializer, compliant with SMPTE 292M and SMPTE 259M-C.
• Operation at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s • Dual serial digital input buffers with 2 x 1 mux • Integrated serial digital signal termination • Built in re-clocker • Re-clocked serial digital output buffer / cable driver • Automatic or manual rate selection / indication (HD / SD) • SMPTE 292M and SMPTE 259M Compliant Descrambling and NRZI - > NRZ decoding (with bypass) • De-scrambler Bypass Option • CRC error detection and TRS error detection • ANC data indication • Line number error detection • Internal Flywheel for Noise Immune H, V, F Extraction • FIFO load Pulse • 20-Bit / 10-Bit CMOS parallel output data bus • Differential (BGA package only) and TTL compatible PCLK output • 148.5MHz / 74.25MHz / 27MHz / 13.5MHz parallel digital output • DVB ASI sync word detection and auto configuration • EDH error detection and indication • Automatic standards detection and indication • User selectable additional processing features including: - CRC, TRS, ANC data checksum, line number and EDH CRC error correction and insertion - Programmable ANC data detection - Illegal code re-mapping • 1.8V core Power Supply and 3.3V charge pump power supply • 3.3V digital I/O supply • JTAG test interface • Small footprint compatible with GS1532 • Low power operation (< 450mW) APPLICATIONS • SMPTE 292M Serial Digital Interfaces •
SMPTE 259M-C Serial Digital Interfaces
•
DVB-ASI Serial Digital Interfaces
AVAILABLE PACKAGING 80 pin TQFP / 100 pin FBGA
When used in conjunction with a GS1504 / GS1524 / GS9004 automatic cable equalizer, a dual rate (1.485 / 1.483Gb/s and 270Mb/s), receive solution can be realized. In addition to providing robust serial to parallel conversion with word alignment, the GS1560 includes a range of additional data processing functions such as error detection and correction, automatic standards detection, DVB-ASI and EDH support. The GS1560 performs the functions of re-clocking and serial-to-parallel conversion. Following this, the device performs NRZI to NRZ decoding, de-scrambling as per SMPTE 292M / 259M and word-aligns to the incoming data stream. The SMPTE de-scrambler and word alignment features can optionally be bypassed to support the reception of signals with other coding schemes. Two serial digital input buffers are provided with a 2x1 multiplexor. This allows the device to select from one of two serial digital input signals. The integrated re-clocker features a very wide Input Jitter Tolerance (IJT) of ±0.3 UI, a rapid (typically less than two video lines) asynchronous lock time, and full compliance with DVB-ASI data streams. A SMPTE 259M-C and SMPTE 292M compliant cable driver output is also provided for serial input loop through applications. The serial digital output can be selected as either pre or post the integrated re-clocker. The cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing and automatic dual slew-rate selection depending on HD / SD operational requirements. The GS1560 also features a number of signal integrity checks and measurement capabilities. Line-based CRC errors, Line number errors, TRS errors, EDH CRC errors and ancillary data check sum errors can all be detected. A single 'error' pin is provided which is a logical 'or'ing of all the detected errors. Individual error status can be read from the host interface port. In addition to detecting signal errors, the device also includes the ability to correct all of the above detected errors. Each error correction function may be individually enabled / disabled via host interface control.
Revision Date: September 2001 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail:
[email protected] www.gennum.com
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GS1560
FEATURES
The device will detect the presence of DVB ASI sync words and will automatically switch into bypass mode. The DVB ASI data will be word aligned to K28.5 sync characters and 8b/10b decoding is applied to the received data stream.
Other processing functions include H:V:F timing extraction, Y and C ancillary data indication and video standard indication. The device may also be used in data pass through mode where no processing of the data is performed. Parallel data outputs are provided in both 10 bit multiplexed and 20 bit de-multiplexed format for HD and SD signal rates. An associated parallel clock output signal is provided operating at 148.5 or 148.5 / 1.001 MHz (HDTV 10 bit multiplexed output), 74.25 / 74.25 / 1.001 MHz (HDTV 20 bit de-multiplexed output), 27 MHz (SD 10 bit multiplexed and DVB-ASI output) and 13.5 MHz (SD 20 bit de-multiplexed output).
Line number generation is also performed by the device, and for HDTV interfaces, the line number may be inserted into the output data stream. As well as detecting and extracting SMPTE 352M payload identifier packets, the GS1560 can also automatically identify the received video standard and the payload data type. The detected video standard and data format may be read via the host interface port.
The parallel clock output, is provided in TTL compatible and differential forms (BGA package only) and TTL compatible forms. Additional capabilities such as DVB-ASI decoding, SMPTE 352M payload identifier packet decoding and EDH processing are also provided by the device.
20bit/10bit
IOPROC_EN/DIS
FW_EN/DIS
DVB-ASI
SMPTE_BYPASS
MASTER_SLAVE
HD/SD
LOCKED
PCK_DIFF
PCK_DIFF
PCLK
CP_CAP
VCO VCO LB_CONT LB VCO_VCC VCO_GND
CP_GND
CP_VCC
PD_GND
PD_VCC
IP_SEL
carrier detect
CD1
H V F
LOCK DETECT
CD2
pll lock IO_VCC(x3)
S->P
ASI sync detect
SDI_1 RE-CLOCKER BUFF_VCC
SDI_2 SDI_2
Smpte sync detect
SDI_1
SMPTE Descramble, Word alignment and flywheel
DOUT[19:0] FIFO_LD CRC check Line mumber check TRS check CSUM check ANC data detection
K28.5 sync detect, DVB-ASI word alignment and 8b/10b decode
(output mute)
CRC correct Line number correct TRS correct CSUM correct EDH check & correct Illegal code remap
DATA_ERROR
I/O Buffer & mux
LOCKED SDO_EN/DIS
C_ANC Y_ANC
SDO SDO RSET
POR POWER ON RESET
HOST INTERFACE / JTAG TEST IO_GND(x3)
JTAG_EN/DIS
CS_TMS SCLK_Tck
SDIN_TDI
SDOUT_TDO
RESET
RC_BYP
CORE_VCC
CORE_GND
CD_VCC
CD_GND
GS1560 Dual Rate Serial Digital Re-clocking De-serializer with DVB-ASI and EDH support.
GS1560 FUNCTIONAL BLOCK DIAGRAM CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale.
REVISION NOTES: New Document.
GENNUM CORPORATION
GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. © Copyright September 2001 Gennum Corporation. All rights reserved. Printed in Canada.
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EDH FF and AP CRC calculation and comparison is performed. Error flags are generated based on these CRC comparisons. Re-calculated CRC's may be inserted into the output data stream.
