Transcript
To our customers,
Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com
April 1st, 2010 Renesas Electronics Corporation
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HD74LV373A Octal D-type Transparent Latches with 3-state Outputs REJ03D0331–0200Z (Previous ADE-205-274 (Z)) Rev.2.00 Jun. 25, 2004
Description The HD74LV373A has eight D type latches with three state outputs in a 20 pin package. When the latch enables input is high, the Q outputs will follow the D inputs. When the latch enables goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features • • • • • • •
VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Part Name
Package Type
Package Code
Package Abbreviation
Taping Abbreviation (Quantity)
HD74LV373AFPEL HD74LV373ARPEL HD74LV373ATELL
SOP–20 pin (JEITA) SOP–20 pin (JEDEC) TSSOP–20 pin
FP–20DAV FP–20DBV TTP–20DAV
FP RP T
EL (2,000 pcs/reel) EL (1,000 pcs/reel) ELL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Function Table Inputs OE
LE
D
Output Q
H L L L
X H H L
X L H X
Z L H Q0
Note: H: High level L: Low level X: Immaterial Z: High impedance Q0: Output level before the indicated steady state input conditions were established.
Rev.2.00 Jun. 25, 2004 page 1 of 10
HD74LV373A
Pin Arrangement
OE 1
20 VCC
1Q 2
19 8Q
1D 3
18 8D
2D 4
17 7D
2Q 5
16 7Q
3Q 6
15 6Q
3D 7
14 6D
4D 8
13 5D
4Q 9
12 5Q
GND 10
11 LE
(Top view)
Absolute Maximum Ratings Item
Symbol
Ratings
Unit
Supply voltage range Input voltage range*1 Output voltage range*1, 2
VCC VI VO
V V V
Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)*3
IIK IOK IO
–0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±35 ±70
Storage temperature
Tstg
ICC or IGND PT
835 757 –65 to 150
mA mA mA mA mW
Conditions
Output: H or L VCC: OFF or Output: Z VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
SOP TSSOP
°C
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00 Jun. 25, 2004 page 2 of 10
HD74LV373A
Recommended Operating Conditions Item
Symbol
Min
Max
Unit
Supply voltage range
VCC
Input voltage range Output voltage range
VI VO IOH
5.5 5.5 VCC 5.5 –50 –2 –8 –16 50 2 8 16 200 100 20
V V V
Output current
2.0 0 0 0 — — — — — — — — 0 0 0 –40
85
°C
IOL
Input transition rise or fall rate
∆t /∆v
Operating free-air temperature
Ta
Conditions
H or L High impedance state VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V
µA mA
µA mA
ns/V
Note: Unused or floating inputs must be held high or low.
Logic Diagram OE LE
1
11
C1 1D
3
1D
To Seven Other Channels
Rev.2.00 Jun. 25, 2004 page 3 of 10
2
1Q
HD74LV373A
DC Electrical Characteristics Ta = –40 to 85°C Item
Symbol
VCC (V)*
Min
Typ
Max
Unit
Input voltage
VIH
1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — —
— — — — — — — — — — — — — — — — — —
— — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 ±5
V
Input current Off-state output current
IIN IOZ
2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5
Quiescent supply current
ICC
5.5
—
—
Output leakage current
IOFF
0
—
Input capacitance
CIN
3.3
—
VIL
Output voltage
VOH
VOL
Test Conditions
µA µA
IOH = –50 µA IOH = –2 mA IOH = –8 mA IOH = –16 mA IOL = 50 µA IOL = 2 mA IOL = 8 mA IOL = 16 mA VIN = 5.5 V or GND VO = VCC or GND
20
µA
VIN = VCC or GND, IO = 0
—
5
µA
VI or VO = 0 to 5.5 V
2.9
—
pF
VI = VCC or GND
V
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.2.00 Jun. 25, 2004 page 4 of 10
HD74LV373A
Switching Characteristics VCC = 2.5 ± 0.2 V Item
Symbol
Ta = 25°C Min
Typ
Max
Min
Max
Unit
Test Conditions
FROM (Input)
TO (Output)
Propagation delay time
tPLH tPHL
— — — — — — — — 4.5 1.5 6.0
8.3 9.1 10.4 11.1 8.9 10.9 6.2 8.3 — — —
15.2 15.7 18.0 18.6 15.8 18.8 12.6 17.4 — — —
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 5.0 1.5 6.5
17.0 19.0 21.0 22.0 19.0 22.0 15.0 19.0 — — —
ns
CL = 15 pF
D LE
Q
CL = 50 pF
D LE OE
Q
OE
Q
Enable time
tZH tZL
Disable time
tHZ tLZ
Setup time Hold time Pulse width
tSU th tw
Ta = –40 to 85°C
ns ns
CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
Data before LE ↓ Data after LE ↓ LE "H"
ns ns ns
VCC = 3.3 ± 0.3 V Item
Symbol
Ta = 25°C Min
Typ
Max
Min
Max
Unit
Test Conditions
FROM (Input)
TO (Output)
Propagation delay time
tPLH tPHL
— — — — — — — — 4.0 1.0 5.0
5.8 6.4 7.3 7.8 6.3 7.7 4.7 6.0 — — —
11.4 11.0 14.9 14.5 11.4 14.9 10.0 13.2 — — —
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 1.0 5.0
13.5 13.0 17.0 16.5 13.5 17.0 12.0 15.0 — — —
ns
CL = 15 pF
D LE
Q
CL = 50 pF
D LE OE
Q
OE
Q
Enable time
tZH tZL
Disable time
tHZ tLZ
Setup time Hold time Pulse width
tSU th tw
Ta = –40 to 85°C
ns ns
CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
Data before LE ↓ Data after LE ↓ LE "H"
ns ns ns
VCC = 5.0 ± 0.5 V Item
Symbol
Ta = 25°C Min
Typ
Max
Min
Max
Unit
Test Conditions
FROM (Input)
TO (Output)
Propagation delay time
tPLH tPHL
— — — — — — — — 4.0 1.0 5.0
4.1 4.5 5.1 5.5 4.5 5.5 3.3 4.0 — — —
7.2 7.2 9.2 9.2 8.1 10.1 7.2 9.2 — — —
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 4.0 1.0 5.0
8.5 8.5 10.5 10.5 9.5 11.5 8.5 10.5 — — —
ns
CL = 15 pF
D LE
Q
CL = 50 pF
D LE OE
Q
OE
Q
Enable time
tZH tZL
Disable time
tHZ tLZ
Setup time Hold time Pulse width
tSU th tw
Rev.2.00 Jun. 25, 2004 page 5 of 10
Ta = –40 to 85°C
ns ns ns ns ns
CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF
Data before LE ↓ Data after LE ↓ LE "H"
HD74LV373A
Output-skew Characteristics CL = 50 pF Ta = 25°C
Ta = –40 to 85°C
Item
Symbol
VCC = (V)
Min
Max
Min
Max
Unit
Output skew
tsk (O)
2.3 to 2.7 3.0 to 3.6 4.5 to 5.5
— — —
2.0 1.5 1.0
— — —
2.0 1.5 1.0
ns
Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
Operating Characteristics CL = 50 pF Ta = 25°C Item
Symbol
VCC = (V)
Min
Typ
Max
Unit
Test Conditions
Power dissipation capacitance
CPD
3.3
—
16.6
—
pF
f = 10 MHz
5.0
—
18.2
—
Noise Characteristics CL = 50 pF Ta = 25°C Item
Symbol
VCC = (V)
Min
Typ
Max
Unit
Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL
VOL (P)
3.3
—
0.6
0.8
V
VOL (V)
3.3
—
–0.6
–0.8
V
Quiet output, minimum dynamic VOH
VOH (V)
3.3
—
2.9
—
V
High-level dynamic input voltage
VIH (D)
3.3
2.31
—
—
V
Low-level dynamic input voltage
VIL (D)
3.3
—
—
0.99
V
Test Circuit Output 1 kΩ
S2
OPEN GND
CL
VCC TEST t PLH /t PHL
S2 OPEN
t ZH/t HZ t ZL /t LZ
GND VCC
Note: C L includes the probe and jig capacitance.
Rev.2.00 Jun. 25, 2004 page 6 of 10
Test Conditions
HD74LV373A • Waveform − 1 tf
tr
VCC
90% 90% 50%VCC
Input LE
Vref
10% tr
10% tf
VCC
90%
90%
Input D
GND
10%
10%
t PHL
t PLH
GND VOH
Output Q
50%VCC
50%VCC VOL
• Waveform − 2 tr VCC
90%
Input LE
10%
Input D
90% 50%VCC
10%
GND
tf
tr
VCC
90% 50%VCC
10% t PHL
t PLH
GND VOH
Vref
Output Q
Vref VOL
• Waveform − 3 tf
tr Input LE 10%
90% 90% 50% 50% VCC V tw CC tsu
VCC 10%
GND
th VCC
Input D
50%VCC
50%VCC GND
Rev.2.00 Jun. 25, 2004 page 7 of 10
HD74LV373A • Waveform − 4 tf Input OE
tr
90% 50%VCC 10% t ZL
VCC
90% 50%VCC 10% t LZ
GND VCC
Waveform − A
50%VCC t ZH
Waveform − B
50%VCC
VOL + 0.3 V t HZ VOH − 0.3 V
VOL VOH OV
Notes: 1. tr ≤ 3 ns, tf ≤ 3 ns 2. Input waveform: PRR ≤ 1 MHZ, duty cycle 50% 3. Waveform−A is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Waveform−B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.2.00 Jun. 25, 2004 page 8 of 10
HD74LV373A
Package Dimensions As of January, 2002 Unit: mm
12.6 13 Max 11
1
10
1.27 *0.40 ± 0.06
0.20 7.80 +– 0.30
1.15
0˚ – 8˚
0.10 ± 0.10
0.80 Max
*0.20 ± 0.05
2.20 Max
5.5
20
0.70 ± 0.20
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value)
*Pd plating
FP–20DAV — Conforms 0.31 g
As of January, 2003 Unit: mm
12.8 13.2 Max 11
1
10
1.27 *0.40 ± 0.06
0.20 ± 0.10
0.935 Max
*0.25 ± 0.05
2.65 Max
7.50
20
0.25 10.40 +– 0.40
1.45
0˚ – 8˚ 0.57 0.70 +– 0.30
0.15 0.12 M *Ni/Pd/Au plating
Rev.2.00 Jun. 25, 2004 page 9 of 10
Package Code JEDEC JEITA Mass (reference value)
FP-20DBV Conforms — 0.52 g
HD74LV373A
As of January, 2002 Unit: mm 6.50 6.80 Max 11
1
10
4.40
20
0.65 *0.20 ± 0.05
1.0
0.13 M 6.40 ± 0.20
*Pd plating
Rev.2.00 Jun. 25, 2004 page 10 of 10
0.07 +0.03 –0.04
0.10
*0.15 ± 0.05
1.10 Max
0.65 Max 0˚ – 8˚
0.50 ± 0.10
Package Code JEDEC JEITA Mass (reference value)
TTP–20DAV — — 0.07 g
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