Hi3050 - Ihs.com

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HI3050 TM Triple 10-Bit, 50 MSPS, High Speed, 3-Channel D/A Converter August 1997 Features Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit The HI3050 is a triple, 10-bit D/A converter, fabricated in a silicon gate CMOS process, ideally suited for RGB video applications. • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 50MHz • 3-Channel, RGB, I/O The converter incorporates three 10-bit input data registers with a common blanking capability, forcing all outputs to 0mA. The HI3050 features low glitch, high impedance current outputs and single 5V supply operation. Low current inputs accept standard TTL/CMOS levels. The architecture is a current cell arrangement providing low differential and integral linearity errors. • RS-343A/RS-170 Compatible Outputs • Low Power Consumption (Typ) . . . . . . . . . . . . . 500mW • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Low Glitch Energy The HI3050 requires a 2V external reference and a set resistor to control the output current. The HI3050 also features a chip enable/disable pin for reducing power consumption (<5mW) when the part is not in use. • CMOS Compatible Inputs • Direct Replacement for Sony CXD2308 Applications The HI3050 can generate RS-343A and RS-170 compatible video signals into doubly terminated and singly terminated 75Ω loads. • NTSC, PAL, SECAM Displays • High Definition Television (HDTV) Ordering Information • Presentation and Broadcast Video • Image Processing PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. • Graphics Displays HI3050JCQ -20 to 75 64 Ld MQFP Q64.14x20-S Pinout DVDD AVDD AVDD BOUT BOUT AVDD AVDD GOUT GOUT AVDD AVDD ROUT ROUT HI3050 (MQFP) TOP VIEW 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 50 2 49 3 48 4 47 5 46 6 45 7 44 8 43 9 42 10 41 11 40 12 39 13 14 38 15 37 36 16 35 17 34 18 19 33 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND COMP B VREF OUT B COMP G VREF OUT G COMP R VREF OUT R VREFB VREFG VREFR FS ADJUST B FS ADJUST G FS ADJUST R AGND VBIAS DGND BCLK GCLK RCLK G9 (MSB) B0 (LSB) B1 B2 B3 B4 B5 B6 B7 B8 B9 (MSB) BLANK CE R0 (LSB) R1 R2 R3 R4 R5 R6 R7 R8 R9 (MSB) G0 (LSB) G1 G2 G3 G4 G5 G6 G7 G8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 FN3936.2 HI3050 Functional Block Diagram R0 (LSB) 1 R1 2 R2 3 R3 4 R4 5 4 LSBs CURRENT CELLS 6 MSBs CURRENT CELLS 64 DVDD 62 AVDD 63 AVDD 46 COMP R 52 ROUT 53 ROUT 33 RCLK 45 VREF OUT R 42 VREFR 39 FS ADJUST R 58 AVDD 59 AVDD 48 COMP G 56 GOUT 57 GOUT 34 GCLK 47 VREF OUT G 43 VREFG 40 FS ADJUST G 54 AVDD 55 AVDD 50 COMP B 60 BOUT 61 BOUT 35 BCLK 49 VREF OUT B 44 VREFB 41 FS ADJUST B 37 VBIAS 38 AGND 51 AGND 36 DGND LATCHES R5 6 R6 7 R7 8 R8 9 R9 10 G0 (LSB) 11 G1 12 G2 13 G3 14 G4 15 DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) + 4 LSBs CURRENT CELLS 6 MSBs CURRENT CELLS LATCHES G5 16 G6 17 G7 18 G8 19 G9 20 B0 (LSB) 21 B1 22 B2 23 B3 24 B4 25 DECODER CLOCK GENERATOR DECODER CURRENT CELLS (FOR FULL SCALE) + 4 LSBs CURRENT CELLS 6 MSBs CURRENT CELLS LATCHES B5 26 B6 27 B7 28 B8 29 DECODER CLOCK GENERATOR DECODER B9 30 CURRENT CELLS (FOR FULL SCALE) BLANK 31 BIAS VOLTAGE GENERATOR CE 32 2 + HI3050 Pin Descriptions and Equivalent Circuits PIN NO. SYMBOL 1 - 10 R0 - R9 11 - 20 G0 - G9 21 - 30 B0 - B9 EQUIVALENT CIRCUIT DESCRIPTION Digital Inputs. DVDD 1 TO 30 DGND 31 BLANK Output Blanking Input. High: Outputs Set to 0mA. Low: Normal Output Operation. DVDD 31 DGND 37 VBIAS DVDD DVDD Internal Bias Decoupling. Connect a 0.1µF decoupling capacitor to DGND. + 37 - DGND 33 RCLK 34 GCLK 35 BCLK Clock Inputs. All input pins are TTL/CMOS compatible. DVDD 33 34 35 DGND 36 DGND Digital Ground. 38, 51 AGND Analog Ground. 32 CE Chip Enable pin. High: Part Disabled Low: Part Enabled DVDD 32 DGND 54, 55, 58, 59, 62, 63 AVDD Analog Power Supply. 3 HI3050 Pin Descriptions and Equivalent Circuits (Continued) PIN NO. SYMBOL EQUIVALENT CIRCUIT 45 V REF OUT R 47 VREF OUT G 49 V REF OUT B 47 46 COMP R 49 48 COMP G AGND 50 COMP B AVDD 39 FS ADJUST R DESCRIPTION Reference Output. Typically connected to the Reference Decoupling inputs (COMP R, COMP G, COMP B). See Figures 11 and 12 for various configurations. AVDD 45 Reference Decoupling. Connect a decoupling capacitor (0.1µF) to reduce noise on reference to AVDD . Full Scale Adjust. Typically connect a 1.2kΩ resistor, RSET , to AGND. RSET is used to determine full scale output current. 46 40 FS ADJUST G 41 FS ADJUST B 42 VREFR AGND 43 VREFG AVDD 44 VREFB 48 50 Voltage Reference Input. Typically set to 2V and determines full scale output current. 39 V REF I OUT ( Full Scale ) = --------------- × 16 R SET 40 41 AGND + - AVDD 42 43 44 AGND 52 ROUT 56 GOUT 60 BOUT 53 ROUT Current Outputs. AVDD 52 56 Inverted Current Outputs. 60 57 GOUT 61 BOUT AGND AVDD 53 57 61 AGND 64 DVDD Digital Power Supply. 4 HI3050 Absolute Maximum Ratings TA = 25oC Thermal Information Digital Supply Voltage, DV DD to DGND . . . . . . . . . . . . . . . . . . +7V Analog Supply Voltage, AVDD to AGND . . . . . . . . . . . . . . . . . . +7V Digital Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . DVDD to DGND Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Operating Conditions Supply Voltage, AVDD , AVSS . . . . . . . . . . . . . . . . . .4.75V to 5.25V DV DD , DVSS . . . . . . . . . . . . . . . . . . .4.75V to 5.25V Clock Pulse Width (tPW1 , tPW0) . . . . . . . . . . . . . . . . . . . . 10ns (Min) Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . .-20oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications AVDD = +5V, DVDD = +5V, fCLK = 50MHz, RL = 75Ω, VREF = 2V, RSET = 1.2kΩ , TA = 25oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - 10 - Bits 50 - - MSPS SYSTEM PERFORMANCE Resolution Maximum Conversion Speed Integral Linearity Error, INL “Best Fit” Straight Line Differential Linearity Error, DNL Output Offset Voltage, VOS - 2.0 LSB - 0.5 LSB - - 1 mV 0 1.5 3 % Full Scale Output Current, IFS - 27 30 mA Full Scale Output Voltage, VFS 1.8 1.9 2.0 V - 2.5 - V - 50 - pV/s Output Full Scale Ratio Error, FSRE (Note 2) -2.0 -0.5 Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Glitch Energy, GE Settling Time IOUT = 13.5mA - 40 - ns Crosstalk 10MHz Output Sine Wave - 50 - dB Input Logic High Voltage, VIH 2.0 - - V Input Logic Low Voltage, V IL - - 0.8 V DIGITAL INPUTS Input Logic Current, IIH - - 5 µA Input Logic Current, IIL -5 - - µA Digital Input Capacitance, CIN - 10 - pF 5 7 ns TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 1 - Data Hold Time, tHLD See Figure 1 - 1 3 ns Propagation Delay Time, tPD See Figure 1 - 10 - ns Clock Pulse Width, tPW1, tPW0 See Figure 1 10 - - ns POWER SUPPLY CHARACTERISITICS Total Supply Current, AIDD + DIDD - 100 110 mA Analog Supply Current, AIDD - 92 - mA Digital Supply Current, DIDD - 8 - mA Power Dissipation - 500 550 mW NOTE: 2. Configured for Common Reference. Full Scale Voltage of Channel F SRE = ------------------------------------------------------------------------------------------------------------------ – 1 × 100% Average Full Scale Voltage of All Channels 5 HI3050 Timing Diagram tPW1 tPW0 50% CLK tSU tSU tSU tHLD tHLD tHLD R9-R0 G9-G0 B9-B0 100% tPD ROUT GOUT BOUT 50% 0% tPD tPD FIGURE 1. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM Typical Performance Curves 80 SUPPLY CURRENT (mA) CROSSTALK (dB) 110 70 60 50 VDD = 5.0V, TA = 25oC VDD = 5.0V, fCLK = 50MHz VREF = 2.0V 100 40 100K 1M 10M -20 0 25 50 75 AMBIENT TEMPERATURE (oC) OUTPUT FREQUENCY (Hz) FIGURE 3. SUPPLY CURRENT vs AMBIENT TEMPERATURE FIGURE 2. CROSSTALK vs OUTPUT FREQUENCY 6 HI3050 Typical Performance Curves 65 1.9 60 SFDR (dB) FULL-SCALE VOLTAGE (V) 70 VDD = 5.0V, VREF = 2.0V 55 50 45 40 1.8 35 -20 0 25 50 30 0.1 70 AMBIENT TEMPERATURE (oC) 1.0 OUTPUT FREQUENCY (MHz) FIGURE 4. FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 5. SFDR vs OUTPUT FREQUENCY 7 10.0 HI3050 DAC INPUT/OUTPUT CODE TABLE (NOTE 1) INPUT CODE MSB D9 D8 D7 D6 D5 1 1 1 1 1 D4 D3 D2 D1 LSB D0 OUTPUT VOLTAGE 1 1 1 1 1 2.0V 0 0 0 0 0 1.0V 0 0 0 0 0 0V • • • 1 0 0 0 0 • • • 0 0 0 0 0 NOTE: 1. VREF = 2.0V, R SET = 1.2K, RLOAD = 75Ω . Detailed Description Rise and fall times and propagation delay of the line will be affected by the Shunt Terminator. The terminator can be connected to DGND. The HI3050 contains three matched, individual, 10 bit current output digital-to-analog converters. The DACs can convert at 50MHz and run on +5V for both the analog and digital supplies. The architecture is a current cell arrangement. 10-bit linearity is obtained without laser trimming due to an internal calibration. Power Supplies To reduce power supply noise, separate analog and digital power supplies should be used with 0.1µF and 0.01µF ceramic capacitors placed as close to the body of the HI3050 as possible on the analog (AVDD) and digital (DVDD) supplies. The analog and digital ground returns should be connected together at the device to ensure proper operation on power up. Digital Inputs The digital inputs to the HI3050 have TTL level thresholds. Due to the low input currents CMOS logic can be used as well. The digital inputs are latched on the rising edge of the clock. Reference To reduce switching noise from the digital data inputs, a series termination resistor is the best solution. Using a 50Ω to 130Ω resistor in series with the data lines, the edge rates are slowed. Slower edge rates reduce the amount of overshoot and undershoot that directly couples through the lead frame of the device. TTL drivers such as the 74ALS or 74F series or CMOS logic series drivers, ACT, AC, or FCT, are excellent for driving the TTL/CMOS inputs of the converter. The HI3050 DACs have their own references and can be set individually, see Figure 13. The three references can also share a common reference voltage, see Figure 12. A shared reference gives DAC to DAC matching of 1.5%, typically. The HI3050 requires an external reference voltage to set the full scale output current. The external reference voltage is connected to the VREF inputs (VREFR , VREFG , and VREFB). The Full Scale Adjust input (FS ADJUST R, FS ADJUST G, FS ADJUST B) should be connected to AGND through a 1.2kΩ resistor, RSET . The reference outputs (VREF OUT R, VREF OUT G, V REF OUT B) should be connected to the decoupling input (COMP R, COMP G, COMP B) and decoupled to AVDD with a 0.1µF capacitor. This improves settling time by decoupling switching noise from the reference output of the HI3050. Clocks and Termination The HI3050 clock rate can run to 50MHz, therefore, to minimize reflections and clock noise into the part, proper termination should be considered. In PCB layout clock traces should be kept short and have a minimum of loads. To guarantee consistent results from board to board controlled impedance traces should be used with a characteristic line impedance. To terminate the clock line, a shunt terminator to an AC ground is the most effective type at a 50MHz clock rate. Shunt termination is best used at the receiving end of the transmission line or as close to the HI3050 CLK pin as possible. The full scale output current is controlled by the voltage reference pin and the set resistor (RSET). The ratio is: IOUT (Full Scale) = (VREF/R SET) x 16, IOUT is in mA (EQ.1) Blanking Input The BLANK input, when pulled high, will force the outputs of all three DACs to 0mA. HI3050 DAC ZO = 50Ω CLK Chip Enable RT = 50Ω The chip enable input, CE, will shut down the HI3050 causing the outputs to go to 0mA. The analog and digital supply current will decrease to less than 1mA, reducing power for low power applications. FIGURE 6. AC TERMINATION OF THE HI3050 CLOCK LINE 8 HI3050 to change before another. To minimize this, the Intersil HI3050 employs an internal register, just prior to the current sources, that is updated on the clock edge. Outputs The HI3050 DAC outputs are complementary current outputs. Current is steered to either IOUT or IOUT in proportion to the digital input code. The current output can be converted to a voltage by using a resistor load or I/V converting op amp. If only one output of a converter is being used, the unused output can be connected to ground or to a load equal to the used output. The output voltage when using a resistor load is: VOUT = IOUT x ROUT In measuring the output glitch of the HI3050, the output is terminated into a 75Ω load. The glitch is measured at the major carries throughout the DACs output range. HI3050 50MHz LOW PASS FILTER I OUT (EQ. 2) To convert the output current of the D/A converter to a voltage a load resistor followed by a buffer amplifier can be used as shown in Figure 5. The DAC needs a 75Ω termination resistor on the IOUT pin to ensure proper settling. FIGURE 8. GLITCH TEST CIRCUIT The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 9 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt/seconds (pV/s). HI3050 DAC 75Ω - 50Ω 75Ω The compliance range of the outputs is from 0V to +2.5V. + I OUT SCOPE V 75Ω 75Ω 1/3 HA5013 HEIGHT (H) FIGURE 7. HIGH SPEED CURRENT TO VOLTAGE CONVERSION Glitch The output glitch of the HI3050 is measured by summing the area under the switching transients after an update of the DAC. Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (TTL designs). Unequal delay paths through the device can also cause one current source T (ps) WIDTH (W) GLITCH AREA = 1/2 (H X W) FIGURE 9. GLITCH ENERGY Test Circuits R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 10-BIT COUNTER WITH LATCH R0 52 75Ω R0 53 AGND G0 56 OSCILLOSCOPE 75Ω G0 57 31 BLK B0 60 0.1µF B0 61 46, 48, 50 DGND 33 RCLK 75Ω AVDD 37 VB CLK 50MHz SQUARE WAVE AGND 32 CE 45, 47, 49 34 GCLK 42 - 44 35 BCLK 0.1 µF AGND 2V 39 - 41 1.2kΩ FIGURE 10. MAXIMUM CONVERSION SPEED TEST CIRCUIT 9 HI3050 Test Circuits (Continued) R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 10-BIT COUNTER WITH LATCH R0 52 75Ω R0 53 AGND G0 56 OSCILLOSCOPE 75Ω G0 57 31 BLK B0 60 0.1µF DELAY CONTROLLER B0 61 46, 48, 50 33 RCLK DELAY CONTROLLER 75Ω AVDD 37 VB DGND CLK 50MHz SQUARE WAVE AGND 32 CE 34 GCLK 35 BCLK 0.1 µF 45, 47, 49 AGND 2V 42 - 44 39 - 41 1.2kΩ FIGURE 11. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT ALL “1” R0 - R9 1 - 10 G0 - G9 11 - 20 B0 - B9 21 - 30 DIGITAL WAVEFORM GENERATOR R0 52 75Ω R0 53 AGND G0 56 OSCILLOSCOPE 75Ω G0 57 31 BLK B0 60 0.1µF B0 61 75Ω AVDD 37 VB 46, 48, 50 DGND 33 RCLK CLK 50MHz SQUARE WAVE AGND 32 CE 34 GCLK 35 BCLK 45, 47, 49 42 - 44 0.1 µF 2V 39 - 41 1.2kΩ FIGURE 12. CROSSTALK TEST CIRCUIT 10 AGND HI3050 Applications Circuits 1kΩ CLOCK INPUT 0.1 µF 0.1µF 1.2kΩ NC NC NC NC ROUT 75Ω GOUT 75Ω BOUT 75Ω 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R CHANNEL INPUT B CHANNEL INPUT AVDD DVDD AGND DGND G CHANNEL INPUT FIGURE 13. COMMON VOLTAGE REFERENCE 1kΩ 1kΩ 0.1µF 0.1 0.1 µF µF 1.2kΩ 1.2kΩ 1.2kΩ 1kΩ 0.1 µF CLOCK INPUT ROUT 75Ω GOUT 75Ω BOUT 75Ω 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 53 31 54 30 55 29 56 28 57 27 58 26 59 25 60 24 61 23 62 22 63 21 64 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FIGURE 14. INDEPENDENT REFERENCES 11 B CHANNEL INPUT AVDD DVDD AGND DGND HI3050 Definition of Specifications Differential Phase, DP, is the peak difference in chrominance phase (in degrees) at two different DC levels. Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Signal to Noise Ratio, SNR, is the ratio of a fundamental to the noise floor of the analog output. The first 5 harmonics are ignored, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the harmonics. The first 5 harmonics are included, and an output filter of 1/2 the clock frequency is used to eliminate alias products. Crosstalk, is the undesirable signal coupling from one channel to another. Spurious Free Dynamic Range, SFDR, is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. A sine wave is loaded into the D/A and the output filtered at 1/2 the clock frequency to eliminate noise from clocking alias terms. Feedthrough, is the measure of the undesirable switching noise coupled to the output. Output Voltage Full Scale Settling Time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1/2 LSB error band. Intermodulation Distortion, IMD, is the measure of the sum and difference products produced when a two tone input is driven into the D/A. The distortion products created will arise at sum and difference frequencies of the two tones. IMD is: Output Voltage Small Scale Settling Time, is the time required from the 50% point on the clock input for a 100mV step to settle within an 1/2 LSB error band. This is used by applications reconstructing highly correlated signals such as sine waves with more than 5 points per cycle. 20 Log (RMS of Sum and Difference Distortion Products) IMD = ------------------------------------------------------------------------------------------------------------------------------------------------------( RM S Amplitude of the Fundamental ) Glitch Energy, GE, is the switching transient appearing on the output during a code transition. It is measured as the area under the curve and expressed as a Volt-Time specification. Differential Gain, DG, is the peak difference in chrominance amplitude (in percent) at two different DC levels. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine, CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. 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