Hm90340-cm44-10125-2e-corr-x1

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Corrections of Hardware Manual MB90340 hm90340-cm44-10125-2e-corr-x1-17 © Fujitsu Microelectronics Europe GmbH Addendum, MB90340 Hardware Manual (CM44-10125-2E) This is the Addendum for the Hardware Manual CM42-10125-2E of the MB90340 microcontroller series. It describes all known discrepancies of the MB90340 microcontroller series Hardware Manual. Ref. Number (Internal ref. number) Date Version Chapter/Page No. (Text Link) dd.mm.yy HWM90340001 03.12.02 1.00 HWM90340002 14.02.03 1.00 18 HWM90340003 14.02.03 1.00 18 HWM90340004 HWM90340005 HWM90340006 HWM90340007 HWM90340008 HWM90340009 15.08.03 15.08.03 15.08.03 03.03.03 16.04.04 16.04.04 3.9 21 20 10, 18 20.6 20.7.3 HWM90340010 HWM90340011 HWM90340012 16.04.04 1.01 10.05.04 1.02 10.05.04 1.02 20.8 21 25 HWM90340013 10.05.04 1.02 23.02.07 1.16 9.2.3 1.00 1.00 1.00 1.00 1.01 1.01 hm90340-cm44-10125-2e-corr-x1-17.doc 1 / 29 Description/Correction Transition to standby mode, Standby Cancel failure behavior added Connecting analogue Voltage supply Notes when using analogue and digital function µDMAC Interrupts I²C multi master mode UART, different behaviour ADER7 Register UART Baud Rates, typos corrected Operation with LIN Function Figure corrected Notes on using UART 400 kHz I2C INTERFACE, Note added 0.5M/1M/2M/3M/4M-BIT FLASH MEMORY, Pin state during serial Flash programming added IO Port Function of Pin shared with ext. Bus Function (HACR register) Ref. Number (Internal ref. number) Date Version Chapter/Page No. Description/Correction (Text Link) dd.mm.yy HWM90340014 10.12.04 1.03 20.8 HWM90340015 31.01.05 1.04 3.5.2 HWM90340016 31.01.05 1.04 3.8 HWM90340017 31.01.05 1.04 12.1 HWM90340018 31.01.05 1.04 13.4.2 HWM90340019 31.01.05 1.04 20.4.3 HWM90340020 31.01.05 1.04 26.1 HWM90340004 31.01.05 1.04 3.9 HWM90340021 HWM90340022 HWM90340023 08.07.05 18.07.05 18.07.05 11.08.05 14.09.06 6.0 25.4 12.1 HWM90340024 11.08.05 1.07 23.02.07 1.16 9.2.4 IO Port Function of Pin shared with ext. Bus Function (ECSR register) HWM90340025 HWM90340026 14.09.05 1.08 24.10.05 1.09 22.6.1 20.4.6 HWM90340001 15.11.05 1.09 8.8 HWM90340027 HWM90340028 HWM90340019 15.11.05 1.09 15.11.05 1.09 02.01.06 1.10 20.4.3 HWM90340020 18.04.06 1.11 26.1 HWM90340029 18.04.06 1.11 20.7.2 HWM90340014 18.04.06 1.11 20.8 HWM90340030 18.07.06 1.12 16.3.3 HWM90340031 HWM90340031 08.08.06 1.13 08.10.06 1.14 20.8 20.8 Typo in Figure 22.6-2 Flag ECCR.TBI can be used in Mode 2, Master Transition to standby mode, description changed F2MC-16LX µDMAC problem F2MC-16LX ADC interrupt problem Serial Status Register (SSR), typos corrected Basic Configuration of Serial Programming Connection, text changed. Operation in Synchronous Mode, Typo corrected, Communication flow changed. Notes on Using UART, clearing reception errors and changing settings added PPG Register PPG0/1, typo in bit constellation in table 16.3-3 Notes on Using UART Notes on Using UART 1.05 1.06 1.06 1.07 1.08 hm90340-cm44-10125-2e-corr-x1-17.doc 2 / 29 Notes on Using UART, typo corrected Occurrence and Release of Hardware Interrupt, typo corrected Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS), typo corrected Outline of Watch-Dog Timer, typo corrected Control Status Register of Output Compare, typo corrected Serial Status Register (SSR), typo corrected Basic Configuration of MB90F342/C(S), F343/C(S), F345/C(S), F346A(S), F346CA(S), F347A(S), F347CA(S), F349/C(S) Serial Programming Connection, typo corrected µDMAC Interrupts, fixed versions added Clock Modulator FMCS Bit 0 Description Typos, Corrections, Corrections Ref. Number (Internal ref. number) Date Version Chapter/Page No. (Text Link) dd.mm.yy HWM90340032 24.10.06 1.15 11.2, 11.3 HWM90340033 13.04.07 1.17 22.6.5 HWM90340034 02.05.07 1.17 15.2, 15.3 hm90340-cm44-10125-2e-corr-x1-17.doc 3 / 29 Description/Correction Notes on time base timer (TBOF bit) Bit Timing Register (BTR), operation conditions Notes on Watch timer (WTOF bit) TOP HWM90340001 Transition to standby mode The definition of Standby Cancel Failure is that the CPU will execute wrong instructions when an interrupt is executed during transition to Standby mode1 at a certain time 1 :Definition of Standby mode Main sleep mode, PLL sleep mode, Sub-sleep mode Time base timer mode, Watch mode, Main watch mode Main stop mode, PLL stop mode, Sub-stop mode In the following cases, no problem occurs: -Standby mode is not used -Standby mode is released only by external reset For further information refer to Hardware Manual ‘Usage Notes on Low-Power Consumption Mode’. HWM90340002 TOP Connecting Analogue Voltage supply (AVcc) Series MB90V340/S MB90F347/C/CS/S Affected date codes 02xx xx 02xx xx Fixed date codes 03xx xx 03xx xx Description: When AVcc < Vcc it could happen that the analogue circuit get damaged. Workaround: Always connect AVcc=Vcc even when not using the AD/C. HWM90340003 TOP Chapter 18 AD Converter Notes on using AD Converter The complete analogue port is supplied with AVcc. Also when using the Port or some pins as digital I/O port. When using AVcc < Vcc take care when using some pins of the analogue ports as I/O pins. The external connection must be at same voltage as AVcc. Otherwise a Latch-up will damage the port. HWM90340004 Chapter 3 Interrupts Chapter 3.9 µDMAC Interrupts hm90340-cm44-10125-2e-corr-x1-17.doc 4 / 29 TOP Affected devices MB90V340/S MB90F347D MB90F342/S/C/CS MB90F349/S/C/CS NOT affected devices MB90V340A-101/-102 MB90F342(C)A(S) MB90F345(C)A(S) MB90F347(C)A(S) MB90F349(C)A(S) Description: µDMAC Function does not work. Do not use µDMAC for affected parts. Workaround: Use not affected versions or EIIOS instead. HWM90340005 TOP Chapter 21 400kHz I²C Interface Affected devices Corrected versions / date code MB90V340/S MB90F347D Description: I²C Interface do not support multi-master mode Workaround: None Note: Following series are not affected (do support multi master mode): - MB90F342C/CS - MB90F349C/CS HWM90340006 TOP Chapter 20 UART Different behaviour of UART Series MB90V340/S MB90F347D MB90F342A(S)/CA(S) MB90F349A(S)/CA(S) UART behaviour A A B B Behaviour ‘A’: - initial value of transmission data register: "00000000" - LBD flag: hm90340-cm44-10125-2e-corr-x1-17.doc 5 / 29 can be used in mode 0 and mode 3 - effect of setting RXE bit: * Receive enabled immediately * start bit memorized during receive disable Behaviour ‘B’: - initial value of transmission data register: "11111111" - SPI interface capability: Serial clock can be delayed by half cycle (programmable) - LBD flag: can only be used in mode 3 (LIN mode) - effect of setting RXE bit: * Receive enabled after SIN = high * start bit cleared by receive disable HWM90340007 TOP Chapter 18 A/D Converter Chapter 10 I/O Ports 10.2.4 Analogue Input Enable Register Use of ADER Register. Affected devices MB90(F)342A/S MB90(F)345A/S MB90(F)347A/S MB90(F)349A/S Description: Although the none-C versions of MB90340 series have 16 analogue channels [AN0-AN15], the ADER7 Register is also implemented. After Power on, this port is initialised as analogue port. Set this port to 0x00 to activate digital I/O function or other resource function. hm90340-cm44-10125-2e-corr-x1-17.doc 6 / 29 HWM90340008 TOP Chapter 20.6 UART Baud Rates Table 20.6-1: Suggested baud rates and reload values at different machine speeds. Notes correction: Old: Note: 2) Maximum Synchronous Baud Rate: MCU-Clock div. by __5___ Correction: Note: 2) Maximum Synchronous Baud Rate: MCU-Clock div. by __6___ Table entry 20MHz, Baud rate: 4MHz Note is missed. Note: Please see AC-Spec for constraints HWM90340009 TOP Chapter 20.7 Operation of UART 20.7.3 Operation with LIN Function (Operation Mode 3) Correction of Figure 20.7-6: NEW: HWM90340010 Chapter 20.8 Notes on using LIN-UART: hm90340-cm44-10125-2e-corr-x1-17.doc 7 / 29 TOP a) Clearing reception errors (CRE) resets the reception state machine. Therefore check any reception errors before the next start-bit or start condition begins, to do not disturb any ongoing reception. b) The start bit detection is level sensitive. Exception: if RXE is "0" (reception disable) and the level at SIN is "0" the LIN-UART waits for the next falling edge "1"->"0" if RXE is set to "1". (This mechanism does not work for MB90V340, MB90F347, and MB90347 Fixed versions: MB90V340A, MB90F347A, MB90347A, MB90(F)342, MB90(F)349(A), MB90(F)038, MB90(F)345, and all MB90(F)35x devices) c) LIN-Break detection is always working in the background and is level sensitive (only in mode 3 at fixed versions named in b) above, in the other versions also in mode 0). Be careful in case of a bus error (bus always dominant). The LIN break detection flag (LBD) will go "1" or stay "1" after each 11 Bit times independent from en- or disabled LIN break detection interrupt. If you use LIN break detection interrupt be sure to check and clear always this flag in your reception interrupt handler. HWM90340011 TOP Chapter 21 400 kHz I2C INTERFACE Restriction of specification at sending General Call Address for MCU with I2C When using Multi-Master mode for I2C and another Master is sending a General Code Address at same time as Fujitsu MCU, an arbitration lost* occurs after 2nd byte. Under following conditions the restriction do not exist: - No usage of I2C peripheral - Usage of I2C with Single Master system - Usage of I2C with Multi Master system, no General Call Address used - Usage of I2C with Multi Master system, General Call Address used by Fujitsu MCU, only - Usage of I2C with Multi Master system, General Call Address used. If the value of data, send by Fujitsu MCU, is smaller than another transfer data, the arbitration lost does not occur. *: If the data value is smaller than another one, oneself never has "Arbitration lost" because one with large transmission data value will have "Arbitration lost". hm90340-cm44-10125-2e-corr-x1-17.doc 8 / 29 HWM90340012 TOP Chapter 25 0.5M/1M/2M/3M/4M-BIT FLASH MEMORY Pin state during serial Flash Programming. Note: In serial programming mode (MD2=MD1=1, MD0=0) UART0 is used for serial communication. The pin state of the SOT0, SIN0 and SCK0 in serial asynchronous mode is as follows: SCK0: output driving high level SOT0: output SIN0: input Effected parts: • MB90(F)34x HWM90340013 TOP CHAPTER 9 MEMORY ACCESS MODES 9.2.3 External Address Output Control Register (HACR) Note: In the case that the ext. bus is used, the pins shared with ext. bus (A16...A23) can only be used as general purpose ports (P20...P27) or as resource inputs (IN0...IN3). Resource output (PPG9(8)...PPGF(E)) *cannot* be used. (KDi, HWe) HWM90340014 TOP Chapter 20.8 Notes on Using UART Typo in following sentence: Software reset of UART Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "1". CORRECTION: Software reset of UART Perform the software reset (SMR: UPCL=1), when the TXE bit of the SCR register is "0". Clearing reception errors Please set SCR:CRE in synchronous slave mode only, if SCR:RXE = 0. Changing settings It is recommended to disable the communication (RXE = 0, TXE = 0), if the UART setting or mode is changed or UART is initialized. (MWi) hm90340-cm44-10125-2e-corr-x1-17.doc 9 / 29 HWM90340015 TOP Chapter 3.5.2 Occurrence and Release of Hardware Interrupt Table 3.5-1 was corrected as indicated by shading below. Wrong: Correct: HWM90340016 TOP Chapter 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) The following sentence of “□ When a stop request is issued from a resource” was added as indicated by shading below. Wrong: (36+6xTable 3.8-3 ”Interrupt handling times”) machine cycles Correct: (36+6xTable 3.8-3 ”Compensation values for interrupt handling times”) machine cycles The following sentence of “□ When the counting is completed” was added as indicated by shading below. Wrong: (Table 3.8-1 “Execution time when the extended EI2OS continues” + Table 3.8-2 “Data transfer compensation values for extended EI2OS execution time” +21+6xTable 3.8-3 ”Interrupt handling times”) machine cycles Correct: (Table 3.8-1 “Execution time when the extended EI2OS continues” + Table 3.8-2 “Data transfer compensation values for extended EI2OS execution time”+21+6xTable 3.8-3 ”Compensation values for interrupt handling times”) machine cycles Table 3.8-3 was corrected as indicated by shading below. hm90340-cm44-10125-2e-corr-x1-17.doc 10 / 29 Wrong: Table 3.8-3 Interrupt handling times Correct: Table 3.8-3 Compensation values for interrupt handling times HWM90340017 TOP Chapter 12.1 Outline of Watch-Dog Timer The following description of " [bits 7 to 3] PONR, WRST, ERST, and SRST" in "□ Watch-dog timer control register (WDTC)" was added as indicated by shading below. [bit 7, bits 5 to 3] PONR, WRST, ERST, and SRST These flags indicate the reset causes. The flags are set upon a reset as described in Table 12.1-1 “Reset cause registers”. All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. HWM90340018 TOP Chapter 13.4.2 Control Status Register of Output Compare Figure 13.4-3 was corrected as indicated by shading below. Wrong: Correct: hm90340-cm44-10125-2e-corr-x1-17.doc 11 / 29 hm90340-cm44-10125-2e-corr-x1-17.doc 12 / 29 Table 13.4-1 was corrected as indicated by shading below. Wrong: Correct: Figure 13.4-4 was corrected as indicated by shading below. Wrong: Correct: hm90340-cm44-10125-2e-corr-x1-17.doc 13 / 29 Table 13.4-2 was corrected as indicated by shading below. Wrong: Correct: Table 13.4-2 was corrected as indicated by shading below. hm90340-cm44-10125-2e-corr-x1-17.doc 14 / 29 Wrong: Correct: HWM90340019 TOP Chapter 20.4.3 Serial Status Register (SSR) Table 20.4-3 was corrected as indicated by shading below Wrong: Correct: bit15 Bit name PE: Parity error flag bit Function • This bit is set to 1 when a parity error occurs during reception at PE=1 and is cleared when 1 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. hm90340-cm44-10125-2e-corr-x1-17.doc 15 / 29 bit14 ORE: Overrun error flag bit bit13 FRE: Framing error flag bit • This bit is set to 1 when an overrun error occurs during reception and is cleared when 1 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. • This bit is set to 1 when a framing error occurs during reception and is cleared when 1 is written to the CRE bit of the serial control register (SCR). • A reception interrupt request is output when this bit and the RIE bit are 1. • Data in the reception data register (RDR) is invalid when this flag is set. HWM90340020 TOP Chapter 26.1 Basic Configuration of MB90F342/C(S), F343/C(S), F345/C(S), F346A(S), F346CA(S), F347A(S), F347CA(S), F349/C(S) Serial Programming Connection Table 26.1-1 was changed as indicated by shading below Old: New: hm90340-cm44-10125-2e-corr-x1-17.doc 16 / 29 HWM90340021 TOP The clock modulator is being evaluated, so it cannot be used. HWM90340022 Chapter 25.4 Flash Memory Control Status Register (FMCS) The following description was changed for bit0 of the FMCS. OLD: [bit0] : Reserved bit NEW: [bit0] : LPM This bit controls the current consumption of flash memory only in the subclock mode. This bit should be set to "1" after the machine clock is switched from the main clock to the subclock, and should be cleared to "0" before the machine clock is switched from the subclock to the main clock. This bit is initialized to "0" by a reset. hm90340-cm44-10125-2e-corr-x1-17.doc 17 / 29 TOP HWM90340023 The table 12.1-2 and the table 12.1—3 were corrected. Wrong: hm90340-cm44-10125-2e-corr-x1-17.doc 18 / 29 TOP Correct: HWM90340024 TOP CHAPTER 9 MEMORY ACCESS MODES 9.2.4 Bus Control Signal Selection Register (ECSR) Note: In the case that the ext. bus is used, the pins shared with ext. bus (WR/WRL, WRH, HRQ, HAK, RDY, CLK) can only be used as general purpose ports (P32...P37) or as resource input (INT10R). Resource output (OUT4...OUT7) *cannot* be used. (HWe, KDi, FJ) hm90340-cm44-10125-2e-corr-x1-17.doc 19 / 29 HWM90340025 TOP The table 22.6-2 were corrected. Wrong: Correct: HWM90340026 TOP In Chapter 20.4.6 “Extended Communication Control Register (ECCR)”, the usage of the TBI and RBI flags is forbidden in LIN-UART Mode 2 when SSM=0. This is wrong. hm90340-cm44-10125-2e-corr-x1-17.doc 20 / 29 Correct is that TBI must not be used in LIN-UART Mode 2 when in LIN-UART Mode 2 when MS=1. TBI can be used in LIN-UART Mode 2 when MS=0. RBI must not be used in LIN-UART Mode 2. HWM90340027 TOP F2MC-16LX µDMAC problem The µDMAC problem is defined as a malfunction that is caused by the garbling of the DMA transfer source or destination address or transfer data. This type of malfunction may be caused when one of the affected devices is used to perform an access to the CAN message buffer RAM concurrently with a data transfer using the µDMAC. Note that this error symptom does not occur if one of the following is met: • The µDMAC is not used. • CAN is not used. • The µDMAC is not used during CAN message buffer RAM access. For further information refer to ‘F2MC-16LX uDMAC Problem’ document (CI-300004-E-V11-16LX_uDMAC_Problem.pdf). HWM90340028 TOP F2MC-16LX ADC interrupt problem Under certain conditions the A/D conversion results may get corrupted. When the consecutive ADC operation is paused by the data protection function*1 at the time that the interrupt is cleared, the data protection function malfunctions under certain conditions. The result is that an unnecessary conversion completion interrupt occurs or the A/D conversion result that should be acquired is omitted once. Note that this problem does not occur in any of the following cases. • The A/D converter is not used. • The A/D converter is used with interrupt disabled. • The A/D converter is used with two or less analogue input channels in single-shot conversion mode. • The A/D converter is started by an external trigger or timer in conversion stop mode and used with two or less analogue input channels. • The A/D converter is started in the following procedure by software in conversion stop mode after the A/D conversion ends: (1) Reading A/D conversion data, (2) Clearing interrupt factors, (3) Starting the next A/D conversion. For further information refer to ‘F2MC-16LX ADC Interrupt Problem’ document (CI-300003-E-V11-16LX_ADC_Interrupt_Problem.pdf). HWM90340029 Chapter 20.7.2 - Operation in Synchronous Mode (Operation Mode 2) hm90340-cm44-10125-2e-corr-x1-17.doc 21 / 29 TOP For initialization of the synchronous slave mode, following settings have to be done. Corrected flow ============== Communication: For initialization of the synchronous slave mode, following settings have to be done: Baud rate generator registers (BGR0/1): Set the desired reload value for the dedicated baud rate reload counter. Serial control register (SCR): RXE, TXE: set both of these flags to "0" A/D: no Address/Data selection - don't care CL: automatically fixed to 8-bit data - don't care CRE: "1" to clear receive error flags. -- when SSM=0 (default): PEN, P, SBL: don't care -- when SSM=1: PEN: "1" if parity bit is added/detected, "0" if not P: "0" for even parity, "1" odd parity SBL: "1" for 2 stop bits, "0" for 1 stop bit. Serial mode control register (SMR): MD1, MD0: "10B" (Mode 2) SCKE: "1" for the dedicated Baud Rate Reload Counter "0" for external clock input SOE: "1" for transmission and reception "0" for reception only Serial status register (SSR): BDS: "0" for LSB first, "1" for MSB first RIE: "1" if interrupts are used; "0" reception interrupts are disabled. TIE: "1" if interrupts are used; "0" transmission interrupts are disabled. Extended communication control register (ECCR): SSM: "0" if no start/stop bits are desired (normal); "1" for adding start/stop bits (special) MS: "0" for master mode (UART generates the serial clock); "1" for slave mode (UART receives serial clock from the master device) Serial control register (SCR): RXE, TXE: set one or both of these control bits to "1" to begin communication. (MWi) HWM90340030 TOP PPG Register PPG0/1, typo in bit constellation in table 16.3-3 Chapter 16.3.3, page 291 PPG Register PPG0/1. There is a typo in the bit constellation in table 16.3-3. The setting shown in figure 16.3-4 is correct. Incorrect: hm90340-cm44-10125-2e-corr-x1-17.doc 22 / 29 Correction: The same applies for PCS[0:2]. (PHu) hm90340-cm44-10125-2e-corr-x1-17.doc 23 / 29 HWM90340031 TOP Chapter 20.8: Notes on using UART Notes on using UART: ==================== 1.) (Graphic 1) CRE resets reception state machine and next falling edge at SINn starts reception of new byte (graphic 1) Therefore either set CRE bit immediately (within half bit time) after receiving errors to prevent data stream desynchronization (Graphic 2) or wait an application dependent time after receiving errors and set CRE, when SINn is idle. 2.) Please note, that in case a framing error occurred (stop bit: SINn = "0") and next start bit (SINn = "0") follows immediately, this start bit is recognized regardless of no falling edge before (Graphic 3). This is used to remain UART synchronized to the data stream and to determine bus always dominant errors (Graphic 3 above) by producing next framing errors, if a recessive stop bit is expected. If this behaviour is not wanted, please disable the reception temporarily (RXE = 1 -> 0 -> 1) after framing error. In this case, reception goes on at next falling edge on SINn. (Graphic 3 below). hm90340-cm44-10125-2e-corr-x1-17.doc 24 / 29 Graphic 1: CRE bit timing within ½ Bit Time of Stop Bit Last Data Bit Stop Bit SIN Start Bit ½ Bit Time Sample Point Error Flags CRE Reception State Machine is reset Falling Edge detected: Receive new Frame CRE bit timing out of ½ Bit Time of Stop Bit Last Data Bit Stop Bit SIN Start Bit ½ Bit Time Sample Point Error Flags CRE Falling Edge detected: Receive new Frame Reception State Machine is reset, Start Bit Condition is reset, actual Reception is desynchronized hm90340-cm44-10125-2e-corr-x1-17.doc 25 / 29 Graphic 2: Example for Desynchronization SIN CRE during Start Bit CRE Reception is reset RX read Next falling Edge is treated as Start Bit 1st Frame 2nd Frame 1st desynchronized Frame Missed Bits hm90340-cm44-10125-2e-corr-x1-17.doc 26 / 29 Begin of 2nd desynchronized Frame Missed Bits Graphic 3: USART Dominant Bus Behaviour Reception always enabled (RXE = 1) SIN FRE CRE Framing Error occurs Error is cleared Reception is ongoing regardless of no falling edge Next Framing Error occurs Falling Edge is next Start Bit Edge Reception disabled temporary (RXE = 1 → 0 → 1) SIN FRE CRE RXE Framing Error occurs Error is cleared Reception is reset: Waiting for falling Edge Reception is ongoing regardless of no falling edge (MWi) hm90340-cm44-10125-2e-corr-x1-17.doc 27 / 29 No further Errors Falling Edge is next Start Bit Edge HWM90340032 TOP Notes on time base timer (TBOF bit) =================================== Chapter 11.2, table 11.2-1 bit 11 (TBOF) Note: To clear the TBOF bit, disable interrupts (TBIE = 0) or mask interrupts using the interrupt mask register (ILM) in the processor status. Chapter 11.3 Note: To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a timebase timer interrupt at interrupt processing (TBTC: TBIE = 0) or mask a timebase timer interrupt by using the ILM bit in the processor status (PS) to write "0" to the TBOF bit. Do not enable timebase timer interrupt (TBTC: TBIE = 1) and clear interrupt flag (TBTC: TBOF = 0) at the same time! (HWe, KDi) HWM90340033 Bit Timing Register (BTR) ========================= Chapter 22.6.5, operation conditions. WRONG: -----• Device with "G" suffix: For 1 ≤ PSC ≤ 63: TSEG1 ≥ 2TQ TSEG1 ≥ RSJW TSEG2 ≥ 2TQ TSEG2 ≥ RSJW For PSC = 0: TSEG1 ≥ 5TQ TSEG2 ≥ 2TQ TSEG2 ≥ RSJW • Device without "G" suffix: For 1 ≤ PSC ≤ 63: TSEG1 ≥ RSJW TSEG2 ≥ RSJW + 2TQ For PSC = 0: TSEG1 ≥ 5TQ TSEG2 ≥ RSJW + 2TQ hm90340-cm44-10125-2e-corr-x1-17.doc 28 / 29 TOP CORRECT: -------- For 1 ≤ PSC ≤ TSEG1 ≥ TSEG1 ≥ TSEG2 ≥ TSEG2 ≥ For PSC = 0: TSEG1 ≥ TSEG2 ≥ TSEG2 ≥ 63: 2TQ RSJW 2TQ RSJW 5TQ 2TQ RSJW (HWe, KDi, FJ) HWM90340034 TOP Notes on Watch timer (WTOF bit) =============================== Chapter 15.2, [Bit 4] WTOF Note: To clear the WTOF bit, disable interrupts (WTIE = 0) or mask interrupts using the interrupt mask register (ILM) in the processor status. Chapter 15.3 Watch Timer Operation Note: To clear the overflow interrupt request flag bit (WTC: WTOF), disable a watch timer interrupt at interrupt processing (WTC: WIE = 0) or mask watch timer interrupt by using the ILM bit in the processor status (PS) to write "0" to the WTOF bit. Do not enable watch timer interrupt (WTC: WIE = 1) and clear interrupt flag (WTC: WTOF = 0) at the same time! (HWe, SJa) hm90340-cm44-10125-2e-corr-x1-17.doc 29 / 29