Transcript
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D D
I210-AS/IS REFERENCE DESIGN SERDES-SFP REFERENCE DESIGN C
C
EXTERNAL INTERFACES PROVIDED: - PCIE V2.1 (2.5GT/S) GEN1 X1 - SERIALIZER-DESERIALIZER (SERDES) TO SUPPORT 1000BASE-SX/LX (OPTICAL FIBER - IEEE802.3) - SERIALIZER-DESERIALIZER (SERDES) TO SUPPORT 1000BASE-KX (802.3AP) AND 1000BASE-BX (PICMIG 3.1) FOR GIGABIT BACKPLANE APPLICATIONS - SGMII (SERIAL-GMII SPECIFICATION) INTERFACE FOR SFP (SFP MSA INF-8074I)/EXTERNAL PHY CONNECTIONS - NC-SI (DMTF NC-SI OVER RMII) OR LEGACY SMBUS OR NC-SI OVER MCTP OVER PCI-E OR SMBUS FOR MANAGEABILITY CONNECTION TO BMC - IEEE 1149.1 JTAG
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B
A
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LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
1 1
8
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5
4
3
2
1
REVISION CONTROL R1.90
INITIAL RELEASE (INTEL PUBLIC)
D D
TABLE OF CONTENTS 1. TITLE PG 2. TOC 3. PCI-E & NC-SI I/O 4. SERDES-SFP LED 5. SUPPORT CIRCUITS 6. POWER SUPPLY TREE 7. POWER SUPPLY & I210 REGULATOR 8. POWER MUX 9. SVR 12V-4V 10.SVR BUCK-BOOST 11.NC-SI PHY 12.NC-SI MDI & CLK 13.TEST I/O & LED
C
B
C
B
A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
2 1
8
7
6
5
4
3
2
1
PCIE_NC-SI_SMB D D
V12P0_PE_MAIN
V3P3_LAN
V3P3_PE_AUX
1
1
R107 R108
R121 R122
1 1
1
F4
1
1
F3
1206LF
2
R132
0
2 2
R66
0
EU2
NCSI_ARB_IN NCSI_ARB_OUT
IN OUT
PE_V3P3_NC
R102
2
1 1
13A2> 13A1<
2
C
PE_V12
I210_AS PE_RP PE_RN
26 25
PE_CLKP PE_CLKN
17 16
PE_RST_N PE_WAKE_N
34 36 35
SMB_CLK SMB_DATA SMB_ALRT_N
PE_TP PE_TN NC_SI_CLK_IN NC_SI_CRS_DV NC_SI_TX_EN
21 20
PET_P PET_N
2 3 7
R105 33 1 2
43 44 9 8 6 5
NC_SI_ARB_IN NC_SI_ARB_OUT NC_SI_TXD0 NC_SI_TXD1 NC_SI_RXD0 NC_SI_RXD1
B
R127 1 10.0K
2
1
1
2
2
C33
0.1UF
1 C341
22
J1
PER0_P PER0_N
0.1UF
FCONN36_PCI_EXPRESSX1
NCSI_CLK_IN
IN
12A2>
13A2>
NCSI_TX_EN
IN
11B1>
13A2>
NCSI_CRS_DV
OUT
11B4<
13A2<
NCSI_TXD_0 NCSI_TXD_1 NCSI_RXD_0 NCSI_RXD_1
IN IN OUT OUT
11B4> 11B4>
13A2> 13A2>
11B4< 11B4<
13A2< 13A2<
A1 A2 A3 A4 NC A5 NC A6 NC A7 NC A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
R37 10.0K
24 23
10.0K
100K
R111 100K
R67 10.0K
R71 10.0K
R68
2
10.0K 10.0K
2
10.0K 10.0K
2
10.0K
C52 10UF 6.3V 2 X5R 0603LF
1
2
V3P3_LAN
C
C40 22.00UF
R44
PRSNT1A_N 12V3 12V4 GND35 JTAG2 JTAG3 JTAG4 JTAG5 3_3V2 3_3V3 PERST*
KEY
12V1 12V2 RSVD1 GND1 SMCLK SMDAT GND2 3_3V1 JTAG1 3_3VAUX WAKE_N RSVD2 GND3 PETP[0] PETN[0] GND4 PRSNT2_N GND5
GND36 REFCLKP REFCLKN GND37 PERP[0] PERN[0] GND38
B1 B2 B3 B4 B5 B6 B7 B8 B9 NC B10 B11
SMCLK SMDAT
PE_V3P3_AUX
B
B12 B13 B14 B15 B16 B17 B18
PE_CLK_N PE_CLK_P 13B2> 13B2<
PE_RST_N PE_WAKE_N PET0_N PET0_P
IN OUT
NOTE: PE_(T/R)_N/P INTENTIONALLY SWAPPED FOR ROUTING
A
R9 1 R731 R741
SMBALRT_N
13A4<
OUT
13A4<
BI
SMBD
13A4<
BI
SMBCLK
20 2 2
0 0
A
EMPTY
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
3 1
8
7
6
5
4
3
2
1
SFP_LED_SDP V3P3_LAN_SUPPORT
V3P3_SFP
R70 0
D
2
C73 4.7UF
1 2
1
1
1
1
2
2
2
2
330
2
2
2
DS12 RED SFP_PWR
1
1
2
C72 4.7UF
FET_P
D 3
G
1
Q7
R92
SFP_PWR 1
2
SERDES I2C EXT PU OPTIONAL.
1
2 S
SFP_MOD_ABS SFP_TX_DIS SFP_TX_FAULT SFP_PWR
2
* INTERNAL PULL UP L5 3.3UH
R141 R142 R145
-
1
10.0K 10.0K 10.0K
SDP0 SDP1 SDP2 SDP3
1
R140
L4 3.3UH
0 2 1/2W
10.0K
1/2W EMPTY
1 R69
R137
1
10.0K
D
* *
ADD CAGE C18025-003
J22
SCONN20_SFP
VCCR VCCT
13B4< 13B4<
13A1> 13B4< 13B4<
BI BI BI BI
SDP0 SDP1 SDP2 SDP3
R65
1
160 2
B
R64
1
SET_P
63 61 62 60
SDP0
31 30 33
LED0 LED1 LED2
58
NC_58
SET_N
SDP1/PCIE_DIS SDP2
SER_P
SDP3
SER_N
53 52
SFP_TD_P SFP_TD_N
50 49
SFP_RD_P SFP_RD_N
I2C_CLK
57 55
SRDS_SIG_DET
54
I2C_DAT
VEER_11
18 19
TD+ TD-
20
VEET_20
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10
2160
VEER_10
RDRD+
RS1 RX_LOS
VEER_14
RS0
VCCR_15 VCCT_16
MOD-ABS
VEET_17
SCL SDA TX_DISABLE TX_FAULT VEET_1
CHASSIS GND CGND_1 CGND_11 CGND_2 CGND_12 CGND_3 CGND_13 CGND_4 CGND_14 CGND_5 CGND_15 CGND_16 CGND_6 CGND_7 CGND_17 CGND_8 CGND_18 CGND_19 CGND_9 CGND_20 CGND_10
10
C
9 8 7 6 5 4 3 2 1
1 2
0
R147
EU2
I210_AS
11 12 13 14 15 16 17
R146
NOTE: KX/SFP DATA FLOW DIRECTION. C
1 2
0
G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
B
SDA SCL SIG_DET
OUT OUT OUT
13A4< 13A4< 13A4<
DS11 1
R139 2 470
LED_DUAL_4P
SDP LED AT SFP CAGE
A
GREEN
LED0->IF LINKED AT 100BASE-TX THEN LOW.
3
1
LED2->IF LINKED AT 1000BASE-T THEN LOW.
4
2
LED1->IF LINK UP THEN LOW. BLINK HIGH FOR ACTIVITY. 1
R58
DS10 2
160
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
2
A
V3P3_SFP
YELLOW
1
GREEN
1
R136 2 160
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
4 1
8
7
6
5
4
3
2
1
SUPPORT CIRCUITS D D
Y3
2
1
1 2
2
J13 EMPTY
COG
2
2
2
2
U7
EU2
NONE
1
R771
2
R94 R841 R1061 R991
2
R85 R1041
2
1
XTAL_IN XTAL_OUT
0
46 45
JTCK 19 JTDI 29 JTDO 4 JTMS 18
23.3K 23.3K 23.3K 3.3K
RSET 48 1
28 1
DEV_OFF_N LAN_PWR_GOOD
3.3K 3.3K
2
1
IN 2
DEV_OFF PU IS OPTIONAL. NOT REQUIRED WHEN CONNECTED TO GPIO
5 6
XTAL1 XTAL2 JTAG_CLK
NVM_CS_N
JTAG_TDI
NVM_SI
JTAG_TDO
NVM_SO
JTAG_TMS
NVM_SK
15 12 14 13
33 2 33 2 33 2 33 2
R164 1 R168 1 R169 1 R170 1
D C
1
S_N
3
W_N
7
HOLD_N
SOCKET_SST25VF040b
RSET
C25 0.1UF
VCC
I210_AS
EMPTY
13B2>
2
V3P3_LAN
2
Q
C
2
GND
DNC_6
EMPTY
1
C83 1
2
2
4
15.0PF
DNC_1
EMPTY
GND DNC_3
DNC_10
OUT
3
E/D
10
DNC_2
C24 1
0.01UF
2
C
DNC_7
9 VCC
PLACE NEAR IC 5 LAN_CLK_IN
R76 0
R97
SOICLF IC
4
2
1
1
8
25.000MHZ OSC_10PIN_TXCO
R78 0
1
3.3K
1
R51
1
3.3K
COG
R103 33K
2
Y4
8 7 6
EMPTY
C30 27.0PF
DEV_OFF_N LAN_PWR_GOOD
R75 4.99K 1% PLACE NEAR IC
NVM_SK=JTAG MODE JTAG_MAIN->PU(INT) JTAG_RSVD->PD (R20)
MISO SS SCLK MOSI
1 2
OUT OUT OUT IN
13A4< 13A4< 13A4< 13A3<
CAD NOTE: KEEP SPI TRACES SHORT FOR 70MHZ SIGNALING 1
R96 1 3.3K
1
33K
1588 OPTION <1PPM OSC
Y1_P1
EMPTY
V3P3_LAN
Y1_P2 C20 27.0PF
1
R20
V3P3_LAN
V3P3_LAN
25.000MHZ 2 1
1
B
B
J14 SI-PU_SEC-ENA SI-PD_SEC-DIS
2
2
R59
3.3K
1 2
INSTALLING J14 DISABLES SECURITY AND THE INVM LOCK BY PULLING DOWN NVM_SI (PIN 12) DURING POWER_UP. FOR INFORMATION SEE DATA SHEET: 3.3.1.2 FLASH DETECTION, NVM VALIDITY FIELD, AND NON-SECURE MODE
A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
5 1
8
7
6
5
4
3
2
1
POWER SUPPLY TREE THESE POWER SUPPLIES ARE EXAMPLES. POWER SUPPLIES SHOULD BE OPTIMIZED BY SYSTEM POWER DESIGNER FOR EACH PLATFORM.
D
PE_V12P0 MAIN
C
D
C
V3P3 ENABLE I210-SVR 1.5V 0.9V
3.3V LAN TPD54620 SWITCHING REGULATOR FOR 12V TO 4V
SHEET 8
LTC3533 BUCK/BOOST REGULATOR FOR 3.3V
V3P3 DIODE OR SHEET 9
SHEET 11
SHEET 10
3.3V SUPPORT
PE_V3P3 MAIN
B
NOT USED IN THIS DESIGN
B
PE_V3P3 AUX
A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
6 1
8
7
6
5
4
3
2
1
D
POWER SUPPLY & I210 REGULATOR
D
THICK TRACES = PLANE V3P3_LAN V3P3_LAN
C78 10UF NC_22
B
C90 10UF
1
NC_56
22
RSVD_22_NCI210_AS
51 47
VDD1P5_51 VDD1P5_47
42 32 11 59
VDD0P9_42 VDD0P9_32 VDD0P9_11 VDD0P9_59
27 10 64
VDD3P3_27 VDD3P3_10 VDD3P3_64
41 56
VDD3P3_41 RSVD_56_NC
0805LF
*
2
* 1
1
2
2
1
C75
0.1UF
2
1
C79
0.1UF
2
1
2
C104 0.1UF
1
C113
0.1UF
1
EU2
C101 10UF
2
1
6.3V
J15 EMPTY
1
1 C111 47UF
J16
2
V0P9_LAN
V1P5_LAN
EMPTY
1
V1P5_LAN V0P9_LAN
J17
2
C
EMPTY
1
C
2
2
C88 10UF
2
V1P5_LAN
* VDD1P5_39
39
VDD0P9_38
38
CTOP CBOT
E_PAD_GND
C77 47UF
1
CTOP C26 0.039UF X7R CAD NOTE: KEEP CLOSE TO IC
40 37
65
1
10UF
EMPTY 2
C97
2
1
C95
1
C110
1
C82
1
C89
0.1UF
20.1UF
20.1UF
20.1UF
2
1
1
1
1
1 2
B
V0P9_LAN
*
2
C98 47UF
1
1
EMPTY 2
2
C105 10UF
C115
C76
C102
C103 0.1UF
0.1UF
2
0.1UF
2
2
0.1UF
2
1 2
*LOCALIZED AND DISTRIBUTED BULK CAPACITANCE RANGE ~15UF A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
7 1
8
7
6
5
4
3
2
1
POWER MUX (AUX / MAIN SWITCH)
D
D
INPUTS TO V3P3 DIODE OR V3P3_NC
~4.3V TYP
CONN15_E33878_001
GND_10 GND_11 GND_12
C
12V_13 12V_14 12V_15
EMPTY
MBRS540LT3
2
IC
V5P0_CONN_UNFUSED
1
V3P3_OR
CR4 2
2
1
2
J12 EMPTY
1
MBRS540LT3
CR3
V12P0_NC
1
VCC_7 VCC_8 VCC_9
J25
1
F1
CR2
1
GND_4 GND_5 GND_6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2
VCC3_1 VCC3_2 VCC3_3
V3P3_OR
TPS54620_OUTPUT
5V_USB
2
EXTERNAL SATA POWER J10
2
1
MBRS540LT3 1 C32
C80
C99
2
2
EMPTY 7343LF
EMPTY 7343LF
100UF 20%
V3P3_PE_AUX
1
1
1
2
2
J11 EMPTY
2
C13 10UF
1
C14 10UF
1 2
R32 100K
2
1
R25
U4
2 3 4 7
B
1
1
2
100K EMPTY
2
180UF 20% 6.3V
1812LF
180UF 20% 6.3V
IDEAL DIODE
LTC4352
100K 2 EMPTY
R30
C
1 C3 10UF
VCC
0.1UF
9
100K 2
13
1
CPO
10 12
UV 0V REV
1 C10
R28
VIN
GND EPAD
SOURCE GATE OUT STATUS FAULT
1
C62 0.1UF 1
2
R23
2
8.2K S1
11
8
G
5 6
4
B
U3
NTGS4141N
3 G
D1 D2 D3 D4
1 2 5 6
A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
8 1
8
7
6
5
4
3
2
1
TPS54620 SWITCHING REGULATOR
D
D
VIN-MIN = 11.0V VIN-MAX = 13.0V
VOUT-MIN = 4.22V VOUT-MAX = 4.46V
V12P0_PE_MAIN PLACEMENT NOTE:: PLACE ALL CAPS CLOSE TO ASSOCIATED PINS PLACE 0.1 UF CAP CLOSE TO VIN PIN
C
1
1
1
J23
1
1206LF 1
2
2
C49 22.00UF
2
R154
2
C47 22.00UF 1206LF
2
C48 22.00UF
C45 0.1UF
TPS54620
4
1206LF 2
2
5
PVIN_4 PVIN_5
6
VIN
10
13
PH_11 PH_12
PWRGD
9 1 8
SS/TR RT/CLK COMP
TPS54620_RT TPS54620_COMP
TPS54620_OUTPUT
TPS54620_BOOT
1
C46
0.1UF
11 12
EN
14
TPS54620_SS
R157 30.10K 1%
BOOT
L1
2
1
ENABLES CONVERTER FOR VIN ~8V OR GREATER
VSENSE
7
GND_2 GND_3 PWRPAD
2
2
10UH
1
3 15
R101 37.40K 1%
C42 150.0PF
2
C108 1.0UF
TPS54620_VSENSE ~3.5MS STARTUP-TIME
1
2
B
1
196.00K 1%
TPS54620_EN 1
1
C
EU3
C114 0.01UF
1
R116 100K
1
1% 2
2
1
C106 820.00PF
R158 1.15K
1210LF
1%
2
1
2 1
C87 22UF
C22 22UF 1210LF
C85 22UF 1210LF
B
R109 8.45K 1%
2
C35 0.047UF
2
A
A
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
9 1
8
7
6
D
5
4
3
2
1
LTC3533 BUCK/BOOST REGULATOR FOR 3.3V R98
1
C41 2
2.20
1
C39
L3
2
1
6.8UH IND
1000PF
2
R91
1
1000PF
D
2
V3P3_LAN
V3P3_POWER
2.20
V3P3_OR
C29 10UF 2
1
1
2
R95 33.2K 1%
C31
R150
1
1
2
8.2K
2
1000PF
1
R93 340K 1%
2
C94 1
2
1
1
C112 0.1UF
2
1
R159 390K
1
R86 200K 1%
1C37
2
1206LF
2
SIZE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
R149 2
1/2W 1206LF
C36 10UF
4
B
J8
2
REV
490116
B 5
V3P3_LAN_SUPPORT
VOUT_MIN = 3.18V VOUT_MAX = 3.41V I3533-MAX = 1.5A
A
TITLE
2
222.00UF
VOLTAGE BOOST REQUIRED TO COMPENSATE FOR VOLTAGE DROP FROM DIODE OR CIRCUIT. MANY DESIGNS MAY NOT REQUIRE A BOOST CIRCUIT.
8
EMPTY
0 1
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124
J6 1
6.800PF
B
2 4 1
C96 470PF
CONN4
2
14 2
J7
1 3
2
R87 0 2
PAD
2
C50 0.01UF
PGND_6
2
C51 0.1UF
BURST
6
C44 0.1UF
R113 12.1K 1%
VC
RT
13
15
1
1
1
FB
RUN/SS
PGND_5
1 1
12
2
1/2W 1206LF
1
EN_3.3V
SGND
VDD RESET_N
C
3
1
R155
0
1
5
NC SENSE GND
4 3
3
TPS3803-01D
2
CONN4
9 8
2
1 5 2
EMPTY
1 PVOUT VOUT
VIN
1
2 4
PVIN
J5
U8
2
11 10
7
4
R115 1.0M
R112 U9 7.68K 1% SENSE RANGE: 1.95V-2.12V
SW2
1
SW1
C
LTC3533
2
V3P3_OR
3.3V ENABLE
DATE
2012-09-28
1.90 3
2
A
SHEET
10 1
8
7
6
5
4
3
2
1
NC-SI TEST INTERFACE TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN CONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER
R124 10.0K
2
2
V3P3_LAN_SUPPORT
ISO_EN
R123 10.0K
2
U2
R125 10.0K
DISABLE FX MODE R119 10.0K
1
1
EMPTY 1
1
10.0K
R126 10.0K
EMPTY
ISO_DIS 2
2
2 1
R1
10.0K
D
ENABLE FX R120 10.0K
1
1
1
EMPTY
10MBPS
R16
2
100MBPS
WHEN USING BASE-T OPTION DEPOPULATE NC-SI PHY, PG12-13
2
D
V3P3_LAN_SUPPORT
XI
30 2
2
R130
2
48
NCSI_TX_EN
OUT
13A2>
C
3B2<
26 27 28 29
NCSI_LINK_ACT NCSI_SPD100
OUT OUT
12B1< 12B1<
40 41
NCSI_TX_N NCSI_TX_P
OUT OUT
12B4<> 12B4<>
21 22
NCSI_EN NCSI_BTB
2
R33 10.0K
R31 10.0K
DUPLEX FULL DUPLEX AUTONEG_EN ENABLE AUTONEG BTB
13 24 7 47 38 31 42
R45 10.0K
BTB EN 2
NCSI MODE EN
R48 10.0K
1
ISOLATE
1
10 9 11
NCSI MODE DIS 2
2
R47 10.0K
EMPTY
1
BTB DIS
R46 10.0K
1
1
1
10.0K
10.0K
V3P3_LAN_SUPPORT
14 15 16 17 18 19 20
FIBER_EN
1
1
1%
6.49K
B
R49
IN IN IN IN
TXER NCSI_PHY_CLK NCSI_CRS_DV NCSI_RXD_0 NCSI_RXD_1
10.0K
12A2> 3B2> 3A2> 3A2>
NCSI_TXD_1 NCSI_TXD_0 NCSI_RX_N NCSI_RX_P
R118
13A2< 13A2< 13A2<
OUT OUT IN IN
2
13A2> 13A2> 12B4<> 12B4<>
R43
3A2< 3A2<
25 3 4 5 6 32 33 37
34
2
C
V3P3_LAN_SUPPORT
45 NC
1
1
NC2
XO FXSD_FXEN RXC RXDV_CRSDV_PCS_LPBK RXER_ISO LED0_TEST LED1_SPD100_NFEF LED2 LED3_NWAYEN TXN TXP COL_RMII CRS_RMII_BTB VDDC VDDIO_1 VDDIO_0 VDDPLL VDDRCV VDDRX VDDTX
2
NCSI_MDIO
KS8721
XI MDIO MDC INT_N_PHYAD0 RXD3_PHYAD RXD2_PHYAD2 RXD1_PHYAD3 RXD0_PHYAD4 RXN RXP REXT TXER TXC_REFCLK TXEN TXD0 TXD1 TXD2 TXD3 PD_N RST_N
1
46
EMPTY
GND=GND
B
2
1% TSR > 50 US
V3P3_LAN_SUPPORT
FB3
1
1
2 1
R5 22.60K
1
V2P5_NCSI
1
600
R27 10.0K
C2 0.1UF
2
1
C59 10UF
2
1
A
FB1
2 V2P5_NCSI_PLL
1
2
V2P5_NCSI_C
2
600 1
C60 10UF
1
C66 10UF 2
EMPTY
2
C53 10UF
1
1
C11 10UF
EMPTY 2
2
C12 10UF
1
EMPTY
2
1
C65 0.1UF
C56 0.1UF 2
A
R29 0
2
EMPTY
NC-SI PHY SUPPLIES
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
11 1
8
7
6
5
4
3
2
1
NC-SI TEST INTERFACE ELM BASE-T OPTION DEPOPULATE NC-SI PHY, PG12-13. USE NC-SI HEADER TO PLATFORM. TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN CONNECT NS-SI INTERFACE TO A MANAGEMENT CONTROLLER
D
D
DS9 GREEN
C54 1
0.1UF
600
1
FB2
1
R3
1
2
11
1
1% 49.9
R40 0 2
12
TRP1+
TRD1+ TRCT1
CH-A TRP1-
4
R36 0 2
6
49.9 R21
1
R2
C17
1%
C19
LED_DUAL_4P
2
130
0.1UF
C1
49.9 R24
GREEN
1
1
3
TRP2-
TRD3+
1
TRCT3
TRP3+
TRP3-
TRD3-
0.1UF
2
4
2
1%
3
2
1
0.1UF 2 NCSI_RX_N
CH-B
DS8
1
2 1
TRCT2
TRD2-
2
CLOSE TO PHY
C TRP2+
TRD2+
5
1
BI
JA1
TRD1-
2
11B4<
11B1>
10
NCSI_RX_P
BI
IN
CONN12_1840426_3
1
11B4<
NCSI_LINK_ACT
RJ45
2
NCSI_TX_N
C
11B1>
130
R15 2
IN
2
BI
1
11B1>
1% 49.9
2
BI
R8
1
11B1>
2
NCSI_TX_P
CLOSE TO PHY
NCSI_SPD100
V3P3_LAN_SUPPORT
V2P5_NCSI
YELLOW
8
TRD4+
7
TRCT4
TRP4+
9
B
B TRP4-
TRD4-
0.01UF
+-50 PPM
3
OUT
VDD=V3P3_LAN_SUPPORT; GND=GND;
2
C5 0.01UF
5
ICLK
8
OE
13
CLOSE TO SOURCE
1
2 3 6
1
R41
2
33 R129
7
1
GND=GND VDD=V3P3_LAN_SUPPORT
2
33 R128 1
V3P3_LAN_SUPPORT
2
A
Q0 Q1 Q2 Q3
ICS553
C2
2
NCSI_PHY_CLK
OUT
11B4<
NCSI_CLK_IN
OUT
13A2> 3B2<
J9 1
33
EMPTY
2
2
C4 1
OE
50MHZ NC-SI CLOCK U5
1
Y1 OSC 50MHZ 1
R22 10.0K
1
2
V3P3_LAN_SUPPORT
C1
14
V3P3_LAN_SUPPORT
A
AS CLOSE TO THE DEVICE
1
AS POSIBLE
C15 0.01UF 2
LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 8
SIZE
TITLE
I210-AS/IS REFERENCE SCHEMATIC 7
6
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
12 1
8
7
6
5
4
3
2
1
TEST CONNECTORS I/O TEST INTERFACE IS NOT REQUIRED IN A NORMAL DESIGN LED FUNCTION INTENTIONALLY INVERTED (LED OFF - NORMAL)
D
D V3P3_LAN_SUPPORT
V3P3_PE_AUX
* SDP PU-OPTIONAL
*
2
R17
1
*
2 S
1 2
1
RED
LAN_PWR
G
2 S
Q3 FET_P 1
D 3
FET_P 1
D 3
G
2 S
Q4 G
Q2
S
Q5
FET_P
D 3
G
S
FET_P
D
Q6
1
DS2
FET_P 1
D 3
G
2 S
Q1
8 6 4 2
SMBALRT_N SIG_DET
R165 2 330
1R167
SIG_DET_LED 2 S
Q8
EMPTY 3A4<> 3A4<> 5B1> 5B1> 5B1>
A
IN IN IN IN IN
2
SMBCLK
SMBD MISO SCLK SS
PLACE NEAR SPI
8
JTDO JTDI
CONN10 1 3 5 7 9
2 4 6 8 10
MOSI
IN
J20 SCONN10_966926_5
1 3 5 7 9 NC
JRST_N
J2
2 4 6 8 10 NC
OUT
JTCK
OUT
OUT IN IN IN OUT OUT OUT OUT IN
NCSI_CLK_IN NCSI_CRS_DV NCSI_RXD_0 NCSI_RXD_1 NCSI_TXD_0 NCSI_TXD_1 NCSI_TX_EN NCSI_ARB_IN LINK_ACT
R6 2 1 2
B
V12P0_PE_MAIN
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
IO1 IO3 IO5 IO7 IO9 IO11 IO13 IO15 IO17 IO19 IO21 IO23 IO25 IO27 IO29
IO2 IO4 IO6 IO8 IO10 IO12 IO14 IO16 IO18 IO20 IO22 IO24 IO26 IO28 IO30
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1R166
0 2
R134 0 EMPTY
NCSI_ARB_OUT
IN OUT
SDP1 FM_LAN0_DISABLE_N
LAN_PWR_GOOD RST_RSMRST_N
OUT
UNKNOWN
TITLE
I210-AS/IS REFERENCE SCHEMATIC 6
3B2> 4B4<> 13B4<
13B2>
A
JTAG TEST INTERFACE.
SIZE
7
JTMS
12A2> 3B2> 3A2> 3A2> 11B4> 11B4> 11B1> 3B2<
J4
5B1<
ARDVARK I2C/SPI TEST INTERFACE 1. SCL 2. GND 3. SDA 4. NC/+5V 5. MISO 6. NC/+5V 7. SCLK 8. MOSI 9. SS 10. GND LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124
1 2
OUT IN OUT
3B2< 11B4< 11B4< 11B4< 3A2< 3A2< 3B2<
V3P3_LAN_SUPPORT
R61
FET_P
D 3
G
V3P3_LAN_SUPPORT
1
V3P3_LAN_SUPPORT
SCONN30_E95855001
0 2
V3P3_LAN_SUPPORT
10.0K 1
R79 33K
330
V3P3_PE_AUX
2
7 5 3 1
1
SCL SDA
DS13 BLUE
IN IN IN IN
NC-SI_I/0 PLATFORM MGMT HEADER
1
J19 CONN8 4A1> 4A1> 3A4> 4A1>
2
DEV_OFF_N PLACE JUMPER PULL_DOWN_TO DISABLE
V3P3_LAN_SUPPORT
B
R7
1
PE_RESET LED
PE_WAKE LED BLUE
1
7 5 3 1
C
1
GREEN
IN OUT OUT OUT
2
3A4> 3A4< 13A1> 5B4<
DS1
1
330
R112
2
YELLOW
1
1
DS6
DS7
AMBER
1
330
R102 1
2
BLUE
RED
DS5
CONN8 8 6 4 2
PE_WAKE_N PE_RST_N LAN_PWR_GOOD DEV_OFF_N
1
SDP1-DEV-OFF OPT SDP3-PE-DIS OPT TIME-SYNCH_I/O-J18
2
J21 DS3
DS4
2
330
7 5 3 1
R122
IN IN IN IN
1
4B4<> 4B4<> 4B4<> 4B4<>
1
13A1>
8 6 4 2
SDP0 SDP1 SDP2 SDP3
R142 330
CONN8
C
FET_P
D
G
J18
330
2
R34
1
10.0K
*
10.0K
2
R39
1
10.0K
10.0K
330
*
2
1
R42
R26
PU EMPTY WHEN NOT USED OR WHEN USED WITH GPIO
CODE
DOCUMENT NUMBER
490116
B 5
REV
4
DATE
2012-09-28
1.90 3
2
SHEET
13 1
