Ics9lprs387 Advance Information Programmable Timing Control Hub

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Advance Information PROGRAMMABLE TIMING CONTROL HUB FOR INTEL BASED SYSTEMS ICS9LPRS387 Recommended Application: Features/Benefits: CK505M+ clock, with fully integrated voltage regulators and series resistors • Supports spread spectrum modulation, 0 to -0.5% down spread for CPU, SRC and PCI clocks • Supports CPU clocks up to 400MHz • Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Output Features: VDDSRC SRCC6_LPR SRCT6_LPR CR#6 GNDSRC SRCC7_LPR CR7# VDDCPU_IO CPUC1_LPR_F CPUT1_LPR_F GNDCPU CPUC0_LPR_F CPUT0_LPR_F VDDCPU Pin Configuration CPU outputs cycle-cycle jitter < 85ps SRC outputs cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 500ps +/- 100ppm frequency accuracy on USB and 100MHz spread DOT clocks SRCT7_LPR • • • • • • VDDSRC_IO • • • • Key Specifications: CPUC2_ITP_LPR/SRCC8_LPR • 2 - CPU differential low power push-pull pairs 8 - Differential low-power push-pull pairs for SATA and PCI Express* 1 - CPU_ITP/SRC selectable differential low power push-pull pair 4 - PCI (33MHz) 1 - PCICLK_F, (33MHz) free-running 1 - USB, 48MHz 1 - SRC/DOT selectable differential low power pushpull pair 2 - REF, double-strength 14.318MHz 1 - Selectable SRC differential pair or 27MHz single ended pair CPUT2_ITP_LPR/SRCT8_LPR • • 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CK_PWRGD/PD# 1 FSLB/TEST_MODE 2 GNDREF 3 X2 4 54 PCI_STOP# 53 CPU_STOP# 52 VDDSRC_IO 51 SRCC10_LPR X1 5 VDDREF 6 50 SRCT10_LPR FSLC/TEST_SEL/REF0 7 REF1 8 48 SRCT11_LPR 49 CR10# 47 SRCC11_LPR SDATA 9 SCLK 10 NC 11 46 CR#11 45 SRCC9_LPR 44 SRCT9_LPR 9LPRS387 VDDPCI 12 43 CR#9 PCI1 13 PCI2/TME 14 PCI3 15 PCI4/27_Select 16 42 GNDSRC 41 CR#4 40 SRCC4_LPR 39 SRCT4_LPR PCI_F5/ITP_EN 17 GNDPCI 18 38 VDDSRC_IO 37 CR#3 SRCC3_LPR SRCT3_LPR GNDSRC SRCC2_LPR/SATAC_LPR SRCT2_LPR/SATAT_LPR VDDPLL3_IO GND 27MHz_SS/SRCC1_LPR/SE2 27MHz_NonSS/SRCT1_LPR/SE1 VDDPLL3 GND SRCC0_LPR/DOTC_96_LPR SRCT0_LPR/DOTT_96_LPR VDD96_IO GND48 CR#A VDD48 USB_48MHz/FSLA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72-pin MLF TM TM IDT /ICS Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 1 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Pin Description Pin# Pin Name 1 CK_PWRGD/PD# 2 FSLB/TEST_MODE 3 4 5 6 GNDREF X2 X1 VDDREF 7 FSLC/TEST_SEL/REF0 8 9 10 11 12 13 REF1 SDATA SCLK NC VDDPCI PCI1 14 PCI2/TME 15 PCI3 16 PCI4/27_Select 17 PCI_F5/ITP_EN 18 19 GNDPCI VDD48 20 USB_48MHz/FSLA 21 22 23 CR#A GND48 VDD96_IO 24 SRCT0_LPR/DOTT_96_LPR 25 SRCC0_LPR/DOTC_96_LPR 26 27 GND VDDPLL3 28 27MHz_NonSS/SRCT1_LPR/SE1 29 27MHz_SS/SRCC1_LPR/SE2 30 31 GND VDDPLL3_IO 32 SRCT2_LPR/SATAT_LPR 33 SRCC2_LPR/SATAC_LPR 34 GNDSRC 35 SRCT3_LPR 36 SRCC3_LPR Type Pin Description IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS IN and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. PWR Ground pin for the REF outputs. OUT Crystal output, Nominally 14.318MHz IN Crystal input, Nominally 14.318MHz. PWR Ref, XTAL power supply, nominal 3.3V 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input I/O electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table OUT 14.318 MHz reference clock. I/O Data pin for SMBus circuitry, 3.3V tolerant. IN Clock pin of SMBus circuitry, 5V tolerant. N/A No Connection. PWR Power supply for PCI clocks, nominal 3.3V OUT 3.3V PCI clock output 3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows I/O 0=Overclocking of CPU and SRC allowed 1=Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output OUT 3.3V PCI clock output 3.3V PCI clock output / 27MH mode select for pin28, 29 strap. On powerup, the logic value on this I/O pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function table for the pin28 and pin29. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 63 and 64 are an I/O ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# PWR Ground pin for the PCI outputs PWR Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS I/O and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. IN Clock Request control A for either SRC0 or SRC2 pair selectable via SMBUS PWR Ground pin for the 48MHz outputs PWR Power pin for the DOT96 clocks, nominal 1.05V to 3.3V. True clock of differential 0.8V push-pull SRC/DOT96 output with integrated 33ohm series resistor. I/O No 50ohm resistor to GND needed.The power-up default function depends on 27_Select,1= SRC0, 0=DOT96. Complement clock of SRC or DOT96. The power-up default function depends on 27_Select,1= I/O SRC0, 0=DOT96. No Rs needed. PWR Ground pin. PWR Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal. True clock of differential SRC1 clock pair (No Rs needed) / 3.3V single-ended output. 27_Select I/O determins the power-up default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. Complement clock of differential SRC1 clock pair (No Rs needed) / 3.3V single-ended output. I/O 27_Select determins the power-up default, 1=27MHz SS SE clock, 0 = LCD_SST 100MHz differential clock. PWR Ground pin. PWR 1.05V to 3.3V from external power supply True clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series resistor. OUT No 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC/SATA output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. PWR Ground pin for the SRC outputs True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 2 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Pin Description Pin# Pin Name 37 CR#3 38 VDDSRC_IO 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 SRCT4_LPR SRCC4_LPR CR#4 GNDSRC CR#9 SRCT9_LPR SRCC9_LPR CR#11 SRCC11_LPR SRCT11_LPR CR10# SRCT10_LPR SRCC10_LPR VDDSRC_IO CPU_STOP# PCI_STOP# VDDSRC SRCC6_LPR SRCT6_LPR CR#6 GNDSRC SRCC7_LPR SRCT7_LPR VDDSRC_IO 63 CPUC2_ITP_LPR/SRCC8_LPR 64 65 66 67 68 69 70 71 72 CPUT2_ITP_LPR/SRCT8_LPR CR7# VDDCPU_IO CPUC1_LPR_F CPUT1_LPR_F GNDCPU CPUC0_LPR_F CPUT0_LPR_F VDDCPU Type Pin Description IN Clock request for SRC3, 0 = enable, 1 = disable PWR 1.05V to 3.3V from external power supply True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC4, 0 = enable, 1 = disable PWR Ground pin for the SRC outputs IN Clock request for SRC9, 0 = enable, 1 = disable True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. IN Clock request for SRC11, 0 = enable, 1 = disable Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. IN Clock request for SRC10, 0 = enable, 1 = disable True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. PWR 1.05V to 3.3V from external power supply IN Stops all CPU clocks, except those set to be free running clocks IN Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. PWR Supply for SRC clocks, 3.3V nominal Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. IN Clock request for SRC6, 0 = enable, 1 = disable PWR Ground pin for the SRC outputs Complementary clock of differential 0.8V push-pull SRC output with integrated 33ohm series OUT resistor. No 50ohm resistor to GND needed. True clock of differential 0.8V push-pull SRC output with integrated 33ohm series resistor. No OUT 50ohm resistor to GND needed. PWR 1.05V to 3.3V from external power supply Complement clock of low power differential CPU2/Complement clock of differential SRC pair. No Rs needed. The function of this pin is determined by the latched input value on pin 17, PCIF5/ITP_EN on powerup. The function is as follows: OUT Pin 17 latched input Value 0 = SRC 1 = CPU_ITP True clock of low power differential CPU2/True clock of differential SRC pair. No Rs needed. The function of this pin is determined by the latched input value on pin 17, PCIF5/ITP_EN on powerup. The function is as follows: OUT Pin 17 latched input Value 0 = SRC 1 = CPU_ITP IN Clock request for SRC7, 0 = enable, 1 = disable PWR 1.05V to 3.3V from external power supply Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series OUT resistor. Free running during iAMT. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. OUT Free running during iAMT No 50 ohm resistor to GND needed. PWR Ground pin for the CPU outputs Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series OUT resistor. Free running during iAMT. No 50ohm resistor to GND needed. True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. OUT Free running during iAMT PWR Supply for CPU clocks, 3.3V nominal OUT IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 3 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information General Description The ICS9LPRS387 is a CK505 clock synthesizer. The ICS9LPRS387 provides a single-chip solution for Intel based systems. The ICS9LPRS387 is driven with a 14.318MHz crystal and generates CPU outputs up to 400MHz. Funtional Block Diagram X1 REF R EF X2 OSC CPU(1:0) SRC8/ITP CPU CPU PLL1 SS SRC SRC(11:9, 7:6, 4:3) SR C _M A IN PCI33MHz SRC PLL3 SS PCI PCI33MHz SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# SRC1/SE(2:1) CPU_STOP# CR# 27_Select Control Logic Differential Output ITP_EN SE Outputs 7 FSLC/TESTSEL FSLB/TESTMODE SRC0/DOT96 SATA PLL2 Non-SS DOT96MHz 48MHz 48MHz IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 4 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Table 1: CPU Frequency Select Table 2 FSLC B0b7 0 0 0 0 1 1 1 1 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 FSLA B0b5 0 1 0 1 0 1 0 1 1 FSLB B0b6 0 0 1 1 0 0 1 1 SRC MHz PCI MHz REF MHz USB MHz DOT MHz 100.00 33.33 14.318 48.00 96.00 Reserved 1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Table 2: pin28, 29 Configuration 27_Select B1b4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Spread % Reserved Pin 28 Pin 29 MHz MHz 0 1 0 1 0 1 0 1 0 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 -0.50% -1% -1.50% (+/-0.25) (+/-0.5) N/A None 0 1 24.576 98.304 None 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 98.304 27.000 25.000 98.304 27.000 25.000 None None None N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_nonSS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS 27MHz_SS -0.5% N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A B1b3 B1b2 B1b1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Comment SRCCLK1 from SRC_MAIN Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 N/A 24.576Mhz on SE1 and SE2 24.576Mhz on SE1, 98.304Mhz on SE2 98.304Mhz on SE1 and SE2 27Mhz on SE1 and SE2 25Mhz on SE1 and SE2 N/A N/A N/A -1% -1.5% -2% -0.75% -1.25% -1.75% +-0.5% +-0.75% 1368—11/24/08 5 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Table 3: IO_Vout select table B9b2 0 0 0 0 1 1 1 1 B9b1 0 0 1 1 0 0 1 1 B9b0 0 1 0 1 0 1 0 1 IO_Vout 0.3V 0.4V 0.5V 0.6V 0.7V 0.8V 0.9V 1.0V Table 4: Device ID table B8b7 B8b6 B8b5 B8b4 Comment 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 56 pin TSSOP 64 pin TSSOP Reserved Reserved Reserved 72 pin QFN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 6 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information General SMBus serial interface information for the ICS9LPRS387 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Not acknowledge stoP bit 1368—11/24/08 7 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Byte 0 FS Readback and PLL Selection Register Bit 7 6 5 Pin - Name FSLC FSLB FSLA 4 - iAMT_EN 3 2 1 - Reserved SRC_Main_SEL SATA_SEL 0 - PD_Restore Description Type CPU Freq. Sel. Bit (Most Significant) R CPU Freq. Sel. Bit R CPU Freq. Sel. Bit (Least Significant) R Set via SMBus or dynamically by CK505 if detects R dynamic M1 Reserved RW Select source for SRC Main RW Select source for SATA clock RW 1 = on Power Down de-assert return to last known state 0 = clear all SMBus configurations as if cold powerRW on and go to latches open state This bit is ignored and treated at '1' if device is in iAMT mode. 0 1 Legacy Mode iAMT Enabled SRC Main = PLL1 SATA = SRC_Main SRC Main = PLL3 SATA = PLL2 Default Latch Latch Latch iAMT power on status 0 0 0 Configuration Not Saved Configuration Saved 1 0 SRC0 Down spread - 1 DOT96 Center spread - See Table 1 : CPU Frequency Select Table Byte 1 DOT96 Select and PLL3 Quick Config Register, Note 1 : When 27_Select pin = 0, B1b7 PWO = 1; When 27_Select pin = 1, PWO = 0 Bit 7 6 5 4 3 2 1 0 Pin 24/25 28/29 Name SRC0_SEL PLL1_SSC_SEL Reserved PLL3_CF3 PLL3_CF2 PLL3_CF1 PLL3_CF0 PCI_SEL Description Select SRC0 or DOT96 Select 0.5% down or center SSC Reserved PLL3 Quick Config Bit 3 PLL3 Quick Config Bit 2 PLL3 Quick Config Bit 1 PLL3 Quick Config Bit 0 PCI_SEL Type RW RW RW RW RW RW RW RW PCI from PLL1 PCI from SRC_MAIN Default Note 1 0 0 0 0 1 0 1 Description Output enable for REF0, if disabled output is tristated Output enable for USB Output enable for PCI5 Output enable for PCI5 Output enable for PCI3 Output enable for PCI2 Output enable for PCI1 Reserved Type 0 1 Default RW Output Disabled Output Enabled 1 RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output Output Output Output Output Enabled Enabled Enabled Enabled Enabled Enabled - 1 1 1 1 1 1 1 Description Output enable for SRC11 Output enable for SRC10 Output enable for SRC9 Output enable for SRC8 or ITP Output enable for SRC7 Output enable for SRC6 Reserved Output enable for SRC4 Type RW RW RW RW RW RW RW RW 1 Enabled Enabled Enabled Enabled Enabled Enabled See Table 2: pin28/29 Configuration Only applies if Byte 0, bit 2 = 0. Byte 2 Output Enable Register Bit Pin Name 7 REF0_OE 6 5 4 3 2 1 0 USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE Reserved Disabled Disabled Disabled Disabled Disabled Disabled - Byte 3 Output Enable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC11_OE SRC10_OE SRC9_OE SRC8/ITP_OE SRC7_OE SRC6_OE Reserved SRC4_OE Output Disabled Output Enabled Default 1 1 1 1 1 1 1 1 0 Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Output Disabled Spread Disabled Spread Disabled 1 Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Output Enabled Spread Enabled Spread Enabled Default 1 1 1 1 1 1 1 1 Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Output Output Output Output Output Output Byte 4 Output Enable and Spread Spectrum Disable Register Bit 7 6 5 4 3 2 1 0 Pin Name SRC3_OE SATA/SRC2_OE SRC1_OE SRC0/DOT96_OE CPU1_OE CPU0_OE PLL1_SSC_ON PLL3_SSC_ON Description Output enable for SRC3 Output enable for SATA/SRC2 Output enable for SRC1 Output enable for SRC0/DOT96 Output enable for CPU1 Output enable for CPU0 Enable PLL1's spread modulation Enable PLL3's spread modulation IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Type RW RW RW RW RW RW RW RW 1368—11/24/08 8 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Byte 5 Clock Request Enable/Configuration Register Bit 7 6 5 4 3 2 1 0 Pin Name CR#_A_EN CR#_A_SEL CR#_3_EN CR#4_EN CR#_6_EN CR#_7_EN CR#_9_EN CR#_10_EN Description Enable CR#_A (clk req) Sets CR#_A to control either SRC0 or SRC2 Enable CR#_3 (clk req) -> SRC3 Enable CR#_4 (clk req) -> SRC4 Enable CR#_6 (clk req) -> SRC6 Enable CR#_7 (clk req) -> SRC7 Enable CR#_9 (clk req) -> SRC9 Enable CR#_10 (clk req) -> SRC10 Type RW RW RW RW RW RW RW RW 0 Disable CR#_A CR#_A -> SRC0 Disable CR#_3 Disable CR#_4 Disable CR#_6 Disable CR#_7 Disable CR#_9 Disable CR#_10 1 Enable CR#_A CR#_A -> SRC2 Enable CR#_3 Enable CR#_4 Enable CR#_6 Enable CR#_7 Enable CR#_9 Enable CR#_10 Default 0 0 0 0 0 0 0 0 Description Enable CR#_11 (clk req) -> SRC11 Slew Rate Control Slew Rate Control Slew Rate Control Slew Rate Control Reserved Type RW RW RW RW RW RW 0 Disable CR#_11 2 V/ns 2 V/ns 2 V/ns 2 V/ns - Default 0 0 0 0 0 0 If set, LCD_SS stops with PCI_STOP# RW Free Running If set, SRCs stop with PCI_STOP# RW Free Running 1 Enable CR#_11 1 V/ns 1 V/ns 1 V/ns 1 V/ns Stops with PCI_STOP# assertion Stops with PCI_STOP# assertion Description Type R R R R R R R R 0 1 Default 0 0 1 1 0 0 0 1 Type R R R R 0 1 Default 0 1 0 1 RW Output Disabled Output Enabled 1 RW RW RW Disabled Disabled Enabled Enabled 0 1 1 0 1 Stops with PCI_STOP# assertion no overclocking Outputs = REF/N Test mode Default Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit 7 6 5 4 3 2 Pin 1 0 Name CR#_11_EN USB48 Slew REF Slew PCI Slew 27MHz Slew Reserved SSCD_STP_CRTL SRC_STP_CRTL 0 0 Byte 7 Vendor ID/ Revision ID Bit 7 6 5 4 3 2 1 0 Pin Name Rev Code Bit Rev Code Bit Rev Code Bit Rev Code Bit Vendor ID bit Vendor ID bit Vendor ID bit Vendor ID bit 3 2 1 0 3 2 1 0 Revision ID Vendor ID ICS is 0001, binary Vendor specific Byte 8 Device ID and Output Enable Register Bit 7 6 5 4 Pin Name Device_ID3 Device_ID2 Device_ID1 Device_ID0 3 REF1_OE 2 1 0 Reserved 27MHz_nonSS/SE1_OE 27MHz_SS/SE2_OE Description Table of Device identifier codes, used for differentiating between CK505 package options, etc. Output enable for REF1, if disabled output is tristated Reserved Output enable for SE1 Output enable for SE2 See Device ID Table Byte 9 Output Control Register Bit Pin Name 7 PCIF5 STOP EN 6 5 4 3 2 1 0 TME_Readback Reserved Test Mode Select Test Mode Entry IO_VOUT2 IO_VOUT1 IO_VOUT0 Description Type Allows control of PCIF5 with assertion of RW PCI_STOP# Truested Mode Enable (TME) strap status R Reserved RW Allows test select, ignores REF/FSC/TestSel RW Allows entry into test mode, ignores FSB/TestMode RW IO Output Voltage Select (Most Significant Bit) RW IO Output Voltage Select RW IO Output Voltage Select (Least Significant Bit) RW IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Free running normal operation Outputs HI-Z Normal operation See Table 3: V_IO Selection (Default is 0.8V) 0 TMD latch 1 0 0 1 0 1 1368—11/24/08 9 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Byte 10 Output Control Register Bit 7 6 5 4 3 2 1 0 Pin Name 27_Select Latch read back PLL3_EN PLL2_EN SRC_DIV_EN PCI_DIV_EN CPU_DIV_EN CPU 1 Stop Enable CPU 0 Stop Enable Description Readback of 27_Select latch PLL3 Enable PLL2 Enable SRC Divider Enable PCI Divider Enable CPU Divider Enable Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP# Type R RW RW RW RW RW RW RW 0 Dot96/ LCD_SS /SE Powered Down Powered Down Disable Disable Disable Free Running Free Running 1 SRC0/ 27MHz Powered Up Powered Up Enable Enable Enable Stoppable Stoppable Default 27_Select latch 1 1 1 1 1 1 1 Description Reserved Reserved Reserved Reserved M1 mode clk enable, only if ITP_EN=1 M1 mode clk enable Determines if PCI-E Gen2 compliant Enables control of CPU 0 with CPU_STOP# Type RW RW RW RW RW RW R RW 0 1 Disable Disable non-Gen2 Free Running Enable Enable PCI-E Gen2 Compliant Stoppable Default 0 0 0 1 0 1 0 1 Description Type RW RW RW RW RW RW RW RW 0 1 Byte 11 Reserved Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved Reserved Reserved CPU2_AMT_EN CPU1_AMT_EN PCI-E_GEN2 CPU 2 Stop Enable Byte 12 Byte Count Register Bit 7 6 5 4 3 2 1 0 Pin Name Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0 Read Back byte count register, max bytes = 32 IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Default 0 0 0 0 1 1 0 1 1368—11/24/08 10 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Test Clarification Table HW Comments Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control SW FSLC/ TEST_SEL HW PIN FSLB/ TEST_MODE HW PIN TEST ENTRY BIT B9b3 REF/N or HI-Z B9b4 <2.0V >2.0V >2.0V >2.0V X 0 0 1 0 X X X 0 0 1 0 OUTPUT NORMAL HI-Z REF/N REF/N >2.0V 1 X 1 REF/N <2.0V X 1 0 HI-Z <2.0V X 1 1 REF/N B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z) IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 11 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MAX UNITS Notes Maximum Supply Voltage VDDxxx Core/Logic Supply MIN 4.6 V 1,7 Maximum Supply Voltage VDDxxx_IO Low Voltage Differential I/O Supply 3.8 V 1,7 Maximum Input Voltage VIH 3.3V LVCMOS Inputs 4.6 V 1,7,8 Minimum Input Voltage VIL Any Input V 1,7 GND - 0.5 Storage Temperature Ts - -65 Input ESD protection ESD prot Human Body Model 2000 150 ° C 1,7 V 1,7 Notes Electrical Characteristics - Input/Supply/Common Output Parameters PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Ambient Operating Temp Tambient - 0 70 °C 1 Supply Voltage VDDxxx Supply Voltage 3.135 3.465 V 1 Supply Voltage VDDxxx_IO Low-Voltage Differential I/O Supply 1 3.465 V 1 Input High Voltage VIHSE Single-ended inputs 2 VDD + 0.3 V 1 Input Low Voltage VILSE Single-ended inputs VSS - 0.3 0.8 V 1 Input Leakage Current IIN -5 5 uA 1 Input Leakage Current IINRES VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND -200 200 uA 1 Output High Voltage VOHSE Single-ended outputs, IOH = -1mA V 1 Output Low Voltage VOLSE Single-ended outputs, IOL = 1 mA Output High Voltage VOHDIF Differential Outputs, IOH = TBD mA Output Low Voltage Low Threshold InputHigh Voltage (Test Mode) Low Threshold InputHigh Voltage Low Threshold InputLow Voltage VOLDIF Differential Outputs, IOL = TBD mA VIH_FS_TEST 3.3 V +/-5% VIH_FS VIL_FS Operating Supply Current 0.4 V 1 0.9 V 1 0.4 V 1 2 VDD + 0.3 V 1 3.3 V +/-5% 0.7 1.5 V 1 3.3 V +/-5% VSS - 0.3 0.35 V 1 0.7 IDD_PLL3DIF 3.3V supply, PLL3 Differential Out 167 mA 1 IDD_PLL3SE 184 mA 1 33 mA 1 IDD_PD3.3 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 27 mA 1 1 IDD_IO Power Down Current 2.4 IDD_PDIO 0.8V IO supply, Power Down Mode 0 mA IDD_iAMT3.3 3.3V supply, iAMT Mode 49 mA 1 IDD_iAMT0.8 0.8V IO supply, iAMTMode 7 mA 1 Input Frequency Fi VDD = 3.3 V 14.318 MHz 2 Pin Inductance Lpin 7 nH 1 5 pF 1 iAMT Mode Current Input Capacitance Spread Spectrum Modulation Frequency CIN Logic Inputs COUT Output pin capacitance 6 pF 1 CINX X1 & X2 pins TBD pF 1 fSSMOD Triangular Modulation 33 kHz 1 IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1.5 30 1368—11/24/08 12 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information AC Electrical Characteristics - Input/Common Parameters PARAMETER SYMBOL Clk Stabilization TSTAB Tdrive_SRC TDRSRC Tdrive_PD# TDRPD Tdrive_CPU TDRSRC Tfall_PD# TFALL Trise_PD# TRISE CONDITIONS From VDD Power-Up or de-assertion of PD# to 1st clock SRC output enable after PCI_STOP# de-assertion Differential output enable after PD# de-assertion CPU output enable after CPU_STOP# de-assertion MIN Fall/rise time of PD#, PCI_STOP# and CPU_STOP# inputs MAX UNITS Notes 1.8 ms 1 15 ns 1 300 us 1 10 ns 1 5 ns 1 5 ns 1 AC Electrical Characteristics - Low Power Differential Outputs PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Rising Edge Slew Rate tSLR Differential Measurement 2.5 8 V/ns 1,2 2.5 Falling Edge Slew Rate tFLR Differential Measurement 8 V/ns 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 20 % 1 Maximum Output Voltage VHIGH Includes overshoot 1150 mV 1 Minimum Output Voltage VLOW Includes undershoot -300 mV 1 Differential Voltage Swing VSWING Differential Measurement 300 mV 1 Crossing Point Voltage VXABS Single-ended Measurement 300 550 mV 1,3,4 Crossing Point Variation VXABSVAR Single-ended Measurement 140 mV 1,3,5 Duty Cycle DCYC Differential Measurement 55 % 1 CPU Jitter - Cycle to Cycle CPUJ C2C Differential Measurement 85 ps 1 SRC Jitter - Cycle to Cycle SRCJ C2C Differential Measurement 125 ps 1 DOT Jitter - Cycle to Cycle DOTJ C2C Differential Measurement 250 ps 1 CPU[1:0] Skew CPUSKEW10 Differential Measurement 100 ps 1 CPU[2_ITP:0] Skew CPUSKEW20 Differential Measurement 150 ps 1 SRC[11:0] Skew SRCSKEW Differential Measurement TBD ps 1 IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 45 1368—11/24/08 13 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Electrical Characteristics - PCICLK/PCICLK_F PARAMETER SYMBOL CONDITIONS MIN MAX UNITS NOTES Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,6 30.00900 ns 6 30.15980 ns 6 30.65980 ns 6 V 1 0.4 V 1 mA 1 -33 mA 1 33.33MHz output nominal Clock period Tperiod Absolute min/max period Tabs 33.33MHz output nominal/spread 29.49100 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V Falling Edge Slew Rate tFLR Duty Cycle Skew Intentional PCI-PCI delay tdelay VT = 1.5 V Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V 33.33MHz output spread V OH @MIN = 1.0 V 29.99100 -33 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V 30 mA 1 38 mA 1 1 4 V/ns 1 Measured from 2.0 to 0.8 V 1 4 V/ns 1 dt1 VT = 1.5 V 45 tskew VT = 1.5 V VOL @ MAX = 0.4 V 55 % 1 250 ps 1 ps 1,9 ps 1 200 nominal 500 Intentional PCI Clock to Clock Delay 200 ps nominal steps PCI_0 PCI_1 PCI_2 PCI_3 PCI_4 PCI_F5 1.0ns Electrical Characteristics - USB48MHz PARAMETER Long Accuracy SYMBOL ppm CONDITIONS see Tperiod min-max values MIN -100 MAX 100 UNITS ppm NOTES 1,2 Clock period T period 48.00MHz output nominal 20.83125 20.83542 ns 2 Absolute min/max period T abs 48.00MHz output nominal 20.48130 21.18540 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH V OH @MIN = 1.0 V 0.4 -29 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V -23 29 V 1 V 1 mA 1 mA 1 mA 1 Output Low Current IOL 27 mA 1 Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 2 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 2 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 Jitter, Cycle to cycle tjcyc-cyc VT = 1.5 V VOL @ MAX = 0.4 V IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 55 % 1 350 ps 1 1368—11/24/08 14 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Electrical Characteristics - SMBus Interface PARAMETER SYMBOL SMBus Voltage VDD CONDITIONS Low-level Output Voltage Current sinking at VOLSMB = 0.4 V SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time Maximum SMBus Operating Frequency VOLSMB @ IPULLUP IPULLUP SMB Data Pin TFI2C (Max VIL - 0.15) to (Min VIH + 0.15) (Min VIH + 0.15) to (Max VIL - 0.15) FSMBUS Block Mode TRI2C MIN MAX UNITS 2.7 5.5 V 1 0.4 V 1 mA 1 1000 ns 1 300 ns 1 100 kHz 1 4 Notes Electrical Characteristics - 27MHz_Spread / 27MHz_NonSpread PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values MIN -15 15 37.0376 Clock period Tperiod 27.000MHz output nominal 37.0365 VOH IOH = -1 mA 2.4 Output Low Voltage VOL IOL = 1 mA Output High Current IOH Output Low Current IOL Edge Rate tslewr/f Rising/Falling edge rate Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle dt1 VT = 1.5 V tltj Long Term (10us) Jitter 1,2 1,2,3 V 1 1 mA 1 -23 mA 1 mA 1 27 mA 1 1 4 V/ns 1 0.5 2 ns 1 0.5 2 ns 1 45 55 % 1 800 ps 1 250 ps 1 500 ps 1 -29 29 -250 VT = 1.5 V tjcyc-cyc *TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7Ω 1 ppm Notes V VOL @ MAX = 0.4 V tjpk-pk UNITS 0.55 VOH@MAX = 3.135 V VOL @ MIN = 1.95 V MAX 50 Output High Voltage V OH @MIN = 1.0 V TYP -50 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 At nominal voltage and temperature IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 15 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Electrical Characteristics - REF-14.318MHz PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Notes Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2 Clock period Tperiod 14.318MHz output nominal 69.8203 69.8622 ns 2 Absolute min/max period T abs 14.318MHz output nominal 69.8203 70.86224 ns 2 Output High Voltage VOH IOH = -1 mA 2.4 V 1 Output Low Voltage VOL IOL = 1 mA 0.4 V 1 Output High Current IOH -33 -33 mA 1 Output Low Current IOL 30 38 mA 1 Rising Edge Slew Rate tSLR Measured from 0.8 to 2.0 V 1 4 V/ns 1 Falling Edge Slew Rate tFLR Measured from 2.0 to 0.8 V 1 4 V/ns 1 Duty Cycle dt1 VT = 1.5 V 45 Jitter tjcyc-cyc VT = 1.5 V VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 55 % 1 1000 ps 1 Notes on Electrical Characteristics: 1 Guaranteed by design and characterization, not 100% tested in production. 2 Slew rate measured through Vswing centered around differential zero 3 Vxabs is defined as the voltage where CLK = CLK# 4 Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 7 Operation under these conditions is neither implied, nor guaranteed. 8 Maximum input voltage is not to exceed maximum VDD 9 See PCI Clock-to-Clock Delay Figure IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 16 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE DIMENSIONS SYMBOL A A1 A3 b e DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. 72L TOLERANCE 72 18 18 10.00 x 10.00 5.75 / 6.15 5.75 / 6.15 0.30/ 0.50 Ordering Information ICS9LPRS387yKLFT Example: ICS XXXX y K LF T Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator Device Type Prefix ICS = Standard Device IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems 1368—11/24/08 17 ICS9LPRS387 Programmable Timing Control Hub for Intel Based Systems Advance Information Revision History Rev. 0.1 0.2 Issue Date 06/27/07 09/13/07 0.3 12/03/07 0.4 0.5 0.6 02/27/08 07/03/08 11/24/08 Description Initial Release 1. Added Intentional PCI Clock Delay Diagram 1. B9b5 is Reserved 2. B10b7 is Read-Only 3. B8b[1:0] = 1 4. Revision ID (Byte 7) = 31h Updted Features/Benefits Updated Clock Period Spec Updated Table 2. IDTTM/ICSTM Programmable Timing Control Hub for Intel Based Systems Page # 14 9, 10 1 5 1368—11/24/08 18