Transcript
®
IDT™ EB-LOGAN-23 Evaluation Board Manual (Evaluation Board: 18-691-001)
February 2011
6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc.
DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed.
LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.
Table of Contents ®
Notes
Description of the EB-LOGAN-23 Evaluation Board Introduction ..................................................................................................................................... 1-1 Board Features ............................................................................................................................... 1-2 Hardware ................................................................................................................................ 1-2 Software.................................................................................................................................. 1-2 Other....................................................................................................................................... 1-2 Revision History .............................................................................................................................. 1-2
Installation of the EB-LOGAN-23 Evaluation Board EB-LOGAN-23 Installation .............................................................................................................. 2-1 PCI Express Mezzanine and Edge Adapters.................................................................................. 2-1 Hardware Description ..................................................................................................................... 2-3 Reference Clocks............................................................................................................................ 2-4 Global Reference Input Clocks ............................................................................................... 2-4 Local Port Input Clocks........................................................................................................... 2-6 CLKMODE Selection ................................................................................................... 2-8 Power Sources ....................................................................................................................... 2-9 PCI Express Analog Power Voltage Regulator..................................................................... 2-10 PCI Express Digital Power Voltage Converter...................................................................... 2-10 PCI Express Transmitter Analog Voltage Converter ............................................................ 2-10 Core Logic Voltage Converter .............................................................................................. 2-10 3.3V I/O Voltage Regulator................................................................................................... 2-10 Power-up Sequence for PES32NT24AG2............................................................................ 2-10 Heatsink Requirement .................................................................................................................. 2-10 Reset............................................................................................................................................. 2-10 Fundamental Reset .............................................................................................................. 2-10 Downstream Reset ...............................................................................................................2-11 Stack Configuration .............................................................................................................. 2-11 Boot Configuration Vector............................................................................................................. 2-11 SMBus Interfaces.......................................................................................................................... 2-12 SMBus Slave Interface ......................................................................................................... 2-12 SMBus Master Interface ....................................................................................................... 2-13 JTAG Header ................................................................................................................................ 2-13 Miscellaneous Jumpers, Headers................................................................................................. 2-14 LEDs ............................................................................................................................................. 2-15 EB-LOGAN-23 Board Figure ........................................................................................................ 2-23
Software For EB-LOGAN-23 Introduction ..................................................................................................................................... 3-1 Device Management Software........................................................................................................ 3-1 Device Drivers................................................................................................................................. 3-1
Schematics Schematics ..................................................................................................................................... 4-1
EB-LOGAN-23 Evaluation Board
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IDT Table of Contents
Notes
EB-LOGAN-23 Evaluation Board
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List of Figures ®
Notes
Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 Figure 2.10 Figure 2.11
EB-LOGAN-23 Evaluation Board
Function Block Diagram of the EB-LOGAN-23 Evaluation Board ......................................1-1 Bifurcated and Merged Mezzanine Cards ..........................................................................2-1 MiniSAS Mezzanine Adapter ............................................................................................2-2 EB-LOGAN-23 iSAS-to-SATA Breakout Cable ..................................................................2-2 EB-LOGAN-23 iSAS-to-iSAS Cable ..................................................................................2-2 PCIe x4 Edge-to-SATA Adapter ........................................................................................2-3 PCIe x8 Edge-to-SAS Adapter ...........................................................................................2-3 EB-LOGAN-23 Evaluation Main Board ..............................................................................2-4 12-PACK PCIe Slots Breakout Board ................................................................................2-4 Differential Jumper Arrangement Example ........................................................................2-5 Reference Clock Configuration ..........................................................................................2-5 EB32NT24AG2 Evaluation Board ....................................................................................2-23
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IDT List of Figures
Notes
EB-LOGAN-23 Evaluation Board
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List of Tables ®
Notes
Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 Table 2.18 Table 2.19 Table 2.20
EB-LOGAN-23 Global Clock Select .................................................................................... 2-5 Clock Buffer Input Sources ................................................................................................. 2-6 Global Reference Input Clock Frequency Select ................................................................ 2-6 Onboard Clock Generator Frequency Select ......................................................................2-6 Onboard Reference Clock Generator Access Points ......................................................... 2-6 EB-LOGAN-23 Port (0, 2, 4, 6, 12, 20) Clock Select .......................................................... 2-7 EB-LOGAN-23 Port 8 Clock Source Select ........................................................................ 2-7 EB-LOGAN-23 Port 16 Clock Source Select ......................................................................2-7 EB-LOGAN-23 Slot Clock Select ........................................................................................ 2-8 CLKMODE Selection for the PES32NT24AG2 ................................................................... 2-9 EPS12V 24-pin Power Connector - J69 ............................................................................. 2-9 EPS12V 8-Pin Connector - J68 .......................................................................................... 2-9 Ports in Each Stack .......................................................................................................... 2-11 Boot Configuration Vector Signals .................................................................................... 2-11 Boot Configuration Vector Switch SW10 .......................................................................... 2-12 Slave SMBus Interface Connector .................................................................................... 2-12 SMBus Slave Interface Address Configuration ................................................................. 2-13 JTAG Connector Pin Out .................................................................................................. 2-13 Miscellaneous Jumpers, Headers ..................................................................................... 2-14 LED Indicators .................................................................................................................. 2-15
VB64H16AG2 Validation Board Manual
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IDT List of Tables
Notes
VB64H16AG2 Validation Board Manual
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Chapter 1
Description of the EB-LOGAN-23 Evaluation Board ®
Notes
Introduction The 89H32NT24AG2 switch (also referred to as PES32NT24AG2 in this manual) is a member of the IDT PCI Express® Inter-Domain Switch family of products. It is a PCIe® Base Specification 2.1 compliant (Gen2) 32-lane, 24-port switch. The EB-LOGAN-23 Evaluation Board provides an evaluation platform for both the PES32NT24AG2 and PES32NT24BG2 switches and for several other members of this switch family including PES24NT24AG2, PES32NT8AG2, and PES24NT6AG2 . Detailed information related to configuration of number of ports and lanes in the switch device can be found in the Device User Manual and the Device Data Sheet. The evaluation board, along with additional adapters and daughter boards provide by IDT, can be configured to test every possible combination of the number of lanes and ports offered by the switch. Advanced capabilities such as switch partitioning, NTB, DMA, and local port clocking can be evaluated with the evaluation board. The EB-LOGAN-23 brings out all 32 lanes of the device to 4 Mezzanine connectors (see Figure 1.1) located close to the device — one connector per stack of 8 lanes. Various types of daughter cards (provided by IDT) can then be plugged into these connectors to facilitate connectivity to one x8 or two x4 or four x2 or eight x1 link partners. Link partners may be plugged directly into these daughter cards, or they can be connected to these daughter cards via SAS or SATA cables and a different board with PCIe slots known as the 12-PACK board (provided by IDT). Given that the majority of the hosts/servers offer PCIe standard slots, IDT provides the necessary adapter cards that may be plugged into these host/server slots as well as the cables that connect such adapters to the daughter cards, which in turn are plugged into the main evaluation board on which the IDT PCIe switch device is populated. The EB-LOGAN-23 is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EBLOGAN-23 board.
Figure 1.1 Function Block Diagram of the EB-LOGAN-23 Evaluation Board
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IDT Description of the EB-LOGAN-23 Evaluation Board
Notes
Board Features Hardware 32NT24AG2 PCIe 24-port switch – Twenty four ports (8 x2 and 16 x1) — adjacent ports may be combined to create x4 or x8 ports – PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S) – Up to 2048 byte maximum Payload Size – Automatic lane reversal and polarity inversion supported on all lanes – Automatic per port link width negotiation to x8, x4, x2, x1 – Power on reconfiguration via optional serial EEPROM connected to the SMBUS Master interface Upstream, Downstream Ports – The EB-LOGAN-23 has a minimum of one port configured as an upstream port to be plugged into a host slot through an adaptor and a cable. – Up to 23 ports can be configured as downstream ports, for PCIe endpoint add-on cards to be plugged in. The slot connectors can be configured to be x1, x2, x4, or x8, but are mechanically open-ended on one side to allow card widths greater than x8 (e.g. x16) to be populated. – When used in multi-partition mode, the device can be programmed through the serial EEPROM to generate the appropriate number of upstream and downstream ports per partition. Numerous user selectable configurations set using onboard jumpers and DIP-switches – Source of clock - host clock or onboard clock generator – Two clock rates (100/125 MHz) from an onboard clock generator – Flexible clocking modes • Common clock • Non-common clock • Local port clocking on ports that support this feature – Boot mode selection SMBUS Slave Interface (4 pin header) SMBUS Master Interface connected to the Serial EEPROMs and I/O Expanders Push button for Warm Reset Many LEDs to display status, reset, power, hot-plug, etc. JTAG connector to the 32NT24AG2 JTAG pins. Software There is no software or firmware executed on the board. However, useful software is provided along with the Evaluation Board to facilitate configuration and evaluation of the 32NT24AG2 within host systems running popular operating systems. Installation programs – Operating Systems Supported: WindowsServer200x, WindowsXP, Vista, Linux GUI based application for Windows and Linux
– Allows users to view and modify registers in the 32NT24AG2 – Binary file generator for programming the serial EEPROMs attached to the SMBUS. Other SMBUS cable/dongle may be required for certain evaluation exercises.
SMA/SATA connectors are provided on the EB-LOGAN-23 board for clock outputs.
Revision History March 15, 2010: Initial publication of evaluation board manual. April 23, 2010: Updated Schematics in Chapter 4. 89EB-LOGAN-23 Evaluation Board
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August 11, 2010: Updated the manual for Rev. 2.0 board. February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4.
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Chapter 2
Installation of the EB-LOGAN-23 Evaluation Board
®
Notes
EB-LOGAN-23 Installation This chapter discusses the steps required to configure and install the EB-LOGAN-23 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1.
Configure jumper/switch options suitable for the evaluation or application requirements.
2.
Connect PCI Express endpoint cards to the downstream port PCIe slots on the daughter cards plugged into the evaluation board. Daughter cards are provided by IDT. In some cases the 12-PACK board will be required as well (specifically when more ports than those supported by the main board are required).
3.
Make sure that the host system (e.g. server with root complex chipset) is powered off.
4.
Connect the evaluation board to the host system via the adapter card and cable provided by IDT.
5.
Apply power to the host system and to the IDT board.
The EB-LOGAN-23 board is typically shipped with all jumpers and switches configured to their default settings which will satisfy the initial needs of the majority of the users. In most cases, the board does not require further modification or setup. However, please visit the IDT website and fill out the Technical Support Request form at http://www.idt.com/?app=TechSupport for other configurations.
PCI Express Mezzanine and Edge Adapters The PCI Express lanes are broken out to four Mezzanine connectors on the EB-LOGAN-23 Evaluation Board. The adapter cards are used to convert Mezzanine connectors into PCI Express slot connector(s) or Internal mini SAS (iSAS) connectors or both. A Bifurcated Mezzanine Card has two mechanical x8 PCIe Slots (x4 electrically) while a Merged Mezzanine Card has single x8 PCIe Slot. Pictured in Figure 2.1.
Figure 2.1 Bifurcated and Merged Mezzanine Cards 89EB-LOGAN-23 Evaluation Board
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Notes
Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATA connectors. Each iSAS connector supports up to two PCI Express x4 width and the SATA connectors are used for clock and reset signals of each x4 or less stack/port. An iSAS-to-SATA breakout cable shown in Figure 2.3 is used connect from iSAS to edge adapter and/or 12PACK. An iSAS-to-iSAS cable shown in Figure 2.4 is used to connect from iSAS to x8 edge adapter.
Figure 2.2 MiniSAS Mezzanine Adapter
SAS (x4) – four SATA (x1) breakout cable
Figure 2.3 EB-LOGAN-23 iSAS-to-SATA Breakout Cable
SAS (x4) –SAS (x4) cable
Figure 2.4 EB-LOGAN-23 iSAS-to-iSAS Cable
The PCI Express Edge to SATA Adapter, pictured in Figure 2.5 and Figure 2.6, can be inserted into any physical PCIe slot on a host system and in combination with mini-SAS Mezzanine Card, such as the one in Figure 2.2, to form a link between evaluation main board and the host system. There are 5 SATA connec89EB-LOGAN-23 Evaluation Board
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Notes
tors: one connector is for clock and reset, and the remainder support one PICe lane per SATA connector. The PCI Express Edge to SAS Adapter shown in Figure 2.6 is similar to the SATA adapter in that it supports up to a x8 width using two SAS cables. The edge adapters can be inserted into a mechanical x4/x8 or greater slot and supports x1, x2, x4, and x8 widths.
Figure 2.5 PCIe x4 Edge-to-SATA Adapter
Figure 2.6 PCIe x8 Edge-to-SAS Adapter
Hardware Description The PES32NT24AG2 is a 32-lane, 24-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides fan-out and switching functions between a PCI Express upstream port and downstream ports or peer-to-peer switching between downstream ports. Furthermore, up to eight ports can be configured as NTB ports for multi-root applications. The device offers additional features such as DMA and local port clocking support (a feature required for enabling multiple spread spectrum clocks in the system). The EB-LOGAN-23 Main Board, shown in Figure 2.7, supports up to 6 PCI Express downstream ports and up to 23 ports when using two 12-PACK Boards. Basic requirements for the board function are: – Host system with a PCI Express root complex supporting x8 configuration through a PCI Express x8 slot. (If your host system does not offer a x8 slot, please contact
[email protected] for alternative solutions.) – – x1, x2, x4, or x8 PCI Express Endpoint Cards. 89EB-LOGAN-23 Evaluation Board
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Notes
Mezzanine tox8 one x8 Mezz to one slot connectors
DUT on bottom side
Mezzanine Mezz to two to x4 two x4 slot connectors
Mezzanine to two x4 iSA connectors
Figure 2.7 EB-LOGAN-23 Evaluation Main Board
8-P IN EPS 12V
24-PIN ATX
+3.3
+12
+12
SMA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
clk[0:11]
SATA
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CL K
CLK
CLK
CL K
CLK
1:12 Buffer
On-Board Clock Gen
SATA S A T A
S A T A S A T A
x2 Data
S L O T 1 1
S A T A S A T A S A T A
S A T A
S A T A
S L O T 1 0
x4 Data
S A T A
S L O T
S A T A S A T A
x2 Data
S A T A S A T A
S A T A
8
9 S A T A
S L O T
S A T A
x8 Data
S L O T
S A T A S A T A
7 S A T A
S A T A
S A T A
S A T A
x2 Data
S L O T
S A T A
6 S A T A
x4 Data
S L O T
S A T A S A T A
S A T A
S L O T
S A T A
x2 Data
S A T A S A T A
S A T A
S A T A
S A T A
4
5 S A T A
x8 Data
S A T A
S A T A
S L O T
S A T A S A T A
3
x2 Data
S L O T
S A T A
2 S A T A
x4 Data
S L O T
S A T A S A T A
1 S A T A
x2 Data
S A T A
S L O T
S A T A S A T A
0 S A T A
S A T A
x8 Data
Figure 2.8 12-PACK PCIe Slots Breakout Board
Reference Clocks Global Reference Input Clocks The PES32NT24AG2 requires two differential reference clocks. The EB-LOGAN-23 derives these clocks from SMA connectors (J17/J20, J66/J67), clock buffer (U51) with on board clock generator (U49), SMA (J5/J7) or SATA (J8) connectors via jumpers (J6) as described in Table 2.2, or SATA connectors (J21, J22) as described in Table 2.1 and Figures 2.9 and 2.10. Both reference clocks are mandatory and must come from the same reference clock source. The switch will not function normally if only one clock is used.
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Notes Global Clock#
Jumper
GCLK0
J18
[1-3 / 2-4] SMA (J66/J67) [5-7 /6-8] From Clock Buffer U51 (default) [7-9 / 8-10] SATA, J21
GCLK1
J19
[1-3 / 2-4] SMA (J17/J20) [5-7 /6-8] From Clock Buffer U51 (default) [7-9 / 8-10] SATA, J22
Selection
Table 2.1 EB-LOGAN-23 Global Clock Select
1
2
3
4
5
6
7
8
9
10
COM
IOA IOB
CONNECTION IOA <-> COM IOB <-> COM IOC <-> COM IOD <-> COM
IOC
JMP1 1-3 3-5 7-9 9-11
JMP2 2-4 4-6 8-10 10-13
Figure 2.9 Differential Jumper Arrangement Example
sata
sata sata
gclkN gclkN
gclk0
gclk0 gclk1
gclkN gclkN
sata
1:12 Buffer
sma
gclkN gclkN
sata
sata gclkN gclkN
sata
sata
sma
sma
sata
Slot/PC 46
Slot/PC 02
gck0
gclk[2:11]
sata
1:12
On-Board Clock Gen
DUT
sma
sata
gclk1
gclkN gclkN
gclkN gclkN
gclkN gclkN
sata
sata
sata
sata
Slot/PC 1620
sata
gclkN gckN
sata
sata
sata
sata
gck1
Slot/PC 0812
Figure 2.10 Reference Clock Configuration
By default, the clock buffer derives its clock from a common source. The common source can be the host system reference clock via a SATA connector, the onboard clock generator, or SMA connectors. See Table 2.2. 89EB-LOGAN-23 Evaluation Board
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Notes
. Jumper
Selection
J6
[1-3 / 2-4] SMA (J5/J7) [5-7 / 6-8] Onboard Clock Generator (U49) [7-9 / 8-10] SATA (J8) (default) Table 2.2 Clock Buffer Input Sources
The frequency of the global reference clock input may be either 100 MHz or 125 MHz, as shown in Table 2.3, and is selected by the Clock Frequency Select (GCLKFEL) pin.
Global Clock Frequency Switch - SW10[2] SW10[2]
Clock Frequency
ON
100 MHz (Default)
OFF
125 MHz
Table 2.3 Global Reference Input Clock Frequency Select
The source for the onboard clock is the ICS841484 clock generator device (U49) connected to a 25MHz oscillator (X1). When using the onboard clock generator, the output frequency can be selected using ICS_FS (SW10, bit 1). The default setting is ON. See Table 2.4.
Onboard Clock Frequency Switch - SW10[1] SW10[1]
Clock Frequency
ON
100 MHz (Default)
OFF
125 MHz
Table 2.4 Onboard Clock Generator Frequency Select
The output of the onboard clock generator is accessible through SMA or SATA connectors. See Table 2.5. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source.
Onboard Reference Clock Output (Differential) TP119
Positive Reference Clock (SMA)
TP120
Negative Reference Clock (SMA)
J121
Differential Reference Clock (SATA) Table 2.5 Onboard Reference Clock Generator Access Points
Local Port Input Clocks Associated with some ports is a local port reference clock input (PxCLK). Depending on the port clocking mode, a differential reference clock can be driven into the device on the corresponding PxCLKP and PxCLKN pins. The frequency of a port reference clock input MUST always at 100 MHz. Table 2.6 lists the possible sources for the port reference clock input, and Table 2.9 lists the possible sources for the slot clock input. Additional information on port clocking usage and configuration can be found in the Device User Manuals and in IDT’s Application Note AN-715.
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Notes
Port # Header
Selection
0
J9
[1-3 / 2-4] Onboard Clock Generator (U116) [3-5 / 4-6] SATA (J58)
2
J10
[1-3 / 2-4] Onboard Clock Generator (U122) [3-5 / 4-6] SATA (J59)
4
J11
[1-3 / 2-4] Onboard Clock Generator (U123) [3-5 / 4-6] SATA (J60)
6
J12
[1-3 / 2-4] Onboard Clock Generator (U117) [3-5 / 4-6] SATA (J61)
12
J14
[1-3 / 2-4] Onboard Clock Generator (U119) [3-5 / 4-6] SATA (J63)
20
J16
[1-3 / 2-4] Onboard Clock Generator (U121) [3-5 / 4-6] SATA (J65)
Table 2.6 EB-LOGAN-23 Port (0, 2, 4, 6, 12, 20) Clock Select
Local port clock sources for ports 8 and 16 are selected by DIP switch (S17 and S19) via a clock mux/ buffer. See Tables 2.7 and 2.8.
Port 8 Clock Source Select - S19[1] S19[1]
Clock Source
OFF
SATA J62
ON
Port 8 Clock Generator (U118)
Table 2.7 EB-LOGAN-23 Port 8 Clock Source Select
Port 16 Clock Source Select - S17[1] S17[1]
Clock Source
OFF
SATA J64
ON
Port 16 Clock Generator (U120)
Table 2.8 EB-LOGAN-23 Port 16 Clock Source Select
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Notes Slot # Jumper
Selection
0
J23
[1-3 / 2-4] Onboard Clock Generator (U115) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18) [9-11 / 10-12] SATA (J27)
2
J24
[1-3 / 2-4] Onboard Clock Generator (U122) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18) [9-11 / 10-12] SATA (J28)
4
J25
[1-3 / 2-4] Onboard Clock Generator (U123) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18) [9-11 / 10-12] SATA (J29)
6
J26
[1-3 / 2-4] Onboard Clock Generator (U117) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J30)
8
J31
[1-3 / 2-4] Onboard Clock Generator (U118) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J31)
12
J32
[1-3 / 2-4] Onboard Clock Generator (U119) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J32)
16
J33
[1-3 / 2-4] Onboard Clock Generator (U120) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P08CLK Clock Mux (U18) [9-11 / 10-12] SATA (J33)
20
J34
[1-3 / 2-4] Onboard Clock Generator (U121) [3-5 / 4-6] Clock Buffer (U51) [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J34) Table 2.9 EB-LOGAN-23 Slot Clock Select
CLKMODE Selection All ports in the PES32NT24AG2 device (upstream and downstream) use global clocked mode by default. The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot configuration vector as shown in Table 2.10. This field determines the initial value of the Slot Clock Configuration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the advertisement of whether or not the port uses the same reference clock source as the link partner. A one in the SCLK field indicates that the port and its link partner use the same reference clock source. This is defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field indicates that the port and its link partner do not use the same reference clock source.
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Notes SW10[8] CLKMODE[0]
SW10[7] CLKMODE[1]
Port 0 SCLK
Port[15:1] SCLK
ON
ON
0
0
OFF
ON
1
0
ON
OFF
0
1
OFF
OFF
1
1
Table 2.10 CLKMODE Selection for the PES32NT24AG2
Power Sources Power for the PES32NT24AG2 and all downstream ports is generated from a 12V supply via an external power connector. See Table 2.11. A 12V to 3.3V DC-DC converter is used to provide power to five switching regulators to generate VDDCORE, VDDPEA, VDDPETA, VDDPEHA, and VDDIO voltages. The 3.3V from the DC-DC converter will be used to power the clock buffers and circuitries. The external power supply connectors are 24-pin (J69) and 8-pin (J68) molex connectors as described in Tables 2.11 and 2.12. The +12V3 is used to power the PES32NT24AG2 and downstream slots 0, 2, 16, and 20. The +12V2 is used to power downstream slots 4, 6, 8, and 12.
Pin
Signal
Pin
Signal
1
+3.3V
13
+3.3V
2
+3.3V
14
-12V
3
GND
15
GND
4
+5V
16
PS_ON
5
GND
17
GND
6
+5V
18
GND
7
GND
19
GND
8
PWR_OK
20
NC
9
5VSB
21
+5V
10
+12V3
22
+5V
11
+12V3
23
+5V
12
+3.3V
24
GND
Table 2.11 EPS12V 24-pin Power Connector - J69
Pin
Signal
Pin
Signal
1
GND
5
+12V1
2
GND
6
+12V1
3
GND
7
+12V2
4
GND
8
+12V2
Table 2.12 EPS12V 8-Pin Connector - J68
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
The power switch located at S1 can be used to control the supply power from the external power supply connector. Add a shunt to W27 to enable power on switch. PCI Express Analog Power Voltage Regulator A voltage regulator (U65) provides a 2.5V PCI Express analog power voltage (shown as VDDPEHA) to the PES32NT24AG2. PCI Express Digital Power Voltage Converter A separate voltage regulator (U62) provides a 1.0V PCI Express analog power voltage (shown as VDDPEA) to the PES32NT24AG2. PCI Express Transmitter Analog Voltage Converter A separate voltage regulator (U68) provides a 1.0V PCI Express transmitter analog voltage (shown as VDDPETA) to the PES32NT24AG2. Core Logic Voltage Converter A separate voltage regulator (U59) provides the 1.0V core voltage (VDDCORE) to the PES32NT24AG2. 3.3V I/O Voltage Regulator A separate voltage regulator (U56) provides the 3.3V I/O voltage (VDDIO) to the PES32NT24AG2. Power-up Sequence for PES32NT24AG2 During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There are no other power-up sequence requirements for the various operating supply voltages.
Heatsink Requirement The EB-LOGAN-23 evaluation board utilizes a heatsink with integrated fan. All initial shipments of the board are made with the heatsink whether or not one is truly required. There may be low link usage applications within which the heatsink may, in fact, not be required.
Reset The PES32NT24AG2 supports two types of reset mechanisms as described in the PCI Express specification: –
Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree through a single side-band signal PERST# which is connected to the Root Complex, the PES32NT24AG2, and the endpoints. – Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to another. Hot Reset may be initiated by software. This is further discussed in the PES32NT24xG2 User Manual. The EB-LOGAN-23 evaluation board provides seamless support for Hot Reset. Fundamental Reset There are two types of Fundamental Resets which may occur on the EB-LOGAN-23 evaluation board: – Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES32NT24AG2. – Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be initiated by two methods: • Pressing a push-button switch (S3) located on EB-LOGAN-23 board • The host system board IO Controller Hub asserting PERST# signal, which propagates through the PCIe upstream edge connector of the EB-LOGAN-23. Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES32NT24AG2 while power is on.
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Downstream Reset Single Partition Mode without Hot Plug: When the evaluation board initially powers on, it assumes the following:
The switch is configured in single partition mode.
Slot 0 is the root port and controls the downstream port resets.
Ports 1-23 are downstream ports.
Hot Plug is disabled.
The following behavior should be observed:
The resets to slots 1-23 should initially be asserted and remain this way until after the fundamental reset is initially de-asserted.
The assertion of slot 0 reset should propagate to slots 1-23.
Stack Configuration The PES32NT24AG2 contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and Stack 3. Stacks 0 and 1 have four x2 ports each, and stacks 2 and 3 have eight x1 ports each. This provides a total of 24 ports in the device labeled port 0 through port 23. Table 2.13 lists the ports associated with each stack.
Stack
Ports Associated with the Stack
Stack 0
0, 1, 2, 3
Stack 1
4, 5, 6, 7
Stack 2
8, 9, 10, 11, 12, 13, 14, 15
Stack 3
16, 17, 18, 19, 20, 21, 22, 23 Table 2.13 Ports in Each Stack
Boot Configuration Vector A boot configuration vector consisting of the signals listed in Table 2.14 is sampled by the PES32NT24AG2 during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S5, SW8, SW9, and SW10 as defined in Table 2.15.
Signal GCLKFSEL
Description Global Clock Frequency Select. This pin specifies the frequency of the GCLKP and GCLKN signals. Default: low
CLKMODE[1:0]
Clock Mode. These pins specify the clocking mode used by switch ports. See Table 2.10 for a definition of the encoding of these signals. The value of these signals may be overridden by modifying the Port Clocking Mode (PCLKMODE) register.
RSTHALT
Reset Halt. When this pin is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the quasi-reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. Refer to section Switch Fundamental Reset on page 3-2 for further details. Default: low
SSMBADDR[2:1]
Slave SMBus Address. SMBus address of the switch on the slave SMBus. Default: 0x3 Table 2.14 Boot Configuration Vector Signals (Part 1 of 2)
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Signal
Description
SWMODE[3:0]
Switch Mode. These pins specify the switch operating mode.
STK0CFG[1:0]
Stack 0 Configuration. These pins select the configuration of stack 0 during a switch fundamental reset.
STK1CFG[1:0]
Stack 1 Configuration. These pins select the configuration of stack 1 during a switch fundamental reset.
STK2CFG[4:0]
Stack 2 Configuration. These pins select the configuration of stack 2 during a switch fundamental reset.
STK3CFG[4:0]
Stack 3 Configuration. These pins select the configuration of stack 3 during a switch fundamental reset. Table 2.14 Boot Configuration Vector Signals (Part 2 of 2)
Location
Signal
Default
SW10[2]
GCLKFSEL
ON
SW10[4]
RSTHALT
ON
SW10[5]
SSMBADDR[2]
OFF
SW10[6]
SSMBADDR[1]
OFF
Table 2.15 Boot Configuration Vector Switch SW10
SMBus Interfaces The System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system. The SMBus interface consists of an SMBus clock pin and an SMBus data pin. The PES32NT24AG2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers. The Master SMBus interface provides a connection to the external serial EEPROM used for initialization and the I/O expanders used for hot-plug signals. SMBus Slave Interface On the PES32NT24AG2 board, the slave SMBus interface is accessible through a 4-pin header as described in Table 2.16. . Slave SMBus Interface Connector J71 Pin
Signal
1
SDA
2
GND
3
SCL
4
NC
Table 2.16 Slave SMBus Interface Connector
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Notes
For a fixed address, the SMBus address of the PES32NT24AG2 slave interface is 0b1110111 by default and is configurable using DIP Switches SW10[5] and SW10[6] as described in Table 2.17.
Slave Interface Address Configuration Address Bit
Signal
1
SSMBUSADDR[1]
2
SSMBUSADDR[2]
3
1
4
0
5
1
6
1
7
1
Table 2.17 SMBus Slave Interface Address Configuration
The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions: – Byte and Word Write/Read – Block Write/Read SMBus Master Interface Connected to the master SMBus interface are twenty-two 16-bit I/O Expanders (MAX7311AUG) and a serial EEPROM, U77 (24LC512). The I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B). The lower three bits of the bus address for the I/O Expander 0 through 20 are fixed through the stuffing resistor as 0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x50, 0x52, x54, 0x56, 0x58, 0x5A, 0x5C, 0x5E, 0xB0, 0xA2, 0xA4, 0xA6, 0xA8, and 0xAA, respectively. Note: Hot-plug is not implemented when the PES32NT24AG2 is installed. The seven bits address for the selected EEPROM device is fixed at 0b1010_000 by default.
JTAG Header The PES32NT24AG2 provides a JTAG connector J73 for access to the PES32NT24AG2 JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 14-pin connector. Refer to Table 2.18 for the JTAG Connector J73 pin out. JTAG Connector J5 Pin
Signal
Direction
Pin
Signal
Direction
1
/TRST - Test reset
Input
2
GND
—
3
TDI - Test data
Input
4
GND
—
5
TDO - Test data
Output
6
GND
—
7
TMS - Test mode select
Input
8
GND
—
9
TCK - Test clock
Input
10
GND
—
11
3.3V
12
N/C
—
13
GND
14
3.3V
—
Table 2.18 JTAG Connector Pin Out 89EB-LOGAN-23 Evaluation Board
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Notes
Miscellaneous Jumpers, Headers Miscellaneous Jumpers, Headers Ref. Designator
Type
Default
W1
Header
1-2 Shunted
W5
Header
Shunted
2-3: Slot 0, 3.3Vaux source from Direct Power (Default) 1-2: Slot 0, 3.3Vaux source from hot-plug controller
W6
Header
2-3 Shunted
2-3: Slot 2, 3.3Vaux source from Direct Power (Default) 1-2: Slot 2, 3.3Vaux source from hot-plug controller
W11
Header
2-3 Shunted
2-3: Slot 4, 3.3Vaux source from Direct Power (Default) 1-2: Slot 4, 3.3Vaux source from hot-plug controller
W12
Header
2-3 Shunted
2-3: Slot 6, 3.3Vaux source from Direct Power (Default) 1-2: Slot 6, 3.3Vaux source from hot-plug controller
W17
Header
2-3 Shunted
2-3: Slot 8, 3.3Vaux source from Direct Power (Default) 1-2: Slot 8, 3.3Vaux source from hot-plug controller
W18
Header
2-3 Shunted
2-3: Slot 12, 3.3Vaux source from Direct Power (Default) 1-2: Slot 12, 3.3Vaux source from hot-plug controller
W23
Header
2-3 Shunted
2-3: Slot 16, 3.3Vaux source from Direct Power (Default) 1-2: Slot 16, 3.3Vaux source from hot-plug controller
W24
Header
2-3 Shunted
2-3: Slot 20, 3.3Vaux source from Direct Power (Default) 1-2: Slot 20, 3.3Vaux source from hot-plug controller
W4
Header
2-3 Shunted
2-3: Slot 0, +12V source from Direct Power (Default) 1-2: Slot 0, +12V source from hot-plug controller
W8
Header
2-3 Shunted
2-3: Slot 2, +12V source base on W57(Default) 1-2: Slot 2, +12V source from hot-plug controller
W10
Header
2-3 Shunted
2-3: Slot 4, +12V source from Direct Power (Default) 1-2: Slot 4, +12V source from hot-plug controller
W14
Header
2-3 Shunted
2-3: Slot 6, +12V source from Direct Power (Default) 1-2: Slot 6, +12V source from hot-plug controller
W16
Header
2-3 Shunted
2-3: Slot 8, +12V source from Direct Power (Default) 1-2: Slot 8, +12V source from hot-plug controller
W20
Header
2-3 Shunted
2-3: Slot 12, +12V source from Direct Power (Default) 1-2: Slot 12, +12V source from hot-plug controller
W22
Header
2-3 Shunted
2-3: Slot 16, +12V source from Direct Power (Default) 1-2: Slot 16, +12V source from hot-plug controller
W26
Header
2-3 Shunted
2-3: Slot 20, +12V source from Direct Power (Default) 1-2: Slot 20, +12V source from hot-plug controller
W3
Header
2-3 Shunted
2-3: Slot 0, +3.3V source from Direct Power (Default) 1-2: Slot 0, +3.3V source from hot-plug controller
W7
Header
2-3 Shunted
2-3: Slot 2, +3.3V source from Direct Power (Default) 1-2: Slot 2, +3.3V source from hot-plug controller
W9
Header
2-3 Shunted
2-3: Slot 4, +3.3V source from Direct Power (Default) 1-2: Slot 4, +3.3V source from hot-plug controller
Description 1-2: GPIO 8 to DS414 when ALT1 (Default) 2-3: GPIO 8 to IO Expander Interrupt when ALT0
Table 2.19 Miscellaneous Jumpers, Headers (Part 1 of 2) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Miscellaneous Jumpers, Headers Ref. Designator
Type
Default
W13
Header
2-3 Shunted
2-3: Slot 6, +3.3V source from Direct Power (Default) 1-2: Slot 6, +3.3V source from hot-plug controller
W15
Header
2-3 Shunted
2-3: Slot 8, +3.3V source from Direct Power (Default) 1-2: Slot 8, +3.3V source from hot-plug controller
W19
Header
2-3 Shunted
2-3: Slot 12, +3.3V source from Direct Power (Default) 1-2: Slot 12, +3.3V source from hot-plug controller
W21
Header
2-3 Shunted
2-3: Slot 16, +3.3V source from Direct Power (Default) 1-2: Slot 16, +3.3V source from hot-plug controller
W25
Header
2-3 Shunted
2-3: Slot 20, +3.3V source from Direct Power (Default) 1-2: Slot 20, +3.3V source from hot-plug controller
Description
Table 2.19 Miscellaneous Jumpers, Headers (Part 2 of 2)
LEDs There are many LED indicators on the EB-LOGAN-23 which convey status feedback. A description of each is provided in Table 2.20.
Location
Color
Definition
DS1
Green
Board Power Indicator (5V)
DS2
Green
Board Power Indicator (3.3V)
DS4
Green
VDDIO Indicator (3.3V)
DS158
Orange
Port23: Attention Push Button Input
DS159
Orange
Port22: Attention Push Button Input
DS160
Orange
Port21: Attention Push Button Input
DS161
Orange
Port20: Attention Push Button Input
DS162
Orange
Port19: Attention Push Button Input
DS163
Orange
Port18: Attention Push Button Input
DS164
Orange
Port17: Attention Push Button Input
DS165
Orange
Port16: Attention Push Button Input
DS166
Orange
Port15: Attention Push Button Input
DS167
Orange
Port14: Attention Push Button Input
DS168
Orange
Port13: Attention Push Button Input
DS169
Orange
Port12: Attention Push Button Input
DS170
Orange
Port11: Attention Push Button Input
DS171
Orange
Port10: Attention Push Button Input
DS172
Orange
Port9: Attention Push Button Input
DS173
Orange
Port8: Attention Push Button Input
Table 2.20 LED Indicators (Part 1 of 8) 89EB-LOGAN-23 Evaluation Board
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Notes
Location
Color
Definition
DS174
Orange
Port7: Attention Push Button Input
DS175
Orange
Port6: Attention Push Button Input
DS176
Orange
Port5: Attention Push Button Input
DS177
Orange
Port4: Attention Push Button Input
DS178
Orange
Port3: Attention Push Button Input
DS179
Orange
Port2: Attention Push Button Input
DS180
Orange
Port1: Attention Push Button Input
DS181
Orange
Port0: Attention Push Button Input
DS182
Yellow
Port23: Presence Detect Input
DS183
Yellow
Port22: Presence Detect Input
DS184
Yellow
Port21: Presence Detect Input
DS185
Yellow
Port20: Presence Detect Input
DS186
Yellow
Port19: Presence Detect Input
DS187
Yellow
Port18: Presence Detect Input
DS188
Yellow
Port17: Presence Detect Input
DS189
Yellow
Port16: Presence Detect Input
DS190
Yellow
Port15: Presence Detect Input
DS191
Yellow
Port14: Presence Detect Input
DS192
Yellow
Port13: Presence Detect Input
DS193
Yellow
Port12: Presence Detect Input
DS194
Yellow
Port11: Presence Detect Input
DS195
Yellow
Port10: Presence Detect Input
DS196
Yellow
Port9: Presence Detect Input
DS197
Yellow
Port8: Presence Detect Input
DS198
Yellow
Port7: Presence Detect Input
DS199
Yellow
Port6: Presence Detect Input
DS200
Yellow
Port5: Presence Detect Input
DS201
Yellow
Port4: Presence Detect Input
DS202
Yellow
Port3: Presence Detect Input
DS203
Yellow
Port2: Presence Detect Input
DS204
Yellow
Port1: Presence Detect Input
DS205
Yellow
Port0: Presence Detect Input
DS5
Red
Port23: Power Fault Input
DS6
Red
Port22: Power Fault Input
DS7
Red
Port21: Power Fault Input
DS8
Red
Port20: Power Fault Input
DS9
Red
Port19: Power Fault Input
Table 2.20 LED Indicators (Part 2 of 8) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS10
Red
Port18: Power Fault Input
DS11
Red
Port17: Power Fault Input
DS12
Red
Port16: Power Fault Input
DS13
Red
Port15: Power Fault Input
DS14
Red
Port14: Power Fault Input
DS15
Red
Port13: Power Fault Input
DS16
Red
Port12: Power Fault Input
DS17
Red
Port11: Power Fault Input
DS18
Red
Port10: Power Fault Input
DS19
Red
Port9: Power Fault Input
DS20
Red
Port8: Power Fault Input
DS21
Red
Port7: Power Fault Input
DS22
Red
Port6: Power Fault Input
DS23
Red
Port5: Power Fault Input
DS24
Red
Port4: Power Fault Input
DS25
Red
Port3: Power Fault Input
DS26
Red
Port2: Power Fault Input
DS27
Red
Port1: Power Fault Input
DS28
Red
Port0: Power Fault Input
DS29
Green
Port23: Power Good Input
DS30
Green
Port22: Power Good Input
DS31
Green
Port21: Power Good Input
DS32
Green
Port20: Power Good Input
DS33
Green
Port19: Power Good Input
DS34
Green
Port18: Power Good Input
DS35
Green
Port17: Power Good Input
DS36
Green
Port16: Power Good Input
DS37
Green
Port15: Power Good Input
DS38
Green
Port14: Power Good Input
DS39
Green
Port13: Power Good Input
DS40
Green
Port12: Power Good Input
DS41
Green
Port11: Power Good Input
DS42
Green
Port10: Power Good Input
DS43
Green
Port9: Power Good Input
DS44
Green
Port8: Power Good Input
DS45
Green
Port7: Power Good Input
DS46
Green
Port6: Power Good Input
Table 2.20 LED Indicators (Part 3 of 8) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS47
Green
Port5: Power Good Input
DS48
Green
Port4: Power Good Input
DS49
Green
Port3: Power Good Input
DS50
Green
Port2: Power Good Input
DS51
Green
Port1: Power Good Input
DS52
Green
Port0: Power Good Input
DS206
Orange
Port23: Attention Indicator Output
DS207
Orange
Port22: Attention Indicator Output
DS208
Orange
Port21: Attention Indicator Output
DS209
Orange
Port20: Attention Indicator Output
DS210
Orange
Port19: Attention Indicator Output
DS211
Orange
Port18: Attention Indicator Output
DS212
Orange
Port17: Attention Indicator Output
DS213
Orange
Port16: Attention Indicator Output
DS214
Orange
Port15: Attention Indicator Output
DS215
Orange
Port14: Attention Indicator Output
DS216
Orange
Port13: Attention Indicator Output
DS217
Orange
Port12: Attention Indicator Output
DS218
Orange
Port11: Attention Indicator Output
DS219
Orange
Port10: Attention Indicator Output
DS220
Orange
Port9: Attention Indicator Output
DS221
Orange
Port8: Attention Indicator Output
DS222
Orange
Port7: Attention Indicator Output
DS223
Orange
Port6: Attention Indicator Output
DS224
Orange
Port5: Attention Indicator Output
DS225
Orange
Port4: Attention Indicator Output
DS226
Orange
Port3: Attention Indicator Output
DS227
Orange
Port2: Attention Indicator Output
DS228
Orange
Port1: Attention Indicator Output
DS229
Orange
Port0: Attention Indicator Output
DS230
Green
Port23: Power Indicator Output
DS231
Green
Port22: Power Indicator Output
DS232
Green
Port21: Power Indicator Output
DS233
Green
Port20: Power Indicator Output
DS234
Green
Port19: Power Indicator Output
DS235
Green
Port18: Power Indicator Output
DS236
Green
Port17: Power Indicator Output
Table 2.20 LED Indicators (Part 4 of 8) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS237
Green
Port16: Power Indicator Output
DS238
Green
Port15: Power Indicator Output
DS239
Green
Port14: Power Indicator Output
DS240
Green
Port13: Power Indicator Output
DS241
Green
Port12: Power Indicator Output
DS242
Green
Port11: Power Indicator Output
DS243
Green
Port10: Power Indicator Output
DS244
Green
Port9: Power Indicator Output
DS245
Green
Port8: Power Indicator Output
DS246
Green
Port7: Power Indicator Output
DS247
Green
Port6: Power Indicator Output
DS248
Green
Port5: Power Indicator Output
DS249
Green
Port4: Power Indicator Output
DS250
Green
Port3: Power Indicator Output
DS251
Green
Port2: Power Indicator Output
DS252
Green
Port1: Power Indicator Output
DS253
Green
Port0: Power Indicator Output
DS53
Green
Port23: Power Enable Output
DS54
Green
Port22: Power Enable Output
DS55
Green
Port21: Power Enable Output
DS56
Green
Port20: Power Enable Output
DS57
Green
Port19: Power Enable Output
DS58
Green
Port18: Power Enable Output
DS59
Green
Port17: Power Enable Output
DS60
Green
Port16: Power Enable Output
DS61
Green
Port15: Power Enable Output
DS62
Green
Port14: Power Enable Output
DS63
Green
Port13: Power Enable Output
DS64
Green
Port12: Power Enable Output
DS65
Green
Port11: Power Enable Output
DS66
Green
Port10: Power Enable Output
DS67
Green
Port9: Power Enable Output
DS68
Green
Port8: Power Enable Output
DS69
Green
Port7: Power Enable Output
DS70
Green
Port6: Power Enable Output
DS71
Green
Port5: Power Enable Output
DS72
Green
Port4: Power Enable Output
Table 2.20 LED Indicators (Part 5 of 8) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS73
Green
Port3: Power Enable Output
DS74
Green
Port2: Power Enable Output
DS75
Green
Port1: Power Enable Output
DS76
Green
Port0: Power Enable Output
DS77
Red
Slot 23 Reset Output
DS78
Red
Slot 22 Reset Output
DS79
Red
Slot 21 Reset Output
DS80
Red
Slot 20 Reset Output
DS81
Red
Slot 19 Reset Output
DS82
Red
Slot 18 Reset Output
DS83
Red
Slot 17 Reset Output
DS84
Red
Slot 16 Reset Output
DS85
Red
Slot 15 Reset Output
DS86
Red
Slot 14 Reset Output
DS87
Red
Slot 13 Reset Output
DS88
Red
Slot 12 Reset Output
DS89
Red
Slot 11 Reset Output
DS90
Red
Slot 10 Reset Output
DS91
Red
Slot 9 Reset Output
DS92
Red
Slot 8 Reset Output
DS93
Red
Slot 7 Reset Output
DS94
Red
Slot 6 Reset Output
DS95
Red
Slot 5 Reset Output
DS96
Red
Slot 4 Reset Output
DS97
Red
Slot 3 Reset Output
DS98
Red
Slot 2 Reset Output
DS99
Red
Slot 1 Reset Output
DS100
Red
Slot 0 Reset Output
DS326
Red
Partition 7 Fundamental Reset Input
DS327
Red
Partition 6 Fundamental Reset Input
DS328
Red
Partition 5 Fundamental Reset Input
DS329
Red
Partition 4 Fundamental Reset Input
DS330
Red
Partition 3 Fundamental Reset Input
DS331
Red
Partition 2 Fundamental Reset Input
DS332
Red
Partition 1 Fundamental Reset Input
DS333
Red
Partition 0 Fundamental Reset Input
DS415
Red
Slot 20 Reset Header (J131)
Table 2.20 LED Indicators (Part 6 of 8) 89EB-LOGAN-23 Evaluation Board
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IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS416
Red
Slot 16 Reset Header (J130)
DS417
Red
Slot 12 Reset Header (J129)
DS418
Red
Slot 4 Reset Header (J125)
DS419
Red
Slot 6 Reset Header (J128)
DS420
Red
Slot 4 Reset Header (J127)
DS421
Red
Slot 2 Reset Header (J126)
DS422
Red
Slot 0 Reset Header (J125)
DS334
Green
Port23: Link Up Status Output
DS335
Green
Port22: Link Up Status Output
DS336
Green
Port21: Link Up Status Output
DS337
Green
Port20: Link Up Status Output
DS338
Green
Port19: Link Up Status Output
DS339
Green
Port18: Link Up Status Output
DS340
Green
Port17: Link Up Status Output
DS341
Green
Port16: Link Up Status Output
DS342
Green
Port15: Link Up Status Output
DS343
Green
Port14: Link Up Status Output
DS344
Green
Port13: Link Up Status Output
DS345
Green
Port12: Link Up Status Output
DS346
Green
Port11: Link Up Status Output
DS347
Green
Port10: Link Up Status Output
DS348
Green
Port9: Link Up Status Output
DS349
Green
Port8: Link Up Status Output
DS350
Green
Port7: Link Up Status Output
DS351
Green
Port6: Link Up Status Output
DS352
Green
Port5: Link Up Status Output
DS353
Green
Port4: Link Up Status Output
DS354
Green
Port3: Link Up Status Output
DS355
Green
Port2: Link Up Status Output
DS356
Green
Port1: Link Up Status Output
DS357
Green
Port0: Link Up Status Output
DS358
Blue
Port23: Link Activity Status Output
DS359
Blue
Port22: Link Activity Status Output
DS360
Blue
Port21: Link Activity Status Output
DS361
Blue
Port20: Link Activity Status Output
DS362
Blue
Port19: Link Activity Status Output
DS363
Blue
Port18: Link Activity Status Output
Table 2.20 LED Indicators (Part 7 of 8) 89EB-LOGAN-23 Evaluation Board
2 - 21
February 16, 2011
IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
Location
Color
Definition
DS364
Blue
Port17: Link Activity Status Output
DS365
Blue
Port16: Link Activity Status Output
DS366
Blue
Port15: Link Activity Status Output
DS367
Blue
Port14: Link Activity Status Output
DS368
Blue
Port13: Link Activity Status Output
DS369
Blue
Port12: Link Activity Status Output
DS370
Blue
Port11: Link Activity Status Output
DS371
Blue
Port10: Link Activity Status Output
DS372
Blue
Port9: Link Activity Status Output
DS373
Blue
Port8: Link Activity Status Output
DS374
Blue
Port7: Link Activity Status Output
DS375
Blue
Port6: Link Activity Status Output
DS376
Blue
Port5: Link Activity Status Output
DS377
Blue
Port4: Link Activity Status Output
DS378
Blue
Port3: Link Activity Status Output
DS379
Blue
Port2: Link Activity Status Output
DS380
Blue
Port1: Link Activity Status Output
DS381
Blue
Port0: Link Activity Status Output
Table 2.20 LED Indicators (Part 8 of 8)
89EB-LOGAN-23 Evaluation Board
2 - 22
February 16, 2011
IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
EB-LOGAN-23 Board Figure
Figure 2.11 EB32NT24AG2 Evaluation Board
89EB-LOGAN-23 Evaluation Board
2 - 23
February 16, 2011
IDT Installation of the EB-LOGAN-23 Evaluation Board
Notes
89EB-LOGAN-23 Evaluation Board
2 - 24
February 16, 2011
Chapter 3
Software For EB-LOGAN-23 ®
Notes
Introduction This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EB-LOGAN-23 evaluation board using the device management software. Device management software and related user documentation are available on a CD which is included in the Evaluation Board Kit. This information is also available on IDT FTP site and also at my.idt.com. For more information, please go to: http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches or email IDT at
[email protected].
Device Management Software The primary use of the Device Management Software package is to enable users of the evaluation board to access all the registers in the PES32NT24AG2 device. This access can be achieved using the PCI Express in-band configuration cycles through the upstream port on the PES32NT24AG2 or through the SMBUS salve interface available on the IDT PCIe switch. This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. An export/import facility is also available to create and use “Configuration” files which can be used to initialize the switch device with specific values in specific registers. A conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES32NT24AG2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package. The front-end of the Device Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for the PES32NT24AG2 in the absence of the actual device. Much of the Device Management Software is written with device-independent and OS-independent code. The software is expected to work on Linux (/sys interface) and MS Windows XP. It may function well on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-independent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc. The actual program name of the Device Management Software is “PCIeBrowser” (an executable file under Windows or Linux). Revision 5.0.1 or later is required for devices in the PES32NT24AG2 product family family.
Device Drivers The PES32NT24AG2 and other members of this switch family offer Non-Transparent Bridging and builtin DMA capability inside the device. Device drivers are needed to take advantage of these features. Sample code for these drivers is available from IDT for the Linux operating system. Additionally, there a few other software packages available from IDT. These packages are not related to the evaluation board per se, and therefore not listed here. However, several of these packages may prove to be useful for specific device or system functionality. For more information, please go to http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches or email IDT at
[email protected]. 89EB-LOGAN-23 Evaluation Board
3-1
February 16, 2011
IDT Software For EB-LOGAN-23
Notes
89EB-LOGAN-23 Evaluation Board
3-2
February 16, 2011
Chapter 4
Schematics ®
Notes
Schematics
EB-LOGAN-23 Evaluation Board
4-1
February 16, 2011
8
7
6
5
4
3
2
1 REVISIONS
DCN
REV
1.0
DESCRIPTION
INITIAL RELEASE
CHANGE BY
DATE
2009-12-05
T. TRAN
D D
1. TITLE PAGE / TABLE OF CONTENTS
2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26.
C
B
27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52.
MEZZANINE CONNECTOR PORTS 0, 2 MEZZANINE CONNECTOR PORTS 4, 6 MEZZANINE CONNECTOR PORTS 8, 12 MEZZANINE CONNECTOR PORTS 16, 20 32NT24AG2 - SERDES 32NT24AG2 - CLK, CONFIG, GPIO 32NT24AG2 - POWER, GND IOEXPANDER 0-3 IOEXPANDER 4-7 IOEXPANDER 8-11 IOEXPANDER 12-13 IOEXPANDER 16-19 IOEXPANDER 20-21 HOT PLUG CONTROL PORTS 0-2 HOT PLUG CONTROL PORTS 4-6 HOT PLUG CONTROL PORTS 8-12 HOT PLUG CONTROL PORTS 16-20 SLOT RESETS AND WAKE PULL-UPS CLOCK GENERATOR / SOURCE INPUT CLOCK BUFFER - 1 CLOCK SELECTOR DUT PCLK 8 CLOCK SELECTOR DUT PCLK 16 CLOCK SELECTOR - DUT PCLK 0-20, GCLK 1-2 CLOCK SELECTOR - SLOTS 0-20 POWER CONNECTORS
POWER REGULATOR - VDDIO POWER REGULATOR - VDDCORE POWER REGULATOR - VDDPEA POWER REGULATOR - VDDPEHA POWER REGULATOR - VDDPETA RESET, SMBUS, EEPROM, JTAG DIP SWITCHES LED - PORT STATUS (1 OF 7) LED - PORT STATUS (2 OF 7) LED - PORT STATUS (3 OF 7) LED - PORT STATUS (4 OF 7) LED - PORT STATUS (5 OF 7) LED - PORT STATUS (6 OF 7) LED - PORT STATUS (7 OF 7) MIN LOAD RESISTORS 12PK RIBBON CONNECTORS PARTITION RESET SELECT HEADERS SLOT RESET SELECT HEADERS PORT 0 CLOCK GENERATOR PORT 2 CLOCK GENERATOR PORT 4 CLOCK GENERATOR PORT 6 CLOCK GENERATOR PORT 8 CLOCK GENERATOR PORT 12 CLOCK GENERATOR PORT 16 CLOCK GENERATOR PORT 20 CLOCK GENERATOR
C
B
A
A
TITLE
EB-LOGAN-23 SIZE
B
DRAWING NO.
FAB P/N
SCH-PESEB-001
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2010
Derek Huang
Thu Jul 01 15:00:52 2010 8
7
6
5
4
3
2.0
CHECKED BY
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
REV.
18-691-001
2
SHEET
1 OF 52 1
8
7
6
5
4
3
2
1
S0_3VAUX
S2_3VAUX S0_12V S0_3V D
S2_12V D S2_3V
470-1075-600 (1 of 2)
470-1075-600 (2 of 2)
Wafer 0
C1
C1
D2
D2
6
E1
E1
F2
F2
H2
H2
6
K2
K2
6
M2
M2
P2
L1
L1
N1
N1
R1
R1
U1
U1
B12
C11
D12
D12
E11
E11
F12
F12
G11
G11
H12
H12
J11
J11
K12
K12
L11
L11
M12
M12
P2
N11
N11
P12
P12
T2
T2
R11
R11
T12
T12
V2
V2
U11
U11
V12
V12
W11
W11
A13
A13
B14
B14
C13
C13
D14
D14
E13
E13
F14
F14
G13
G13
H14
H14
J13
J13
K14
K14
M14
M14
P14
P14
T14
T14
V14
V14
OUT OUT
PE01RN0 PE01RP0
STK0CFG1
W1
W1
PE03TN0 PE03TP0
A3
A3
B4
B4
6
C3
C3
D4
D4
6
F4
F4
H4
H4
6
K4
K4
6
M4
M4
L13
L13
P4
P4
N13
N13
T4
T4
R13
R13
V4
V4
U13
U13
W13
W13
Wafer 1
6 6
G3
J3
J3
L3
L3
N3
C OUT OUT
CPRSNTN0 M02_ID<2>
N3
R3
R3
U3
U3
W3
W3
OUT OUT
PE00TN1 PE00TP1 PE00RN1 PE00RP1
6
A5
A5
B6
B6
6
C5
C5
D6
D6
6
E5
E5
F6
F6
G5
G5
H6
H6
K6
K6
M6
M6
P6
J5
L5
L5
N5
N5
R5
R5
U5
U5
B16
B16
C15
D16
D16
E15
E15
F16
F16
G15
G15
H16
H16
J15
J15
K16
K16
L15
L15
M16
M16
P6
N15
N15
P16
P16
T6
T6
R15
R15
T16
T16
V6
V6
U15
U15
V16
V16
W15
W15
A17
A17
B18
B18
C17
C17
D18
D18
E17
F18
F18
H18
H18
K18
K18
M18
M18
P18
P18
T18
T18
V18
V18
6 6
OUT OUT
PE00RN0 PE00RP0
W5
W5
A7
A7
B8
B8
25
C7
C7
D8
D8
25
F8
F8
H8
H8
K8
K8
M8
M8
P8
P8
N17
N17
T8
T8
R17
R17
V8
V8
U17
U17
M02_ID<1>
W17
W17
S0_CLKN S0_CLKP
A19
A19
B20
B20
C19
C19
D20
D20
E19
E19
F20
F20
R7
G19
G19
H20
H20
R8
J19
J19
K20
K20
M20
M20
P20
P20
T20
T20
V20
V20
Wafer 3
6 6
E7
G7
G7
J7
J7
L7
L7
N7
N7
R7
R7
U7
U7
W7
W7
A9
A9
B10
B10
25
C9
C9
D10
D10
25
E9
E9
F10
F10
G9
G9
H10
H10
J9
J9
K10
K10
M10
M10
P10
P10
T10
T10
V10
V10
44
43
39
42
7
19
IN OUT
S2_CLKN S2_CLKP SLOT_HDR_RSTN2 SLOT_WAKEN2
100 100
G17 J17 L17
OUT Wafer 4
6 6
L9
L9
N9
N9
R9
R9
U9
U9
W9
W9
44
43
39
42
7
19 2 2
33
7
IN OUT BI IN
OUT
SLOT_HDR_RSTN0 SLOT_WAKEN0 MEZZ_SMBCLK1 MEZZ_SMBDAT1
STK0CFG0
100 100
L19
L19
N19
N19
R19
R19
U19
U19
W19
W19
Common Power
PE01RN1 PE01RP1
IN IN
Signal
OUT OUT
+3V3
B
Wafer 9
Common Power
6
PE01TN1 PE01TP1
Signal
6
IN IN
Common Power
E7
IN IN
Signal
PE02RN0 PE02RP0
Wafer 8
Common Power
OUT OUT
6
PE02TN0 PE02TP0
Signal
6
B
IN IN
X4 - STK0CFG1 = 0, STK0CFG0 = 1
A15
C15
Common Power
J5
PE00TN0 PE00TP0
A15
IN IN
Signal
6
PE02RN1 PE02RP1
Wafer 7
Common Power
OUT OUT
PE02TN1 PE02TP1
Signal
6
IN IN
C
STK0CFG1 & STK0CFG0 SET BY MEZZ CARDS X8 - STK0CFG1 = 0, STK0CFG0 = 0
Wafer 2
6
Common Power
G3
IN IN
Signal
6
PE03RN0 PE03RP0
E3
Wafer 6
Common Power
OUT OUT
E3
Signal
6
IN IN
5%
J1
B12
C11
R10
G1
J1
A11
1K 0603
G1
PE01TN0 PE01TP0
A11
IN IN
5%
OUT
6
R9
7
B2
Common Power
33
CPRSNTN2
B2
Signal
OUT
A1
Common Power
OUT OUT
6
PE03RN1 PE03RP1
Wafer 5
A1
Signal
6
PE03TN1 PE03TP1
1K 0603
6
IN IN
MEZZ_SMBCLK1
J49
6
MEZZ_SMBDAT1
OUT BI
2
2
J1
J1
A
A
TITLE
EB-LOGAN-23
MEZZANINE CONNECTOR PORTS 0/2 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:53 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 2 OF 52 1
8
7
6
5
4
3
2
1
S4_3VAUX
S6_3VAUX S4_12V S4_3V D
S6_12V D S6_3V
470-1075-600 (1 of 2)
470-1075-600 (2 of 2)
Wafer 0
E11
F12
F12
G11
G11
H12
H12
J11
J11
K12
K12
L11
L11
M12
M12
P2
N11
N11
P12
P12
T2
T2
R11
R11
T12
T12
V2
V2
U11
U11
V12
V12
W11
W11
A13
A13
B14
B14
C13
C13
D14
D14
E13
E13
F14
F14
G13
G13
H14
H14
J13
J13
K14
K14
M14
M14
P14
P14
T14
T14
V14
V14
C1
D2
D2
6
E1
E1
F2
F2
H2
H2
K2
K2
M2
M2
P2
J1
L1
L1
N1
N1
R1
R1
U1
U1
6 6
OUT OUT
STK1CFG1
W1
W1
PE07TN0 PE07TP0
A3
A3
B4
B4
6
C3
C3
D4
D4
6
F4
F4
H4
H4
6
K4
K4
6
M4
M4
L13
L13
P4
P4
N13
N13
T4
T4
R13
R13
V4
V4
U13
U13
W13
W13
Wafer 1
6 6
G3
J3
J3
L3
L3
N3
C OUT OUT
CPRSNTN4 M46_ID<2>
N3
R3
R3
U3
U3
W3
W3
OUT OUT
PE04TN1 PE04TP1 PE04RN1 PE04RP1
6
B16
D16
D16
E15
E15
F16
F16
G15
G15
H16
H16
J15
J15
K16
K16
L15
L15
M16
M16
P6
N15
N15
P16
P16
T6
T6
R15
R15
T16
T16
V6
V6
U15
U15
V16
V16
W15
W15
A17
A17
B18
B18
C17
C17
D18
D18
E17
E17
F18
F18
R16
G17
G17
H18
H18
R17
J17
J17
K18
K18
L17
L17
M18
M18
P18
P18
T18
T18
V18
V18
B6
6
D6
D6
6
E5
E5
F6
F6
G5
G5
H6
H6
K6
K6
M6
M6
P6
J5 L5
N5
N5
R5
R5
U5
U5
6 6
IN IN OUT OUT
PE04RN0 PE04RP0
W5
W5
A7
A7
B8
B8
25
C7
C7
D8
D8
25
F8
F8
H8
H8
K8
K8
M8
M8
P8
P8
N17
N17
T8
T8
R17
R17
V8
V8
U17
U17
M46_ID<1>
W17
W17
S4_CLKN S4_CLKP
A19
A19
B20
B20
C19
C19
D20
D20
E19
E19
F20
F20
R18
G19
G19
H20
H20
R19
J19
J19
K20
K20
M20
M20
P20
P20
T20
T20
V20
V20
Wafer 3
6 6
E7
G7
G7
J7
J7
L7
L7
N7
N7
R7
R7
U7
U7
W7
W7
A9
A9
B10
B10
25
C9
C9
D10
D10
25
E9
E9
F10
F10
G9
G9
H10
H10
J9
J9
K10
K10
M10
M10
P10
P10
T10
T10
V10
V10
44
43
39
42
7
19
IN OUT
OUT
S6_CLKN S6_CLKP SLOT_HDR_RSTN6 SLOT_WAKEN6
100 100
Wafer 4
6 6
L9
N9
N9
R9
R9
U9
U9
W9
W9
43
39
42
7
19 3 3
33
7
IN OUT BI IN
OUT
SLOT_HDR_RSTN4 SLOT_WAKEN4 MEZZ_SMBCLK2 MEZZ_SMBDAT2
STK1CFG0
100 100
L19
L19
N19
N19
R19
R19
U19
U19
W19
W19
Common Power
L9
44
IN IN
Signal
OUT OUT
PE05RN1 PE05RP1
+3V3
B
Wafer 9
Common Power
6
PE05TN1 PE05TP1
Signal
6
IN IN
Common Power
E7
IN IN
Signal
PE06RN0 PE06RP0
Wafer 8
Common Power
OUT OUT
6
PE06TN0 PE06TP0
Signal
6
B
IN IN
Common Power
B16
C15
B6
C5
L5
X4 - STK1CFG1 = 0, STK1CFG0 = 1
A15
C15
A5
C5
J5
PE04TN0 PE04TP0
A15
A5
Signal
6
PE06RN1 PE06RP1
Wafer 7
Common Power
OUT OUT
PE06TN1 PE06TP1
Signal
6
IN IN
C
STK1CFG1 & STK1CFG0 SET BY MEZZ CARDS X8 - STK1CFG1 = 0, STK1CFG0 = 0
Wafer 2
6
Common Power
G3
IN IN
Signal
6
PE07RN0 PE07RP0
E3
Wafer 6
Common Power
OUT OUT
E3
Signal
6
IN IN
5%
G1
J1
PE05RN0 PE05RP0
R21
G1
1K 0603
OUT
D12
E11
C1
IN IN
5%
7
D12
6
R20
33
CPRSNTN6
B12
C11
B2
Common Power
OUT
B12
C11
B2
Signal
6
A11
A1
Common Power
OUT OUT
PE07RN1 PE07RP1
Wafer 5
PE05TN0 PE05TP0
A11
A1
Signal
6
PE07TN1 PE07TP1
1K 0603
6
IN IN
MEZZ_SMBCLK2
J50
6
MEZZ_SMBDAT2
OUT BI
3
3
J2
J2
A
A
TITLE
EB-LOGAN-23
MEZZANINE CONNECTOR PORTS 4/6 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:53 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 3 OF 52 1
8
7
6
5
4
3
2
1
S8_3VAUX
S12_3VAUX S8_12V S8_3V D
S12_12V D S12_3V
470-1075-600 (1 of 2)
470-1075-600 (2 of 2)
Wafer 0
E11
F12
F12
G11
G11
H12
H12
J11
J11
K12
K12
L11
L11
M12
M12
P2
N11
N11
P12
P12
T2
T2
R11
R11
T12
T12
V2
V2
U11
U11
V12
V12
W11
W11
A13
A13
B14
B14
C13
C13
D14
D14
E13
E13
F14
F14
G13
G13
H14
H14
J13
J13
K14
K14
M14
M14
P14
P14
T14
T14
V14
V14
C1
D2
D2
6
E1
E1
F2
F2
H2
H2
K2
K2
M2
M2
P2
J1
L1
L1
N1
N1
R1
R1
U1
U1
6 6
OUT OUT
STK2CFG1
W1
W1
PE14TN0 PE14TP0
A3
A3
B4
B4
6
C3
C3
D4
D4
6
F4
F4
H4
H4
6
K4
K4
6
M4
M4
L13
L13
P4
P4
N13
N13
T4
T4
R13
R13
V4
V4
U13
U13
W13
W13
Wafer 1
6 6
G3
J3
J3
L3
L3
N3
C OUT OUT
CPRSNTN8 M812_ID<2>
N3
R3
R3
U3
U3
W3
W3
OUT OUT
PE09TN0 PE09TP0 PE09RN0 PE09RP0
6
B16
D16
D16
E15
E15
F16
F16
G15
G15
H16
H16
J15
J15
K16
K16
L15
L15
M16
M16
P6
N15
N15
P16
P16
T6
T6
R15
R15
T16
T16
V6
V6
U15
U15
V16
V16
W15
W15
A17
A17
B18
B18
C17
C17
D18
D18
E17
E17
F18
F18
R27
G17
G17
H18
H18
R28
J17
J17
K18
K18
L17
L17
M18
M18
P18
P18
T18
T18
V18
V18
B6
6
D6
D6
6
E5
E5
F6
F6
G5
G5
H6
H6
K6
K6
M6
M6
P6
J5 L5
N5
N5
R5
R5
U5
U5
6 6
IN IN OUT OUT
PE08RN0 PE08RP0
W5
W5
A7
A7
B8
B8
25
C7
C7
D8
D8
25
F8
F8
H8
H8
K8
K8
M8
M8
P8
P8
N17
N17
T8
T8
R17
R17
V8
V8
U17
U17
M812_ID<1>
W17
W17
S8_CLKN S8_CLKP
A19
A19
B20
B20
C19
C19
D20
D20
E19
E19
F20
F20
R29
G19
G19
H20
H20
R30
J19
J19
K20
K20
M20
M20
P20
P20
T20
T20
V20
V20
Wafer 3
6 6
E7
G7
G7
J7
J7
L7
L7
N7
N7
R7
R7
U7
U7
W7
W7
A9
A9
B10
B10
25
C9
C9
D10
D10
25
E9
E9
F10
F10
G9
G9
H10
H10
J9
J9
K10
K10
M10
M10
P10
P10
T10
T10
V10
V10
44
43
39
42
7
19
IN OUT
OUT
S12_CLKN S12_CLKP SLOT_HDR_RSTN12 SLOT_WAKEN12
100 100
Wafer 4
6 6
L9
N9
N9
R9
R9
U9
U9
W9
W9
43
39
42
7
19 4 4
33
7
IN OUT BI IN
OUT
SLOT_HDR_RSTN8 SLOT_WAKEN8 MEZZ_SMBCLK3 MEZZ_SMBDAT3
STK2CFG0
100 100
L19
L19
N19
N19
R19
R19
U19
U19
W19
W19
Common Power
L9
44
IN IN
Signal
OUT OUT
PE11RN0 PE11RP0
+3V3
B
Wafer 9
Common Power
6
PE11TN0 PE11TP0
Signal
6
IN IN
Common Power
E7
IN IN
Signal
PE12RN0 PE12RP0
Wafer 8
Common Power
OUT OUT
6
PE12TN0 PE12TP0
Signal
6
B
IN IN
Common Power
B16
C15
B6
C5
L5
X4 - STK2CFG1 = 0, STK2CFG0 = 1
A15
C15
A5
C5
J5
PE08TN0 PE08TP0
A15
A5
Signal
6
PE13RN0 PE13RP0
Wafer 7
Common Power
OUT OUT
PE13TN0 PE13TP0
Signal
6
IN IN
C
STK2CFG1 & STK2CFG0 SET BY MEZZ CARDS X8 - STK2CFG1 = 0, STK2CFG0 = 0
Wafer 2
6
Common Power
G3
IN IN
Signal
6
PE14RN0 PE14RP0
E3
Wafer 6
Common Power
OUT OUT
E3
Signal
6
IN IN
5%
G1
J1
PE10RN0 PE10RP0
R32
G1
1K 0603
OUT
D12
E11
C1
IN IN
5%
7
D12
6
R31
33
CPRSNTN12
B12
C11
B2
Common Power
OUT
B12
C11
B2
Signal
6
A11
A1
Common Power
OUT OUT
PE15RN0 PE15RP0
Wafer 5
PE10TN0 PE10TP0
A11
A1
Signal
6
PE15TN0 PE15TP0
1K 0603
6
IN IN
MEZZ_SMBCLK3
J51
6
MEZZ_SMBDAT3
OUT BI
4
4
J3
J3
A
A
TITLE
EB-LOGAN-23
MEZZANINE CONNECTOR PORTS 8/12 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:53 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 4 OF 52 1
8
7
6
5
4
3
2
1
S16_3VAUX
S20_3VAUX S16_12V S16_3V D
S20_12V D S20_3V
470-1075-600 (1 of 2)
470-1075-600 (2 of 2)
Wafer 0
E11
F12
F12
G11
G11
H12
H12
J11
J11
K12
K12
L11
L11
M12
M12
P2
N11
N11
P12
P12
T2
T2
R11
R11
T12
T12
V2
V2
U11
U11
V12
V12
W11
W11
A13
A13
B14
B14
C13
C13
D14
D14
E13
E13
F14
F14
G13
G13
H14
H14
J13
J13
K14
K14
M14
M14
P14
P14
T14
T14
V14
V14
C1
D2
D2
6
E1
E1
F2
F2
H2
H2
K2
K2
M2
M2
P2
J1
L1
L1
N1
N1
R1
R1
U1
U1
6 6
OUT OUT
STK3CFG1
W1
W1
PE22TN0 PE22TP0
A3
A3
B4
B4
6
C3
C3
D4
D4
6
F4
F4
H4
H4
6
K4
K4
6
M4
M4
L13
L13
P4
P4
N13
N13
T4
T4
R13
R13
V4
V4
U13
U13
W13
W13
Wafer 1
6 6
G3
J3
J3
L3
L3
N3
C OUT OUT
CPRSNTN16 M1620_ID<2>
N3
R3
R3
U3
U3
W3
W3
OUT OUT
PE17TN0 PE17TP0 PE17RN0 PE17RP0
6
B16
D16
D16
E15
E15
F16
F16
G15
G15
H16
H16
J15
J15
K16
K16
L15
L15
M16
M16
P6
N15
N15
P16
P16
T6
T6
R15
R15
T16
T16
V6
V6
U15
U15
V16
V16
W15
W15
A17
A17
B18
B18
C17
C17
D18
D18
E17
E17
F18
F18
R38
G17
G17
H18
H18
R39
J17
J17
K18
K18
L17
L17
M18
M18
P18
P18
T18
T18
V18
V18
B6
6
D6
D6
6
E5
E5
F6
F6
G5
G5
H6
H6
K6
K6
M6
M6
P6
J5 L5
N5
N5
R5
R5
U5
U5
6 6
IN IN OUT OUT
PE16RN0 PE16RP0
W5
W5
A7
A7
B8
B8
25
C7
C7
D8
D8
25
F8
F8
H8
H8
K8
K8
M8
M8
P8
P8
N17
N17
T8
T8
R17
R17
V8
V8
U17
U17
M1620_ID<1>
W17
W17
S16_CLKN S16_CLKP
A19
A19
B20
B20
C19
C19
D20
D20
E19
E19
F20
F20
R40
G19
G19
H20
H20
R41
J19
J19
K20
K20
M20
M20
P20
P20
T20
T20
V20
V20
Wafer 3
6 6
E7
G7
G7
J7
J7
L7
L7
N7
N7
R7
R7
U7
U7
W7
W7
A9
A9
B10
B10
25
C9
C9
D10
D10
25
E9
E9
F10
F10
G9
G9
H10
H10
J9
J9
K10
K10
M10
M10
P10
P10
T10
T10
V10
V10
44
43
39
42
7
19
IN OUT
OUT
S20_CLKN S20_CLKP SLOT_HDR_RSTN20 SLOT_WAKEN20
100 100
Wafer 4
6 6
L9
N9
N9
R9
R9
U9
U9
W9
W9
43
39
42
7
19 5 5
33
7
IN OUT BI IN
OUT
SLOT_HDR_RSTN16 SLOT_WAKEN16 MEZZ_SMBCLK4 MEZZ_SMBDAT4
STK3CFG0
100 100
L19
L19
N19
N19
R19
R19
U19
U19
W19
W19
Common Power
L9
44
IN IN
Signal
OUT OUT
PE19RN0 PE19RP0
+3V3
B
Wafer 9
Common Power
6
PE19TN0 PE19TP0
Signal
6
IN IN
Common Power
E7
IN IN
Signal
PE20RN0 PE20RP0
Wafer 8
Common Power
OUT OUT
6
PE20TN0 PE20TP0
Signal
6
B
IN IN
Common Power
B16
C15
B6
C5
L5
X4 - STK3CFG1 = 0, STK3CFG0 = 1
A15
C15
A5
C5
J5
PE16TN0 PE16TP0
A15
A5
Signal
6
PE21RN0 PE21RP0
Wafer 7
Common Power
OUT OUT
PE21TN0 PE21TP0
Signal
6
IN IN
C
STK3CFG1 & STK3CFG0 SET BY MEZZ CARDS X8 - STK3CFG1 = 0, STK3CFG0 = 0
Wafer 2
6
Common Power
G3
IN IN
Signal
6
PE22RN0 PE22RP0
E3
Wafer 6
Common Power
OUT OUT
E3
Signal
6
IN IN
5%
G1
J1
PE18RN0 PE18RP0
R43
G1
1K 0603
OUT
D12
E11
C1
IN IN
5%
7
D12
6
R42
33
CPRSNTN20
B12
C11
B2
Common Power
OUT
B12
C11
B2
Signal
6
A11
A1
Common Power
OUT OUT
PE23RN0 PE23RP0
Wafer 5
PE18TN0 PE18TP0
A11
A1
Signal
6
PE23TN0 PE23TP0
1K 0603
6
IN IN
MEZZ_SMBCLK4
J52
6
MEZZ_SMBDAT4
OUT BI
5
5
J4
J4
A
A
TITLE
EB-LOGAN-23
MEZZANINE CONNECTOR PORTS 16/20 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:53 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 5 OF 52 1
8
7
6
5
4
3
2
32NT24AG2 5/7
32NT24AG2 3/7 24 24
24 24
D
IN IN IN IN
1
P00CLKP P00CLKN
W20
P00CLKP
22
V20
P00CLKN
22
P02CLKP P02CLKN
E20
P02CLKP
24
F20
P02CLKN
24
IN IN IN IN
P08CLKP P08CLKN
E3
P08CLKP
F3
P08CLKN
P12CLKP P12CLKN
V3
P12CLKP
W3
P12CLKN
D 2 2
2 2
IN IN IN IN
PE00RP1 PE00RN1
T18
PE00RP1
PE00TP1
T22
T19
PE00RN1
PE00TN1
T21
PE00RP0 PE00RN0
U18
PE00RP0
PE00TP0
U22
U19
PE00RN0
PE00TN0
U21
PE00TP1 PE00TN1 PE00TP0 PE00TN0
OUT OUT
2
4
2
4
OUT OUT
2
4
2
4
4 4 2 2
IN IN
PE01RP1 PE01RN1
N18
PE01RP1
PE01TP1
N22
N19
PE01RN1
PE01TN1
N21
PE01RP0 PE01RN0
P18
PE01RP0
PE01TP0
P22
P19
PE01RN0
PE01TN0
P21
PE02RP1 PE02RN1
K18
PE02RP1
PE02TP1
K22
K19
PE02RN1
PE02TN1
K21
PE01TP1 PE01TN1
OUT OUT
2
OUT OUT
2
OUT OUT
2
2
4 4
2 2
IN IN
PE01TP0 PE01TN0
4
2
IN IN
PE02TP1 PE02TN1
2
4 4
2
C
2
IN IN
PE02RP0 PE02RN0
L18 L19
PE02RP0 PE02RN0
PE02TP0
L22
PE02TN0
L21
PE02TP0 PE02TN0
OUT OUT
2
4
4
2
2 2
IN IN IN IN
PE03RP1 PE03RN1
G18 G19
PE03RP0 PE03RN0
PE03TP1
G22
PE03RN1
PE03TN1
G21
H18
PE03RP0
PE03TP0
H22
H19
PE03RN0
PE03TN0
H21
PE03RP1
PE03TP1 PE03TN1 PE03TP0 PE03TN0
IN IN IN IN
G5
PE08RP0
PE08TP0
G1
G4
PE08RN0
PE08TN0
G2
PE09RP0 PE09RN0
H5
PE09RP0
PE09TP0
H1
H4
PE09RN0
PE09TN0
H2
PE10RP0 PE10RN0
K5
PE10RP0
PE10TP0
K1
K4
PE10RN0
PE10TN0
K2
PE11RP0 PE11RN0
L5
PE11RP0
PE11TP0
L1
L4
PE11RN0
PE11TN0
L2
PE12RP0 PE12RN0
N5
PE12RP0
PE12TP0
N1
N4
PE12RN0
PE12TN0
N2
PE13RP0 PE13RN0
P5
PE13RP0
PE13TP0
P1
P4
PE13RN0
PE13TN0
P2
PE14RP0 PE14RN0
T5
PE14RP0
PE14TP0
T1
T4
PE14RN0
PE14TN0
T2
PE15RP0 PE15RN0
U5
PE15RP0
PE15TP0
U1
U4
PE15RN0
PE15TN0
U2
IN IN IN IN
OUT OUT
2
OUT OUT
2
4
IN IN IN IN
23
24
24
24 24
B
IN IN
A13
P04CLKP
B13
P04CLKN
P06CLKP P06CLKN
A11
P06CLKP
B11
P06CLKN
24
5 5
5 3 3
IN IN
PE04RP1 PE04RN1
E17
PE04RP1
PE04TP1
A18
D17
PE04RN1
PE04TN1
B18
PE04RP0 PE04RN0
E18
PE04RP0
PE04TP0
A19
PE04TN0
B19
PE04TP1 PE04TN1
OUT OUT
5
3
3
IN IN
D18
PE04RN0
PE04TP0 PE04TN0
OUT OUT
3
5
5
3
IN IN
PE05RP1 PE05RN1
E14
PE05RP1
PE05TP1
A15
D14
PE05RN1
PE05TN1
B15
PE05RP0 PE05RN0
E15
PE05RP0
PE05TP0
A16
D15
PE05RN0
PE05TN0
B16
PE05TP1 PE05TN1
OUT OUT
3
OUT OUT
3
3
IN IN
PE05TP0 PE05TN0
5
5
3
3 3
A
3 3
3 3
IN IN IN IN
IN IN IN IN
PE06RP1 PE06RN1
E10
PE06RP1
PE06TP1
A8
D10
PE06RN1
PE06TN1
B8
PE06RP0 PE06RN0
E11
PE06RP0
PE06TP0
A9
D11
PE06RN0
PE06TN0
B9
PE07RP1 PE07RN1
E7
PE07RP1
PE07TP1
A5
D7
PE07RN1
PE07TN1
B5
PE07RP0 PE07RN0
E8
PE07RP0
PE07TP0
A6
D8
PE07RN0
PE07TN0
B6
PE06TP1 PE06TN1 PE06TP0 PE06TN0
PE07TP1 PE07TN1 PE07TP0 PE07TN0
OUT OUT OUT OUT
IN IN IN IN
IN IN IN IN
P16CLKP P16CLKN
AB11
P16CLKP
AA11
P16CLKN
P20CLKP P20CLKN
AB12
P20CLKP
AA12
P20CLKN
PE16RP0 PE16RN0
V6
PE16RP0
PE16TP0
AB5
W6
PE16RN0
PE16TN0
AA5
PE17RP0 PE17RN0
V7
PE17RP0
PE17TP0
AB6
W7
PE17RN0
PE17TN0
AA6
IN IN
PE18RP0 PE18RN0
V9
PE18RP0
PE18TP0
AB8
W9
PE18RN0
PE18TN0
AA8
PE19RP0 PE19RN0
V10
PE19RP0
PE19TP0
AB9
IN IN
W10
PE19RN0
PE19TN0
AA9
IN IN
PE20RP0 PE20RN0
V13
PE20RP0
PE20TP0
AB14
W13
PE20RN0
PE20TN0
AA14
3
5
3
5
3
5
3
5
IN IN
PE21RP0 PE21RN0
V14
PE21RP0
PE21TP0
AB15
W14
PE21RN0
PE21TN0
AA15
PE22RP0 PE22RN0
V16
PE22RP0
PE22TP0
AB17
IN IN
W16
PE22RN0
PE22TN0
AA17
PE23RP0 PE23RN0
V17
PE23RP0
PE23TP0
AB18
IN IN
W17
PE23RN0
PE23TN0
AA18
3
OUT OUT
3
OUT OUT
4
OUT OUT
4
OUT OUT
4
OUT OUT
4
4
PE12TP0 PE12TN0 PE13TP0 PE13TN0
4
PE14TP0 PE14TN0
4
PE15TP0 PE15TN0
C
4
4
PE16TP0 PE16TN0
5
OUT OUT
PE17TP0 PE17TN0
B
5
OUT OUT
5
OUT OUT
5
OUT OUT
5
OUT OUT
5
OUT OUT
5
OUT OUT
5
OUT OUT
5
5
PE18TP0 PE18TN0 PE19TP0 PE19TN0
5
5
PE20TP0 PE20TN0
5
PE21TP0 PE21TN0 PE22TP0 PE22TN0 PE23TP0 PE23TN0
5
5
5
A
3 TITLE
EB-LOGAN-23
32NT24AG2 - SERDES SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:00:54 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
7
4
U1
3
OUT OUT
U1
8
OUT OUT
4
3 5
3
4
3 5
3
OUT OUT
4
3 5
3
4
3 5
3
PE11TP0 PE11TN0
OUT OUT
4
32NT24AG2 6/7 23
P04CLKP P04CLKN
PE10TP0 PE10TN0
4
U1
2
32NT24AG2 4/7 IN IN
PE09TP0 PE09TN0
OUT OUT
2
U1
24
PE08TP0 PE08TN0
2
4
2
IN IN
PE08RP0 PE08RN0
2
4
2
IN IN
2
SHEET 6 OF 52 1
8
7
6
5
4
3
2
1
32NT24AG2 1/6 D
24 24
24 24
DUT RESET 33 HDR_2x10
51
50
49
48
47
46 44
45
44
41
32 52
43
39
2
44
43
39
2
44
43
39
3
44
43
39
3
44
43
39
4
44
43
39
4
44
43
39
5
44
43
39
5
MAIN_RSTN SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20
IN IN IN IN IN IN IN IN IN
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
33
33
11
12
12
13
13
14
14
33
15
15
16
16
33
17
17
18
18
19
19
20
20
33 33
J118
2.0MM NO-SHROUD
33 33
YEL
TP108
33
C
33
33
2
33
2
33
3
33
3
33 33 33 33
4
33
4
33 33
IN
Y11
GCLKP1
GCLK1N
Y12
GCLKN1
GCLK0P
A12
GCLKP0
GCLK0N
B12
GCLKN0
GCLKFSEL
AB2
GCLKFSEL
PERSTN
B20
PERSTN
RSTHALT
AA4
RSTHALT
D
33 33
5
33
5
IN IN IN IN IN IN IN IN IN IN IN IN IN
IN IN IN IN IN IN IN IN IN IN
Y14
REFRES07
REFRES06
Y9
REFRES06 REFRES05
Y5
SWMODE2
Y4
SWMODE2
REFRES05
N6
SWMODE1
AA3
SWMODE1
REFRES04
K6
REFRES04
SWMODE0
Y3
SWMODE0
REFRES03
C9
REFRES03
REFRES02
D13
REFRES02
REFRES01
K17
REFRES01 REFRES00 REFRESPLL
SWMODE3
G3
C2
G2
D2
G2
REFRES00
N17
G1
D3
G1
REFRESPLL
D12
G0
D1
G0
G3
CLKMODE1
B22
CLKMODE1
CLKMODE0
AA1
CLKMODE0
STK0CFG1
AB21 Y1
STK0CFG0
IN IN
REFRES07 SWMODE3
NC
C16
NC
Y8
R46
3.01K 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K
R47 R48 R49 R50 R51 R52 R53 R54
C
STK0CFG1 STK0CFG0
STK1CFG1
AB20
STK1CFG1
STK1CFG0
AB1
STK1CFG0
STK2CFG4
B1
STK2CFG4
STK2CFG3
A3
STK2CFG3
STK2CFG2
A2
STK2CFG2
STK2CFG1
A1
STK2CFG1
STK2CFG0
AA2
STK2CFG0
STK3CFG4
C3
STK3CFG4
STK3CFG3
C1
STK3CFG3
STK3CFG2
B3
STK3CFG2
STK3CFG1
B2
STK3CFG1
STK3CFG0
Y2
STK3CFG0
5%
R55
5%
+3V3
R24
IN IN
GCLK1P
PLACE RESISTORS AS CLOSE TO U1 AS POSSIBLE 33
11
VERT_SM
IN IN
U1
B
32 32
14 14
13 13
12 12
11 11
10 10
9 9
OUT BI
32NT24AG2 2/7
1K 0603
1K 0603
B
0
MSMBCLK
R45
A20 C20
MSMBDAT
MSMBCLK MSMBDAT
JTAG_TCK
C22
DUT_JTAG_TCK
JTAG_TDI
D20
DUT_JTAG_TDI
JTAG_TDO
A21
DUT_JTAG_TDO
JTAG_TMS
B21
DUT_JTAG_TMS
A22
DUT_JTAG_TRST_N
JTAG_TRST_N 33 33
32 32
IN IN IN BI
SSMBADDR2
D22
SSMBADDR2
SSMBADDR1
Y22
SSMBADDR1
SSMBCLK
D21
SSMBDAT
C21
GPIO00
AA19
GPIO0
GPIO01
Y18
GPIO1
SSMBCLK
GPIO02
AA20
GPIO2
SSMBDAT
GPIO03
Y19
GPIO3
GPIO04
Y20
GPIO4
GPIO05
AB22
GPIO5
GPIO06
AA21
GPIO6
GPIO07
AA22
GPIO7
GPIO08
Y21
GPIO8
IN IN OUT IN IN
32
OUT OUT OUT OUT OUT OUT OUT OUT OUT
34
32 32 32 32
34 34 34 34 34 34 34 34
U1
A
A
TITLE
EB-LOGAN-23
32NT24AG2 CLK, CONFIG, GPIO SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:54 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 7 OF 52 1
8
7
6
5
4
3
2
1
CP4
0.1UF
5
6
7
8
5
6
7
8
5
6
7
8
C118
CP2
0.1UF
CP7
0.1UF
1
2
3
4
6
5
4 5
7
3 6
8
2
4 5
1
3 6
7
2 7
8
1 8
D
0.1UF
C115
0.1UF
0.1UF
0.1UF
C111
C109
C107 C54
0.1UF
0.1UF
0.1UF C49
0.1UF
0.1UF
C104
C101
C97 C31
0.01UF
C93
0.1UF
0.1UF C27
0.01UF
C90
C87
0.1UF
0.1UF
C23
47UF
C82
0.1UF C18
47UF
C78
0.1UF C13
47UF
C74
0.1UF C8
47UF
C70
C65
0.1UF
0.1UF C3
1.0UF
C61
0.1UF
C57
C52
0.1UF
0.1UF
C42
C47
0.1UF
0.1UF
C39
0.1UF
C34
C30
C21
47UF
0.01UF
C16
3
0.01UF
C11
47UF
2
47UF
W31 1
C6
W30
+5V0_PS
47UF
LABEL: FAN LABEL: 1 GND 2 12V/5V 3 NC
C1
+12V3_PS D
1.0UF
+1V0_CORE
CP5
CP8
4
3
2
1
0.1UF
4
3
0.1UF
4
3
2
1
4
3
2
1
CP3
0.1UF
2
CP1
0.1UF
1
5
6
7
8
+1V0_PEA
C
C +3V3_IO +2V5_PEHA
VSS
VDDPETA
J14
VDDCORE
VSS
C18
K12
VSS
VSS
P12
T8
VSS
P17
VDDPETA
VDDPEA
G9
H13
VDDCORE
VSS
C19
J11
VSS
VSS
M5
V18
VSS
U13
VDDPETA
VDDPEA
G10
H14
VDDCORE
VSS
B17
K15
VSS
VSS
N11
V19
VSS
VDDPEA
G11
L9
VDDCORE
VSS
A14
VSS
VSS
P15
V21
VSS
L10
A17
J12
M8
AA7
VSS
U14
VDDPETA
VDDPEA
G12
VDDCORE
VSS
VSS
VSS
T17
VDDPETA
VDDPEA
G13
L11
VDDCORE
VSS
D4
H11
VSS
VSS
N12
V22
VSS
R17
VDDPETA
VDDPEA
G14
L12
VDDCORE
VSS
D5
J15
VSS
VSS
N15
Y6
VSS
U9
VDDPETA
VDDPEA
J7
VDDCORE
VSS
D6
H12
VSS
VSS
P20
L13
K20
Y7
VSS
W5
VSS
VDDPETA
VDDPEA
K16
VDDCORE
VSS
C4
VSS
VSS
M15
U10
VDDPETA
VDDPEA
J16
K10
VDDCORE
VSS
C5
J18
VSS
VSS
R1
U11
VDDPETA
VDDPEA
L6
L14
VDDCORE
VSS
D9
H15
VSS
VSS
N20
U12
VDDPETA
VDDPEA
L7
P9
VDDCORE
VSS
C6
J19
VSS
VSS
R2
VDDPEA
K7
P10
VDDCORE
VSS
C7
J20
VSS
VSS
R3
J21
VSS
M18
G7
VDDPEHA
VDDPEA
L16
VDDCORE
VSS
B4
F7
VDDPEHA
VDDPEA
L17
P13
VDDCORE
VSS
C8
VSS
F8
VDDPEHA
VDDPEA
P7
N10
VDDCORE
VSS
F21
J22
VSS
G16
VDDPEHA
VDDPEA
N7
P14
VDDCORE
VSS
F22
H20
F15
VDDPEHA
VDDPEA
M6
VDDCORE
VSS
D16
K3
VDDPEA
M7
N13
VDDCORE
VSS
G3
L8
M10
VDDCORE
VSS
D19
J1
F16
VDDPEHA
N9
M9
L3
AA10
VSS
AA13
VSS
Y10
VSS
W8
VSS
VSS
R4
Y13
VSS
VSS
R5
W11
VSS
VSS
VSS
R8
Y15
VSS
VSS
VSS
U17
W12
VSS
VSS
VSS
R11
Y16
VSS
T15
Y17
VSS
H7
VDDPEHA
VDDPEA
P16
VSS
VSS
H16
VDDPEHA
VDDPEA
N16
N14
VDDCORE
VSS
F1
J2
VSS
VSS
R12
W15
VSS
R7
VDDPEHA
VDDPEA
M16
M11
VDDCORE
VSS
F2
J3
VSS
VSS
U20
AB3
VSS
U15
VDDPEHA
VDDPEA
M17
M12
VDDCORE
VSS
F4
J4
VSS
VSS
R15
W18
VSS
U16
VDDPEHA
VDDPEA
T9
M13
VDDCORE
VSS
G8
K8
VSS
VSS
V1
AB4
VSS
T16
VDDPEHA
VDDPEA
T10
M14
VDDCORE
VSS
F5
J5
VSS
VSS
T20
AB7
VSS
R16
VDDPEHA
VDDPEA
T11
R9
VDDCORE
VSS
F6
L15
VSS
VSS
V2
AB13
VSS
U7
VDDPEHA
VDDPEA
T12
R10
VDDCORE
VSS
E5
M19
VSS
VSS
R18
AB19
VSS
U8
VDDPEHA
VDDPEA
T13
R13
VDDCORE
AB10
VSS
VDDPEA
T14
R14
VDDCORE
AB16
VSS
T7
VDDPEHA
C12
C17
C22
C26
C35
C40
C45
C48
C53
C62
C66
C75
C79
C83
C94
C98
C116
C119
47UF
47UF
47UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
VSS
AA16
VSS
+1V0_PETA
CP6
0.1UF
1
K9
T6
C5
VDDPETA
H8
5
VSS
V15
P6
CP9
0.1UF
4
V12
N8
6
M4
VSS
7
VSS
VSS
3
VSS
J8
8
K11
B14
2
A10
VSS
1
VSS
VDDCORE
5
VDDCORE
H10
4
J13
W19
6
W4
VDDIO
3
VDDIO
VDDPETA
7
VDDPETA
J6
2
H17
B C114
VSS
0.1UF
V11
8
P11
C106
VSS
C103
VSS
H3
0.1UF
C17
0.1UF
VSS
C96
VDDCORE
H9
0.1UF
W2
C92
VDDIO
0.1UF
VSS
VDDPETA
J17
C91
T3
C77
M3
0.1UF
VSS
0.1UF
VSS
C86
E16
C69
C15
0.1UF
VSS
0.1UF
VDDCORE
C72
K14
C60
VSS
W1
0.1UF
VSS
U6
VDDIO
VDDPETA
H6
0.1UF
V8
M2
C64
M1
VSS
C51
VSS
VSS
0.1UF
VSS
F19
0.1UF
F18
A7
C55
C14
VSS
0.1UF
VSS
VDDCORE
VDDIO
C46
VDDCORE
J10
VDDIO
VDDPETA
0.1UF
K13
W22
VDDPETA
F14
C43
W21
G17
+2V5_PEHA
C41
VSS
VSS
VDDIO
0.1UF
VSS
VDDCORE
VDDPETA
0.01UF
VSS
VSS
R22
C44
U3
P8
C33
N3
B10
0.1UF
VSS
J9
E4
0.01UF
VSS
F17
E2
C37
E13
VDDIO
0.01UF
C13
VDDPETA
F13
C29
VSS
VSS
F12
0.01UF
R21
C24
L20
47UF
VSS
C25
VSS
E1
47UF
G20
VDDIO
C19
C12
VDDPETA
C14
VSS
VSS
F11
47UF
R20
47UF
M22
VSS
C20
VSS
E22
C15
VSS
VDDIO
47UF
E12
VDDPETA
47UF
VSS
A4
F10
C9
VSS
VSS
V5
C11
47UF
VSS
R19
P3
B7
VSS
C10
V4
M21
VSS
VSS
E21
C4
M20
VSS
E19
VDDIO
1.0UF
VSS
VSS
VDDIO
VDDPETA
R6
A
VSS
E9
C10
VDDPETA
F9
1.0UF
B
E6 G15
VSS
G6
C7
32NT24AG2 7/7
47UF
+1V0_CORE
47UF
+1V0_PEA
C2
+3V3_IO
1.0UF
+1V0_PETA
A
TITLE
EB-LOGAN-23
32NT24AG2 - POWER U1
SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:54 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 8 OF 52 1
8
7
6
5
4
3
+3V3
2
1
+3V3
D R69
D
V+
R59
21
A0
R60
2
R61
3
14
13
13
12
12
11
11 10
10
9
9
7
7
IN BI
MSMBCLK MSMBDAT
0 0
P0 P1
5
P2
6
A1
P3
7
A2
P4
8
P5
9
P6
10
P7
11
P8
13
R65
22
SCL
P9
14
R66
23
SDA
P10
15
P11
16
C184
32
14
0.1UF
C 12
U22
+3V3 4
P12
17
P13
18
P14
19
P15
20
P0_APN P0_PDN P0_PFN P0_PWRGDN P0_AIN P0_PIN P0_PEP P0_RSTN P4_APN P4_PDN P4_PFN P4_PWRGDN P4_AIN P4_PIN P4_PEP P4_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
MAX7311AUG
34
24
34
42
15
35
42
15
35
42
0 2.7K 0
36
R71
21
R72
2
R73
3
1
0
R1612
IOEXPINTN
OUT
15
37
42
14
19
37
5
A0
P2
6
A1
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
A2
34 34
42 32
16
35
42
16
35
42
32
14
14
13
13 12
12 11
11 10
10
9
9
7
7
MSMBCLK MSMBDAT
IN BI
0 0
R77
22
SCL
P9
14
R78
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
36 36 16
37
42
14
19
37
9
10
11
12
13
14
34
12
P2_APN P2_PDN P2_PFN P2_PWRGDN P2_AIN P2_PIN P2_PEP P2_RSTN P6_APN P6_PDN P6_PFN P6_PWRGDN P6_AIN P6_PIN P6_PEP P6_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
15
35
42
15
35
42
15
37
42
14
19
37
36 36
34 34
42
16
35
42
16
35
42
16
37
42
14
19
37
36 36
C
VSS INT_N
IOEXPANDER 0
1
0
R1614
IOEXPINTN
10
11
12
13
14
34
IOEXPANDER 2
ADDR: 0X20
ADDR: 0X24
+3V3
+3V3
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U21
+3V3
B
4
P1
36
VSS INT_N
P0
V+
C186
24
0.1UF
32
MAX7311AUG
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 0 0 0
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
1K
U20
U23
+3V3
MAX7311AUG
B
MAX7311AUG V+
21
A0
P0 P1
5
P2
6
R63
2
A1
P3
7
R64
3
A2
P4
8
P5
9
P6
10
P7
32 14
13
13
12
12
11
11 10
10
9
9
7
7
IN BI
MSMBCLK MSMBDAT
0 0
11
P8
13
R67
22
SCL
P9
14
R68
23
SDA
P10
15
P11
16
P12
0.1UF
C185
32
14
12
P8_APN P8_PDN P8_PFN P8_PWRGDN P8_AIN P8_PIN P8_PEP P8_RSTN P16_APN P16_PDN P16_PFN P16_PWRGDN P16_AIN P16_PIN P16_PEP P16_RSTN
17
P13
18
P14
19
P15
20
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
24
34
42
17
35
17
35
42
2.7K 2.7K 0
42
36
1
0
R1613
IOEXPINTN
OUT
5
A0
P2
6
21
R75
2
A1
P3
7
R76
3
A2
P4
8
P5
9
P6
10
P7
11
P8
13
36 17 14
37 19
42 37
34 34
42
18
35
42
18
35
42
32 32
14
14
13
13 12
12 11
11 10
10
9
9
7
7
MSMBCLK MSMBDAT
IN BI
0 0
R79
22
SCL
P9
14
R80
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
36 36 18
37
42
14
19
37
9
10
11
12
13
14
34
12
P12_APN P12_PDN P12_PFN P12_PWRGDN P12_AIN P12_PIN P12_PEP P12_RSTN P20_APN P20_PDN P20_PFN P20_PWRGDN P20_AIN P20_PIN P20_PEP P20_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34 34
42
17
35
42
17
35
42
17
37
42
14
19
37
36 36
34 34
42
18
35
42
18
35
42
36 36 18
37
42
14
19
37
VSS INT_N
IOEXPANDER 1
1
0
R1615
IOEXPINTN
OUT
9
10
11
12
13
14
34
IOEXPANDER 3
ADDR: 0X22
A
4
P1
R74
VSS INT_N
P0
V+
C187
R62
4
0.1UF
2.7K 0 0
24
A
ADDR: 0X26
TITLE
EB-LOGAN-23
IOEXPANDER 0-3 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:55 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 9 OF 52 1
8
7
6
5
4
3
2
1
+3V3 +3V3
D D
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
U24
+3V3
14
13 13
12 12
11 11
10 10
9 9
7 7
IN BI
A0
R84
2
A1
R85
MSMBCLK MSMBDAT
3
0 0
R89
22
R90
23
A2
SCL SDA
C188
32
14
21
0.1UF
C
12
4
P1
5
P2
6
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
MAX7311AUG
P1_APN P1_PDN P1_PFN P1_PWRGDN P1_AIN P1_PIN P1_PEP P1_RSTN P3_APN P3_PDN P3_PFN P3_PWRGDN P3_AIN P3_PIN P3_PEP P3_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
24
0 2.7K 2.7K
36 36 37
42
14
19
R95
21
R96
2
R97
3
1
0
R1616
IOEXPINTN
4
P1
5
A0
P2
6
A1
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
A2
37
34 34
42
MSMBCLK MSMBDAT
R101
22
SCL
R102
23
SDA
P9
14
P10
15
36
P11
16
36
P12
17
P13
18
P14
19
P15
20
35
42
35
42
32 32
37
42
14
19
14
14 13
13
12
12
11
11 10
10
9
9
7
7
IN BI
0 0
37
VSS INT_N
P0
V+
C190
32
R83
P0
10
11
12
13
14
0.1UF
0 0 2.7K
V+
U26
+3V3
MAX7311AUG
24
34
12
P10_APN P10_PDN P10_PFN P10_PWRGDN P10_AIN P10_PIN P10_PEP P10_RSTN P14_APN P14_PDN P14_PFN P14_PWRGDN P14_AIN P14_PIN P14_PEP P14_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
36 36 37
42
14
19
37
34 34
42
35
42
35
42
36 36 37
42
14
19
C 37
VSS INT_N
1
0
R1618
IOEXPINTN
10
11
12
13
14
34
IOEXPANDER 4 IOEXPANDER 6 ADDR: 0X28 ADDR: 0X2C +3V3 +3V3
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U25
+3V3 B
14
13 13
12 12
11 11
10 10
9 9
7 7
IN BI
MSMBCLK MSMBDAT
21
A0
R87
2
R88
3
0 0
R91
22
R92
23
4
P1
5
P2
6
A1
P3
7
A2
P4
8
SCL SDA
0.1UF
C189
32
14
R86
P0
12
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
24
2.7K 2.7K 2.7K
36 36 37
42
14
19
1
0
R1617
IOEXPINTN
P0
4
P1
5
A0
P2
6
V+
R98
21
R99
2
A1
P3
7
R100
3
A2
P4
8
P5
9
P6
10
P7
11
P8
13
37
34 34
42
MSMBCLK MSMBDAT
R103
22
SCL
R104
23
SDA
P9
14
P10
15
36
P11
16
36
P12
17
P13
18
P14
19
P15
20
35
42
35
42
32 32
37
42
14
19
14
14 13
13 12
12 11
11 10
10
9
9
7
7
IN BI
0 0
37
VSS INT_N
B
MAX7311AUG
P5_APN P5_PDN P5_PFN P5_PWRGDN P5_AIN P5_PIN P5_PEP P5_RSTN P7_APN P7_PDN P7_PFN P7_PWRGDN P7_AIN P7_PIN P7_PEP P7_RSTN
C191
32
V+
10
11
12
13
14
0.1UF
2.7K 0 2.7K
24
U27
+3V3
MAX7311AUG
34
12
P18_APN P18_PDN P18_PFN P18_PWRGDN P18_AIN P18_PIN P18_PEP P18_RSTN P22_APN P22_PDN P22_PFN P22_PWRGDN P22_AIN P22_PIN P22_PEP P22_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
36 36 37
42
14
19
37
34 34
42
35
42
35
42
36 36 37
42
14
19
37
VSS INT_N
1
0
R1619
IOEXPINTN
10
11
12
13
14
34
IOEXPANDER 5 IOEXPANDER 7
ADDR: 0X2A
A
A
ADDR: 0X2E
TITLE
EB-LOGAN-23
IOEXPANDER 4-7 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:55 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 10 OF 52 1
8
7
6
5
4
3
2
+3V3
1
+3V3
D D
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U28
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
13
12
11
10
9
7
14
13
12
11
10
9
7
IN BI
2
R109
3
0 0
A0 A1 A2
P0
4
P1
5
P2
6
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
R113
22
SCL
P9
14
R114
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
0.1UF
C
12
P9_APN P9_PDN P9_PFN P9_PWRGDN P9_AIN P9_PIN P9_PEP P9_RSTN P11_APN P11_PDN P11_PFN P11_PWRGDN P11_AIN P11_PIN P11_PEP P11_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
24
34 34
42
35
42
35
0 2.7K 0
42
36
R119
21
R120
2
R121
3
1
0
R1620
IOEXPINTN
OUT
4
P1
5
A0
P2
6
A1
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
A2
36 37
42
14
19
37
34 34
32
42
35
42
35
42
32
14
14 13
13 12
12 11
11
10
9
9
7
10
7
IN BI
MSMBCLK MSMBDAT
0 0
R125
22
SCL
P9
14
R126
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
36 36 37
42
14
19
37
VSS INT_N
P0
V+
C194
14
32
21
R108
C192
32
MSMBCLK MSMBDAT
R107
V+
MAX7311AUG
0.1UF
24
0 0 0
U30
+3V3
MAX7311AUG
9
10
11
12
13
14
34
12
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
36 36 37
42
14
19
37
34 34
42
35
42
35
42
36 36 37
42
14
19
C 37
VSS INT_N
1
IOEXPANDER 8
IOEXPANDER 10
ADDR: 0X50
ADDR: 0X54
+3V3
P17_APN P17_PDN P17_PFN P17_PWRGDN P17_AIN P17_PIN P17_PEP P17_RSTN P19_APN P19_PDN P19_PFN P19_PWRGDN P19_AIN P19_PIN P19_PEP P19_RSTN 0
R1622
IOEXPINTN
10
11
12
13
14
34
+3V3
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
U29
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
14
13
12
11
10
9
7
32
14
13
12
11
10
9
7
IN BI
MSMBCLK MSMBDAT
21
R111
2
R112
3
0 0
4
P1
5
A0
P2
6
A1
P3
7
A2
P4
8
P5
9
P6
10
P7
11
P8
13
R115
22
SCL
P9
14
R116
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
0.1UF
C193
32
R110
P0
V+
12
P13_APN P13_PDN P13_PFN P13_PWRGDN P13_AIN P13_PIN P13_PEP P13_RSTN P15_APN P15_PDN P15_PFN P15_PWRGDN P15_AIN P15_PIN P15_PEP P15_RSTN
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
24
34
42
35
42
35
42
0 2.7K 0
36
1
0
R1621
IOEXPINTN
P0
4
P1
5
A0
P2
6
V+
R122
21
R123
2
A1
P3
7
R124
3
A2
P4
8
P5
9
P6
10
P7
11
P8
13
36 37
42
14
19
37
34 34
42
35
42
35
32 32
14
14 13
13 12
12 11
11
10
9
9
7
10
7
IN BI
MSMBCLK MSMBDAT
0 0
R127
22
SCL
P9
14
R128
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
42
36 36 37
42
14
19
37
VSS INT_N
B
MAX7311AUG
C195
24
0 0 0
U31
+3V3
MAX7311AUG
0.1UF
B
10
11
12
13
14
34
12
IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT
34
OUT
9
34
42
35
42
35
42
36 36 37
42
14
19
37
34 34
42
35
42
35
42
36 36 37 14
42 19
37
VSS INT_N
IOEXPANDER 9
P21_APN P21_PDN P21_PFN P21_PWRGDN P21_AIN P21_PIN P21_PEP P21_RSTN P23_APN P23_PDN P23_PFN P23_PWRGDN P23_AIN P23_PIN P23_PEP P23_RSTN
1
0
R1623
IOEXPINTN
10
11
12
13
14
34
IOEXPANDER 11
A
A
ADDR: 0X56 ADDR: 0X52
TITLE
Logan Validation Board EB-LOGAN-23
IOEXPANDER 8-11 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2009 2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:55 2010 3
2.0 1.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 11 OF 52 1
8
7
6
5
4
3
+3V3
2
1
+3V3
D D
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U89
+3V3
U96
+3V3
MAX7311AUG
32
14
13 13
12 12
11 11
10 10
9 9
7 7
IN BI
21
R1149
2
R1150
3
0 0
A0 A1 A2
R1154
22
SCL
R1155
23
SDA
C645
32
14
MSMBCLK MSMBDAT
R1148
0.1UF
C
12
P0
4
P1
5
P2
6
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
P0_MRLN P1_MRLN P2_MRLN P3_MRLN P4_MRLN P5_MRLN P6_MRLN P7_MRLN P8_MRLN P10_MRLN P12_MRLN P14_MRLN P16_MRLN P18_MRLN P20_MRLN P22_MRLN
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
24
38
0 2.7K 2.7K
38 38 38
R1160
21
R1161
2
R1162
3
1
0
R1624
IOEXPINTN
OUT
38
P7
11
P8
13
P9
14
38 38
32
14
13
12
11
10
9
7
IN BI
MSMBCLK MSMBDAT
0 0
R1166
22
SCL
R1167
23
SDA
P10
15
38
P11
16
38
P12
17
P13
18
P14
19
P15
20
38
32
14
13
12
11
10
9
7
38 38 38
9
10
11
12
13
14
34
12
12
11
10
9
7
IN BI
MSMBCLK MSMBDAT
R1151
21
R1152
2
R1153
3
0 0
INT_N
9
38 38 38 38 38 38 39 39 39 39 39 39
C
39 39
1
R1626
0
IOEXPINTN
10
11
12
13
14
34
ADDR: 0X5C
U97
+3V3
R1156
22
R1157
23
P0
4
P1
5
A0
P2
6
A1
P3
7
V+
A2
SCL SDA
0.1UF
12
P4
8
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
P9_MRLN P11_MRLN P13_MRLN P15_MRLN P17_MRLN P19_MRLN P21_MRLN P23_MRLN
IN IN IN IN IN IN IN IN
24
38
P0
4
P1
5
A0
P2
6
V+
38
R1163
21
R1164
2
A1
P3
7
R1165
3
A2
P4
8
P5
9
38
P6
10
38
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
0 2.7K 2.7K
38 38 38 38
32 32
14
14
13
13 12
12
11
11
10
10 9
9
7
7
IN BI
MSMBCLK MSMBDAT
0 0
R1168
22
R1169
23
VSS INT_N
B
MAX7311AUG
SCL SDA
1
0
R1625
IOEXPINTN
OUT
9
10
11
12
13
14
34
12
P1_ILOCKST P3_ILOCKST P5_ILOCKST P7_ILOCKST P10_ILOCKST P14_ILOCKST P18_ILOCKST P22_ILOCKST P1_ILOCKP P3_ILOCKP P5_ILOCKP P7_ILOCKP P10_ILOCKP P14_ILOCKP P18_ILOCKP P22_ILOCKP
IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT
38
OUT
9
38 38 38 38 38 38 38 39 39 39 39 39 39 39 39
VSS INT_N
IOEXPANDER 13 A
OUT
38
VSS
C648
13
7
38
IOEXPANDER 14
0.1UF
14
9
P4
8 10
U90
C646
32
10
7
IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
24
11
P3
P6
MAX7311AUG
12
A1
P0_ILOCKST P2_ILOCKST P4_ILOCKST P6_ILOCKST P8_ILOCKST P12_ILOCKST P16_ILOCKST P20_ILOCKST P0_ILOCKP P2_ILOCKP P4_ILOCKP P6_ILOCKP P8_ILOCKP P12_ILOCKP P16_ILOCKP P20_ILOCKP
+3V3
+3V3
13
6
P5
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
14
P2
38
+3V3
32
A0
38
ADDR: 0X58
0 0 2.7K
5
A2
IOEXPANDER 12
B
4
P1
9
VSS INT_N
P0
V+
38
C647
0 0 2.7K
V+
0.1UF
24
MAX7311AUG
1
R1627
0
IOEXPINTN
10
11
12
13
14
34
IOEXPANDER 15 A
ADDR: 0X5E
ADDR: 0X5A
TITLE
EB-LOGAN-23
IOEXPANDER 12-15 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:55 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 12 OF 52 1
8
7
6
5
4
3
+3V3
2
1
+3V3
D D
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
0 0 0
32
14
13 13
12 12
11 11
10 10
9 9
7 7
IN BI
21
R1125
2
R1126
3
0 0
V+
A0 A1 A2
R1130
22
SCL
R1131
23
SDA
C641
32
14
MSMBCLK MSMBDAT
R1124
U87 MAX7311AUG
0.1UF
C
12
P0
4
P1
5
P2
6
P3
7
P4
8
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
P9_ILOCKST P11_ILOCKST P13_ILOCKST P15_ILOCKST P17_ILOCKST P19_ILOCKST P21_ILOCKST P23_ILOCKST P9_ILOCKP P11_ILOCKP P13_ILOCKP P15_ILOCKP P17_ILOCKP P19_ILOCKP P21_ILOCKP P23_ILOCKP
IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT
24
P0
4
P1
5
A0
P2
6
A1
P3
7
P4
8
38
P5
9
38
P6
10
38
P7
11
P8
13
P9
14
38
0 0 0
38 38 38
R1136
21
R1137
2
R1138
3
1
0
R1628
IOEXPINTN
OUT
A2
39 39
32
14
13
12
11
10
9
7
IN BI
MSMBCLK MSMBDAT
0 0
R1142
22
SCL
R1143
23
SDA
P10
15
39
P11
16
39
P12
17
P13
18
P14
19
P15
20
39
32
14
13
12
11
10
9
7
39 39 39
VSS INT_N
V+
38
C643
24
U85 MAX7311AUG
0.1UF
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
9
10
11
12
14
34
12
INT_N
U86
13
12
11
10
9
7 7
IN BI
MSMBCLK MSMBDAT
21
R1128
2
R1129
3
0 0
R1132
22
R1133
23
4
P1
5
A0
P2
6
A1
P3
7
A2
SCL SDA
0.1UF
12
P4
8
P5
9
P6
10
P7
11
P8
13
P9
14
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
P0_LINKUPN P1_LINKUPN P2_LINKUPN P3_LINKUPN P4_LINKUPN P5_LINKUPN P6_LINKUPN P7_LINKUPN P8_LINKUPN P9_LINKUPN P10_LINKUPN P11_LINKUPN P12_LINKUPN P13_LINKUPN P14_LINKUPN P15_LINKUPN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
24
40
40 40 40 40 40 40 40
C
40 40
4
P1
5
A0
P2
6
21
R1140
2
A1
P3
7
R1141
3
A2
P4
8
P5
9
40
P6
10
40
P7
11
40
P8
13
P9
14
P10
15
40
P11
16
40
P12
17
P13
18
P14
19
P15
20
40 40 40
40
32
40
32
14
14
13
13 12
12
11
11
10
10 9
9
7
7
IN BI
MSMBCLK MSMBDAT
0 0
R1144
22
R1145
23
40 40 40
VSS INT_N
B
R1139
2.7K 0 0
40
SCL SDA
1
12
P16_LINKUPN P17_LINKUPN P18_LINKUPN P19_LINKUPN P20_LINKUPN P21_LINKUPN P22_LINKUPN P23_LINKUPN P16_ACTIVEN P17_ACTIVEN P18_ACTIVEN P19_ACTIVEN P20_ACTIVEN P21_ACTIVEN P22_ACTIVEN P23_ACTIVEN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40
VSS INT_N
IOEXPANDER 17 A
40
1
P0
V+
40
C644
14
9
R1127
P0
V+
C642
32
10
40
MAX7311AUG
0.1UF
24
11
40
U88
+3V3
MAX7311AUG
12
40
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
+3V3
13
40
+3V3
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
14
40
ADDR: 0XA4
+3V3
32
40
IOEXPANDER 18
ADDR: 0XB0
2.7K 0 0
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
VSS
IOEXPANDER 16
B
P0_ACTIVEN P1_ACTIVEN P2_ACTIVEN P3_ACTIVEN P4_ACTIVEN P5_ACTIVEN P6_ACTIVEN P7_ACTIVEN P8_ACTIVEN P9_ACTIVEN P10_ACTIVEN P11_ACTIVEN P12_ACTIVEN P13_ACTIVEN P14_ACTIVEN P15_ACTIVEN
1
IOEXPANDER 19 ADDR: 0XA6
ADDR: 0XA2
TITLE
A
EB-LOGAN-23
IOEXPANDER 16-19 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:56 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 13 OF 52 1
8
7
6
5
4
3
2
1
+3V3
D
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD
D
U83 MAX7311AUG
24
0 0 0
14
13
12
11
10
9
7
32
14
13
12
11
10
9
7
MSMBCLK MSMBDAT
IN BI
21
R132
2
R133
3
0 0
P0
4
P1
5
A0
P2
6
A1
P3
7
A2
P4
8
P5
9
P6
10
P7
11
P8
13
V+
R137
22
SCL
P9
14
R138
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
C196
32
R131
9
19
37
9
19
37
9
19
37
9
19
37
9
19
37
9
19
37
9
19
37
9
19
37
OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN
39
43
39
43
39
43
39
43
39
43
39
43
39
43
39
43
OUT
9
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
10
19
37
10
19
37
C
VSS INT_N
0.1UF
C
12
P0_RSTN P2_RSTN P4_RSTN P6_RSTN P8_RSTN P12_RSTN P16_RSTN P20_RSTN PART0_PERSTN PART1_PERSTN PART2_PERSTN PART3_PERSTN PART4_PERSTN PART5_PERSTN PART6_PERSTN PART7_PERSTN
1
0
R1633
IOEXPINTN
10
11
12
13
34
IOEXPANDER 20 ADDR: 0XA8
+3V3
PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U84
+3V3
MAX7311AUG
B
24
2.7K 0 0
14
13
12
11
10
9
7
32
14
13
12
11
10
9
7
MSMBCLK MSMBDAT
IN BI
P0
4
P1
5
R134
21
A0
P2
6
R135
2
A1
P3
7
R136
3
A2
P4
8
P5
9
P6
10
P7
11
0 0
P8
13
R139
22
SCL
P9
14
R140
23
SDA
P10
15
P11
16
P12
17
P13
18
P14
19
P15
20
C197
32
V+
12
10
19
37
10
19
37
11
19
37
10
19
37
11
19
37
11
19
37
10
19
37
11
19
37
11
19
37
10
19
37
11
19
B
37
11
19
37
10
19
37
11
19
37
VSS INT_N
0.1UF
P1_RSTN P3_RSTN P5_RSTN P7_RSTN P9_RSTN P10_RSTN P11_RSTN P13_RSTN P14_RSTN P15_RSTN P17_RSTN P18_RSTN P19_RSTN P21_RSTN P22_RSTN P23_RSTN
1
IOEXPANDER 21 ADDR: 0XAA
A
A
TITLE
EB-LOGAN-23
IOEXPANDER 20-21 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:56 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 14 OF 52 1
6
5
3
2
+3V3_PS
S0_3V R186
0.047UF
Q3
D S0_12V W4
8
7
D D D D
NMOSFET
W3 C253
4
3
15
R182
R175
R174
R173
R172
R171
R170
R169
R168
0.013
R167
2
1
C251
0.015UF
R178
6
10
5
4
3
S S S G 2
Q1
1
NMOSFET
D
R184
S S S G
R180
10
D D D D
5
51
R176
0.008
LTC4242CUHF
10K 10K 10K 10K 10K 10K 10K 10K
33
C
1
+12V3_PS
8
+3V3_PS
4
7
7
6
8
C 28
12VOUT1
29
12VGATE1
30
12VSENSE1
31
12VIN1
3VIN1
5
3VSENSE1
4
3VGATE1
3
3VOUT1
2
S0_3VAUX W5
42
42
35
35
37
IN OUT
9
OUT
9
OUT
9
OUT 9
IN
P0_PFN P0_PWRGDN P2_PFN P2_PWRGDN P2_PEP
AUXIN1
1
AUXON1
38
ON1
R157
35
R158
34
R159
32
AUXPGOODN1
R160
33
R161
17
R162
18
AUXFAULTN2
R163
20
R164 R165 R166
AUXOUT1
27
FAULTN1
FON1
37
AUXFAULTN1
ENN1
36
PGOODN1
GND1
26
FAULTN2
GND2
39
AUXPGOODN2
ENN2
16
19
PGOODN2
FON2
15
14
ON2
13
AUXON2 AUXOUT2
25
8
10K 10K
B
C250
42
35
9
9
6 R156
R154
42
37
35
VCC
R155
R153
42
42
100 100 100 100 100 100 100 100 100 100 100 100
P0_PEP
7
AUXIN2
21
12VIN2
22
12VSENSE2
23
12VGATE2
24
12VOUT2
S2_3VAUX
3VOUT2
12
3VGATE2
11
3VSENSE2
10
3VIN2
W6
B
9
1.0UF
U45
S2_3V W7
0.013
C254
0.047UF
W8
A
8
7
6
NMOSFET
R187
S2_12V
4
3
2
15
D D D D
Q4
R179
5
10
0.015UF
51 4
3
S S S G 2
Q2
NMOSFET
1
A
R185
S S S G
1
C252
R181
8
7
10
D D D D
6
R177
5
0.008
R183
TITLE
EB-LOGAN-23
HOT PLUG CONTROL PORTS 0-2 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:56 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 15 OF 52 1
6
5
3
2
+3V3_PS
S4_3V R221
0.047UF
Q7
D S4_12V W10
8
7
D D D D
NMOSFET
W9 C258
4
3
15
R217
R210
R209
R208
R207
R206
R205
R204
R203
0.013
R202
2
1
C256
0.015UF
R213
6
10
5
4
3
S S S G 2
Q5
1
NMOSFET
D
R219
S S S G
R215
10
D D D D
5
51
R211
0.008
LTC4242CUHF
10K 10K 10K 10K 10K 10K 10K 10K
33
C
1
+12V2_PS
8
+3V3_PS
4
7
7
6
8
C 28
12VOUT1
29
12VGATE1
30
12VSENSE1
31
12VIN1
3VIN1
5
3VSENSE1
4
3VGATE1
3
3VOUT1
2
S4_3VAUX W11
42
42
35
35
37
IN OUT
9
OUT
9
OUT
9
OUT 9
IN
P4_PFN P4_PWRGDN P6_PFN P6_PWRGDN P6_PEP
AUXIN1
1
AUXON1
38
ON1
R192
35
R193
34
R194
32
AUXPGOODN1
R195
33
R196
17
R197
18
AUXFAULTN2
R198
20
R199 R200 R201
AUXOUT1
27
FAULTN1
FON1
37
AUXFAULTN1
ENN1
36
PGOODN1
GND1
26
FAULTN2
GND2
39
AUXPGOODN2
ENN2
16
19
PGOODN2
FON2
15
14
ON2
13
AUXON2 AUXOUT2
25
8
10K 10K
B
C255
42
35
9
9
6 R191
R189
42
37
35
VCC
R190
R188
42
42
100 100 100 100 100 100 100 100 100 100 100 100
P4_PEP
7
AUXIN2
21
12VIN2
22
12VSENSE2
23
12VGATE2
24
12VOUT2
S6_3VAUX
3VOUT2
12
3VGATE2
11
3VSENSE2
10
3VIN2
W12
B
9
1.0UF
U46
S6_3V W13
0.013
C259
0.047UF
W14
A
8
7
6
NMOSFET
R222
S6_12V
4
3
2
15
D D D D
Q8
R214
5
10
0.015UF
51 4
3
S S S G 2
Q6
NMOSFET
1
A
R220
S S S G
1
C257
R216
8
7
10
D D D D
6
R212
5
0.008
R218
TITLE
EB-LOGAN-23
HOT PLUG CONTROL PORTS 4-6 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:57 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 16 OF 52 1
6
5
3
2
+3V3_PS
S8_3V R256
0.047UF
D S8_12V W16
8
7
Q11
D D D D
NMOSFET
W15 C263
4
3
15
R252
R245
R244
R243
R242
R241
R240
R239
R238
0.013
R237
2
1
C261
0.015UF
R248
6
10
5
4
3
S S S G 2
Q9
1
NMOSFET
D
R254
S S S G
R250
10
D D D D
5
51
R246
0.008
LTC4242CUHF
10K 10K 10K 10K 10K 10K 10K 10K
33
C
1
+12V2_PS
8
+3V3_PS
4
7
7
6
8
C 28
12VOUT1
29
12VGATE1
30
12VSENSE1
31
12VIN1
3VIN1
5
3VSENSE1
4
3VGATE1
3
3VOUT1
2
S8_3VAUX W17
42
42
35
35
37
IN OUT
9
OUT
9
OUT
9
OUT 9
IN
P8_PFN P8_PWRGDN P12_PFN P12_PWRGDN P12_PEP
AUXIN1
1
AUXON1
38
ON1
R227
35
R228
34
R229
32
AUXPGOODN1
R230
33
R231
17
R232
18
AUXFAULTN2
R233
20
R234 R235 R236
AUXOUT1
27
FAULTN1
FON1
37
AUXFAULTN1
ENN1
36
PGOODN1
GND1
26
FAULTN2
GND2
39
AUXPGOODN2
ENN2
16
19
PGOODN2
FON2
15
14
ON2
13
AUXON2 AUXOUT2
25
8
10K 10K
B
C260
42
35
9
9
6 R226
R224
42
37
35
VCC
R225
R223
42
42
100 100 100 100 100 100 100 100 100 100 100 100
P8_PEP
7
AUXIN2
21
12VIN2
22
12VSENSE2
23
12VGATE2
24
12VOUT2
S12_3VAUX
3VOUT2
12
3VGATE2
11
3VSENSE2
10
3VIN2
W18
B
9
1.0UF
U47
S12_3V W19
0.013
C264
0.047UF
W20
A
8
7
6
NMOSFET
R257
S12_12V
4
3
2
15
D D D D
Q12
R249
5
10
0.015UF
51 4
3
S S S G 2
Q10
NMOSFET
1
A
R255
S S S G
1
C262
R251
8
7
10
D D D D
6
R247
5
0.008
R253
TITLE
EB-LOGAN-23
HOT PLUG CONTROL PORTS 8-12 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:57 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 17 OF 52 1
6
5
3
2
+3V3_PS
S16_3V R291
0.047UF
D S16_12V W22
8
7
Q15
D D D D
NMOSFET
W21 C268
4
3
15
R287
R280
R279
R278
R277
R276
R275
R274
R273
0.013
R272
2
1
C266
0.015UF
R283
6
10
5
4
3
S S S G 2
Q13
1
NMOSFET
D
R289
S S S G
R285
10
D D D D
5
51
R281
0.008
LTC4242CUHF
10K 10K 10K 10K 10K 10K 10K 10K
33
C
1
+12V3_PS
8
+3V3_PS
4
7
7
6
8
C 28
12VOUT1
29
12VGATE1
30
12VSENSE1
31
12VIN1
3VIN1
5
3VSENSE1
4
3VGATE1
3
3VOUT1
2
S16_3VAUX W23
42
42
35
35
37
IN OUT
9
OUT
9
OUT
9
OUT 9
IN
P16_PFN P16_PWRGDN P20_PFN P20_PWRGDN P20_PEP
AUXIN1
1
AUXON1
38
ON1
R262
35
R263
34
R264
32
AUXPGOODN1
R265
33
R266
17
R267
18
AUXFAULTN2
R268
20
R269 R270 R271
AUXOUT1
27
FAULTN1
FON1
37
AUXFAULTN1
ENN1
36
PGOODN1
GND1
26
FAULTN2
GND2
39
AUXPGOODN2
ENN2
16
19
PGOODN2
FON2
15
14
ON2
13
AUXON2 AUXOUT2
25
8
10K 10K
B
C265
42
35
9
9
6 R261
R259
42
37
35
VCC
R260
R258
42
42
100 100 100 100 100 100 100 100 100 100 100 100
P16_PEP
7
AUXIN2
21
12VIN2
22
12VSENSE2
23
12VGATE2
24
12VOUT2
S20_3VAUX
3VOUT2
12
3VGATE2
11
3VSENSE2
10
3VIN2
W24
B
9
1.0UF
U48
S20_3V W25
0.013
C269
0.047UF
W26
A
8
7
6
NMOSFET
R292
S20_12V
4
3
2
15
D D D D
Q16
R284
5
10
0.015UF
51 4
3
S S S G 2
Q14
NMOSFET
1
A
R290
S S S G
1
C267
R286
8
7
10
D D D D
6
R282
5
0.008
R288
TITLE
EB-LOGAN-23
HOT PLUG CONTROL PORTS 16-20 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:57 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 18 OF 52 1
8
7
6
5
+3V3
37
14
11
P23_RSTN
IN
1
OE_N
2
A
3
GND
3
+3V3
SN74LVC1G125
D
4
5
37
14
11
P15_RSTN
IN
1
OE_N
2
A
3
GND
1
+3V3
+3V3
SN74LVC1G125
VCC
2
SN74LVC1G125
VCC
5
37
14
10
P7_RSTN
IN
1
OE_N
2
A
3
GND
VCC
5
D R1
10K
Y
4
SLOT_RSTN23
OUT
41
42
43
SN74LVC1G125
14
10
P22_RSTN
IN
1
OE_N
2
A
3
VCC
5
37
Y
4
10
P14_RSTN
IN
R2
10K
GND
14
SLOT_RSTN22
OUT
41
42
43
1
OE_N
2
A
3
11
P21_RSTN
IN
1
OE_N
2
A
3
GND
14
9
P20_RSTN
IN
1
VCC
5
37
Y
4
14
11
P13_RSTN
IN
R3
10K
2 3
OE_N
SLOT_RSTN21
OUT
41
42
43
1
A
3
GND
11
P19_RSTN
IN
VCC
5
37
Y
4
14
9
P12_RSTN
IN
R4
10K
GND
OE_N
2
A
3
GND
1 2
SLOT_RSTN20
OUT
42
3
44
10
P18_RSTN
IN
1
OE_N
2
A
3
5
37
4
11
P11_RSTN
IN
R11
10K
Y
14
37
14
11
IN
OE_N
2
A
3
GND
9
P16_RSTN
IN
1
SLOT_RSTN19
2
A
3
GND
P6_RSTN
IN
OUT
41
42
1
OE_N
2
A
3
43
OUT
41
42
43
3
GND
5
37
4
14
10
P5_RSTN
IN
R23
5
Y
4
37
14
10
P10_RSTN
IN
SLOT_RSTN13
R12
SLOT_RSTN18
OUT
41
42
43
2
A
3
OUT
41
42
43
OE_N
A
3
GND
VCC
5
37
4
14
9
1
P4_RSTN
IN
R25
2
SLOT_RSTN12
OUT
42
3
44
VCC
37
Y
4
14
11
IN
R13
10K
SLOT_RSTN17
OUT
41
42
43
OE_N
A
3
GND
5
37
4
14
10
P3_RSTN
IN
37
4
9
P8_RSTN
IN
R14
10K
Y
14
SLOT_RSTN16
OUT
42
44
U11
1
R26
SLOT_RSTN11
2
A
3
GND
R1285 SLOT_WAKEN0
1K 1K 1K 1K
R1289 SLOT_WAKEN4
1K 1K 1K 1K
R1293 SLOT_WAKEN8 R1294 SLOT_WAKEN9
1K 1K 1K 1K
R1297 SLOT_WAKEN12
1K 1K 1K 1K
R1301 SLOT_WAKEN16
1K 1K 1K 1K
R1305 SLOT_WAKEN20
R1286 SLOT_WAKEN1 R1287 SLOT_WAKEN2 R1288 SLOT_WAKEN3
R37
4
SLOT_RSTN6
OUT
42
R44
SLOT_RSTN5
OUT
41
VCC
42
43
5 R1280
10K
A
GND
Y
4
SLOT_RSTN4
OUT
42
OUT
41
42
43
OE_N
2
A
3
GND
VCC
44
5
4
VCC
5
Y
4
VCC
5
R1292 SLOT_WAKEN7
R1295 SLOT_WAKEN10 R1296 SLOT_WAKEN11
R1298 SLOT_WAKEN13 R1299 SLOT_WAKEN14 R1300 SLOT_WAKEN15
R1302 SLOT_WAKEN17 R1303 SLOT_WAKEN18 R1304 SLOT_WAKEN19
R1306 SLOT_WAKEN21 R1307 SLOT_WAKEN22 R1308 SLOT_WAKEN23
2
OUT OUT OUT OUT
3
OUT OUT OUT OUT
4
OUT OUT OUT OUT
4
OUT OUT OUT OUT
5
OUT OUT OUT OUT
5
42
42 2
42
42
42
42 3
42
42
42
42 42 42
42
42 42 42
C
42
42 42 42
42
42 42 42
R1281
10K
Y
R1291 SLOT_WAKEN6
44
5
4
R1290 SLOT_WAKEN5
OUT OUT OUT OUT
SLOT_RSTN3
OUT
41
42
OUT
42
44
43
SN74LVC1G125
VCC
5
Y
4
37
14
9
P2_RSTN
IN
R33
SLOT_RSTN10
OUT
41
42
1
OE_N
2
A
3
43
R1282
10K
GND
SLOT_RSTN2
U113
B
SN74LVC1G125
VCC
5
37
Y
4
14
10
P1_RSTN
IN
R34
10K
OE_N
VCC
Y
1
SLOT_RSTN9
OUT
41
42
43
1
OE_N
2
A
3
GND
R1283
10K
Y
4
VCC
5
SLOT_RSTN1
OUT
41
42
OUT
42
44
43
U114
SN74LVC1G125
5
5
10K
OE_N
U106
VCC
1K 1K 1K 1K
U112
GND
2
43
SN74LVC1G125
VCC
10K
1
42
U111
SN74LVC1G125
P9_RSTN
Y
2
U105
5
41
U110
Y
OE_N
OUT
SN74LVC1G125
10K
1
SLOT_RSTN7
10K
1
SN74LVC1G125
VCC
VCC
GND
U104
10K
OE_N
VCC
Y
A
SN74LVC1G125
14
9
SLOT_RSTN14
10K
2
4
SN74LVC1G125
Y
OE_N
Y
U109
GND
U10
37
14
R22
10K
1
SN74LVC1G125
1
4
A
U9
P17_RSTN
37
SN74LVC1G125
VCC
GND
B
5
U103
SN74LVC1G125
14
Y
OE_N
U8
37
VCC
U102
A
1
43
SN74LVC1G125
SN74LVC1G125
14
42
SN74LVC1G125
10K
OE_N
2
U7
37
41
R36
10K
U108
GND
U6
37
OUT
SN74LVC1G125
SN74LVC1G125
C
SLOT_RSTN15
U101
SN74LVC1G125
14
4
SN74LVC1G125
U5
37
Y
U100
U4
37
R15
10K
SN74LVC1G125
VCC
5
37
4
9
P0_RSTN
IN
R35
10K
Y
14
SLOT_RSTN8
OUT
42
44
OE_N
2
A
3
GND
R1284
10K
Y
4
SLOT_RSTN0
C661
C662
C663
C664
C665
C666
C667
C668
C669
C670
C671
C672
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
U115
0.1UF
U107
1
A
A
TITLE
EB-LOGAN-23
SLOT RESETS AND WAKE PULL-UPS SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:57 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 19 OF 52 1
8
7
6
5
4
3
2
1
C281
C279
10UF
1.0UF
C278
0.1UF
C280
C277
0.1UF
0.1UF
C276
C275
0.1UF
0.1UF
C274
0.1UF
D
1%
16V
C273
10UF
DNP 0402 DNP 0402 DNP 0402 1%
400MA
22PF
DNP 0402 DNP 0402
2
2
R296
1
R294
1
C270
X1
FB1
120OHM 0805
D
22PF
5%
1%
1%
R299
1%
R297
R295
+3V3 R306
10 0603
C271
ICS841484
1
XTAL_IN
2
XTAL_OUT
31
VDD
4
VDD
14
VDD
24
VDD
29
VDDA
28
REF_IN
21
33.2
R301
Q0
5
R302
FSEL1
nQ0
6
Q1
7
OE_REFOUT
nQ1
8
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
30
REF_SEL
22
FSEL0
23 20
REF_OUT
YEL
TP2
C
25
SSM
Q3
12
R293
IN
27
BYPASS
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
9
20
R305 R310
NC NC NC NC
C28
678005005
C32 C36 C38
CG_SATA_CLKP CG_SATA_CLKN CG_SMA_CLKP CG_SMA_CLKN J119
1
1
2
2
3
3
4
4
5
5
6
6
7
7
CONNSMA
R318
ICS_SSM
1%
33
R309
R317
11
0.1UF 0.1UF 0.1UF 0.1UF
R316
nQ2
R304
R315
IREF
MR_nOE
20
R308
R314
26
OUT OUT
R303
R313
Q2
10
3
C CGCLKP CGCLKN
R307
R312
IN
R311
33
ICS_FS
5
4
MTG1
MTG1
MTG2
MTG2
1 J121 2
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
475
U49 3
221789-0
J120
B
R300
R298
CONNSMA 5
4
B
1
10K DNP
2
3
221789-0
J7
CONNSMA 5
PLACE R317 & R318 U51 678005005
1
2
3
3
221789-0
2
221789-0
A
1
1
2
2
3
3
4
4
5
5
6
6
7
7
MTG1
MTG1
MTG2
MTG2
DNP DNP
4
SATAIN_CLKP SATAIN_CLKN SATAIN_RSTN
R70
4
1
R57
5
OUT
OUT OUT
20 20
32
DNP DNP
CONNSMA
R58
J5
R56
+3V3
A
J8 HDR_2x5
21
OUT
20
IN
20
IN
MAIN_CLKP SMAIN_CLKP CGCLKP SATAIN_CLKP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
J6
VERT-SM
10
MAIN_CLKN SMAIN_CLKN CGCLKN SATAIN_CLKN
OUT
21
IN
20
IN
20
TITLE
EB-LOGAN-23
2.00MM NO-SHROUD
CLOCK PLACE J6 CLOSE TO U51 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:58 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 20 OF 52 1
8
7
6
5
4
3
2
1
+3V3 FB3
120OHM 0805
C303
C752
0.1UF
C302
C751
0.1UF
1.0UF
C299
0.1UF
0.1UF
C298
0.1UF
C301
C297
0.1UF
0.1UF
C296
0.1UF
C300
C295
0.1UF
400MA
10UF
C294
1.0UF
5%
C293
D
R386
0.1UF
10 0603
D
57
VDD6
48
VDD5
DIF_11_P
59
41
VDD4
DIF_11_N
58
24
VDD3
17
VDD2
DIF_10_P
54
8
VDD1
DIF_10_N
53
1
VDD0 DIF_9_P
51
DIF_9_N
50
DIF_8_P
46
DIF_8_N
45
DIF_7_P
43
64
DIF_IN_P
3
DIF_IN_N
60
A
2
2
3
3
4
4
5
5
6
6
7
7
MTG1
MTG1
MTG2
MTG2
33.2 33.2
R398
BS08CLKP_R BS08CLKN_R
33.2 33.2
R400
BS12CLKP_R BS12CLKN_R
33.2 33.2
R402
BS16CLKP_R BS16CLKN_R
33.2 33.2
R1638
BS20CLKP_R BS20CLKN_R
33.2 33.2
R1640
33.2 33.2
R408
33.2 33.2
R410
OUT OUT
24
OUT OUT
25
OUT OUT
25
OUT OUT
25
OUT OUT
25
OUT OUT
25
OUT OUT
25
OUT OUT
25
OUT OUT
25
24
24
25
25
DIF_5_P
27
DIF_5_N
28
DIF_4_P
22
DIF_4_N
23
DIF_3_P
19
BS06CLKP BS06CLKN
R399
25
25
OE8_N
21
OE4_N
DIF_3_N
20
18
OE3_N
DIF_2_P
14
DIF_2_N
15
13
OE2_N DIF_1_P
11
OE1_N
DIF_1_N
12
OE0_N
DIF_0_P
6
DIF_0_N
7
BYPASS_N_PLL
9
30
HIGH_BW_N
32
SMBCLK
0.1UF 0.1UF
C50
0.1UF 0.1UF
C58
C56
C59
25
25
25
25
SMAOUT_CLKP SMAOUT_CLKN SATAOUT_CLKP SATAOUT_CLKN
62
B
J122
CONNSMA GND6
56
GND5
49
GND4
40
GND3
25
GND2
16
GND1
9
33
SMBDAT
GND0
4
29
N_C
AGND
63
4
5 1
3
2
221789-0
R1645
35
IREF
R1644
VTTPWRGD_N_PD
R411
R1643
36
R409
R1642
FS0
R1641
R427
FS1
61
11
BS20CLKP BS20CLKN
R426
34
12
R1639
R425
13
BS16CLKP BS16CLKN
R424
FS2
SMAOUT_CLKP_R SMAOUT_CLKN_R
R403
R423
OE5_N
BS12CLKP BS12CLKN
R422
OE6_N
26
R401
R421
39
BS08CLKP BS08CLKN
R420
OE7_N
31
10
BS06CLKP_R BS06CLKN_R
J123
CONNSMA 4
5
U51 1
DNP 10K DNP 10K 10K 10K
1
37
14
678005005
1
38
DIF_6_N
R419
S8B
DIF_6_P
R397
R418
S8A
OE9_N
BS04CLKP BS04CLKN
R417
S7B
R396
R416
S7A
33.2 33.2
R395
R415
S6B
BS04CLKP_R BS04CLKN_R
BS02CLKP BS02CLKN
R414
S6A
R394
R413
S5B
33.2 33.2
R393
R412
S4B
S5A
52
15
R378
8
S4A
BS02CLKP_R BS02CLKN_R
BS00CLKP BS00CLKN
R1649
7
S3B
42
5
16
R392
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
6
S3A
DIF_7_N
R385
5
S2B
R384
4
S1B
S2A
R383
3
S1A
R382
2
OE10_N
10
R380
1
B
33.2 33.2
R391
R1647
S11
BS00CLKP_R BS00CLKN_R
BGCLK1P BGCLK1N
24
C
55
44
SM_SW8
R390
OUT OUT
OE11_N
47
SILKSCREEN LABEL: SWITCH S11 POS DESCRIPTION ------------------1 P0_CLK_EN 2 P2_CLK_EN 3 P4_CLK_EN 4 P6_CLK_EN 5 P8_CLK_EN 6 P12_CLK_EN 7 P16_CLK_EN 8 P20_CLK_EN -------------------
33.2 33.2
R433
C
BGCLK1P_R BGCLK1N_R
BGCLK0P BGCLK0N
R389
R432
IN IN
VDDA
2
R388
1%
20
MAIN_CLKP MAIN_CLKN
33.2 33.2
R387
20
BGCLK0P_R BGCLK0N_R
475 0402
R381
R379
R377
R376
R375
R374
R373
R372
R371
R1637
R1636
R1635
IDT ICS9DB1200yGLF
10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K DNP 10K
R1634
+3V3
3
2
221789-0
SATAOUT_CLKP SATAOUT_CLKN
A
TITLE
EB-LOGAN-23
J124
CLOCK BUFFER - 1 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:00:58 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 21 OF 52 1
8
7
6
5
4
3
2
1
P08CLK - DUT PORT 8 CLK LP8CLK - LOCAL CLOCK GEN. PORT 8 CLK P8SHXXCLK - TO SLOT CLK HEADERS
PLACE 470 AND 56 OHM RESISTORS CLOSE TO DESTINATION. +3V3
+3V3 +3V3
D
45
nQA3
44
OEB3
R647
1
C147
C146
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
DNP DNP
J62
C145
OUT
C144
C138
22
C143
YEL
TP129
44
C142
6
C141
5 P8_SATARSTN
6
C140
5
MTG2
C139
MTG1
MTG2
3
R632
R629
R627
R625
R623
R621
R619
R617
R615
R613
R611
R609
R607
R605
470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C156
6
OUT OUT OUT OUT OUT OUT OUT OUT
25
6 25 25 25 25 25 25
QB1
21
nQB1
20
QB2
38
nQB2
39
QB3
40
nQB3
41
VCC VCC
12
VCC
18
VCC
NC
19
VCC
VEE
6
25
VCC
VEE
13
30
VCC
VEE
24
36
VCC
VEE
31
42
VCC
VEE
37
43
VCC
VEE
48
10
P8SH16_CLKP P8SH16_CLKN P8SATA_CLK1P P8SATA_CLK1N P8SATA_CLK2P P8SATA_CLK2N P8SMA_CLKP P8SMA_CLKN
C157 C158 C159 C160 C161 C162 C163
25 22 22 22
C
22 22 22
R634
32
22
R631
OEB2
23
R628
33
QB0 nQB0
R626
OEB1
R624
OEB0
34
OUT OUT OUT OUT OUT OUT OUT OUT
11
DIV_SELB
R622
35
+3V3
MTG1
nCLK0
R620
U17
5
R618
P8_OEB0 P8_OEB1 P8_OEB2 P8_OEB3
14
CLK0
R616
IN IN
4
C155
R614
LP8_CLKP LP8_CLKN
C154
R612
49
C153
R610
18
CLK_SEL
C152
R608
17
7
C151
R606
GND
QA3
P8ECLK_SEL
CLK1
C150
R604
nCLK
nQA2
46
9
P08CLKP P08CLKN P8SH0_CLKP P8SH0_CLKN P8SH2_CLKP P8SH2_CLKN P8SH4_CLKP P8SH4_CLKN
C149
R602
CLK
13
QA2
47
C148
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
R502
49
12
17
nCLK1
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
R585
nQ
nQA1
8
R584
Q
16
PLACE R502 CLOSE TO U18 100
NC
QA1
R568
20
OEA3
R567
NC
29
R566
16
15
R550
NC
NC
nQA0
R549
3
15
OEA2
R548
NC
NC
14
28
R532
2
P8JA_FSEL0
QA0
DIV_SELA
R531
BW_SEL
9
OEA1
R530
6
F_SEL0
2
OEA0
27
R514
PLL_SEL
7
26
R513
1
F_SEL1
P8_OEA0 P8_OEA1 P8_OEA2 P8_OEA3
R512
MR
P8ECLK_ENABLE
R511
3
R652
R648 7
3 P8_SATACLKN
11
R653
4
7
2
R645
0 0
R650
1
OE
R505
5
DNP DNP
678005005
4
19
VDD
4
C
VDDO
ICS853S1208I 10
P8JA_PLL_SEL P8JA_BW_SEL
2 P8_SATACLKP
VDDA
180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180
C137
10UF
8
DNP DNP
C136
0.1UF
C135
0.1UF
ICS874001I-02
+3V3
1
R603
C136 CLOSE TO VDDA
5%
R586
R501
R504
R503
D +3V3 10 0603
U18
B
22 678005005
22 22
44
22
P8SATA_CLK1P P8SATA_CLK1N
IN IN
P8_SATARSTN
IN
678005005
1
1
1
2
2
22
3
3
22
1
2
2
3
4
4
3
4
5
5
4
5
5
6 7
6
6
6
7
7
7
44
22
IN IN IN
P8SATA_CLK2P P8SATA_CLK2N P8_SATARSTN
OFF OFF OFF OFF ON
B
J72
J74
CONNSMA
4
MTG1
MTG1
MTG1
MTG2
MTG2
MTG2
MTG2
3
5
5
1
1
2
2
221789-0
J57
J56
S19:1 S19:3 S19:4 S19:5 S19:6
P8SMA_CLKP P8SMA_CLKN
IN IN
CONNSMA
MTG1
DEFAULT DIPSW SETTING
22
4
3
221789-0
(SATACLK) (PLL) (2.2MHZ) (U17 OUTPUT ON) (100MHZ) U18 OUTPUTS OFF (ENABLE) ON (DISABLE)
R500
R499
R498
R497
R496
+3V3
A
A
4.7K 4.7K 4.7K 4.7K 4.7K
S20 S19
SM_SW6 1 2 3 4 5 6
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
SM_SW8 1
P8ECLK_SEL
2
11 10 9 8 7
3
P8JA_PLL_SEL P8JA_BW_SEL P8ECLK_ENABLE P8JA_FSEL0
4 5 6 7 8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A
S7B
S8A
S8B
16 P8_OEA0 15 P8_OEA1 14 P8_OEA2 13 P8_OEA3
TITLE
EB-LOGAN-23
12 P8_OEB0 11 P8_OEB1
CLOCK SELECTOR DUT PCLK 8
10 P8_OEB2 9 P8_OEB3
SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Tue Aug 10 13:51:12 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 22 OF 52 1
8
7
6
5
4
3
2
1
P16CLK - DUT PORT 16 CLK LP16CLK - LOCAL CLOCK GEN. PORT 16 CLK P16SHXXCLK - TO SLOT CLK HEADERS
PLACE 470 AND 56 OHM RESISTORS CLOSE TO DESTINATION. +3V3 +3V3
+3V3
OEB1
33
OEB2
32
OEB3
C214
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
DNP DNP
J64
C213
OUT
C212
23
C211
44
C210
TP131
C209
YEL
C208
6
6
C207
5 P16_SATARSTN
C206
5
1
VCC
3
VCC
R470
R468
R466
R464
R462
R460
R458
R456
R454
R452
R450
R448
R446
R444
R442
R440
R369
470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C223
6
OUT OUT OUT OUT OUT OUT OUT OUT
25
6 25 25 25 25 25 25
QB0
23
nQB0
22
QB1
21
nQB1
20
QB2
38
nQB2
39
QB3
40
nQB3
41
12
VCC
18
VCC
NC
19
VCC
VEE
6
25
VCC
VEE
13
30
VCC
VEE
24
36
VCC
VEE
31
42
VCC
VEE
37
43
VCC
VEE
48
10
P16SH20_CLKP P16SH20_CLKN P16SATA_CLK1P P16SATA_CLK1N P16SATA_CLK2P P16SATA_CLK2N P16SMA_CLKP P16SMA_CLKN
C224 C225 C130 C131 C132 C133 C134
25 23 23
C
23 23 23 23
R471
OEB0
34
R469
U15
35
OUT OUT OUT OUT OUT OUT OUT OUT
11
DIV_SELB
R467
P16_OEB0 P16_OEB1 P16_OEB2 P16_OEB3
14
C222
R465
nCLK0
44
R463
5
nQA3
R461
CLK0
C221
R459
4
45
R457
LP16_CLKP LP16_CLKN
QA3
R453
CLK_SEL
C220
R451
7
46
R449
P16ECLK_SEL
QA2 nQA2
C219
R447
GND
CLK1
C218
R445
nCLK
9
47
C217
R443
13
IN IN
nCLK1
P16CLKP P16CLKN P16SH6_CLKP P16SH6_CLKN P16SH8_CLKP P16SH8_CLKN P16SH12_CLKP P16SH12_CLKN
C216
R441
51
8
C215
56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56
CLK
nQA1
17
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
R439
R367
51
12
16
R438
18
QA1
R437
nQ
OEA3
R436
17
29
PLACE R367 CLOSE TO U16 100
Q
15
R435
20
nQA0
R434
NC
NC
OEA2
R431
4
16
14
28
2
R430
NC
NC
QA0
DIV_SELA
R429
3
15
OEA1
R428
NC
NC
P16JA_FSEL0
OEA0
27
R761
BW_SEL
9
C205
MTG2
6
F_SEL0
R643
MTG1
PLL_SEL
7
+3V3
7
MTG2
1
F_SEL1
26
R636 R639
7 MTG1
MR
P16_OEA0 P16_OEA1 P16_OEA2 P16_OEA3
P16ECLK_ENABLE
R760
3 P16_SATACLKN
11
R407
3
OE
R406
2
4
5
2
R640
R638 1
4
R635
0 0
VDD
DNP DNP
678005005
2 P16_SATACLKP
19
R405
P16JA_PLL_SEL P16JA_BW_SEL
1
VDDO
ICS853S1208I 10
+3V3
C
VDDA
DNP DNP
8
R404
C204
ICS874001I-02
180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180
C203
10UF
5%
+3V3
C85 CLOSE TO VDDA
R366
0.1UF
0.1UF
C202
10 0603
R368
D
R455
D
U16
23 678005005
B 1 23 23
44
23
P16SATA_CLK1P P16SATA_CLK1N
IN IN
P16_SATARSTN
IN
678005005
1
1
1
2
2
23
2
2
3
3
23
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
44
23
IN IN IN
P16SATA_CLK2P P16SATA_CLK2N P16_SATARSTN
23
P16SMA_CLKP P16SMA_CLKN
IN IN
J54
J55
CONNSMA 4
MTG1
MTG1
MTG1
MTG1
MTG2
MTG2
MTG2
MTG2
3
CONNSMA 5
5
1
1
2
2
221789-0
J42
J41
B
4
3
221789-0
DEFAULT DIPSW SETTING S17:1 S17:3 S17:4 S17:5 S17:6
OFF OFF OFF OFF ON
(SATACLK) (PLL) (2.2MHZ) (U15 OUTPUT ON) (100MHZ)
U16 OUTPUTS OFF (ENABLE) ON (DISABLE)
R759
R657
R656
A
R655
R654
+3V3
A
S18
SM_SW6 1 2 3 4 5 6
S1A
S1B
S2A
S2B S3B
S3A S4A
S4B
S5A
S5B
S6A
S6B
12
4.7K 4.7K 4.7K 4.7K 4.7K
SM_SW8 S17
1 2
P16ECLK_SEL
3
11 10 9 8 7
4
P16JA_PLL_SEL P16JA_BW_SEL P16ECLK_ENABLE P16JA_FSEL0
5 6 7 8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A
S7B
S8A
S8B
P16_OEA0 P16_OEA1 P16_OEA2 P16_OEA3 P16_OEB0 P16_OEB1 P16_OEB2 P16_OEB3
16 15 14 13 12 11 10 9
TITLE
EB-LOGAN-23
CLOCK SELECTOR DUT PCLK 16 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Tue Aug 10 13:51:21 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 23 OF 52 1
8
7
6
5
4
3
2
1
PXXCLK - DUT CLK LPXXLCK - LOCAL CLOCK GEN. PORT CLK
1
2
3
3
4
4
5
5
6
6
J9
VERT-SM
LP0_CLKN P00CLKN P0_SATACLKN
IN OUT IN
45
2
2 P0_SATACLKP
4
3
3 P0_SATACLKN
7
7
6
MTG1
MTG1
5
5 P0_SATARSTN
24
MTG2
MTG2
6
6
OUT OUT
24 24
YEL
TP125
678005005
J66
2.00MM NO-SHROUD
J67
CONNSMA
J58
CONNSMA
5
4
4
5
678005005
HDR_2X3
46 6 24
LP2_CLKP P02CLKP P2_SATACLKP
IN OUT IN
1 3 5
1 3 5
2
2
4
4
6
6
J10
VERT-SM
LP2_CLKN P02CLKN P2_SATACLKN
IN OUT IN
46
1
1
2
2 P2_SATACLKP
4
4
3
3 P2_SATACLKN
7
7 5
5 P2_SATARSTN
6
6
6
MTG1
24
MTG2
MTG1 MTG2
OUT OUT
1
24
1
24
2
3
3
2
1
1
2
2
3
3
4
4
5
5
6
6
7
7
DNP DNP
IN OUT IN
1
4
G0_SATACLKP G0_SATACLKN
YEL
TP126
221789-0
221789-0
2.00MM NO-SHROUD
J59
MTG1
MTG1
MTG2
MTG2
R334
6 24
2
R328
45
D
1
D OUT OUT
24 24
DNP DNP
HDR_2X3
LP0_CLKP P00CLKP P0_SATACLKP
R327
678005005
1
R333
+3V3
SHXXCLK - SLOT HDR. CLK
J21
678005005
2
3
3
4
4
6
6
5
5
J11
VERT-SM
LP4_CLKN P04CLKN P4_SATACLKN
IN OUT IN
47
7
7 5
5 P4_SATARSTN
YEL
6
6
6
MTG1
24
MTG2
24 24
HDR_2x5
7
MTG1 MTG2
TP127
21
OUT IN
2.00MM NO-SHROUD
24
J60
IN
GCLK0P BGCLK0P G0_SATACLKP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
J18
VERT-SM
HDR_2X3
48 6 24
LP6_CLKP P06CLKP P6_SATACLKP
IN OUT IN
1
1
2
2
3
3
4
4
5
5
6
6
J12
VERT-SM
LP6_CLKN P06CLKN P6_SATACLKN
IN OUT IN
48
1
1
2
2 P6_SATACLKP
4
4
3
3 P6_SATACLKN
7
7
6
MTG1
MTG1
5
5 P6_SATARSTN
24
MTG2
MTG2
6
6
OUT OUT
HDR_2X3
50 6 24
IN OUT IN
1
1
2
2
3
3
4
4
5
6
6
5
J14
VERT-SM
LP12_CLKN P12CLKN P12_SATACLKN
IN OUT IN
7
50 6
MTG1
24
MTG2
4
24
C
YEL
TP128
J20
J17
CONNSMA
5
678005005
LP12_CLKP P12CLKP P12_SATACLKP
IN
4
4
5 1
1
2
2 P12_SATACLKP
3
3 P12_SATACLKN
OUT OUT
24
2
24
3
3
5
5 P12_SATARSTN
MTG2
6
6
221789-0
YEL
TP130
1
1
2
2
3
3
4
4
5
5
6
6
7
7
G1_SATACLKP G1_SATACLKN
2
7 MTG1
+3V3
678005005
J61
1
21
24
2.00MM NO-SHROUD
4
G0_SATACLKN
IN
24
CONNSMA
1
BGCLK0N
7
OUT
2.00MM NO-SHROUD
678005005
C
10
GCLK0N
R335
2
OUT OUT
R329
1
3 P4_SATACLKN
DNP DNP
24
1
2 P4_SATACLKP
3
221789-0
MTG1
MTG1
MTG2
MTG2
R336
6
LP4_CLKP P04CLKP P4_SATACLKP
IN OUT IN
2
4
R330
47
1
4
OUT OUT
24 24
DNP DNP
HDR_2X3
1
J22
2.00MM NO-SHROUD
J63 678005005
HDR_2X3
52 6
B
24
LP20_CLKP P20CLKP P20_SATACLKP
IN OUT IN
1
1
3
3
5
5
VERT-SM
2
2
4
4 6
6
J16
LP20_CLKN P20CLKN P20_SATACLKN
IN OUT IN
1
1
2
2 P20_SATACLKP
4
4
3
3 P20_SATACLKN
7
52
OUT OUT
24
HDR_2x5
24
7
OUT
GCLK1P
7
6
MTG1
MTG1
5
5 P20_SATARSTN
24
MTG2
MTG2
6
6
21
YEL
TP132
24
2.00MM NO-SHROUD
BGCLK1P
IN
G1_SATACLKP
IN
J65
2
4
4
5
6
6
7
7
8
8
9
9
10
J19
10
GCLK1N BGCLK1N G1_SATACLKN
OUT
7
IN
21
IN
24
B
2.00MM NO-SHROUD
R145
R143
DNP DNP R146
DNP DNP
R144
R105
R117 R118
R106
P20_SATACLKP P20_SATACLKN
DNP DNP
R332
P12_SATACLKP P12_SATACLKN
DNP DNP
R326
2
3
5
+3V3
DNP DNP
R331
R325
+3V3
DNP DNP
R323
R321
DNP DNP R324
P6_SATACLKP P6_SATACLKN
1
3
VERT-SM
+3V3
DNP DNP
R322
R151
R319
P4_SATACLKP P4_SATACLKN
R320
R152
P2_SATACLKP P2_SATACLKN
DNP DNP
R150
R148
DNP DNP
P0_SATACLKP P0_SATACLKN
+3V3
DNP DNP
R149
+3V3
DNP DNP
R147
+3V3
1
A
A
TITLE
EB-LOGAN-23
CLOCK SELECTOR DUT PCLK 0-20, GCLK 0-1 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:59 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 24 OF 52 1
8
7
6
5
4
3
2
1
SXXCLK - SLOT CLK BSXXLCK - BUFFER SLOT CLK LSXXCLK - LOCAL CLOCK GEN. SLOT CLK SHXXCLK - SLOT HDR.CLK
D D HDR_2x6 678005005
1
2
2
3
3
4
4
5
5
2
6
6
21
7
7
HDR_2x6
45 2 21 22
25
IN OUT IN IN IN
LS0_CLKP S0_CLKP BS00CLKP P8SH0_CLKP S0_SATACLKP
1 3 5 7 9 11
2
2
3
4
4
5
6
6
7
8
8
9
10
1
11
12
J23
VERT-SM
LS0_CLKN S0_CLKN BS00CLKN P8SH0_CLKN
10 12
S0_SATACLKN
IN OUT IN IN IN
49
1
45
4
S0_SATACLKP S0_SATACLKN
OUT OUT
S0_SATA_RSTN S0_SATA_WAKE
OUT
25
21
25
23
25
44
IN OUT IN IN IN
LS8_CLKP S8_CLKP BS08CLKP P16SH8_CLKP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
S8_SATACLKP
11
12
12
DNP
11
J31
VERT-SM
TP89
LS8_CLKN S8_CLKN BS08CLKN P16SH8_CLKN
IN OUT IN IN
S8_SATACLKN
IN
49 4
678005005
21
1
1
23
2
2
3
3
4
4
5
5
6
6
7
7
25
2.00MM NO-SHROUD
22
25
2.00MM NO-SHROUD
MTG1
MTG1
MTG2
MTG2
MTG1
MTG1
MTG2
MTG2
S8_SATACLKP S8_SATACLKN S8_SATA_RSTN S8_SATA_WAKE
OUT OUT
25
OUT
44
25
DNP
TP93
J27 J35
HDR_2x6 678005005
1
2
2
3
3
4
4
46
5
5
2
6
6
21
7
7
C HDR_2x6
46 2 21 22
25
IN OUT IN IN IN
LS2_CLKP S2_CLKP BS02CLKP P8SH2_CLKP
1
1
2
2
3
3
4
4
5
5
6
6
8
8
7 9
S2_SATACLKP
11
7 9
10
11
12
J24
VERT-SM
LS2_CLKN S2_CLKN BS02CLKN P8SH2_CLKN
10 12
S2_SATACLKN
IN OUT IN IN IN
50
1
4
S2_SATACLKP S2_SATACLKN
OUT OUT
S2_SATA_RSTN S2_SATA_WAKE
OUT
21
25
23
25
25
44
IN OUT IN IN IN
LS12_CLKP S12_CLKP BS12CLKP P16SH12_CLKP
1
1
2
2
3
3
4
4
5
5
6
6
8
8
7 9
S12_SATACLKP
DNP
11
7 9
10
10
11
12
12
J32
VERT-SM
TP90
LS12_CLKN S12_CLKN BS12CLKN P16SH12_CLKN S12_SATACLKN
IN OUT IN IN IN
50 4
678005005
21
1
1
23
2
2
3
3
4
4
5
5
6
6
7
7
25
2.00MM NO-SHROUD
22
25
2.00MM NO-SHROUD
MTG1
MTG1
MTG2
MTG2
MTG1
MTG1
MTG2
MTG2
S12_SATACLKP S12_SATACLKN S12_SATA_RSTN S12_SATA_WAKE
OUT OUT
25
OUT
44
C
25
DNP
TP94
J28 J36
HDR_2x6 678005005 1 2
2
3
3
4
4
5
5
3
6
6
21
7
7
HDR_2x6
47 3 21
B
22
25
IN OUT IN IN IN
LS4_CLKP S4_CLKP BS04CLKP P8SH4_CLKP S4_SATACLKP
1 3 5 7 9 11
2
2
3
4
4
5
6
6
7
8
8
9
10
10
12
12
1
11
J25
VERT-SM
LS4_CLKN S4_CLKN BS04CLKN P8SH4_CLKN S4_SATACLKN
IN OUT IN IN IN
51
1
47
5
S4_SATACLKP S4_SATACLKN
OUT OUT
S4_SATA_RSTN S4_SATA_WAKE
OUT
25
21
25
22
25
44
IN OUT IN IN IN
LS16_CLKP S16_CLKP BS16CLKP P8SH16_CLKP S16_SATACLKP
DNP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
12
12
11
11
J33
VERT-SM
TP91
LS16_CLKN S16_CLKN BS16CLKN P8SH16_CLKN
IN OUT IN IN
S16_SATACLKN
IN
51 5
678005005
21
1
1
22
2
2
3
3
4
4
5
5
6
6
7
7
25
2.00MM NO-SHROUD
22
25
2.00MM NO-SHROUD
MTG1
MTG1
MTG2
MTG2
MTG1
MTG1
MTG2
MTG2
S16_SATACLKP S16_SATACLKN S16_SATA_RSTN S16_SATA_WAKE
OUT OUT
25
OUT
44
25
DNP
TP95
B
J29 J37
HDR_2x6 678005005 1
1
2
2
3
3
4
4
48
5
5
3
6
6
21
7
7
HDR_2x6
48 3 21 23
25
IN OUT IN IN IN
LS6_CLKP S6_CLKP BS06CLKP P16SH6_CLKP S6_SATACLKP
1
1
2
2
3
3
4
4
5
5
6
6 8
7
7
8
9
9
10
11 VERT-SM
11
12
J26
LS6_CLKN S6_CLKN BS06CLKN P16SH6_CLKN
10 12
S6_SATACLKN
IN OUT IN IN IN
52 5
S6_SATACLKP S6_SATACLKN
OUT OUT
S6_SATA_RSTN S6_SATA_WAKE
OUT
25
21
25
23
44
25
IN OUT IN IN IN
LS20_CLKP S20_CLKP BS20CLKP P16SH20_CLKP S20_SATACLKP
DNP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
12
11 VERT-SM
TP92
J34
LS20_CLKN S20_CLKN BS20CLKN P16SH20_CLKN S20_SATACLKN
IN OUT IN IN IN
52 5
678005005
21
1
1
23
2
2
3
3
4
4
5
5
6
6
7
7
25
2.00MM NO-SHROUD
23
25
2.00MM NO-SHROUD
MTG1
MTG1
MTG2
MTG2
MTG1
MTG1
MTG2
MTG2
S20_SATACLKP S20_SATACLKN S20_SATA_RSTN S20_SATA_WAKE
OUT OUT
25
OUT
44
25
DNP
TP96
J30 J38
A
A
TITLE
EB-LOGAN-23
CLOCK SELECTOR SLOTS 0-20 SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:00:59 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 25 OF 52 1
7
6
5
4
3
2
1
3
8
+3V3_PS
C
R506
W27
1K 0603
MMBT3904
1
U98
5%
B
2
E
A
C330
C334
C337
C340
C342
C344
C346
C348
C350
C352
C354
C356
C358
C360
C362
C364
C367
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C328
0.1UF
C332
C326
47UF
D
ON COM
PS_ENABLEN
2
B
OFF
MTG1 MTG2
+5V0_PS
42
OUT
3
+12V3_PS
0.1UF
C324
47UF
SPDT_TGL 1
0.1UF
C322
47UF
D
4 5
+5V0_PS
S1
+3V3_PS
+3V3_PS 0039291247
10 11
22 23
C
R508
24
C320
25V
21
J69
C317
RIGHT ANGLED
22UF
C316
20
47UF
10UF
22UF
C315
12
19
R507
9
18
150
8
17
330
C
16
DS2
7
15
DS1
6
14
GRN
5
13
+3.3V_4 -12V_1 GND_4 PS-ON GND_5 GND_6 GND_7 -5V +5V_3 +5V_4 +5V_5 GND_8
GRN
4
+3.3V_1 +3.3V_2 GND_1 +5V_1 GND_2 +5V_2 GND_3 PWROK +5VAB +12V3_1 +12V3_2 +3.3V_3
25V
3
C321
2
47UF
1
+12V3_PS +12V3_PS
+3V3
+12V1_PS
B
B
+12.0V -> +3.3V VR1
7
P12V22
8
R337
7
3
PTH08T240WAD
150
4
GND1
DS4
GND2
C369
Vo_Adj
47UF
22UF
USE W28/W29 FOR LIGHTLY LOADED SYSTEMS
1%
R509
C339
25V
C336
25V
22UF
C319
POPULATE W28/W29 FOR POWER SUPPLIES WITH ONLY 24-PIN CONNECTOR
VO_SEN-
Inhibit
GRN
P12V21
GND4
11 8
5
1.21K 0603
P12V12
GND3
25V
25V
C318
GND2
6
10UF
4
5
10UF
3
P12V11
GND1
TURBOTRANS
YEL
DNP
2
YEL
TP29
W29
POWER 8-PIN
1
SYNC
9
TP28
Vout
Track
1
6
10V
DNP
W28
0039301080
VO_SEN+
220UF
10
Vin
C366
2
+12V2_PS
J68
RIGHT ANGLED
A
A
WHT
TP32
WHT
TP31
WHT
TP30
TP27
WHT
TP26
WHT
TP25
WHT
TP24
WHT
TP23
WHT
TP22
WHT
TP19
TP21
TP18
WHT
TP17
WHT
TP16
TP20
GND TEST POINTS SCATTER AROUND BOARD
TITLE
EB-LOGAN-23
POWER CONNECTORS SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:00 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 26 OF 52 1
8
7
6
5
4
3
2
1
+12V3_PS
+3V3
VDD_IO, 3.3V
D
D CONN BANANA
A1
VIN1
VOUT1
J1
A2
VIN2
VOUT2
J2
A3
VIN3
VOUT3
J3
A4
VIN4
VOUT4
J4
A5
VIN5
VOUT5
J5 CONN BANANA
BLK
VOUT16
K6
VIN17
VOUT17
K7
C6
VIN18
VOUT18
K8
VOUT19
K9
VOUT20
K10
VOUT21
K11
VOUT22
L1
VOUT23
L2
VOUT24
L3
VOUT25
L4
VOUT26
L5
VOUT27
L6
VOUT28
L7
VOUT29
L8
VOUT30
L9
VOUT31
L10
VOUT32
L11
VOUT33
M1
VOUT34
M2
VOUT35
M3
VOUT36
M4
VOUT37
M5
VOUT38
M6
VOUT39
M7
VOUT40
M8
L12
A9
C383
S9
1 2 3
S1A
S1B
S2A
S2B
S3A
4 5 6
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
PS_IO_MARG0
11
PS_IO_MARG1
10
PS_IO_CTRL3
9
PS_IO_CTRL2
8
PS_IO_CTRL1
7
PS_IO_CTRL0
487K 487K
R517
487K
R519
R518
8% 4%
MARGINING CONTROL 1.96M 1.96M
1.96M
R520 R521
2%
R522
1%
A
VOUT_LCL
TRACK/SS
MARG0
VOUT41
M9
D12
MARG1
VOUT42
M10
VOUT43
M11
H12
SM_SW6
DIFFVOUT
C12
A12
DNP
B
MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN
PLLIN
MPGM
SGND
VFB
F12
VOSNSP
J12
VOSNSN
M12
D1
GND1
D2
GND2
D3
GND3
D4
GND4
D5
GND5
D6
GND6
E1
GND7
E2
GND8
E3
GND9
E4
GND10
E5
GND11
GND26
G4
E6
GND12
GND27
G5
E7
GND13
GND28
G6
F1
GND14
GND29
G7
F2
GND15
GND30
G8
F3
GND16
GND31
G9
F4
GND17
GND32
H1
F5
GND18
GND33
H2
F6
GND19
GND34
H3
F7
GND20
GND35
H4
F8
GND21
GND36
H5
F9
GND22
GND37
H6
G1
GND23
GND38
H7
G2
GND24
GND39
H8
G3
GND25
GND40
H9
B
R526
0 0
R525
K12
PLACE W33 CLOSE TO J112
DRVCC
R527
0 0
R528 R529
PLACE R526 & R527 CLOSE TO U57, NOISE-FREE ROUTING PLACE R528 & R529 CLOSE TO U1, NOISE-FREE ROUTING
B12
FSET
191K
TP38
INTVCC
A
TITLE
U56
EB-LOGAN-23
POWER REGULATOR - VDDIO SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
7
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:01:00 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
8
C
PLACE CLOSE TO U1
C385
A8
COMP
FB5
0.01UF
W33
R1390
E12
10K 10K
R1389
A7
26NH
6.5A
R524
A11
TP37
PGOOD
REG_2V5_VDDIO
R523
G12
RUN
+3V3_IO ROUTE AS POWER NET OR ISLAND
C396
K5
VIN16
C5
1.0UF
VOUT15
C395
VIN15
C4
10UF
K4
C3
C394
VOUT14
C392
VIN14
0.1UF
K3
C2
1.0UF
K2
VOUT13
C391
VOUT12
VIN13
C390
VOUT11
VIN12
C1
1 J79
51.1K
100K
100K
VIN11
B6
A10
DNP
J10 K1
+3V3
DNP
VOUT10
47UF
VIN10
1.0UF
B4
C389
J9
C388
VOUT9
47UF
VIN9
47UF
B3
C387
J8
47UF
J7
VOUT8
16V
VOUT7
VIN8
C386
VIN7
B2
100UF
VOUT6
B1
J78
C384
VIN6
J6
1
100PF
A6
B5
C
RED
18.2K
R516
R515
C381
10UF
10UF
C380
LTM4603
2
SHEET 27 OF 52 1
8
7
6
5
4
3
2
1
+12V3_PS
+3V3 D D A1
VIN1
VOUT1
J1
A2
VIN2
VOUT2
J2
A3
VIN3
VOUT3
J3
CONN BANANA
A4
VIN4
VOUT4
J4
RED
A5
VIN5
VOUT5
J5
VOUT14
K4
VIN15
VOUT15
K5
C4
VIN16
VOUT16
K6
C5
VIN17
VOUT17
K7
C6
VIN18
VOUT18
K8
VOUT19
K9
VOUT20
K10
VOUT21
K11
VOUT22
L1
VOUT23
L2
VOUT24
L3
VOUT25
L4
VOUT26
L5
VOUT27
L6
VOUT28
L7
VOUT29
L8
VOUT30
L9
VOUT31
L10
VOUT32
L11
VOUT33
M1
VOUT34
M2
VOUT35
M3
VOUT36
M4
VOUT37
M5
VOUT38
M6
VOUT39
M7
VOUT40
M8
DRVCC
PLLIN
PLACE W34 CLOSE TO J114
L12
A9
1 2 3
S1A
S1B
S2A
S2B
S3A
4 5 6
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
PS_CORE_MARG0
11
PS_CORE_MARG1
10
PS_CORE_CTRL3
9
PS_CORE_CTRL2
8
PS_CORE_CTRL1
7
PS_CORE_CTRL0
VOUT41
M9
MARG1
VOUT42
M10
VOUT43
M11
MPGM
SGND
D1
GND1
D2
GND2
D3
GND3
D4
GND4
D5
GND5
VFB
F12
VOSNSP
J12
VOSNSN
M12
D6
GND6
487K 487K
R535
E1
GND7
R536
E2
GND8
E3
GND9
E4
GND10
487K
R537
E5
GND11
GND26
G4
E6
GND12
GND27
G5
E7
GND13
GND28
G6
F1
GND14
GND29
G7
F2
GND15
GND30
G8
F3
GND16
GND31
G9
F4
GND17
GND32
H1
F5
GND18
GND33
H2
F6
GND19
GND34
H3
F7
GND20
GND35
H4
F8
GND21
GND36
H5
F9
GND22
GND37
H6
G1
GND23
GND38
H7
G2
GND24
GND39
H8
G3
GND25
GND40
H9
1.96M 1.96M
1.96M
A
MARG0
8% 4%
R538 R539
2%
R540
1%
MARGINING CONTROL
B12
FSET
B
R544
0 0 R541
C400
S6
TRACK/SS
D12
H12
SM_SW6
VOUT_LCL
C12
A12
DNP
B
MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN
DIFFVOUT
R543
K12
R545
0 0
R546 R547
PLACE R544 & R545 CLOSE TO U57, NOISE-FREE ROUTING PLACE R546 & R547 CLOSE TO U1, NOISE-FREE ROUTING
191K
DNP
TP42
INTVCC
A
TITLE
U59
EB-LOGAN-23
POWER REGULATOR - VDDCORE SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
7
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:01:00 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
8
C
PLACE CLOSE TO U1
C402
A8
COMP
FB6
0.01UF
W34
R1392
E12
10K 10K
R1391
A7
1%
A11
DNP
TP41
PGOOD
26NH
6.5A
1%
G12
REG_1V0_CORE
R542
C
RUN
+1V0_CORE ROUTE AS POWER NET OR ISLAND
316K
A10
+3V3
J113
C413
VIN14
C3
1.0UF
C2
1
C412
K3
10UF
VOUT13
C411
VIN13
C409
C1
BLK
0.1UF
K2
1.0UF
K1
VOUT12
C408
J10
VOUT11
VIN12
C407
VOUT10
VIN11
B6
47UF
VIN10
B5
1.0UF
B4
J114 CONN BANANA
C406
J9
C405
J8
VOUT9
47UF
VOUT8
VIN9
47UF
VIN8
B3
C404
B2
1
47UF
J7
C403
VOUT7
16V
VIN7
100UF
VOUT6
B1
C401
VIN6
J6
100PF
A6
VDD_CORE, 1.0V
127K
100K
R533
100K
R534
C398
10UF
10UF
C397
LTM4603
2
SHEET 28 OF 52 1
8
7
6
5
4
3
2
1
+12V3_PS
+3V3 D D A1
VIN1
VOUT1
J1
A2
VIN2
VOUT2
J2
A3
VIN3
VOUT3
J3
CONN BANANA
A4
VIN4
VOUT4
J4
RED
A5
VIN5
VOUT5
J5
VIN15
VOUT15
K5
C4
VIN16
VOUT16
K6
C5
VIN17
VOUT17
K7
C6
VIN18
VOUT18
K8
VOUT19
K9
VOUT20
K10
VOUT21
K11
VOUT22
L1
VOUT23
L2
VOUT24
L3
VOUT25
L4
VOUT26
L5
VOUT27
L6
VOUT28
L7
VOUT29
L8
VOUT30
L9
VOUT31
L10
VOUT32
L11
VOUT33
M1
VOUT34
M2
VOUT35
M3
VOUT36
M4
VOUT37
M5
VOUT38
M6
VOUT39
M7
VOUT40
M8
L12
A9
C417
S7
1 2 3
S1A
S1B
S2A
S2B
S3A
4 5 6
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
PS_PEA_MARG0
11
PS_PEA_MARG1
10
PS_PEA_CTRL3
9
PS_PEA_CTRL2
8
PS_PEA_CTRL1
7
PS_PEA_CTRL0
487K 487K
R553
487K
R555
1.96M 1.96M
1.96M
A
R554
8% 4%
R556 R557
2%
R558
1%
MARGINING CONTROL
TRACK/SS
MARG0
VOUT41
M9
D12
MARG1
VOUT42
M10
VOUT43
M11
H12
SM_SW6
VOUT_LCL
C12
A12
DNP
B
MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN
DIFFVOUT
MPGM
SGND
VFB
F12
VOSNSP
J12
VOSNSN
M12
D1
GND1
D2
GND2
D3
GND3
D4
GND4
D5
GND5
D6
GND6
E1
GND7
E2
GND8
E3
GND9
E4
GND10
E5
GND11
GND26
G4
E6
GND12
GND27
G5
E7
GND13
GND28
G6
F1
GND14
GND29
G7
F2
GND15
GND30
G8
F3
GND16
GND31
G9
F4
GND17
GND32
H1
F5
GND18
GND33
H2
F6
GND19
GND34
H3
F7
GND20
GND35
H4
F8
GND21
GND36
H5
F9
GND22
GND37
H6
G1
GND23
GND38
H7
G2
GND24
GND39
H8
G3
GND25
GND40
H9
B12
FSET
B
R562
0 0
R561
K12
PLLIN
R563
0 0
R564 R565
PLACE R562 & R563 CLOSE TO U60, NOISE-FREE ROUTING PLACE R564 & R565 CLOSE TO U1, NOISE-FREE ROUTING
191K
PLACE W35 CLOSE TO J115
DRVCC
A
TITLE
U62
EB-LOGAN-23
POWER REGULATOR - VDDPEA SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
7
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:01:00 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
8
C
PLACE CLOSE TO U1
C419
DNP
TP46
INTVCC
FB7
0.01UF
A8
COMP
R559
W35
R1394
E12
10K 10K
R1393
A7
1%
A11
DNP
TP45
PGOOD
26NH
6.5A
1%
G12
REG_1V0_PEA
R560
C
RUN
316K
A10
+3V3
+1V0_PEA ROUTE AS POWER NET OR ISLAND
C430
K4
C3
1.0UF
VOUT14
C429
VIN14
10UF
K3
C2
C428
VOUT13
C426
VIN13
0.1UF
K2
C1
1.0UF
K1
VOUT12
C425
J10
VOUT11
VIN12
C424
VOUT10
VIN11
B6
47UF
VIN10
B5
1.0UF
B4
J115
C423
J9
C422
J8
VOUT9
47UF
VOUT8
VIN9
47UF
VIN8
B3
C421
B2
1
47UF
J7
16V
VOUT7
C420
VIN7
100UF
VOUT6
B1
C418
VIN6
J6
100PF
A6
VDD_PEA, 1.0V
127K
100K
R551
100K
R552
C415
10UF
10UF
C414
LTM4603
2
SHEET 29 OF 52 1
8
7
6
5
4
3
2
1
+12V3_PS
+3V3 D D A1
VIN1
VOUT1
J1
A2
VIN2
VOUT2
J2
A3
VIN3
VOUT3
J3
CONN BANANA
A4
VIN4
VOUT4
J4
RED
A5
VIN5
VOUT5
J5
VIN15
VOUT15
K5
C4
VIN16
VOUT16
K6
C5
VIN17
VOUT17
K7
C6
VIN18
VOUT18
K8
VOUT19
K9
VOUT20
K10
VOUT21
K11
VOUT22
L1
VOUT23
L2
VOUT24
L3
VOUT25
L4
VOUT26
L5
VOUT27
L6
VOUT28
L7
VOUT29
L8
VOUT30
L9
VOUT31
L10
VOUT32
L11
VOUT33
M1
VOUT34
M2
VOUT35
M3
VOUT36
M4
VOUT37
M5
VOUT38
M6
VOUT39
M7
VOUT40
M8
PLACE W36 CLOSE TO J116
K12 L12
A9
C434
S8
1 2 3
S1A
S1B
S2A
S2B
S3A
4 5 6
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
PS_PEHA_MARG0
11
PS_PEHA_MARG1
10
PS_PEHA_CTRL3
9
PS_PEHA_CTRL2
8
PS_PEHA_CTRL1
7
PS_PEHA_CTRL0
VOUT_LCL
TRACK/SS
MARG0
VOUT41
M9
MARG1
VOUT42
M10
VOUT43
M11
MPGM
SGND
D1
GND1
D2
GND2
D3
GND3
D4
GND4
D5
GND5
VFB
F12
VOSNSP
J12
VOSNSN
M12
D6
GND6
487K 487K
R571
E1
GND7
R572
E2
GND8
E3
GND9
E4
GND10
487K
R573
E5
GND11
GND26
G4
E6
GND12
GND27
G5
E7
GND13
GND28
G6
F1
GND14
GND29
G7
F2
GND15
GND30
G8
F3
GND16
GND31
G9
F4
GND17
GND32
H1
F5
GND18
GND33
H2
F6
GND19
GND34
H3
F7
GND20
GND35
H4
F8
GND21
GND36
H5
F9
GND22
GND37
H6
G1
GND23
GND38
H7
G2
GND24
GND39
H8
G3
GND25
GND40
H9
1.96M 1.96M
1.96M
A
DIFFVOUT
D12
H12
SM_SW6
PLLIN
C12
A12
DNP
B
MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN
DRVCC
8% 4%
R574 R575
2%
R576
1%
MARGINING CONTROL
R580 R581
0 0
R582 R583
PLACE R580 & R581 CLOSE TO U63, NOISE-FREE ROUTING PLACE R582 & R583 CLOSE TO U1, NOISE-FREE ROUTING
B12
FSET
A
TITLE
U65
EB-LOGAN-23
POWER REGULATOR - VDDPEHA SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
7
6
5
2010
4
IDT
2.0
CHECKED BY
Thu Jul 01 15:01:01 2010 3
REV.
18-691-001 Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
8
C
B
0 0
R579
DNP
TP50
INTVCC
6.5A
PLACE CLOSE TO U1
DNP
A8
COMP
FB8
C436
W36
R1396
E12
10K 10K
R1395
A7
26NH
0.01UF
A11
DNP
TP49
PGOOD
R578
G12
REG_2V5_PEHA
R577
C
RUN
34.8K
A10
+3V3
+2V5_PEHA ROUTE AS POWER NET OR ISLAND
C447
K4
C3
1.0UF
VOUT14
C446
VIN14
10UF
K3
C2
C445
VOUT13
C443
VIN13
0.1UF
K2
C1
1.0UF
K1
VOUT12
C442
VOUT11
VIN12
C441
J10
VIN11
B6
47UF
VOUT10
1.0UF
VIN10
B5
C440
J9
B4
C439
J8
VOUT9
47UF
VOUT8
VIN9
47UF
VIN8
B3
C438
B2
J116 1
47UF
J7
C437
VOUT7
16V
VIN7
100UF
VOUT6
B1
C435
VIN6
J6
100PF
A6
VDD_PEHA, 2.5V
42.2K
100K
R569
100K
R570
C432
10UF
10UF
C431
LTM4603
2
SHEET 30 OF 52 1
8
7
6
5
4
3
2
1
+12V3_PS
+3V3 D D A1
VIN1
VOUT1
J1
A2
VIN2
VOUT2
J2
A3
VIN3
VOUT3
J3
CONN BANANA
A4
VIN4
VOUT4
J4
RED
A5
VIN5
VOUT5
J5
VIN15
VOUT15
K5
C4
VIN16
VOUT16
K6
C5
VIN17
VOUT17
K7
C6
VIN18
VOUT18
K8
VOUT19
K9
VOUT20
K10
VOUT21
K11
VOUT22
L1
VOUT23
L2
VOUT24
L3
VOUT25
L4
VOUT26
L5
VOUT27
L6
VOUT28
L7
VOUT29
L8
VOUT30
L9
VOUT31
L10
VOUT32
L11
VOUT33
M1
VOUT34
M2
VOUT35
M3
VOUT36
M4
VOUT37
M5
VOUT38
M6
VOUT39
M7
VOUT40
M8
L12
A9
2 3 4 5 6
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
12
PS_PETA_MARG0
11
PS_PETA_MARG1
10
PS_PETA_CTRL3
9
PS_PETA_CTRL2
8
PS_PETA_CTRL1
7
PS_PETA_CTRL0
487K 487K
R589
487K
R591
1.96M 1.96M
1.96M
A
TRACK/SS
MARG0
VOUT41
M9
MARG1
VOUT42
M10
VOUT43
M11
MPGM
C451 R590
8% 4%
R592 R593
2%
R594
1%
MARGINING CONTROL
SGND
VFB
F12
VOSNSP
J12
VOSNSN
M12
D1
GND1
D2
GND2
D3
GND3
D4
GND4
D5
GND5
D6
GND6
E1
GND7
E2
GND8
E3
GND9
E4
GND10
E5
GND11
GND26
G4
E6
GND12
GND27
G5
E7
GND13
GND28
G6
F1
GND14
GND29
G7
F2
GND15
GND30
G8
F3
GND16
GND31
G9
F4
GND17
GND32
H1
F5
GND18
GND33
H2
F6
GND19
GND34
H3
F7
GND20
GND35
H4
F8
GND21
GND36
H5
F9
GND22
GND37
H6
G1
GND23
GND38
H7
G2
GND24
GND39
H8
G3
GND25
GND40
H9
B12
FSET
B
R598
0 0 R595
S10
S1A
VOUT_LCL
D12
H12
SM_SW6 1
DIFFVOUT
C12
A12
DNP
B
MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN
PLLIN
R599
R597
K12
PLACE W37 CLOSE TO J117
DRVCC
0 0
R600 R601
PLACE R598 & R599 CLOSE TO U66, NOISE-FREE ROUTING PLACE R600 & R601 CLOSE TO U1, NOISE-FREE ROUTING
191K
DNP
TP54
INTVCC
A
TITLE
U68
EB-LOGAN-23
POWER REGULATOR - VDDPETA SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
7
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:01:01 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
8
C
PLACE CLOSE TO U1
C453
A8
COMP
FB9
0.01UF
W37
R1398
E12
10K 10K
R1397
A7
26NH
6.5A
1%
A11
DNP
TP53
PGOOD
1%
G12
REG_1V0_PETA
R596
C
RUN
316K
A10
+3V3
+1V0_PETA ROUTE AS POWER NET OR ISLAND
C464
K4
C3
1.0UF
VOUT14
C463
VIN14
10UF
K3
C2
C462
VOUT13
C460
VIN13
0.1UF
K2
C1
1.0UF
K1
VOUT12
C459
VOUT11
VIN12
C458
J10
VIN11
B6
47UF
VOUT10
1.0UF
VIN10
B5
C457
J9
B4
C456
J8
VOUT9
47UF
VOUT8
VIN9
47UF
VIN8
B3
C455
B2
J117 1
47UF
J7
C454
VOUT7
16V
VIN7
100UF
VOUT6
B1
C452
VIN6
J6
100PF
A6
VDD_PETA, 1.0V
127K
100K
100K
R587
R588
C449
10UF
10UF
C448
LTM4603
2
SHEET 31 OF 52 1
8
7
6
5
4
3
2
1
R641
+3V3
+3V3 +3V3
+3V3
2
A
3
GND
VCC
5
Y
4
TP61
YEL
+3V3 1K
OE_N
TLC7733D 2 7 1
C489
VCC RESET RESETN GND
8 6
R644
1K 0603
5
MAIN_RSTN
5%
4
U73
0.1UF
C487
RESET
0.1UF
FUNDAMENTAL
0.1UF
3
RESINN SENSE CONTROL CT
7
OUT
41
44
45
46
47
48
49
50
51
52
DS3
1
D
RED
SATAIN_RSTN
C491
IN
1K 0603
20
R646
R642
U72 SN74LVC1G125
5%
TP60
D
YEL
1K
+3V3
SPDT_MOM 3
A
NC COM
C
1
MOMSW_RSTN
C
2
B
NO
MTG1 MTG2
4 5
S3
+3V3
MSMBCLK MSMBDAT
6 5 3 2 1
A0-2 INTERNALLY PULLED DOWN
SCL SDA
VCC
A2 A1 A0
8
WP
7
GND
4
7
2
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
5%
R651
5%
R649
SSMBCLK
OUT
SSMBDAT
BI
7
7
14
14
J73
1K 0603
2
3
J71
1
3
VERT-TH
5%
1K 0603
1
2.54MM SHROUD
5%
IN BI
5%
7
R661
7
9
DUT_JTAG_TRST_N DUT_JTAG_TDI DUT_JTAG_TDO DUT_JTAG_TMS DUT_JTAG_TCK
R659
9
10
7
OUT OUT IN BI BI
B
1K 0603 1K 0603
10
11
7
0.1UF
11
12
7
C499
1%
R658 12
13
DNP 0603
13
14
JTAG HDR_2x7
7
24LC512 14
R662
1K 0603
DNP
DNP
DNP
+3V3
5%
R660
R1335
R1334
R1333
SOCKETED (52-298-000)
B
+3V3
+3V3
BOOT EEPROM
1K 0603
+3V3
U77
A
A
TITLE
EB-LOGAN-23
RESET, SMBUS, EEPROM, JTAG SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:01 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 32 OF 52 1
8
7
6
5
4
3
2
1
R1357
D
8
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
OFF
ON
16 15 14 13 12 11 10 9
STK2CFG0 STK2CFG1 STK2CFG2 STK2CFG3 STK2CFG4 STK1CFG0 STK1CFG1 SPARE1
OUT OUT OUT OUT OUT OUT OUT
4
7
33
4
7
33
7
33
7
33
7
33
3
7
33
3
7
33 DNP
TP106
33
7
IN
33
7
4
IN
33
7
4
IN
33
7
3
IN
33
7
3
IN
DS102
STK2CFG3
150
R797
GRN
DS103
STK2CFG2
150
R798
GRN
DS104
STK2CFG1
150
R799
GRN
DS105
STK2CFG0
150
R800
GRN
DS106
STK1CFG1
150
R801
GRN
DS107
STK1CFG0
150
R802
GRN
DS108
+3V3
SW8
R1367
7
A1
GRN
R1366
6
IN
R796
R1365
5
7
150
R1364
4
33
STK2CFG4
R1363
3
IN
R1360
2
7
R1362
DIPSW8 1
33
R1361
R1354
R1348
R1345
R1351
(GREEN) ACTIVE HIGH - DIP STK12CFG
1K 1K 1K 1K 1K 1K 1K 1K
STK12CFG
R1342
D
R1339
R1336
+3V3
+3V3 1K 1K 1K 1K 1K 1K 1K 1K
CLOCK R1358
R1355
R1352
R1349
R1346
R1343
R1340
R1337
C
(GREEN) ACTIVE HIGH - DIP STK03CFG 1 2
DIPSW8 1 2 3 4 5 6 7 8
33
7
33
7
IN
33
7
IN
IN
1K 1K 1K 1K 1K 1K 1K 1K
STK03CFG
B1
A1
B2
A2 A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
OFF
ON
16 15 14 13 12 11 10 9
STK3CFG0 STK3CFG1 STK3CFG2 STK3CFG3 STK3CFG4 STK0CFG0 STK0CFG1 SPARE2
OUT OUT OUT OUT OUT OUT OUT
5
7
33
5
7
33
7
33
7
33
7
33
33
33
2
7
33
2
7
33 DNP
TP107
7
7
5
5
IN IN
33
7
2
IN
33
7
2
IN
STK3CFG4
150
R812
GRN
DS118
STK3CFG3
150
R813
GRN
DS119
STK3CFG2
150
R814
GRN
DS120
3 4 5 6 7 8
STK3CFG1
150
C
DIPSW8
R815
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
OFF
ON
16 15 14 13 12 11 10 9
ICS_FS GCLKFSEL ICS_SSM RSTHALT SSMBADDR2 SSMBADDR1 CLKMODE1 CLKMODE0
DS121
GRN
STK3CFG0
150
R816
GRN
DS122
STK0CFG1
150
R817
GRN
DS123
STK0CFG0
150
R818
GRN
DS124
20
OUT OUT OUT OUT OUT OUT OUT OUT
7
33 33
20
33
7
33
7
33
7
33
7
33
7
33
SW10
SW9
(GREEN) ACTIVE HIGH - DIP CLOCK
+3V3 B
33
20
IN
7
IN
20
IN
R1359
R1356
R1353
R1350
R1347
R1344
R1341
33
(GREEN) ACTIVE HIGH - DIP MODE 33
7
IN
33
7
IN
33
7
IN
1K 1K 1K 1K 1K 1K 1K 1K
R1338
33
S4
SM_SW4 1 2 3 4
S1B
S2A
S2B
S3A
S3B
S4A
S4B
7 6 5
G0 G1 G2 G3
OUT OUT OUT OUT
7
33
7
33
7
33
7
33
33
7
IN
33
7
IN
33
7
IN
33
7
IN
33
S5
MODE A
S1A
8
7
IN
G3
150
R819
YEL
DS125
G2
150
R820
YEL
DS126
G1
150
R821
YEL
DS127
G0
150
R822
YEL
DS128
SWMODE3
150
R823
GRN
DS129
SWMODE2
150
R824
GRN
DS130
SWMODE1
150
R825
GRN
DS131
150
R826
GRN
DS132
SWMODE0
33
7
IN
33
7
IN
33
7
IN
33
7
IN
33
7
IN
ICS_FS
150
R803
GRN
DS109
GCLKFSEL
150
R804
GRN
DS110
ICS_SSM
150
R805
GRN
DS111
RSTHALT
150
R806
GRN
DS112
SSMBADDR2
150
R807
GRN
DS113
SSMBADDR1
150
R808
GRN
DS114
CLKMODE1
150
R809
GRN
DS115
CLKMODE0
150
R810
GRN
DS116
B
SM_SW4 1 2 3 4
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
8 7 6 5
SWMODE0 SWMODE1 SWMODE2 SWMODE3
OUT OUT OUT OUT
7
33
7
33
7
33
7
33
A
TITLE
EB-LOGAN-23
DIP SWITCHES SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:01:01 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 33 OF 52 1
TP88
5
YEL
TP87
YEL
TP86
YEL
TP85
6
YEL
TP84
YEL
TP83
YEL
TP82
YEL
YEL
YEL
TP81
7
TP80
8
4
3
2
1
+3V3
(YELLOW) ACTIVE LOW - GPIO D 7
IN
7
IN
7
IN
7
IN
7
IN
7
IN
7
IN
7
IN
GPIO0
150
R1368
DS406
YEL
GPIO1
150
R1369
DS407
YEL
GPIO2
150
R1370
DS408
YEL
GPIO3
150
R1371
DS409
YEL
GPIO4
150
R1372
DS410
YEL
GPIO5
150
R1373
DS411
YEL
150
R1375
DS413
YEL
150
R1376
DS414
YEL
TP58
GPIO6 GPIO7 W1
7
GPIO8
IN
IOEXPINTN
IN
9
10
11
12
13
GPIO | ALT0 | ALT1 ----------------------------------0 | PART0PERSTN | P16LINKUPN ----------------------------------1 | PART1PERSTN | P16ACTIVEN ----------------------------------2 | PART2PERSTN | P4LINKUPN ----------------------------------3 | PART3PERSTN | P4ACTIVEN ----------------------------------4 | FAILOVER0 | P0LINKUPN ----------------------------------5 | GPEN | P0ACTIVEN ----------------------------------6 | FAILOVER1 | FAILOVER3 ----------------------------------7 | FAILOVER2 | P8LINKUPN ----------------------------------8 | IOEXPINTN | P8ACTIVEN | W1:1-2 | W1:2-3
D
+3V3
14
(YELLOW) ACTIVE LOW - PRESENCE DETECT C
C
+3V3
42
11
IN
42
10
IN
42
11
42
9
(GREEN) ACTIVE LOW - ATTENTION INPUT
11
10
11
9
11
10
B
IN IN IN IN IN
11
IN
9
IN
11
10
11
9
11
10
11
9
10
9
A
IN
IN IN IN IN IN IN IN IN IN IN
10
IN
9
IN
10
IN
9
10
9
IN IN IN
P23_APN
42
11
42
10
1K
R852
DS158
P22_APN
1K
R853
DS159
ORG
PORT 22
P21_APN
1K
R854
DS160
ORG
PORT 21
P20_APN
1K
R855
DS161
ORG
PORT 20
P19_APN
1K
R856
DS162
ORG
PORT 10
42
10
P18_APN
1K
R857
DS163
ORG
PORT 18
42
11
P17_APN
1K
R858
DS164
ORG
PORT 17
P16_APN
1K
R859
DS165
ORG
PORT 16
P15_APN
1K
R860
DS166
ORG
PORT 15
P14_APN
1K
R861
DS167
ORG
PORT 14
P13_APN
1K
R862
DS168
ORG
PORT 13
P12_APN
1K
R863
DS169
ORG
P11_APN
1K
R864
DS170
ORG
PORT 11
P10_APN
1K
R865
DS171
ORG
PORT 10
P9_APN
1K
R866
DS172
ORG
PORT 9
P8_APN
1K
R867
DS173
ORG
PORT 8
P7_APN
1K
R868
DS174
ORG
P6_APN
1K
R869
DS175
ORG
PORT 6
P5_APN
1K
R870
DS176
ORG
PORT 5
P4_APN
1K
R871
DS177
ORG
PORT 4
P3_APN
1K
R872
DS178
ORG
PORT 3
P2_APN
1K
R873
DS179
ORG
PORT 2
P1_APN
1K
R874
DS180
ORG
PORT 1
P0_APN
1K
R875
DS181
ORG
PORT 0
ORG
PORT 23
42
11
42
42
42
IN IN IN IN IN IN IN IN
42
11
IN
42
10
11
42
42
9
10
42
42
9
10
42
42
PORT 7
IN
9
42
PORT 12
9
11
IN
9
10
42
42
9
10
42
9
IN IN IN IN IN IN IN IN IN IN IN
P23_PDN
150
R876
DS182
YEL
PORT 23
P22_PDN
150
R877
DS183
YEL
PORT 22
P21_PDN
150
R878
DS184
YEL
PORT 21
P20_PDN
150
R879
DS185
YEL
PORT 20
P19_PDN
150
R880
DS186
YEL
PORT 19
P18_PDN
150
R881
DS187
YEL
PORT 18
P17_PDN
150
R882
DS188
YEL
PORT 17
P16_PDN
150
R883
DS189
YEL
PORT 16
P15_PDN
150
R884
DS190
YEL
PORT 15
P14_PDN
150
R885
DS191
YEL
PORT 14
P13_PDN
150
R886
DS192
YEL
PORT 13
P12_PDN
150
R887
DS193
YEL
PORT 12
P11_PDN
150
R888
DS194
YEL
PORT 11
P10_PDN
150
R889
DS195
YEL
PORT 10
P9_PDN
150
R890
DS196
YEL
PORT 9
P8_PDN
150
R891
DS197
YEL
PORT 8
P7_PDN
150
R892
DS198
YEL
PORT 7
P6_PDN
150
R893
DS199
YEL
PORT 6
P5_PDN
150
R894
DS200
YEL
PORT 5
P4_PDN
150
R895
DS201
YEL
PORT 4
P3_PDN
150
R896
DS202
YEL
PORT 3
P2_PDN
150
R897
DS203
YEL
PORT 2
P1_PDN
150
R898
DS204
YEL
PORT 1
P0_PDN
150
R899
DS205
YEL
PORT 0
TITLE
B
EB-LOGAN-23
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6
5
2010
4
IDT
2.0
Derek Huang
Thu Jul 01 15:01:02 2010 3
REV.
18-691-001 CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
7
A
LED - PORT STATUS (1 OF 7) SIZE
8
B
2
SHEET 34 OF 52 1
8
7
6
5
4
3
2
1
D D
+3V3
+3V3
(GREEN) ACTIVE LOW - POWER GOOD
(RED) ACTIVE LOW - POWER FAULT
42
11
IN
42
10
IN
42
42
18
11
9
IN IN
42
11
42
10
IN
42
11
IN
IN
P23_PFN
1K
R663
DS5
RED
PORT 23
42
11
IN
P22_PFN
1K
R664
DS6
RED
PORT 22
42
10
IN
P21_PFN
1K
R665
DS7
RED
PORT 21
P20_PFN
1K
R666
DS8
RED
PORT 20
P19_PFN
1K
R667
DS9
RED
PORT 10
42
11
P18_PFN
1K
R668
DS10
RED
PORT 18
42
10
IN
P17_PFN
1K
R669
DS11
RED
PORT 17
42
11
IN
P16_PFN
1K
R670
DS12
RED
PORT 16
P15_PFN
1K
R671
DS13
RED
PORT 15
P14_PFN
1K
R672
DS14
RED
PORT 14
42
10
P13_PFN
1K
R673
DS15
RED
PORT 13
42
11
P12_PFN
1K
R674
DS16
RED
PORT 12
P11_PFN
1K
R675
DS17
RED
PORT 11
42
11
P10_PFN
1K
R676
DS18
RED
PORT 10
42
10
P9_PFN
1K
R677
DS19
RED
PORT 9
P8_PFN
1K
R678
DS20
RED
PORT 8
P7_PFN
1K
R679
DS21
RED
PORT 7
P6_PFN
1K
R680
DS22
RED
PORT 6
P5_PFN
1K
R681
DS23
RED
PORT 5
P4_PFN
1K
R682
DS24
RED
PORT 4
P3_PFN
1K
R683
DS25
RED
PORT 3
P2_PFN
1K
R684
DS26
RED
PORT 2
P1_PFN
1K
R685
DS27
RED
PORT 1
P0_PFN
1K
R686
DS28
RED
PORT 0
42
42
18
11
9
IN IN IN
P23_PWRGDN
150
R687
DS29
GRN
PORT 23
P22_PWRGDN
150
R688
DS30
GRN
PORT 22
P21_PWRGDN
150
R689
DS31
GRN
PORT 21
P20_PWRGDN
150
R690
DS32
GRN
PORT 20
P19_PWRGDN
150
R691
DS33
GRN
PORT 10
P18_PWRGDN
150
R692
DS34
GRN
PORT 18
P17_PWRGDN
150
R693
DS35
GRN
PORT 17
P16_PWRGDN
150
R694
DS36
GRN
PORT 16
P15_PWRGDN
150
R695
DS37
GRN
PORT 15
P14_PWRGDN
150
R696
DS38
GRN
PORT 14
P13_PWRGDN
150
R697
DS39
GRN
PORT 13
P12_PWRGDN
150
R698
DS40
GRN
PORT 12
P11_PWRGDN
150
R699
DS41
GRN
PORT 11
P10_PWRGDN
150
R700
DS42
GRN
PORT 10
P9_PWRGDN
150
R701
DS43
GRN
PORT 9
P8_PWRGDN
150
R702
DS44
GRN
PORT 8
P7_PWRGDN
150
R703
DS45
GRN
PORT 7
P6_PWRGDN
150
R704
DS46
GRN
PORT 6
P5_PWRGDN
150
R705
DS47
GRN
PORT 5
P4_PWRGDN
150
R706
DS48
GRN
PORT 4
P3_PWRGDN
150
R707
DS49
GRN
PORT 3
P2_PWRGDN
150
R708
DS50
GRN
PORT 2
P1_PWRGDN
150
R709
DS51
GRN
PORT 1
P0_PWRGDN
150
R710
DS52
GRN
PORT 0
C
C
42
18
42
42
42
10
42
11
17
B
11
42
10
17
42
42
16
42
42
16
42
42
15
42
42
9
42
42
42
9
11
15
11
9
IN IN IN IN IN IN IN IN IN
10
IN
9
IN
10
9
IN IN
10
IN
9
IN
10
9
IN IN
42
18
42
42
17
42
42
17
42
42
16
42
42
16
42
42
15
42
42
15
9
11
9
11
9
IN IN IN IN IN IN IN IN IN
10
IN
9
IN
10
9
IN IN
10
IN
9
IN
10
9
IN IN
B
A
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (2 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:02 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 35 OF 52 1
8
7
6
5
4
3
2
1
D D
+3V3 +3V3
(ORANGE) ACTIVE LOW - ATTENTION OUTPUT
11
IN
10
IN
11
9
11
IN IN IN
(GREEN) ACTIVE LOW - POWER INDICATOR
P23_AIN
1K
R900
DS206
ORG
PORT 23
11
IN
P22_AIN
1K
R901
DS207
ORG
PORT 22
10
IN
P21_AIN
1K
R902
DS208
ORG
PORT 21
11
P20_AIN
1K
R903
DS209
ORG
PORT 20
9
P19_AIN
1K
R904
DS210
ORG
PORT 10
11
P18_AIN
1K
R905
DS211
ORG
PORT 18
10
IN
P17_AIN
1K
R906
DS212
ORG
PORT 17
11
IN
P16_AIN
1K
R907
DS213
ORG
PORT 16
9
P15_AIN
1K
R908
DS214
ORG
PORT 15
11
P14_AIN
1K
R909
DS215
ORG
PORT 14
10
P13_AIN
1K
R910
DS216
ORG
PORT 13
11
IN
P12_AIN
1K
R911
DS217
ORG
PORT 12
9
IN
P11_AIN
1K
R912
DS218
ORG
PORT 11
11
P10_AIN
1K
R913
DS219
ORG
PORT 10
10
P9_AIN
1K
R914
DS220
ORG
PORT 9
11
P8_AIN
1K
R915
DS221
ORG
PORT 8
9
P7_AIN
1K
R916
DS222
ORG
PORT 7
10
IN
P6_AIN
1K
R917
DS223
ORG
PORT 6
9
IN
P5_AIN
1K
R918
DS224
ORG
PORT 5
10
P4_AIN
1K
R919
DS225
ORG
PORT 4
9
P3_AIN
1K
R920
DS226
ORG
PORT 3
10
P2_AIN
1K
R921
DS227
ORG
PORT 2
9
P1_AIN
1K
R922
DS228
ORG
PORT 1
10
P0_AIN
1K
R923
DS229
ORG
PORT 0
9
IN IN IN
P23_PIN
150
R924
DS230
GRN
PORT 23
P22_PIN
150
R925
DS231
GRN
PORT 22
P21_PIN
150
R926
DS232
GRN
PORT 21
P20_PIN
150
R927
DS233
GRN
PORT 20
P19_PIN
150
R928
DS234
GRN
PORT 10
P18_PIN
150
R929
DS235
GRN
PORT 18
P17_PIN
150
R930
DS236
GRN
PORT 17
P16_PIN
150
R931
DS237
GRN
PORT 16
P15_PIN
150
R932
DS238
GRN
PORT 15
P14_PIN
150
R933
DS239
GRN
PORT 14
P13_PIN
150
R934
DS240
GRN
PORT 13
P12_PIN
150
R935
DS241
GRN
PORT 12
P11_PIN
150
R936
DS242
GRN
PORT 11
P10_PIN
150
R937
DS243
GRN
PORT 10
P9_PIN
150
R938
DS244
GRN
PORT 9
P8_PIN
150
R939
DS245
GRN
PORT 8
P7_PIN
150
R940
DS246
GRN
PORT 7
P6_PIN
150
R941
DS247
GRN
PORT 6
P5_PIN
150
R942
DS248
GRN
PORT 5
P4_PIN
150
R943
DS249
GRN
PORT 4
P3_PIN
150
R944
DS250
GRN
PORT 3
P2_PIN
150
R945
DS251
GRN
PORT 2
P1_PIN
150
R946
DS252
GRN
PORT 1
P0_PIN
150
R947
DS253
GRN
PORT 0
C
C 10
IN
11
IN
9
11
10
IN IN
11
IN
9
IN
11
10
11
9
B
IN
IN IN IN IN
10
IN
9
IN
10
9
10
9
10
9
IN IN IN IN IN IN
IN IN IN
IN IN IN IN
IN IN IN IN IN IN
B
A
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (3 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:01:02 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 36 OF 52 1
8
7
6
5
4
3
2
1
D D
+3V3
(GREEN) ACTIVE HIGH - POWER ENABLE (RED) ACTIVE LOW - HP SLOT RST
42
11
42
10
42
42
18
42
C
42
42
42
IN
9
IN
18
42
11
42
10
17
11
9
42
11
42
10
42
11
17
16
16
15
42
42
IN
11
42
42
IN
10
42
42
11
IN
42
42
B
9
IN
42
42
42
11
IN
15
9
10
IN
IN IN IN IN IN IN IN IN IN
9
IN
10
IN
9
IN
10
9
10
9
IN IN IN IN
P23_PEP
150
R711
GRN
DS53
PORT 23
19
14
11
P22_PEP
150
R712
GRN
DS54
PORT 22
19
14
10
P21_PEP
150
R713
GRN
DS55
PORT 21
P20_PEP
150
R714
GRN
DS56
PORT 20
P19_PEP
150
R715
GRN
DS57
PORT 10
P18_PEP
150
R716
GRN
DS58
PORT 18
19
14
10
P17_PEP
150
R717
GRN
DS59
PORT 17
19
14
11
IN
P16_PEP
150
R718
GRN
DS60
PORT 16
9
IN
P15_PEP
150
R719
GRN
DS61
P14_PEP
150
R720
GRN
DS62
P13_PEP
150
R721
GRN
DS63
PORT 13
P12_PEP
150
R722
GRN
DS64
PORT 12
P11_PEP
150
R723
GRN
DS65
PORT 11
19
14
11
P10_PEP
150
R724
GRN
DS66
PORT 10
19
14
10
P9_PEP
150
R725
GRN
DS67
PORT 9
19
14
11
P8_PEP
150
R726
GRN
DS68
PORT 8
P7_PEP
150
R727
GRN
DS69
PORT 7
P6_PEP
150
R728
GRN
DS70
PORT 6
P5_PEP
150
R729
GRN
DS71
PORT 5
P4_PEP
150
R730
GRN
DS72
PORT 4
P3_PEP
150
R731
GRN
DS73
PORT 3
P2_PEP
150
R732
GRN
DS74
PORT 2
P1_PEP
150
R733
GRN
DS75
PORT 1
P0_PEP
150
R734
GRN
DS76
PORT 0
19
19
19
19
14
14
14
14
11
9
11
PORT 15
19
14
11
PORT 14
19
14
10
19
19
19
19
19
19
19
19
19
19
19
14
14
14
14
14
14
14
14
14
14
14
11
9
9
10
IN IN IN IN IN IN
IN IN IN IN IN IN IN IN IN
9
IN
10
IN
9
IN
10
9
10
9
IN IN IN IN
P23_RSTN
1K
R735
DS77
RED
PORT 23
P22_RSTN
1K
R736
DS78
RED
PORT 22
P21_RSTN
1K
R737
DS79
RED
PORT 21
P20_RSTN
1K
R738
DS80
RED
PORT 20
P19_RSTN
1K
R739
DS81
RED
PORT 10
P18_RSTN
1K
R740
DS82
RED
PORT 18
P17_RSTN
1K
R741
DS83
RED
PORT 17
P16_RSTN
1K
R742
DS84
RED
PORT 16
P15_RSTN
1K
R743
DS85
RED
PORT 15
P14_RSTN
1K
R744
DS86
RED
PORT 14
P13_RSTN
1K
R745
DS87
RED
PORT 13
P12_RSTN
1K
R746
DS88
RED
PORT 12
P11_RSTN
1K
R747
DS89
RED
PORT 11
P10_RSTN
1K
R748
DS90
RED
PORT 10
P9_RSTN
1K
R749
DS91
RED
PORT 9
P8_RSTN
1K
R750
DS92
RED
PORT 8
P7_RSTN
1K
R751
DS93
RED
PORT 7
P6_RSTN
1K
R752
DS94
RED
PORT 6
P5_RSTN
1K
R753
DS95
RED
PORT 5
P4_RSTN
1K
R754
DS96
RED
PORT 4
P3_RSTN
1K
R755
DS97
RED
PORT 3
P2_RSTN
1K
R756
DS98
RED
PORT 2
P1_RSTN
1K
R757
DS99
RED
PORT 1
P0_RSTN
1K
R758
DS100
RED
PORT 0
C
B
A
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (4 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:03 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 37 OF 52 1
8
7
6
5
4
3
2
1
D D
+3V3
(GREEN) ACTIVE HIGH - INTERLOCK INPUT (RED) ACTIVE LOW - MRL
13
IN
12
IN
13
12
13
IN IN IN
P23_ILOCKST
150
R948
GRN
DS254
PORT 23
12
IN
P22_ILOCKST
150
R949
GRN
DS255
PORT 22
12
IN
P21_ILOCKST
150
R950
GRN
DS256
PORT 21
12
P20_ILOCKST
150
R951
GRN
DS257
PORT 20
12
P19_ILOCKST
150
R952
GRN
DS258
PORT 10
P18_ILOCKST
150
R953
GRN
DS259
PORT 18
12
IN
P17_ILOCKST
150
R954
GRN
DS260
PORT 17
12
IN
P16_ILOCKST
150
R955
GRN
DS261
PORT 16
12
P15_ILOCKST
150
R956
GRN
DS262
PORT 15
12
P14_ILOCKST
150
R957
GRN
DS263
PORT 14
P13_ILOCKST
150
R958
GRN
DS264
PORT 13
12
P12_ILOCKST
150
R959
GRN
DS265
PORT 12
12
P11_ILOCKST
150
R960
GRN
DS266
PORT 11
12
P10_ILOCKST
150
R961
GRN
DS267
PORT 10
12
P9_ILOCKST
150
R962
GRN
DS268
PORT 9
P8_ILOCKST
150
R963
GRN
DS269
PORT 8
12
IN
P7_ILOCKST
150
R964
GRN
DS270
PORT 7
12
IN
P6_ILOCKST
150
R965
GRN
DS271
PORT 6
12
IN
P5_ILOCKST
150
R966
GRN
DS272
PORT 5
12
P4_ILOCKST
150
R967
GRN
DS273
PORT 4
P3_ILOCKST
150
R968
GRN
DS274
PORT 3
12
P2_ILOCKST
150
R969
GRN
DS275
PORT 2
12
P1_ILOCKST
150
R970
GRN
DS276
PORT 1
12
P0_ILOCKST
150
R971
GRN
DS277
PORT 0
12
12
IN IN IN
P23_MRLN
1K
R972
DS278
RED
PORT 23
P22_MRLN
1K
R973
DS279
RED
PORT 22
P21_MRLN
1K
R974
DS280
RED
PORT 21
P20_MRLN
1K
R975
DS281
RED
PORT 20
P19_MRLN
1K
R976
DS282
RED
PORT 10
P18_MRLN
1K
R977
DS283
RED
PORT 18
P17_MRLN
1K
R978
DS284
RED
PORT 17
P16_MRLN
1K
R979
DS285
RED
PORT 16
P15_MRLN
1K
R980
DS286
RED
PORT 15
P14_MRLN
1K
R981
DS287
RED
PORT 14
P13_MRLN
1K
R982
DS288
RED
PORT 13
P12_MRLN
1K
R983
DS289
RED
PORT 12
P11_MRLN
1K
R984
DS290
RED
PORT 11
P10_MRLN
1K
R985
DS291
RED
PORT 10
P9_MRLN
1K
R986
DS292
RED
PORT 9
P8_MRLN
1K
R987
DS293
RED
PORT 8
P7_MRLN
1K
R988
DS294
RED
PORT 7
P6_MRLN
1K
R989
DS295
RED
PORT 6
P5_MRLN
1K
R990
DS296
RED
PORT 5
P4_MRLN
1K
R991
DS297
RED
PORT 4
P3_MRLN
1K
R992
DS298
RED
PORT 3
P2_MRLN
1K
R993
DS299
RED
PORT 2
P1_MRLN
1K
R994
DS300
RED
PORT 1
P0_MRLN
1K
R995
DS301
RED
PORT 0
C
C 12
IN
13
IN
12
13
12
13
12
13
12
13
B
IN IN IN IN IN IN IN IN
12
IN
12
IN
12
IN
12
12
12
12
12
12
IN IN IN IN IN IN
12
12
12
IN IN IN IN IN IN IN IN
IN IN IN IN IN IN
B
A
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (5 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:03 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 38 OF 52 1
8
7
6
5
4
3
2
+3V3
+3V3
(RED) ACTIVE LOW - PARTITION FUND. RESET
D
1
(RED) ACTIVE LOW - SLOT HEADER RESET D
43
14
IN
43
14
IN
43
14
43
14
43
14
43
14
43
14
43
14
IN IN IN IN IN IN
PART7_PERSTN
1K
R1020
DS326
RED
PART 7
44
43
7
5
IN
PART6_PERSTN
1K
R1021
DS327
RED
PART 6
44
43
7
5
IN
PART5_PERSTN
1K
R1022
DS328
RED
PART 5
44
43
7
4
PART4_PERSTN
1K
R1023
DS329
RED
PART 4
44
43
7
4
PART3_PERSTN
1K
R1024
DS330
RED
PART 3
44
43
7
3
PART2_PERSTN
1K
R1025
DS331
RED
PART 2
PART1_PERSTN
1K
R1026
DS332
RED
PART 1
44
43
7
2
PART0_PERSTN
1K
R1027
DS333
RED
PART 0
44
43
7
2
44
43
7
3
IN IN IN IN IN IN
SLOT_HDR_RSTN20
1K
R1650
DS415
RED
SLOT 20
SLOT_HDR_RSTN16
1K
R1651
DS416
RED
SLOT 16
SLOT_HDR_RSTN12
1K
R1652
DS417
RED
SLOT 12
SLOT_HDR_RSTN8
1K
R1653
DS418
RED
SLOT 8
SLOT_HDR_RSTN6
1K
R1654
DS419
RED
SLOT 6
SLOT_HDR_RSTN4
1K
R1655
DS420
RED
SLOT 4
SLOT_HDR_RSTN2
1K
R1656
DS421
RED
SLOT 2
SLOT_HDR_RSTN0
1K
R1657
DS422
RED
SLOT 0
(GREEN) ACTIVE HIGH - INTERLOCK OUTPUT
C
13
12
IN
13
IN
12
13
12
IN IN IN
12
IN
12
IN IN
13
IN
12
IN
13
IN
12
13
12
IN IN IN
12
IN
12
IN
12
12
12
12
A
IN
13
13
B
IN
IN IN IN IN
12
IN
12
IN
C
P23_ILOCKP
150
R996
GRN
DS302
PORT 23
P22_ILOCKP
150
R997
GRN
DS303
PORT 22
P21_ILOCKP
150
R998
GRN
DS304
PORT 21
P20_ILOCKP
150
R999
GRN
DS305
PORT 20
P19_ILOCKP
150
R1000
GRN
DS306
PORT 10
P18_ILOCKP
150
R1001
GRN
DS307
PORT 18
P17_ILOCKP
150
R1002
GRN
DS308
PORT 17
P16_ILOCKP
150
R1003
GRN
DS309
PORT 16
P15_ILOCKP
150
R1004
GRN
DS310
PORT 15
P14_ILOCKP
150
R1005
GRN
DS311
PORT 14
P13_ILOCKP
150
R1006
GRN
DS312
PORT 13
P12_ILOCKP
150
R1007
GRN
DS313
PORT 12
P11_ILOCKP
150
R1008
GRN
DS314
PORT 11
P10_ILOCKP
150
R1009
GRN
DS315
PORT 10
P9_ILOCKP
150
R1010
GRN
DS316
PORT 9
P8_ILOCKP
150
R1011
GRN
DS317
PORT 8
P7_ILOCKP
150
R1012
GRN
DS318
PORT 7
P6_ILOCKP
150
R1013
GRN
DS319
PORT 6
P5_ILOCKP
150
R1014
GRN
DS320
PORT 5
P4_ILOCKP
150
R1015
GRN
DS321
PORT 4
P3_ILOCKP
150
R1016
GRN
DS322
PORT 3
P2_ILOCKP
150
R1017
GRN
DS323
PORT 2
P1_ILOCKP
150
R1018
GRN
DS324
PORT 1
P0_ILOCKP
150
R1019
GRN
DS325
PORT 0
B
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (6 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:03 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 39 OF 52 1
8
7
6
5
4
3
2
1
D D
+3V3
+3V3
(GREEN) ACTIVE LOW - LINK UP
13
IN
13
IN
13
IN
13
13
13
IN IN IN
(BLUE) ACTIVE LOW - LINK ACTIVITY
P23_LINKUPN
150
R1172
DS334
GRN
P22_LINKUPN
150
R1173
DS335
GRN
PORT 22
13
IN
P21_LINKUPN
150
R1174
DS336
GRN
PORT 21
13
IN
P20_LINKUPN
150
R1175
DS337
GRN
PORT 20
13
P19_LINKUPN
150
R1176
DS338
GRN
PORT 10
13
P18_LINKUPN
150
R1177
DS339
GRN
P17_LINKUPN
150
R1178
DS340
GRN
PORT 17
13
IN
P16_LINKUPN
150
R1179
DS341
GRN
PORT 16
13
IN
P15_LINKUPN
150
R1180
DS342
GRN
PORT 15
13
P14_LINKUPN
150
R1181
DS343
GRN
PORT 14
13
P13_LINKUPN
150
R1182
DS344
GRN
P12_LINKUPN
150
R1183
DS345
GRN
PORT 12
13
IN
P11_LINKUPN
150
R1184
DS346
GRN
PORT 11
13
IN
P10_LINKUPN
150
R1185
DS347
GRN
PORT 10
13
P9_LINKUPN
150
R1186
DS348
GRN
PORT 9
13
P8_LINKUPN
150
R1187
DS349
GRN
P7_LINKUPN
150
R1188
DS350
GRN
PORT 7
13
IN
P6_LINKUPN
150
R1189
DS351
GRN
PORT 6
13
IN
P5_LINKUPN
150
R1190
DS352
GRN
PORT 5
13
IN
P4_LINKUPN
150
R1191
DS353
GRN
PORT 4
13
P3_LINKUPN
150
R1192
DS354
GRN
PORT 3
13
P2_LINKUPN
150
R1193
DS355
GRN
PORT 2
13
P1_LINKUPN
150
R1194
DS356
GRN
PORT 1
13
P0_LINKUPN
150
R1195
DS357
GRN
PORT 23
PORT 18
13
13
IN
IN IN IN
P23_ACTIVEN
549R
R1196
DS358
BLUE
PORT 23
P22_ACTIVEN
549R
R1197
DS359
BLUE
PORT 22
P21_ACTIVEN
549R
R1198
DS360
BLUE
PORT 21
P20_ACTIVEN
549R
R1199
DS361
BLUE
PORT 20
P19_ACTIVEN
549R
R1200
DS362
BLUE
PORT 10
P18_ACTIVEN
549R
R1201
DS363
BLUE
PORT 18
P17_ACTIVEN
549R
R1202
DS364
BLUE
PORT 17
P16_ACTIVEN
549R
R1203
DS365
BLUE
PORT 16
P15_ACTIVEN
549R
R1204
DS366
BLUE
PORT 15
P14_ACTIVEN
549R
R1205
DS367
BLUE
PORT 14
P13_ACTIVEN
549R
R1206
DS368
BLUE
PORT 13
P12_ACTIVEN
549R
R1207
DS369
BLUE
PORT 12
P11_ACTIVEN
549R
R1208
DS370
BLUE
PORT 11
P10_ACTIVEN
549R
R1209
DS371
BLUE
PORT 10
P9_ACTIVEN
549R
R1210
DS372
BLUE
PORT 9
P8_ACTIVEN
549R
R1211
DS373
BLUE
PORT 8
P7_ACTIVEN
549R
R1212
DS374
BLUE
PORT 7
P6_ACTIVEN
549R
R1213
DS375
BLUE
PORT 6
P5_ACTIVEN
549R
R1214
DS376
BLUE
PORT 5
P4_ACTIVEN
549R
R1215
DS377
BLUE
PORT 4
P3_ACTIVEN
549R
R1216
DS378
BLUE
PORT 3
P2_ACTIVEN
549R
R1217
DS379
BLUE
PORT 2
P1_ACTIVEN
549R
R1218
DS380
BLUE
PORT 1
P0_ACTIVEN
549R
R1219
DS381
BLUE
PORT 0
C
C 13
IN
13
IN
13
13
13
IN IN
13
IN
13
IN
13
13
13
B
IN
IN IN IN
13
IN
13
IN
13
IN
13
13
13
13
13
IN IN IN IN IN
PORT 13
PORT 8
PORT 0
13
13
13
IN IN IN
IN IN IN
IN IN IN IN IN
B
A
A
TITLE
EB-LOGAN-23
LED - PORT STATUS (7 OF 7) SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:04 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 40 OF 52 1
8 7 6 5 COPYRIGHT (C)
2010
4
1% 1%
1%
1% 1%
R1121
1% 1%
R1120
44
R1123
1%
1% R1116
45
R1122
1%
R1112
1%
R1108
46
R1117
715 1206 715 1206 715 1206 715 1206
47
R1113
1%
R1109
48
R1118
+5V0_PS 715 1206 715 1206 715 1206 715 1206
+12V3_PS
49
1%
1%
R1104
1%
R1100
1%
R1096
1%
R1092
+12V2_PS 50
R1114
715 1206 715 1206 715 1206 715 1206
51
R1110
1%
R1105
1%
R1101
1%
R1097
1%
R1093
1%
R1042
1%
R1038
1%
R1034
1%
R1030
D TP133
YEL
5
124 1206 124 1206 124 1206 124 1206 124 1206
1%
R1106
1%
R1102
+5V0_PS
1%
715 1206 715 1206 715 1206 715 1206
+12V3_PS
R1098
1%
R1088
1%
R1084
1%
R1080
1%
R1076
+12V2_PS
1%
R1094
1%
R1089
1%
R1085
1%
R1081
715 1206 715 1206 715 1206 715 1206
715 1206 715 1206 715 1206 715 1206
6
124 1206 124 1206 124 1206 124 1206
1%
R1090
1%
R1086
1%
R1082
1%
R1077
+12V3_PS
715 1206 715 1206 715 1206 715 1206
1%
R1073
1%
R1070
1%
R1067
1%
R1064
1%
R1059
1%
R1055
1%
R1051
1%
R1047
1%
R1043
1%
R1039
1%
R1035
1%
R1031
+12V2_PS
1%
+3V3_PS 1%
715 1206 715 1206 715 1206 715 1206
715 1206 715 1206 715 1206 715 1206
715 1206 715 1206 715 1206 715 1206
7
R1074
1%
R1071
1%
R1068
1%
R1065
1%
R1060
1%
R1056
1%
R1052
1%
R1048
+12V3_PS
R1078
715 1206 715 1206 715 1206 715 1206
715 1206 715 1206 715 1206 715 1206
1%
R1044
1%
R1040
1%
R1036
1%
R1032
+12V2_PS
124 1206 124 1206 124 1206 124 1206
1%
R1062
1%
R1061
1%
R1057
1%
R1053
+3V3_PS
1%
715 1206 715 1206 715 1206 715 1206
+12V3_PS
R1049
1%
R1045
1%
R1041
1%
R1037
C
1%
R1033
+12V2_PS
53.6 1206 53.6 1206 53.6 1206 53.6 1206 53.6 1206
53.6 1206 53.6 1206 53.6 1206 53.6 1206
8 4 3
+12V1_PS
NOTE:
32 52 7
IN
CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 IDT
3
2
MAIN_RSTN
+12V2_PS
TITLE
SIZE
B
1 1 2
2
3
9 10
10
11 11 12
12
13 13 14
14
15 15 16
16
5
3 4
4
5 6
6
7 7 8
8
9
VERT
11
VERT
J133
1 1 2
2
3 3 4
4
5 5 6
6
7 7 8
8
13
9 9 10
10
11 12
12
13 14
14
15 15 16
16
J134
2
1
MINIMUM POWER SUPPLY LOADS DNP JUMPERS WHEN IOEXPANDER IS ENABLED D
HDR_2x8
SLOT_RSTN1 SLOT_RSTN3 SLOT_RSTN5 SLOT_RSTN7 SLOT_RSTN9 SLOT_RSTN10 SLOT_RSTN11 SLOT_RSTN13
SLOT_RSTN14 SLOT_RSTN15 SLOT_RSTN17 SLOT_RSTN18 SLOT_RSTN19 SLOT_RSTN21 SLOT_RSTN22 SLOT_RSTN23
SCH-PESEB-001
DRAWING NO.
Tony Tran
AUTHOR
Thu Jul 01 15:01:04 2010
OUT OUT OUT OUT OUT OUT OUT OUT
OUT OUT OUT OUT OUT OUT OUT OUT
19 42
19 42
1
43
19 42 43
19 42 43
43
19 42 43
19 42 43
19 42 43
19 42 43
2.54MM NO-SHROUD
HDR_2x8
19 42 43
19 42 43
19 42 43
19 42 43
19 42 43
19 42 43
19 42 43
19 42 43
18-691-001
FAB P/N
Derek Huang
CHECKED BY
SHEET 41 OF 52
C
2.54MM NO-SHROUD
+12V3_PS
B B
+5V0_PS
A A
EB-LOGAN-23
MIN LOAD RESISTORS 2.0
REV.
8
7
6
5
4
HDR_2x30
D
SLOT_RESETN CARD_PRESENTN WAKEN POWERGOOD PWR_FLTN PWR_ENABLE CLOCK_ENABLEN
C
PS_ENABLEN CABLE SENSE
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
10
10
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
19
19
20
20 100
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
35
35
36
36
37
37
38
38
R1222 R1223
28
39
39
40
40
41
41
42
42
43
43
44
44 100
45
45
46
46
47
47
48
48 100
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58 100
60
60
J43
R1221
100
9
VERT
R1220
100
11
59
R1224 R1225
R1226 R1227
R1228
SLOT_RSTN8 P8_PDN SLOT_WAKEN8 P8_PWRGDN P8_PFN P8_PEP P8_CLK_EN SLOT_RSTN9 P9_PDN SLOT_WAKEN9 P9_PWRGDN P9_PFN P9_PEP P9_CLK_EN SLOT_RSTN10 P10_PDN SLOT_WAKEN10 P10_PWRGDN P10_PFN P10_PEP P10_CLK_EN SLOT_RSTN11 P11_PDN SLOT_WAKEN11 P11_PWRGDN P11_PFN P11_PEP P11_CLK_EN PS_ENABLEN
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 4
19
1
2
2
3
3
4
4
5
5
6
6 8
PS_ENABLEN CABLE SENSE
7
7
8
17
35
9
9
10
10
17
37
11
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
17
19 11
35
41
43
34
19
19
20
20 100
11
35
21
21
22
22
11
35
23
23
24
24
11
37
25
25
26
26
27
27
28
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
19
19 10
41
43
34
19 10
35
35
35
36
36
10
35
37
37
38
38
37
39
39
40
40
41
41
42
42
43
43
44
44 100
45
45
46
46
10
19 11
41
43
34
47
47
48
48 100
11
35
49
49
50
50
11
35
51
51
52
52
11
37
53
53
54
54
55
55
56
56
26
42
57
57
58
58 100
60
60
19
59
0.050X0.1 SHROUD
1
2
2
3
3
4
4
5
5
6
6
J45
VERT
7
7
8
8
9
9
10
10
R1229
100
R1230
100
11
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
19
19
20
20 100
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
35
35
36
36
37
37
38
38
39
39
40
40
41
41
42
42
43
43
44
44 100
45
45
46
46
47
47
48
48 100
49
49
50
50
51
51
52
52
53
53
54
54
55
55
56
56
57
57
58
58 100
59
59
60
60
J44
59
R1240
SLOT_RSTN12 P12_PDN SLOT_WAKEN12 P12_PWRGDN P12_PFN P12_PEP P12_CLK_EN SLOT_RSTN13 P13_PDN SLOT_WAKEN13 P13_PWRGDN P13_PFN P13_PEP P13_CLK_EN SLOT_RSTN14 P14_PDN SLOT_WAKEN14 P14_PWRGDN P14_PFN P14_PEP P14_CLK_EN SLOT_RSTN15 P15_PDN SLOT_WAKEN15 P15_PWRGDN P15_PFN P15_PEP P15_CLK_EN PS_ENABLEN
R1241
R1242 R1243
R1244 R1245
R1246 R1247
R1248
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 4
19
1
1
2
2
3
3
4
4
5
5
6
6 8
R1231 R1232
R1233 R1234
R1235 R1236
R1237
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 5
19
1
2
2
3
3
4
4
5
5
6
6 8
100 100
18
35
7
7
8
18
35
9
9
10
10
37
11
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
19 11
41
43
34
19
19
20
20 100
35
21
21
22
22
11
35
23
23
24
24
11
37
25
25
26
26
27
27
28
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
19 11
19 10
41
43
34
19 10
35
35
35
36
36
10
35
37
37
38
38
10
37
39
39
40
40
19 11
41
43
34
11 11
26
41
41
42
42
43
43
44
44 100
45
45
46
46
47
47
48
48 100
35
49
49
50
50
35
51
51
52
52
37
53
53
54
54
55
55
56
56
57
57
58
58 100
59
59
60
60
19 11
42
0.050X0.1 SHROUD
VERT
PORTS 20,21,22,23
J46
R1261
7
7
8
17
35
9
9
10
10
37
11
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
17
19 11
35
41
43
34
19
19
20
20 100
11
35
21
21
22
22
11
35
23
23
24
24
11
37
25
25
26
26
27
27
28
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
19
19 10
41
43
34
19 10
35
35
35
36
36
10
35
37
37
38
38
37
39
39
40
40
41
41
42
42
43
43
44
44 100
45
45
46
46
10
19 11
41
43
34
47
47
48
48 100
11
35
49
49
50
50
11
35
51
51
52
52
11
37
53
53
54
54
55
55
56
56
26
42
57
57
58
58 100
59
59
60
60
19
J47
VERT
R1262 R1263
R1264 R1265
R1266 R1267
R1268
SLOT_RSTN4 P4_PDN SLOT_WAKEN4 P4_PWRGDN P4_PFN P4_PEP P4_CLK_EN SLOT_RSTN5 P5_PDN SLOT_WAKEN5 P5_PWRGDN P5_PFN P5_PEP P5_CLK_EN SLOT_RSTN6 P6_PDN SLOT_WAKEN6 P6_PWRGDN P6_PFN P6_PEP P6_CLK_EN SLOT_RSTN7 P7_PDN SLOT_WAKEN7 P7_PWRGDN P7_PFN P7_PEP P7_CLK_EN PS_ENABLEN
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 3
19
9
16
9
16
35
9
16
37
19 10
35
41
D
43
34
19 10
35
10
35
10
37
19 9
44
34 3
19
9
16
9
16
35
9
16
37
19 10
35
41
43
34
19 10
35
10
35
10
37
26
42
C
0.050X0.1 SHROUD
PORTS 4,5,6,7 HDR_2x30
1
9
18
100
17
0.050X0.1 SHROUD
9
9
R1260
9
9
PORTS 12,13,14,15
SLOT_RSTN20 P20_PDN SLOT_WAKEN20 P20_PWRGDN P20_PFN P20_PEP P20_CLK_EN SLOT_RSTN21 P21_PDN SLOT_WAKEN21 P21_PWRGDN P21_PFN P21_PEP P21_CLK_EN SLOT_RSTN22 P22_PDN SLOT_WAKEN22 P22_PWRGDN P22_PFN P22_PEP P22_CLK_EN SLOT_RSTN23 P23_PDN SLOT_WAKEN23 P23_PWRGDN P23_PFN P23_PEP P23_CLK_EN PS_ENABLEN
100
9
HDR_2x30
1
VERT
100
9
HDR_2x30
B
100
9
9
1
HDR_2x30
1
PORTS 8,9,10,11
SLOT_RESETN CARD_PRESENTN WAKEN POWERGOOD PWR_FLTN PWR_ENABLE CLOCK_ENABLEN
2
HDR_2x30
1
59
3
R1249
SLOT_RSTN16 P16_PDN SLOT_WAKEN16 P16_PWRGDN P16_PFN P16_PEP P16_CLK_EN SLOT_RSTN17 P17_PDN SLOT_WAKEN17 P17_PWRGDN P17_PFN P17_PEP P17_CLK_EN SLOT_RSTN18 P18_PDN SLOT_WAKEN18 P18_PWRGDN P18_PFN P18_PEP P18_CLK_EN SLOT_RSTN19 P19_PDN SLOT_WAKEN19 P19_PWRGDN P19_PFN P19_PEP P19_CLK_EN PS_ENABLEN
R1250
R1251 R1252
R1253 R1254
R1255 R1256
R1257
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 5
19
1
1
2
2
3
3
4
4
5
5
6
6 8
100
R1269
100
R1270
9
18
35
7
7
8
9
18
35
9
9
10
10
37
11
11
12
12
13
13
14
14
15
15
16
16 100
17
17
18
18
9
18
19 11
41
43
34
19
19
20
20 100
11
35
21
21
22
22
11
35
23
23
24
24
11
37
25
25
26
26
27
27
28
28
29
29
30
30 100
31
31
32
32
33
33
34
34 100
19
19 10
41
43
34
19 10
35
35
35
36
36
10
35
37
37
38
38
10
37
39
39
40
40
19 11
41
43
34
41
41
42
42
43
43
44
44 100
45
45
46
46
47
47
48
48 100
35
49
49
50
50
11
35
51
51
52
52
11
37
53
53
54
54
55
55
56
56
57
57
58
58 100
59
59
60
60
19 11
26
42
0.050X0.1 SHROUD
VERT
PORTS 16,17,18,19
J48
R1271 R1272
R1273 R1274
R1275 R1276
R1277
SLOT_RSTN0 P0_PDN SLOT_WAKEN0 P0_PWRGDN P0_PFN P0_PEP P0_CLK_EN SLOT_RSTN1 P1_PDN SLOT_WAKEN1 P1_PWRGDN P1_PFN P1_PEP P1_CLK_EN SLOT_RSTN2 P2_PDN SLOT_WAKEN2 P2_PWRGDN P2_PFN P2_PEP P2_CLK_EN SLOT_RSTN3 P3_PDN SLOT_WAKEN3 P3_PWRGDN P3_PFN P3_PEP P3_CLK_EN PS_ENABLEN
BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN
19 9
44
34 2
19
9
15
9
15
35
9
15
37
19 10
35
41
43
34
19 10
35
10
35
10
37
19 9
B
44
34 2
19
9
15
9
15
35
9
15
37
19 10
35
41
43
34
19 10
35
10
35
10
37
26
42
0.050X0.1 SHROUD
PORTS 0,1,2,3
A
A
S13
S14
SM_SW8 1 2 3 4 5 6 7 8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A
S7B
S8A
S8B
S15
SM_SW8 16 15 14 13 12 11 10 9
P0_CLK_EN P1_CLK_EN P2_CLK_EN P3_CLK_EN P4_CLK_EN P5_CLK_EN P6_CLK_EN P7_CLK_EN
1 2 3 4 5 6 7 8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A
S7B
S8A
S8B
SM_SW8 16 15 14 13 12 11 10 9
P8_CLK_EN P9_CLK_EN P10_CLK_EN P11_CLK_EN P12_CLK_EN P13_CLK_EN P14_CLK_EN P15_CLK_EN
1 2 3 4 5 6 7 8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A
S7B
S8A
S8B
16 15 14 13 12 11 10 9
P16_CLK_EN P17_CLK_EN P18_CLK_EN P19_CLK_EN P20_CLK_EN P21_CLK_EN P22_CLK_EN P23_CLK_EN
TITLE
EB-LOGAN-23
SIDEBAND CONNECTORS SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:04 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 42 OF 52 1
7
6
5
4
3
2
1
YEL
YEL
TP113
TP109
8
HDR_2x10
D
HDR_2x10
OUT
PART0_PERSTN
1 3
1
2
3
2
4
4
6
6
8
8
5
5
7
7
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
J80
VERT_SM
20
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN1 SLOT_RSTN3
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
2
7
39
43
44 39
2
7
39
43
14
44
OUT
PART4_PERSTN
2
2
3
4
4
7
39
43
44
5
5
6
6
3
7
39
43
44
7
7
8
8
4
7
39
43
44
9
9
10
10
4
7
39
43
44
11
11
12
12
5
7
39
43
44
13
13
14
14
5
7
39
43
44
15
15
16
16
17
17
18
18
19
19
20
20
19
41
19
41
42 42
YEL
TP110
1
3
3
J84
VERT_SM
TP135 YEL
YEL
1
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN14 SLOT_RSTN15
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
TP136
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
4
7
39
43
44
5
7
39
43
44
5
7
43
44
39
19
41
42
19
41
42
D
YEL
TP143
TP114
14
YEL
YEL
39
TP144
HDR_2x10 HDR_2x10
OUT
PART1_PERSTN
C
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
11
12
10 12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
J81
VERT_SM
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN5 SLOT_RSTN7
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
7
4
7
39
43
44
9
39
4
7
39
43
14
OUT
PART5_PERSTN
44
2
2
3
4
4
5
5
6
6
7
8
8
9
10
10
11
11
12
12
7
39
43
44
13
13
14
14
5
7
39
43
44
15
15
16
16
18
18
20
20
19
41
42
17
19
41
42
19
YEL
TP111
1
3
5
17 19
J85
VERT_SM
TP137 YEL
YEL
1
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN17 SLOT_RSTN18
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
TP138
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
4
7
39
43
44
5
7
39
43
44
5
7
39
43
44
19
41
42
19
41
42
C
YEL
TP145
TP115
14
YEL
YEL
39
TP146
HDR_2x10 HDR_2x10
OUT
PART2_PERSTN
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
12
11 13
B
13
14
14
15
15
16
16
17
17
18
18
20
20
19
19
J82
VERT_SM
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN9 SLOT_RSTN10
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
9
9
10
10
4
7
39
43
44
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
39
5 5
7 7
19
39 39 41
19
41
43 43
14
OUT
PART6_PERSTN
44 44
42 42
YEL
TP112
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
J86
VERT_SM
TP139 YEL
YEL
1
20
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN19 SLOT_RSTN21
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
TP140
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
4
7
39
43
44
5
7
39
43
44
5
7
39
43
44
19
41
42
19
41
42
B
YEL
TP147
TP116
14
YEL
YEL
39
TP148
HDR_2x10 HDR_2x10
39
14
OUT
PART3_PERSTN
1 3 5
2
2
3
4
4
5
6
6
1
7
7
8
9
9
10
10
11
11
12
12
13
13
14
14
15 17 19 VERT_SM
15
16
17
18
19
20
J83
8
16 18 20
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN11 SLOT_RSTN13
2.0MM NO-SHROUD
IN IN IN IN IN IN IN IN IN IN
2
7
39
43
44 39
2
7
39
43
44
3
7
39
43
44
14
OUT
PART7_PERSTN
1
2
2
3
3
4
4
5
5
6
6 8
3
7
39
43
44
7
7
8
4
7
39
43
44
9
9
10
10
4
7
39
43
44
11
11
12
12
5
7
39
43
44
13
13
14
14
15
15
16
16
17
17
18
18
19
19
5
7
19 19
39 41 41
43
44
42 42
YEL
VERT_SM
TP141
A
1
20
J87
20
SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN22 SLOT_RSTN23
IN IN IN IN IN IN IN IN IN IN
2.0MM NO-SHROUD
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
4
7
39
43
44
5
7
39
43
44
5
7
39
43
44
19
41
42
19
41
42
YEL
A
TP149
YEL
TP142
YEL
TP150
TITLE
EB-LOGAN-23
PARTITION RESET SELECT HEADERS SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:05 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 43 OF 52 1
6
5
4
3
44
43
39
7
2
BI
SLOT_HDR_RSTN0
HDR_2x10
1
1
2
2
3
3
4
4
5
5
6
6 8
7
7
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
18
18
20
20
17 19
17 19
J125
MAIN_RSTN SLOT_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S0_SATA_RSTN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
7
32
41 42 52
19 2
7
39
1
1
2
2
3
3
4
4
44
5
5
6
6
7
7
8
8
9
44
43
45
46
47
48
49
50
51
3
7
39
43
44
3
7
39
43
44
9
10
10
4
7
39
43
44
11
11
12
12
4
7
39
43
44
13
13
14
14
5
7
39
43
44
15
15
16
16
44
17
18
18
20
20
5
7
39
43
44
43
39
7
4
BI
SLOT_HDR_RSTN8
17
19
25
19
43
39
7
2
BI
SLOT_HDR_RSTN2
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
20
20
19
J126
MAIN_RSTN SLOT_RSTN2 SLOT_HDR_RSTN0 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S2_SATA_RSTN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
7
32
41 42 52
19
44
45
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
46
47
48
44
49
43
50
39
51
7
4
BI
SLOT_HDR_RSTN12
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
4
7
39
43
44
11
12
12
4
7
39
43
44
13
13
14
14
5
7
39
43
44
15
15
16
16
5
7
39
43
44
17
17
18
18
20
20
19
25
3
BI
SLOT_HDR_RSTN4
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
12
12
11
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
J127
MAIN_RSTN SLOT_RSTN4 SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S4_SATA_RSTN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
7
32
41 42 52
19
44
45
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
4
7
39
43
46
47
48
44
49
43
50
39
51
7
5
BI
SLOT_HDR_RSTN16
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
12
12
44
11
11
4
7
39
43
44
13
13
14
14
5
7
39
43
44
15
15
16
16
5
7
39
43
44
17
17
18
18
19
19
20
20
25
3
BI
SLOT_HDR_RSTN6
J131
VERT_SM
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
7 32 52 19
48
49
50
51
D
23 2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
5
7
39
43
44
25
MAIN_RSTN SLOT_RSTN12 SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S12_SATA_RSTN
32
41 42 52
19
44
45
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
5
7
39
43
44
5
7
39
43
44
46
47
48
49
50
51
C
25
MAIN_RSTN SLOT_RSTN16 P8_SATARSTN SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN12 SLOT_HDR_RSTN20 S16_SATA_RSTN
32
41 42 52
19
44
45
46
47
48
49
50
51
22 2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
5
7
39
43
44
B
25
2.0MM NO-SHROUD
YEL
YEL
7
7
47
TP124
2.0MM NO-SHROUD
TP120
39
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
46
2.0MM NO-SHROUD
1
HDR_2x10
43
7
45
YEL 1
VERT_SM
44
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
44
HDR_2x10
1
11
B
J130
VERT_SM
YEL
7
41 42 52
TP123
2.0MM NO-SHROUD
19
HDR_2x10
39
32
19
2.0MM NO-SHROUD
11
TP119
VERT_SM
43
7
HDR_2x10
1
19
44
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
YEL
YEL
HDR_2x10
44
J129
VERT_SM
MAIN_RSTN SLOT_RSTN8 P16_SATARSTN SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN12 SLOT_HDR_RSTN20 S8_SATA_RSTN
TP122
2.0MM NO-SHROUD
TP118
VERT_SM
C
1
YEL
YEL
HDR_2x10
D
2
TP121
7
TP117
8
HDR_2x10
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
12
14
14
11 13
13
15
15
16
16
17
17
18
18
19
19
20
20
VERT_SM
J128
MAIN_RSTN SLOT_RSTN6 SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S6_SATA_RSTN
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
7 32 52 19
41
44
45
46
47
48
49
50
51
42
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
12
12
14
14
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
4
7
39
43
44
11
44
13
4
7
39
43
44
43
39
7
5
BI
SLOT_HDR_RSTN20
13
5
7
39
43
44
15
15
16
16
5
7
39
43
44
17
17
18
18
19
19
20
20
25
2.0MM NO-SHROUD
VERT_SM
J132
MAIN_RSTN SLOT_RSTN20 SLOT_HDR_RSTN0 SLOT_HDR_RSTN2 SLOT_HDR_RSTN4 SLOT_HDR_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 S20_SATA_RSTN
41
44
45
46
47
48
49
50
51
42
2
7
39
43
44
2
7
39
43
44
3
7
39
43
44
3
7
39
43
44
4
7
39
43
44
4
7
39
43
44
5
7
39
43
44
25
2.0MM NO-SHROUD
A
A
TITLE
EB-LOGAN-23
SLOT RESET SELECT HEADERS SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:05 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 44 OF 52 1
8
7
6
5
4
3
2
1
R1433
R1430
R1427
R1424
R1421
R1418
R1415
R1412
+3V3
+3V3
1
C680
C679
C484
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
SM_SW8
400MA 2 3
0.1UF
1.0UF
4
10UF
C677
C678
0.1UF
0.1UF
C676
C480
0.1UF
16V
C476
0.1UF
10UF
0.1UF
C675
1%
SW1
FB10
S1A
S1B
S2A
S2B
S3A
S3B
S4A
5
S5A
6 7 8
S4B S5B
S6A
S6B
S7A
S7B
S8A
S8B
16
P0_ICS_FSEL0
15
P2_ICS_FSEL0
14
P4_ICS_FSEL0
13
P6_ICS_FSEL0
12
P8_ICS_FSEL0
11
P12_ICS_FSEL0
10
P16_ICS_FSEL0
9
P20_ICS_FSEL0
OUT OUT OUT OUT OUT OUT OUT
46 47 48 49 50 51 52
22PF
DNP 0402
2
2
1%
R1604
1
D
PCLK_FSEL
1%
R1400
C673
X2
5% 120OHM 0805
1
22PF
R1404
10 0603
DNP 0402 DNP 0402
R1605
D
C674
+3V3
5
23
FSEL1
nQ0
6
Q1
7
20
OE_REFOUT
nQ1
8
Q2
10
IREF
nQ2
11
25
SSM
Q3
12
BYPASS
nQ3
MAIN_RSTN 33.2
R1608
YEL
TP97
26
9
1%
R1434
R1431
R1428
R1425
C
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
13 15
GND
NC
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
7
32
41
44
46
R1609
LP0_CLKP
R1405
LP0_CLKN
R1401
LS0_CLKP
R637
LS0_CLKN
R1402
0.1UF 0.1UF 0.1UF 0.1UF
R1406 R1403 R630
OUT OUT OUT OUT
47
48
49
50
51
SW2
24
SM_SW8
24 25
678005005
25
1
1
1
2
2
2
3
C63
LSATA0_CLKP
C67
LSATA0_CLKN
3
3
4
C68
LSMA0_CLKP
4
4
5
C71
LSMA0_CLKN
5
NC NC NC NC
52
PCLK_MR
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
Q0
MR_nOE
21
R770
FSEL0
REF_OUT
0
22
5
6
6
6
7
7
7
8
MTG1
MTG1
MTG2
MTG2
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A
S5B
S6A
S6B
S7A S8A
S7B S8B
16
P0_ICS_MR
15
P2_ICS_MR
14
P4_ICS_MR
13
P6_ICS_MR
12
P8_ICS_MR
11
P12_ICS_MR
10
P16_ICS_MR
9
P20_ICS_MR
OUT OUT OUT OUT OUT OUT OUT
46 47 48 49 50 51 52
J88
U116
475
B
R1435
R1432
R1429
R1426
R1423
4
R1420
R633
R1411
R1410
R1409
R1408
R1611
R1610
5
R1417
R1414
R1607
J89
CONNSMA
1
10K DNP
PCLK_SSM 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
2
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
R1606
+3V3
R1407
R1399
28
REF_SEL
27
B
VDDA
30
DNP
P0_ICS_SSM
29
REF_IN
3
P0_ICS_MR
24
VDD
TP59
P0_ICS_FSEL0
14
VDD
XTAL_OUT
R1422
31
4
VDD
IN
C
VDD
XTAL_IN
R1419
2
R1416
1
R1413
ICS841484
3 SW3
SM_SW8
221789-0
1 J90
2
CONNSMA
3
5
4
4 5
1
6 7
2
3
8
S1A
S1B
S2A
S2B
S3A
S3B
S4A
S4B
S5A S6A
S5B S6B
S7A
S7B
S8A
S8B
16
P0_ICS_SSM
15
P2_ICS_SSM
14
P4_ICS_SSM
13
P6_ICS_SSM
12
P8_ICS_SSM
11
P12_ICS_SSM
10
P16_ICS_SSM
9
P20_ICS_SSM
OUT OUT OUT OUT OUT OUT OUT
46 47 48 49 50 51 52
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 0 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:05 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 45 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C732
C733
C734
C735
C736
C737
C738
C739
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
1%
R1557
1
400MA
22PF
DNP 0402
2
2
X8
FB16
0.1UF
C731
10UF
16V
1%
R1560
C729 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1558
+3V3 R1567
10 0603
C730
ICS841484
4
VDD
14
VDD
24
VDD
29
45
IN
P2_ICS_FSEL0
31
REF_IN
30
REF_SEL
VDDA
28
FSEL0
Q0
5
23
FSEL1
nQ0
6
Q1
7
nQ1
8
26 25
P2_ICS_SSM
27 9
1%
IN
3
P2_ICS_MR
B
MR_nOE IREF SSM BYPASS
R1562
YEL
Q2
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
R1563
LP2_CLKP
R1568
LP2_CLKN
R1564
LS2_CLKP
R1569
LS2_CLKN
R1565
0.1UF 0.1UF 0.1UF 0.1UF
R1570 R1566 R1571
OUT OUT OUT OUT
7
32
41
44
45
47
48
49
50
51
52
24 24 25
678005005
25
1
1
2
2
C73
LSATA2_CLKP
C76
LSATA2_CLKN
3
3
C80
LSMA2_CLKP
4
4
C81
LSMA2_CLKN
5
5
6
6
7
7
NC NC NC NC
MTG1
MTG1
MTG2
MTG2
J106
U122
475
R1556
45
IN
OE_REFOUT
MAIN_RSTN 33.2
TP103
22
20 45
21
REF_OUT
C
R771
VDD
0
XTAL_OUT
DNP
2
C
TP62
XTAL_IN
IN
1
B
R1579
R1578
R1577
R1576
R1575
R1574
R1573
R1572
5
4
1 2
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
10K DNP
R1559
R1561
J107
CONNSMA
3
221789-0
J108
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 2 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:01:06 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 46 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C744
C745
C746
C747
C748
C749
C750
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C743
10UF 1%
R1581
1
400MA
22PF
DNP 0402
2
2
X9
FB17
0.1UF
C742
1%
R1584
C740 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1582
+3V3 R1591
10 0603
C741
ICS841484
4
VDD
14
VDD
24
VDD
29
45
IN
P4_ICS_FSEL0
31
REF_IN
30
REF_SEL
VDDA
28
FSEL0
Q0
5
23
FSEL1
nQ0
6
Q1
7
nQ1
8
26 25
P4_ICS_SSM
27 9
1%
IN
3
P4_ICS_MR
B
MR_nOE IREF SSM BYPASS
R1586
YEL
Q2
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
R1587
LP4_CLKP
R1592
LP4_CLKN
R1588
LS4_CLKP
R1593
LS4_CLKN
R1589
0.1UF 0.1UF 0.1UF 0.1UF
R1594 R1590 R1595
OUT OUT OUT OUT
7
32
41
44
45
46
48
49
50
51
52
24 24 25
678005005
25
1
1
2
2
C84
LSATA4_CLKP
C85
LSATA4_CLKN
3
3
C88
LSMA4_CLKP
4
4
C89
LSMA4_CLKN
5
5
6
6
7
7
NC NC NC NC
MTG1
MTG1
MTG2
MTG2
J109
U123
475
R1580
45
IN
OE_REFOUT
MAIN_RSTN 33.2
TP104
22
20 45
21
REF_OUT
C
R772
VDD
0
XTAL_OUT
DNP
2
C
TP63
XTAL_IN
IN
1
B
J110
R1603
R1602
R1601
R1600
R1599
R1598
R1597
5 R1596
R1583
R1585
CONNSMA 4
1 3
221789-0
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
10K DNP
2
J111
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 4 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:06 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 47 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C685
C686
C687
C688
C689
C690
C691
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C684
10UF
400MA
1%
R1437
1
FB11
22PF
DNP 0402
2
2
X3
0.1UF
C683
1%
R1440
C681 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1438
+3V3 R1447
10 0603
C682
ICS841484
45
IN
P6_ICS_FSEL0
REF_IN
30
REF_SEL
28 21
Q0
5 6
Q1
7
nQ1
8
9
OE_REFOUT MR_nOE IREF SSM BYPASS
C
MAIN_RSTN 33.2
R1442
YEL
TP98
nQ0
27
Q2
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
R1443
LP6_CLKP
R1448
LP6_CLKN
R1444
LS6_CLKP
R1449
LS6_CLKN
R1445
0.1UF 0.1UF 0.1UF 0.1UF
R1450 R1446 R1451
OUT OUT OUT OUT
7
32
41
44
45
46
47
49
50
51
52
24 24 25
678005005
1
1
2
2
3
3
C100 LSMA6_CLKP
4
4
C102 LSMA6_CLKN
5
5
6
6
7
7
C95
LSATA6_CLKP
C99
LSATA6_CLKN
NC NC NC NC
25
MTG1
MTG1
MTG2
MTG2
J91
U117
475
B
VDDA
REF_OUT
FSEL1
25
P6_ICS_SSM
29
FSEL0
26
1%
IN
24
VDD
23
3
P6_ICS_MR
R1436
45
IN
14
VDD
22
20 45
4
VDD
R773
31
VDD
0
XTAL_OUT
DNP
2
C
TP64
XTAL_IN
IN
1
B
J92 R1441
R1459
R1458
R1457
R1456
R1455
R1454
R1453
5 R1452
R1439
CONNSMA 4
1 3
221789-0
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
10K DNP
2
J93
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 6 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:01:06 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 48 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C696
C697
C698
C699
C700
C701
C702
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C695
10UF 1%
R1461
1
400MA
22PF
DNP 0402
2
2
X4
FB12
0.1UF
C694
1%
R1464
C692 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1462
+3V3 R1471
10 0603
C693
ICS841484
14
VDD
24
VDD
29
VDDA
28
5
nQ0
6
Q1
7
nQ1
8
27 9
SSM BYPASS
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
32
41
44
45
46
47
48
50
51
52
R1467
LP8_CLKP
R1472
LP8_CLKN
R1468
LS8_CLKP
R1473
LS8_CLKN
R1469
0.1UF 0.1UF 0.1UF 0.1UF
R1474 R1470 R1475
OUT OUT OUT OUT
22 22 25
678005005
1
1
2
2
C108 LSATA8_CLKN
3
3
C110 LSMA8_CLKP
4
4
C112 LSMA8_CLKN
5
5
6
6
7
7
C105 LSATA8_CLKP
NC NC NC NC
25
MTG1
MTG1
MTG2
MTG2
J94
U118
475
B
IREF
Q2
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
7
B
R1483
25
P8_ICS_SSM
1%
IN
26
MR_nOE
YEL
DNP
Q0
FSEL1
3
P8_ICS_MR
R1460
45
IN
R1466
TP65
FSEL0
23
OE_REFOUT
MAIN_RSTN 33.2
TP99
22
20 45
21
REF_OUT
R1482
REF_SEL
R1481
P8_ICS_FSEL0
30
R1480
IN
REF_IN
R1476
45
31
C
R774
4
VDD
0
VDD
R1479
XTAL_OUT
R1478
2
C
R1477
XTAL_IN
IN
1
J95 5
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
R1465
R1463
CONNSMA 4
1
10K DNP
2
3
221789-0
J96
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 8 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:06 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 49 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C707
C708
C709
C710
C711
C712
C713
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C706
10UF 1%
R1485
1
400MA
22PF
DNP 0402
2
2
X5
FB13
0.1UF
C705
1%
R1486 C703 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1488
+3V3 R1495
10 0603
C704
ICS841484
4
VDD
14
VDD
24
VDD
29
P12_ICS_FSEL0
30
REF_SEL
VDDA
28
FSEL0
Q0
5
23
FSEL1
nQ0
6
Q1
7
nQ1
8
26 25
P12_ICS_SSM
27 9
1%
IREF SSM BYPASS
YEL
Q2
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
R1491
LP12_CLKP
R1496
LP12_CLKN
R1492
LS12_CLKP
R1497
LS12_CLKN
R1493
0.1UF 0.1UF 0.1UF 0.1UF
R1498 R1494 R1499
OUT OUT OUT OUT
32
41
44
45
46
47
48
49
51
52
24 25
678005005
1
1
2
2
C117 LSATA12_CLKN
3
3
C120 LSMA12_CLKP
4
4
C121 LSMA12_CLKN
5
5
6
6
7
7
C113 LSATA12_CLKP
NC NC NC NC
25
MTG1
MTG1
MTG2
MTG2
J97
R1507
R1506
R1505
R1504
R1500
B
J98
CONNSMA
R1489
5
4
1
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
R1487
7
24
U119
475
B
MR_nOE
R1490
R1503
IN
3
P12_ICS_MR
R1484
45
IN
OE_REFOUT
MAIN_RSTN 33.2
TP100
22
20 45
21
REF_OUT
R1502
IN
REF_IN
R1501
45
31
C
R775
VDD
0
XTAL_OUT
DNP
2
C
TP66
XTAL_IN
IN
1
10K DNP
2
3
221789-0
J99
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 12 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:07 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 50 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C718
C719
C720
C721
C722
C723
C724
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C717
10UF 1%
R1509
1
400MA
22PF
DNP 0402
2
2
X6
FB14
0.1UF
C716
1%
R1512
C714 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1510
+3V3 R1519
10 0603
C715
ICS841484
4
VDD
14
VDD
24
VDD
29
P16_ICS_FSEL0
30
REF_SEL
VDDA
28
FSEL0
Q0
5
23
FSEL1
nQ0
6
Q1
7
nQ1
8
26 25
P16_ICS_SSM
27 9
1%
IREF SSM BYPASS
YEL
Q2
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
R1515
LP16_CLKP
R1520
LP16_CLKN
R1516
LS16_CLKP
R1521
LS16_CLKN
R1517
0.1UF 0.1UF 0.1UF 0.1UF
R1522 R1518 R1523
OUT OUT OUT OUT
7
32
41
44
45
46
47
48
49
50
52
23 23 25
678005005
1
1
2
2
C123 LSATA16_CLKN
3
3
C124 LSMA16_CLKP
4
4
C125 LSMA16_CLKN
5
5
6
6
7
7
C122 LSATA16_CLKP
NC NC NC NC
25
MTG1
MTG1
MTG2
MTG2
J100
U120 R1531
R1530
R1529
R1528
B R1524
475
B
MR_nOE
R1514
R1527
IN
3
P16_ICS_MR
R1508
45
IN
OE_REFOUT
MAIN_RSTN 33.2
TP101
22
20 45
21
REF_OUT
R1526
IN
REF_IN
R1525
45
31
C
R768
VDD
0
XTAL_OUT
DNP
2
C
TP67
XTAL_IN
IN
1
J101 5
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
R1511
R1513
CONNSMA 4
1
10K DNP
2
3
221789-0
J102
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 16 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
CHECKED BY
Thu Jul 01 15:01:07 2010 3
2.0
Derek Huang
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 51 OF 52 1
8
7
6
5
4
D
3
2
1
1%
C514
C510
C518
C522
C513
C727
C728
0.1UF
0.1UF
0.1UF
0.1UF
10UF
0.1UF
1.0UF
16V
C507
10UF 1%
R1533
1
400MA
22PF
DNP 0402
2
2
X7
FB15
0.1UF
C726
1%
R1536
C725 1
22PF
D
5% 120OHM 0805
DNP 0402 DNP 0402
R1534
+3V3 R1543
10 0603
C501
ICS841484
14
VDD
24
VDD
29
VDDA
28
Q1
7
nQ1
8
25
P20_ICS_SSM
27 9
1%
IN
26
SSM BYPASS
10
nQ2
11
Q3
12
nQ3
13
GND
NC
15
19
GND
NC
16
32
GND
NC
17
33
PGND
NC
18
U121
R1535
R1537
475
B
IREF
Q2
33.2 33.2 33.2 33.2 33.2 33.2 33.2 33.2
NC NC NC NC
R1539
LP20_CLKP
R1544
LP20_CLKN
R1540
LS20_CLKP
R1545
LS20_CLKN
R1541
0.1UF 0.1UF 0.1UF 0.1UF
R1546 R1542 R1547
OUT OUT OUT OUT
7
32
41
44
45
46
47
48
49
50
51
24 24 25
678005005
1
1
2
2
C127 LSATA20_CLKN
3
3
C128 LSMA20_CLKP
4
4
C129 LSMA20_CLKN
5
5
6
6
7
7
C126 LSATA20_CLKP
25
DNP
6
TP68
5
nQ0
MR_nOE
YEL
MTG1
MTG1
MTG2
MTG2
R1555
Q0
FSEL1
3
P20_ICS_MR
R1532
45
IN
R1538
R1554
FSEL0
23
OE_REFOUT
MAIN_RSTN 33.2
TP102
22
20 45
21
REF_OUT
R1553
REF_SEL
R1552
P20_ICS_FSEL0
30
R1551
IN
REF_IN
J103
B
J104
49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9
45
31
C
R776
4
VDD
0
VDD
R1550
XTAL_OUT
R1549
2
C
R1548
XTAL_IN
IN
1
CONNSMA 5
4
1
10K DNP
2
3
221789-0
J105
CONNSMA 5
4
1 2
3
221789-0
A
A
TITLE
EB-LOGAN-23
PORT 20 CLOCK GENERATOR SIZE
B
FAB P/N
DRAWING NO.
SCH-PESEB-001
AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC.
8
7
6
5
2010
4
IDT
Derek Huang
Thu Jul 01 15:01:07 2010 3
2.0
CHECKED BY
Tony Tran
6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C)
REV.
18-691-001
2
SHEET 52 OF 52 1
