Transcript
Datasheet | Rev. 5.0 | 2015
IMM2G64D3(L)SOD8AG (Die Revision B) 16GByte (2048M x 64 Bit) 16GB DDR3 Unbuffered SO-DIMM RoHS Compliant Product
Datasheet Version 5.0
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Version: Rev. 5.0, JUN 2015 5.0 – Update the SPD information in Table 19 Update tRFC in Table 18
Version: Rev. 4.0, JAN 2015 4.0 – Added DRAM operation temperature for Industrial Temperature Product in Table 10. Updated notes in Table 12, 13 Moved VSEH information from Table 14 to Table 15 Corrected tCPDED in Table 18
Version: Rev. 3.0, JUN 2014 3.0 – Added module thickness E in Table 9
Version: Rev. 2.0, MAY 2014 2.0 – Updated CAS Latency support to include CL5 Updated IDD values in Table 17 Updated tAA, tRCD, tRRD, tRP, tFAW in Table 18, 19
Version: Rev. 1.0, NOV 2013 1.0 - Initial release Remark: Please refer to the last page of the i) Contents ii) List of Table iii) List of Figures .
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:
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Features 204-Pin Unbuffered Small Outline Dual-In-Line Memory Module Capacity: 16GB JEDEC-Standard Bi-directional Differential Data-Strobe 64 Bit Data Bus Width without ECC Programmable CAS Latency (CL): o PC3-12800: 5, 6, 7, 8, 9, 10, 11 o PC3-10600: 5, 6, 7, 8, 9, 10 Programmable CAS Write Latency (CWL): o PC3-12800: 5, 6, 7, 8 o PC3-10600: 5, 6, 7 Programmable Additive Latency (Posted /CAS): 0, CL-2 or CL-1(Clock) On-Die Termination (ODT) ZQ Calibration Supported Burst Type (Sequential & Interleave) Burst Length: 4, 8 Refresh Mode: Auto and Self 8192 Refresh Cycles / 64ms Asynchronous Reset Serial Presence Detect (SPD) with EEPROM Gold Edge Contacts 100% RoHS-Compliant Standard Module Height: 30.00mm (1.181 inch)
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Table 1 - Ordering Information for RoHS Compliant Product Part Number
Module Density Configuration # of Ranks
Module Type
IMM2G64D3xSOD8AGBzzzy
16GB
16GB DDR3 Unbuffered SO-DIMM
2Gx64
2
Notes: x: Operating Voltage y: Operating Temperature zzz: Speed Grade
Table 2 - Operating Voltage Part Number
Operating Voltage
Blank
VDD, VDDQ = 1.5V (1.425V-1.575V) VDD, VDDQ = 1.35V (1.283V-1.45V) Backward compatible to VDD, VDDQ = 1.5V (1.425V-1.575V)
L
Table 3 - Temperature Grade Part Number
Temperature Grade
Tcase
Blank
Commercial temperature
0°C to 95°C
I
Industrial temperature
-40°C to 95°C
Remark: Tcase is the case surface temperature on the center/top side of the DRAM. The refresh rate is required to double when 85 oC < Tcase <= 95 oC.
Table 4 - Speed Grade Part Number
Speed Grade
Max Clock Frequency (min. Clock Cycle time @ min. CAS Latency)
125
PC3-12800 (DDR3-1600)
800MHz (1.25ns@CL=11)
15E
PC3-10600 (DDR3-1333)
667MHz (1.5ns@CL=9)
Table 5 - Memory Chip Information Part Number
Base Device Brand
Base device
Voltage Type
Chip Packing
IMM2G64D3LSOD8AG-Bzzzy
I’M
IM8G08D3FBBG
1.35V
1024Mx8
Lead Free
IMM2G64D3SOD8AG-Bzzzy
I’M
IM8G08D3EBBG
1.5V
1024Mx8
Lead Free
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Part Number Decoder IMM
2G64 D3 (L) SO D 8 A G - B 125 (I)
Intelligent Memory Module
Temperature Grade Blank = Commercial Temperature (0°C to 95°C TC) I = Industrial Temperature (-40°C to 95°C TC)
Module Configuration 2G64 = 2Gx64 (16GB)
Speed Grade 15E = PC3-10600 / DDR3 1333 125 = PC3-12800 / DDR3 1600
Memory Type D3 = DDR3 DDR3L option Blank = 1.5 Volt L = 1.35 or 1.5 Volt (DDR3L)
IC Revision A = Revision A B = Revision B C = Revision C
Module Form-Factor SO = Unbuffered SO-DIMM
RoHS compliance G = Green / RoHS
Number of Ranks D = Dual Rank
Module PCB Revision A = Revision A B = Revision B C = Revision C DRAM Bit width 8 = using x8 components
Table 6 - Addressing Parameter
16GB
Refresh count Row address Device bank address Device configuration Column address Module rank address Number of devices
8K 64K A[15:0] 8 BA[2:0] 8Gb (1024Mx8) 2K A[9:0], A11 2 /S[1:0] 16
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Table 7 - Pin Assignment Pin
Name
Pin
Name
Pin
Name
Pin
Name
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101
VREFDQ VSS D0 D1 VSS DM0 VSS D2 D3 VSS D8 D9 VSS /DQS1 DQS1 VSS D10 D11 VSS D16 D17 VSS /DQS2 DQS2 VSS D18 D19 VSS D24 D25 VSS DM3 VSS D26 D27 VSS CKE0 VDD NC BA2 VDD A12,/BC A9 VDD A8 A5 VDD A3 A1 VDD CK0
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102
VSS D4 D5 VSS /DQS0 DQS0 VSS D6 D7 VSS D12 D13 VSS DM1 /RESET VSS D14 D15 VSS D20 D21 VSS DM2 VSS D22 D23 VSS D28 D29 VSS /DQS3 DQS3 VSS D30 D31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1
103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
/CK0 VDD A10, AP BA0 VDD /WE /CAS VDD A13 /S1 VDD NC VSS D32 D33 VSS /DQS4 DQS4 VSS D34 D35 VSS D40 D41 VSS DM5 VSS D42 D43 VSS D48 D49 VSS /DQS6 DQS6 VSS D50 D51 VSS D56 D57 VSS DM7 VSS D58 D59 VSS SA0 VDDSPD SA1 VTT
104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
/CK1 VDD BA1 /RAS VDD /S0 ODT0 VDD ODT1 NC VDD VREFCA VSS D36 D37 VSS DM4 VSS D38 D39 VSS D44 D45 VSS /DQS5 DQS5 VSS D46 D47 VSS D52 D53 VSS DM6 VSS D54 D55 VSS D60 D61 VSS /DQS7 DQS7 VSS D62 D63 VSS NC SDA SCL VTT
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Table 8 - Pin Description Pin Name
Description
Pin Name
Description
VDD
SDRAM core power supply
VREFDQ
SDRAM I/O reference supply
VREFCA
SDRAM supply
VSS
Power supply return (ground)
A0-A15
SDRAM address bus
BA0-BA2
SDRAM bank addresses
CK0-CK1
SDRAM clocks (positive line of differential pair)
/CK0-/CK1
SDRAM clocks (negative line of differential pair)
/RAS
SDRAM row address strobe
/CAS
SDRAM column address strobe
/WE
SDRAM write enable
CKE0-CKE1
SDRAM clock enable lines
/S0-/S1
DIMM Rank Select Lines
ODT0-ODT1
On-die termination control lines
DQS0-DQS7
SDRAM data strobes (positive line of differential pair)
/DQS0-/DQS7
SDRAM data strobes (negative line of differential pair)
D0-D63
DIMM memory data bus
DM0-DM7
SDRAM data mask/high data strobes
SCL
EEPROM clock
SDA
EEPROM date line
SA0-SA1
EEPROM address input
VDDSPD
EEPROM positive power supply
/RESET
Reset Pin
VTT
Termination Voltage
NC
Spare Pins (no connect)
Datasheet Version 5.0
command/address
reference
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Figure 1 – Module Dimension 204 Pin DDR3 SDRAM Unbuffered SO-DIMM
B
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Table 9 - PCB Dimension Symbol
MIN
NOM
MAX
A
29.85
30.00
30.15
A1 D
20.00 Basic 67.45
67.60
D2
63.60 Basic
D3
1.65 Basic
D5
9.00 Basic
e1
21.00 Basic
e2
39.00 Basic
E
67.75
3.80
Notes:
All dimensioning and tolerancing conform to ASME Y14.5M-1994. Tolerances for all dimensions ±0.15 unless otherwise specified. All dimensions are in millimeters.
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Figure 2 – Functional Block Diagram (Page 1 of 2)
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Figure 3 – Functional Block Diagram (Page 2 of 2)
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Electrical Parameter Table 10 - Absolute Maximum DC Ratings Parameter
Symbol
Rating
Unit
Notes
Voltage on VDD, pin relative to VSS
VDD
-0.4V ~ 1.975
V
1,3
Voltage on VDDQ, pin relative to VSS
VDDQ
-0.4V ~ 1.975
V
1,3
Voltage on any pins relative to VSS
VIN, VOUT
-0.4V ~ 1.975
1
V
DRAM Storage temperature
TSTG
-55 ~ 100
o
C
1,2
DRAM Operation temperature (Standard Product) DRAM Operation temperature (Industrial Temperature Product)
Tcase
0 ~ 95
o
C
2,4,6
Tcase
-40 ~ 95
o
C
2,5,6
Notes: 1
2
3
4
5
6
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature or DRAM operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6 x VDDQ, when VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-95 °C under all operating conditions. The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between -40-95 °C under all operating conditions. Some applications require operation of the Extended Temperature Range between 85 °C and 95 °C case temperature. Full Specifications are guaranteed in this range but the following additional conditions apply a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Table 11 - DC Electrical Characteristics and Operating Conditions Parameter / Condition Supply voltage I/O supply voltage Supply voltage I/O supply voltage
Symbol VDD VDDQ VDD VDDQ
Rating
Units Notes
Min
Typ.
Max
1.283
1.35
1.45
1.425
1.5
1.575
V V V V
1,2 1,2 1,2,3 1,2,3
Notes: 1 2
3
VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ. VDD and VDDQ may include AC noise of +/-50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. Module is backward-compatible with 1.5V operation.
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Table 12 - DC Electrical Characteristics and Input Conditions Parameter / Condition VIN low; DC/commands/address buses (1.35V Operation) VIN low; DC/commands/address buses (1.5V Operation) VIN high; DC/commands/address buses (1.35V Operation) VIN high; DC/commands/address buses (1.5V Operation) Input reference voltage; command/address bus I/O reference voltage DQ bus Command/address termination voltage (system level, not direct DRAM input)
Symbol
Rating
Units Notes
Min
Typ.
Max
VIL
VSS
-
-0.090
V
VIL
VSS
-
-0.100
V
VIH
0.090
-
VDD
V
VIH
0.100
-
VDD
V
VREFCA(DC)
0.49* VDD
0.50* VDD
0.51* VDD
V
1,2
VREFDQ(DC)
0.49* VDD
0.50* VDD
0.51* VDD
V
2,3
VTT
-
0.50* VDDQ
-
V
4
Notes: 1
2
3
4
VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC). DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC). VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent.
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Table 13 - Input Switching Conditions Parameter / Condition
Symbol
Value
Units
1.35V Operation 1.5V Operation Input high AC voltage: Logic 1 @ 175mV Input high AC voltage: Logic 1 @ 160mV Input high AC voltage: Logic 1 @ 150mV Input high AC voltage: Logic 1 @ 135mV Input high DC voltage: Logic 1 @ 100mV Input high DC voltage: Logic 1 @ 90mV Input low DC voltage: Logic 0 @ -90mV Input low DC voltage: Logic 0 @ -100mV Input low AC voltage: Logic 0 @ -135mV Input low AC voltage: Logic 0 @ -150mV Input low AC voltage: Logic 0 @ -160mV Input low AC voltage: Logic 0 @ -175mV Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0
Command and Address VIH(AC175)min VIH(AC160)min VIH(AC150)min VIH(AC135)min VIH(DC100)min VIH(DC90)min VIL(DC90)max VIL(DC100)max VIL(AC135)max VIL(AC150)max VIL(AC160)max VIL(AC175)max DQ and DM VIH(AC150)min VIH(AC135)min VIH(DC100)min VIH(DC90)min VIL(DC90)max VIL(DC100)max VIL(AC135)max VIL(AC150)max
160 135 90 -90 -135 -160 -
175 150 100 -100 -150 -175
mV mV mV mV mV mV mV mV mV mV mV mV
135 90 -90 -135 -
150 100 -100 -150
mV mV mV mV mV mV mV mV
Notes: 1
2 3 4
All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak).
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Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS) Parameter / Condition Differential input voltage logic high – slew (1.35V Operation) Differential input voltage logic high – slew (1.5V Operation) Differential input voltage logic low – slew (1.35V Operation) Differential input voltage logic low – slew (1.5V Operation) Differential input voltage logic high Differential input voltage logic low Differential Input Cross Point Voltage relative to VDD/2 for CK, CK (1.35V Operation) Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS (1.35V Operation) Differential Input Cross Point Voltage relative to VDD/2 for CK, CK (1.5V Operation) Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS (1.5V Operation)
Symbol
Rating
Units Notes
Min
Max
VIH,diff
+180
-
mV
1
VIH,diff
+200
-
mV
1
VIL,diff
-
-180
mV
1
VIL,diff
-
-200
mV
1
VIH,diff(AC)
2* (VIH(AC) - VREF)
-
mV
2
VIL,diff(AC)
-
2* (VIL(AC) - VREF)
mV
3
VIX
-150
150
mV
4
VIX
-150
150
mV
-150
150
-175
175
-150
150
VIX
VIX
mV
5
mV
Notes: 1 2 3 4
5
Defines slew rate reference points, relative to input crossing voltages. Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable. Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable. The relation between VIX Min/Max and VSEL/VSEH should satisfy following: (VDD/2) + VIX(min)-VSEL >= 25mV; VSEH - ((VDD/2) + VIX(max)) >= 25mV; Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and /CK are monotonic with a single-ended swing VSEL/VSEH of at least VDD/2 +/-250mV, and when the differential slew rate of CK-/CK is larger than 3V/ns.
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Table 15 - Single-Ended Output Driver Characteristics Parameter / Condition Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF 0.1 * VDDQ and VOH(AC) = VREF + 0.1 * VDDQ (1.35V Operation) Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF 0.1 * VDDQ and VOH(AC) = VREF + 0.1 * VDDQ (1.5V Operation) Single-ended high level for strobes Single-ended high level for CK, /CK Single-ended low level for strobes Single-ended low level for CK, /CK Single-ended DC high-level output voltage Single-ended DC mid-level output voltage Single-ended DC low-level output voltage Single-ended AC high-level output voltage Single-ended AC low-level output voltage Test load for AC timing and output slew rates
Notes: 1
2 3
Ω
Symbol
Rating
Units Notes
Min
Max
SRQse
1.75
5
V/ns
1,2,3
SRQse
2.5
5
V/ns
1,2,3
VDDQ/2 + 175
-
mV
2
VDD/2 + 175
-
mV
2
-
VDDQ/2 - 175
mV
3
-
VDD/2 - 175
mV
3
VSEH
VSEL
VOH(DC)
0.8 * VDDQ
V
1
VOM(DC)
0.5 * VDDQ
V
1
VOL(DC)
0.2 * VDDQ
V
1
VOH(AC)
VTT + 0.1 * VDDQ
V
1,2
VOL(AC)
VTT - 0.1 * VDDQ
V
1,2
Ω resistor
Output to VTT (VDDQ/2) via 25
Ω
RZQ of 240 (±1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). VTT = VDDQ/2. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or all switching the opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns.
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Table 16 - Differential Output Driver Characteristics Parameter / Condition Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = 0.2 * VDDQ and VOH,diff(AC) = + 0.2 * VDDQ (1.35V Operation) Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = 0.2 * VDDQ and VOH,diff(AC) = + 0.2 * VDDQ (1.5V Operation) Differential high-level output voltage Differential low-level output voltage Test load for AC timing and output slew rates
Notes: 1
2
Ω
Symbol
Rating
Units Notes
Min
Max
SRQdiff
3.5
12
V/ns
1
SRQdiff
5
10
V/ns
1
VOH,diff(AC)
+0.2 * VDDQ
V
1
VOL,diff(AC)
-0.2 * VDDQ
V
1
Ω resistor
Output to VTT (VDDQ/2) via 25
Ω
RZQ of 240 (±1%) with RZQ/7 enabled (default 34 driver) and is applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). VREF = VDDQ/2; slew rate @ 5V/ns, interpolate for faster slew rate.
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For part number IMM2G64D3(L)SOD8AG-B125(I)
Table 17 - IDD Specifications with Conditions and Operation Current Parameter / Condition
Symbol
Current 1.35V 1.5V Operation Operation
Units
Notes
Operating current 0; One bank ACTIVATE-toPRECHARGE
IDD0
1008
1080
mA
1, 2
Operating current 1; One bank ACTIVATE-to-READto-PRECHARGE
IDD1
1264
1360
mA
1, 2
IDD2P0
448
480
mA
1, 3
IDD2P1
448
480
mA
1, 3
IDD2Q
576
640
mA
1, 3
IDD2N
896
960
mA
1, 3
IDD2NT
1056
1120
mA
1, 3
IDD3P
480
512
mA
1, 3
IDD3N
992
1120
mA
1, 3
IDD4R
2424
2560
mA
1, 2
IDD4W
1344
1440
mA
1, 2
IDD5B
2664
2800
mA
1, 2
IDD6
320
352
mA
1, 3
IDD6ET
320
352
mA
1, 3
IDD7
3464
3640
mA
1, 2
IDD8
368
400
mA
1, 2
Precharge power-down current; Slow exit Precharge power-down current; Fast exit Precharge quiet standby current Precharge standby current Precharge standby ODT current Active power-down current Active standby current Burst read operating current Burst write operating current Refresh current Self refresh temperature current: MAX Tc = 85oC Self refresh temperature current (SRT-enabled): MAX Tc = 95oC All banks interleaved read current Reset current
Notes: 1
2 3
Value shown for DDR3 SDRAM only and are computed from values specified in the 8Gbit component data sheet. One module rank in the active IDD, the other rank in IDD2P0. All ranks in this IDD conditions.
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For part number IMM2G64D3(L)SOD8AG-B125(I)
Table 18 - AC Timing Parameter and Operating Conditions Parameter / Condition
Symbol
Clock period average: TC = 0oC to 85oC DLL disable mode TC => 85oC to 95oC Clock periods average: DLL enable mode (CL = 11, CWL = 8) Clock periods average: DLL enable mode (CL = 9, CWL = 7) High pulse width average Low pulse width average Clock period jitter DLL locked DLL locking Clock absolute period
t
Clock absolute high pulse width
t
Clock absolute low pulse width
t
Cycle-to-cycle jitter
t
Cumulative error across
DLL locked DLL locking 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles 11 cycles 12 cycles n = 14,…49, 50 cycles
Clock Timing CK (DLL_DIS) 8 8 t CK (AVG) 1.25
DQS, /DQS to DQ skew, per access DQ output hold time from DQS, /DQS DQ Low-Z time from CK, /CK DQ High-Z time from CK, /CK DQS, /DQS rising to CK, /CK rising DQS, /DQS differential input low pulse width
Max
Units
7800 3900 <1.5
ns ns
t
1.5
<1.875
ns
t
0.47 0.47 -70 -60 t CK (AVG) MIN + tJITper MIN 0.43
0.53 0.53 70 60 t CK (AVG) MAX + tJITper MAX -
t
0.43
-
CK (AVG)
CH (AVG) CL (AVG) t JITper t JITper,Ick t CK (ABS) t
CH (ABS) CL (ABS)
-103 -122 -136 -147 -155 -163 -169 -175 -180 -184 -188 (1+0.68ln[n]) * tJITper MIN DQ Input Timing Base (specification) tDS (AC135) 25
Data setup time to DQS, /DQS (1.35V Operation) Data setup time to DQS, Base (specification) /DQS (1.5V Operation) Data hold time from DQS, Base (specification) /DQS (1.35V Operation) Data hold time from DQS, Base (specification) /DQS (1.5V Operation) Minimum data pulse width
Datasheet Version 5.0
Min
JITcc JITcc,Ick t ERR2per t ERR3per t ERR4per t ERR5per t ERR6per t ERR7per t ERR8per t ERR9per t ERR10per t ERR11per t ERR12per t ERRnper t
140 120 103 122 136 147 155 163 169 175 180 184 188 (1+0.68ln[n]) * tJITper Max -
t
10
-
t
55
-
t
45
-
DS (AC150) DH (DC90) DH (DC100)
t
DIPW 360 DQ Output Timing t DQSQ t QH 0.38
-
t
225 225
LZDQ -450 HZDQ DQ Strobe Input Timing t DQSS -0.27 t DQSL 0.45 t
19 www.intelligentmemory.com
100 -
0.27 0.55
CK CK ps ps ps t
t CK (AVG) t CK (AVG) ps ps ps ps ps ps ps ps ps ps ps ps ps ps
ps ps ps ps ps ps ps ps ps ps CK (AVG) ps ps t
t
CK CK
t
IMM2G64D3(L)SOD8AG
For part number IMM2G64D3(L)SOD8AG-B125(I)
Parameter / Condition
Symbol
DQS, /DQS falling setup to CK, /CK rising DQS, /DQS falling hold from CK, /CK rising DQS, /DQS differential input high pulse width DQS, /DQS differential WRITE preamble DQS, /DQS differential WRITE postamble
t
DQS, /DQS rising to/from CK, /CK DQS, /DQS differential output high time DQS, /DQS differential output low time DQS, /DQS Low-Z time (RL-1) DQS, /DQS High-Z time (RL+BL/2) DQS, /DQS differential READ preamble DQS, /DQS differential READ postamble
Min
DSS 0.18 DSH 0.18 t DQSH 0.45 t WPRE 0.9 t WPST 0.3 DQ Strobe Output Timing t DQSCK -225 t QSH 0.40 t QSL 0.40 t LZDQS -450 t HZDQS t RPRE 0.9 t
t
RPST
0.3
Command and Address Timing t DLLK 512 t IS (AC160) 60
Max
Units
0.55 -
t
225 225 225 greater of tLZ(DQS) (MIN), t DQSK (MAX) greater of tDQSCK (MIN) + tQSH (MIN), tHZ(DQS) (MAX)
ps t CK t CK ps ps t CK
-
t
CK ps
CK CK t CK t CK t CK t
t
CK
DLL locking time CTRL, CMD, ADDR setup to CK, /CK (1.35V Operation)
Base (specification)
CTRL, CMD, ADDR setup to CK, /CK (1.5V Operation)
Base (specification)
t
45
-
ps
CTRL, CMD, ADDR setup to CK, /CK (1.35V Operation)
Base (specification)
t
185
-
ps
CTRL, CMD, ADDR setup to CK, /CK (1.5V Operation)
Base (specification)
t
170
-
ps
CTRL, CMD, ADDR hold from Base CK, /CK (1.35V Operation) (specification)
t
130
-
ps
CTRL, CMD, ADDR hold from Base CK, /CK (1.5V Operation) (specification)
t
120
-
ps
Minimum CTRL, CMD, ADDR pulse width ACTIVATE to internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period ACTIVATE-to-ACTIVATE minimum period Four ACTIVATE windows (2KB page size) Write recovery time Delay from start of internal WRITE transaction to internal READ command READ-to-PRECHARGE time /CAS-to-/CAS command delay Auto precharge write recovery + precharge time MODE REGISTER SET command cycle time MODE REGISTER SET command update delay MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit
t
IPW RCD t RP t RAS t RC t RRD t FAW t WR t WTR
560 13.125 13.125 35 48.125 greater of 4tCK or 7.5ns 40 15 greater of 4tCK or 7.5ns
9 * tREFI -
ps ns ns ns ns t CK ns ns t CK
t
RTP CCD t DAL
greater of 4tCK or 7.5ns 4 WR + tRP/ tCK (AVG)
-
t
t
4 greater of 12tCK or 15ns 1
-
t
ZQCL command: Long calibration time
t
-
t
-
t
POWER-UP and RESET operation Normal operation ZQCS command: Short calibration time
Datasheet Version 5.0
IS (AC175) IS (AC135) IS (AC150) IH (DC90) IH (DC100)
t
t
MRD MOD t MPRR t
Calibration Timing ZQinit greater of 512 tCK
t
ZQoper ZQcs
t
greater of 256 tCK greater of 64 tCK
20 www.intelligentmemory.com
CK CK t CK t
CK CK t CK t
CK CK CK
t
IMM2G64D3(L)SOD8AG
For part number IMM2G64D3(L)SOD8AG-B125(I)
Parameter / Condition Exit reset from CKE HIGH to valid command
REFRESH-to-ACTIVATE or REFRESH command period Maximum refresh Tc<=85oC period Tc>85oC Maximum average Tc<=85oC periodic refresh Tc>85oC
Symbol
Min
Initialization and Reset Timing t XPR greater of 5tCK or t RFC(min)+10ns Refresh Timing t RFC 300
Max
Units
-
t
-
ns
64 (1X) 32 (2X) t REFI 7.8 (64ms/8192) 3.9 (32ms/8192) Self Refresh Timing Exit self refresh to commands not requiring a tXS greater of 5 tCK or t locked DLL RFC+10ns t t Exit self refresh to commands requiring a XSDLL DLLK (MIN) locked DLL t Minimum CKE low pulse width for self refresh tCKESR CKE (MIN) + tCK entry to self refresh exit timing Valid clocks after self refresh entry or power tCKSRE greater of 5tCK or 10ns down entry t Valid clocks before self refresh exit, powerCKSRX greater of 5tCK or 10ns down exit, or reset exit Power-Down Timing t CKE MIN pulse width CKE (MIN) greater of 3tCK or 5ns t Command pass disable delay CPDED 1 t t Power-down entry to power exit timing PD CKE (MIN) 9 * tREFI Power-Down Entry Minimum Timing t ACTIVATE command to power-down entry ACTPDEN 1 t PRECHARGE/PRECHARGE ALL command to PRPDEN 1 power-down entry t REFRESH command to power-down entry REFPDEN 1 t MRS command to power-down entry MRSPDEN MIN = tMOD (MIN) READ/READ with auto precharge command to tRDPDEN MIN = RL + 4 + 1 power-down entry t WRITE command to BL8 (OTF, MRS) WRPDEN MIN = WL + 4 + tWR/tCK (AVG) power-down entry BC4OTF t BC4MRS WRPDEN MIN = WL + 2 + tWR/tCK (AVG) t WRITE with auto BL8 (OTF, MRS) WRAPDEN MIN = WL + 4 + tWR + 1 precharge command to BC4OTF t power-down entry BC4MRS WRAPDEN MIN = WL + 2 + tWR + 1 Power-Down Exit Timing DLL on, any valid command, or DLL off to t XP greater of 3tCK or 6ns commands not requiring locked DLL Precharge power-down with DLL off to t XPDLL greater of 10tCK or 24ns -commands requiring a locked DLL ODT Timing t RTT turn-on from ODTL on reference AON -225 225 RTT turn-off from ODTL off reference t AOF 0.3 0.7 Asynchronous RTT turn-on delay (power-down with DLL off) Asynchronous RTT turn-off delay (powerdown with DLL off) ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8
Datasheet Version 5.0
-
CK
ms us
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK CK t CK t
t
CK CK
t
t
CK CK t CK t
t
CK
t
CK CK
t
t
CK
t
CK
t
CK
ps t CK (AVG)
t
2
8.5
ns
t
AOFPD
2
8.5
ns
ODTH4
4
-
tCK
ODTH8
6
-
tCK
AONPD
21 www.intelligentmemory.com
IMM2G64D3(L)SOD8AG
For part number IMM2G64D3(L)SOD8AG-B125(I)
Parameter / Condition
Symbol
RTT dynamic change skew
t
Min
Max
Units
0.7
t CK (AVG)
Dynamic ODT Timing
First DQS, /DQS rising edge DQS, /DQS delay Write leveling setup from rising CK, /CK crossing to rising DQS, /DQS crossing Write leveling hold from rising DQS, /DQS crossing to rising CK, /CK crossing Write leveling output delay Write leveling output error
Datasheet Version 5.0
ADC
0.3
Write Leveling Timing WLMRD 40 t WLDQSEN 25 t
-
t
CK CK
t
t
WLS
165
-
ps
tWLH
165
-
ps
t
0 0
7.5 2
ns ns
WLO WLOE
t
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IMM2G64D3(L)SOD8AG
For part number IMM2G64D3(L)SOD8AG-B125(I)
Table 19 - SPD Information Byte NO. Description
Note 1.35V Operation
0
176 / 256 / 0-116
92
1.2 DDR3 SDRAM 64b Unbuffered SO-DIMM 8Gb 8banks Row 16 / Col 11 1.35V/1.5V 1.5V 2Rank , x8 Non-ECC, 64bit 2.5ps 1/8 (0.125ns) 1/8 (0.125ns) 1.25ns 5, 6, 7, 8, 9, 10, 11
12 0B 03 05 22 02 09 03 52 01 08 0A 00 FE
-
00
13.125ns 15ns 13.125ns
69 78 69
7.5ns
3C
13.125ns 35ns
69 11 18
48.125ns
81
300ns
60
300ns
09
7.5ns
3C
7.5ns
3C
40ns 40ns
01 40
DLL off Mode, RZQ/6, RZQ/7 0-95oC Op. Temp. w/2x refresh Without TS Non-Standard SDRAM 29< Height <= 30
83 05
30 31
Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage SPD Revision Key Byte / DRAM Device Type Key Byte / Module Type SDRAM Density and Banks SDRAM Addressing Module Nominal Voltage, VDD Module Organization Module Memory Bus Width Fine Timebase (FTB) Dividend and Divisor Medium Timebase (MTB) Dividend Medium Timebase (MTB) Divisor SDRAM Minimum Cycle Time (tCKmin) Reserved CAS Latencies Supported, Least Significant Byte CAS Latencies Supported, Most Significant Byte Minimum CAS Latency Time (tAAmin) Minimum Write Recovery Time (tWRmin) Minimum /RAS to /CAS Delay Time (tRCDmin) Minimum Row Active to Row Active Delay Time (tRRDmin) Minimum Row Precharge Time (tRPmin) Upper Nibbles for tRAS and tRC Minimum Active to Precharge Time (tRASmin), LSB Minimum Active to Active/Refresh Time (tRCmin), LSB Minimum Refresh Recovery Time (tRFCmin), LSB Minimum Refresh Recovery Time (tRFCmin), MSB Minimum Internal Write to Read Command Delay Time (tWTRmin) Minimum Internal Read to Precharge Command Delay Time (tRTPmin) Upper Nibble for tFAW Minimum Four Activate Window Delay Time (tFAWmin), LSB SDRAM Optional Features SDRAM Thermal and Refresh Options
32 33 34-59 60
Module Thermal Sensor SDRAM Device Type Reserved, General Section Module Nominal Height
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Datasheet Version 5.0
23 www.intelligentmemory.com
Hex 1.5V 1.35V 1.5V Operation Operation Operation
00
00 A1 00 0F IMM2G64D3(L)SOD8AG
Byte NO. Description
Note
Hex
61
Module Maximum Thickness
11
62 63
Reference Raw Card Used Address Mapping from Edge Connector to DRAM Module Type Specific Section, Indexed by Key Byte Module ID: Module Manufacturer’s JEDEC ID Code Module ID: Module Manufacturing Location Module ID: Module Manufacturing Date Module ID: Module Serial Number Cyclical Redundancy Code Module Part Number Module Revision Code DRAM Manufacturer’s JEDEC ID Code Manufacturer’s Specific Data Open For Customer Use
1< Tf <=2 (mm); 1< Tb <=2 (mm) Raw Card F3 Non-Mirrored
65 00
-
00
Reserved
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved 2A 50 Reserved Reserved Reserved Reserved Reserved
64-116 117-118 119 120-121 122-125 126-127 128-145 146-147 148-149 150-175 176-255
Datasheet Version 5.0
24 www.intelligentmemory.com
81 D7
IMM2G64D3(L)SOD8AG
Contents Features
3
Table 1 - Ordering Information for RoHS Compliant Product
4
Table 2 - Operating Voltage
4
Table 3 - Temperature Grade
4
Table 4 - Speed Grade
4
Table 5 - Memory Chip Information
4
Part Number Decoder
5
Table 6 - Addressing
5
Table 7 - Pin Assignment
6
Table 8 - Pin Description
7
Figure 1 – Module Dimension 204 Pin DDR3 SDRAM Unbuffered SO-DIMM
8
Table 9 - PCB Dimension
9
Figure 2 – Functional Block Diagram (Page 1 of 2)
10
Figure 3 – Functional Block Diagram (Page 2 of 2)
11
Electrical Parameter
12
Table 10 - Absolute Maximum DC Ratings
12
Table 11 - DC Electrical Characteristics and Operating Conditions
12
Table 12 - DC Electrical Characteristics and Input Conditions
13
Table 13 - Input Switching Conditions
14
Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS)
15
Table 15 - Single-Ended Output Driver Characteristics
16
Table 16 - Differential Output Driver Characteristics
17
Table 17 - IDD Specifications with Conditions and Operation Current
18
Table 18 - AC Timing Parameter and Operating Conditions
19
Table 19 - SPD Information
23
Contents
25
List of Tables
26
List of Figures
26
Datasheet Version 5.0
25 www.intelligentmemory.com
IMM2G64D3(L)SOD8AG
List of Tables Table 1 - Ordering Information for RoHS Compliant Product
4
Table 2 - Operating Voltage
4
Table 3 - Temperature Grade
4
Table 4 - Speed Grade
4
Table 5 - Memory Chip Information
4
Table 6 - Addressing
5
Table 7 - Pin Assignment
6
Table 8 - Pin Description
7
Table 9 - PCB Dimension
9
Table 10 - Absolute Maximum DC Ratings
12
Table 11 - DC Electrical Characteristics and Operating Conditions
12
Table 12 - DC Electrical Characteristics and Input Conditions
13
Table 13 - Input Switching Conditions
14
Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS)
15
Table 15 - Single-Ended Output Driver Characteristics
16
Table 16 - Differential Output Driver Characteristics
17
Table 17 - IDD Specifications with Conditions and Operation Current
18
Table 18 - AC Timing Parameter and Operating Conditions
19
Table 19 - SPD Information
23
List of Figures Figure 1 – Module Dimension 204 Pin DDR3 SDRAM Unbuffered SO-DIMM
8
Figure 2 – Functional Block Diagram (Page 1 of 2)
10
Figure 3 – Functional Block Diagram (Page 2 of 2)
11
Datasheet Version 5.0
26 www.intelligentmemory.com
IMM2G64D3(L)SOD8AG
