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Institutionen För Systemteknik Department Of Electrical Engineering Low Power And Area Efficient

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Institutionen för systemteknik Department of Electrical Engineering Examensarbete LOW POWER AND AREA EFFICIENT SEMI-DIGITAL PLL ARCHITECTURE FOR HIGH BANDWIDTH APPLICATIONS Examensarbete utfört i Elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Vivek Elangovan LiTH-ISY-EX--11/4439--SE Linköping 2011 Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Linköpings tekniska högskola Linköpings universitet 581 83 Linköping LOW POWER AND AREA EFFICIENT SEMI-DIGITAL PLL ARCHITECTURE FOR HIGH BANDWIDTH APPLICATIONS Examensarbete utfört i Elektroniksystem vid Tekniska högskolan i Linköping av Vivek Elangovan LiTH-ISY-EX--11/4439--SE Handledare: Dr. J Jacob Wikner isy, Linköpings universitet Markus Dietl & Puneet Sareen Texas Instruments Examinator: Dr. J Jacob Wikner isy, Linköpings universitet Linköping, 23 September, 2011 Avdelning, Institution Division, Department Datum Date Department of Electrical Engineering Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Språk Language Rapporttyp Report category ISBN Svenska/Swedish Licentiatavhandling ISRN Engelska/English Examensarbete C-uppsats D-uppsats Övrig rapport 2011-09-23 — LiTH-ISY-EX--11/4439--SE Serietitel och serienummer ISSN Title of series, numbering — URL för elektronisk version http://www.es.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71029 Titel Title Svensk titel LOW POWER AND AREA EFFICIENT SEMI-DIGITAL PLL ARCHITECTURE FOR HIGH BANDWIDTH APPLICATIONS Författare Vivek Elangovan Author Sammanfattning Abstract The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100 MHz to 1 GHz in a 150 nm CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses N storage cells. The N storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100 MHz to 1 GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL. Nyckelord Keywords PLL, High Bandwidth, Low Power, Semi-Digital PLL, Real Time Clock Abstract The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100 MHz to 1 GHz in a 150 nm CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses N storage cells. The N storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100 MHz to 1 GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL. v Acknowledgments At first, I would like to thank Texas Instruments for providing me an interesting topic for Master Thesis with good technical support from my supervisors Mr. Markus Dietl and Mr. Puneet Sareen. And then, I would like to thank my Professor Dr. J Jacob Wikner at the Department of Electronics System in Linköping University, for being my academic supervisor and examiner of the Master Thesis. I also like to thank my friends for their support. vii Contents 1 Background Theory 1.1 Conventional PLL architecture . 1.1.1 Phase-Frequency Detector 1.1.2 Charge Pump . . . . . . . 1.1.3 Loop Filter . . . . . . . . 1.1.4 VCO . . . . . . . . . . . . 1.1.5 Divider . . . . . . . . . . 1.2 PLL operation . . . . . . . . . . 1.3 New PLL architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Mathematical Modelling of the PLL 2.1 Z-Domain model of a conventional PLL . . . . . . . . . 2.1.1 Z-Domain model of frequency to phase transfer . 2.1.2 Z-Domain model of phase-frequency detector . . 2.1.3 Z-Domain model of capacitor and resistor in loop 2.1.4 Z-Domain model of VCO . . . . . . . . . . . . . 2.1.5 Z-Domain model of conventional PLL . . . . . . 2.2 Z-Domain model of new PLL architecture . . . . . . . . 2.3 Transfer function of new PLL architecture . . . . . . . . 3 Design of PLL blocks 3.1 PFD . . . . . . . . . . . . . . . . . 3.1.1 D-flip flop . . . . . . . . . . 3.1.2 NAND gate . . . . . . . . . 3.1.3 PFD schematic . . . . . . . 3.2 Charge Pump . . . . . . . . . . . . 3.3 Storage cell and Reference current 3.3.1 Reference current block . . 3.3.2 Storage cell block . . . . . . 3.4 Voltage Controlled Oscillator . . . 3.4.1 Single stage of VCO . . . . ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 7 8 8 8 8 9 9 . . . . . . . . 13 13 13 14 15 16 16 17 19 . . . . . . . . . . 23 23 23 24 24 26 28 28 29 32 32 x Contents 4 Measuring PLL parameters 4.1 Setup for measuring PLL parameters . . . . . . 4.1.1 VCO proportional gain measuring setup 4.1.2 Charge pump current measuring setup . 4.1.3 Digital step measuring setup . . . . . . 4.1.4 VCO step gain measuring setup . . . . . 4.2 Bandwidth test . . . . . . . . . . . . . . . . . . 4.2.1 Process corners compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 37 37 39 39 39 41 42 . . . . . . . . . . . . . . at 100 MHz . . . . . . . at 1 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 47 48 49 50 51 6 Mixed signal and process corner simulation of PLL 6.1 Verilog-A model of charge pump and REFCUR . . . . 6.1.1 Verilog-A model of charge pump . . . . . . . . 6.1.2 Verilog-A model of REFCUR . . . . . . . . . . 6.2 Mixed signal model of PLL . . . . . . . . . . . . . . . 6.3 Poles in VCO . . . . . . . . . . . . . . . . . . . . . . . 6.4 Exponential scaling . . . . . . . . . . . . . . . . . . . . 6.4.1 Charge pump and REFCUR resistor scaling . . 6.4.2 Charge pump capacitor scaling . . . . . . . . . 6.4.3 Transistor scaling of proportional part of VCO 6.5 Process corner simulations . . . . . . . . . . . . . . . . 6.5.1 Weak and strong corners . . . . . . . . . . . . . 6.6 Jitter and Power measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 58 58 59 60 62 65 66 67 69 69 70 72 7 Conclusion and Future work 7.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 79 Bibliography 81 A PLL parameters measuring graphs 83 B Simulations for PLL operating range 92 5 PLL operating range 5.1 Modified REFCUR block . . . . . . . . 5.2 PLL operating at 100 MHz . . . . . . . 5.2.1 Bandwidth test of PLL operating 5.3 PLL operating at 1 GHz . . . . . . . . . 5.3.1 Bandwidth test of PLL operating C Simulations for process corners . . . . . . . . . . . . . . 100 List of Figures 1.1 1.2 1.3 Conventional PLL architecture . . . . . . . . . . . . . . . . . . . . PFD operation: (a) fref =fCLK and (b) fref > fCLK . . . . . . . . New PLL architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Z-Domain model of frequency to phase transfer . . Z-Domain model of phase-frequency detector . . . Z-Domain model of capacitor and charge pump . . Z-Domain model of resistor and charge pump . . . Z-Domain model of conventional PLL . . . . . . . Z-Domain model of new PLL architecture . . . . . Z-Domain model of PLL forward path . . . . . . . Magnitude and phase plot of PLL operating at 500 . . . . . . . . . . . . . . . . . . . . . MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 16 17 18 19 21 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 Schematic of D-flipflop . . . . . Schematic of NAND gate . . . Schematic of PFD . . . . . . . REFCLK leads SYSCLK . . . SYSCLK leads REFCLK . . . Schematic of charge pump . . . Block diagram of N storage cell Schematic of REFCUR . . . . . Schematic of single storage cell Process of storage cells . . . . . Schematic of VCO single cell . Schematic of five stage VCO . . Frequency range of oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 25 25 26 26 27 29 29 30 31 33 33 34 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Schematic of PLL operation at 500 MHz . . . . . . . . . Phase and frequency lock of PLL operating at 500 MHz Mathematical modelling of PLL operating at 500 MHz . Proportional gain measuring setup . . . . . . . . . . . . Kp , Proportional gain . . . . . . . . . . . . . . . . . . . Icp , Charge pump current . . . . . . . . . . . . . . . . . dt, Digital step . . . . . . . . . . . . . . . . . . . . . . . Ko , Step gain measuring setup . . . . . . . . . . . . . . Ko , Step gain . . . . . . . . . . . . . . . . . . . . . . . . Compensated proportional part of VCO . . . . . . . . . Compensated PLL in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 38 38 39 40 41 41 43 45 5.1 5.2 5.3 5.4 5.5 5.6 Schematic of modified REFCUR . . . . . . . . . . . . . Schematic of PLL operating at 100 MHz . . . . . . . . . Frequency and phase lock of PLL operating at 100 MHz Mathematical modelling of PLL operating at 100 MHz . Frequency and phase lock of PLL operating at 1 GHz . Mathematical modelling of PLL operating at 1 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 48 49 50 52 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Contents 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 Architecture of resistor breech . . . . . . . . . . . . . . . . . . . . . Frequency compensation of proportional part of VCO . . . . . . . Frequency and phase lock of compensated PLL operating at 100 MHz 100 MHz reference modulated at 33 MHz and 50 MHz . . . . . . . Frequency and phase lock of compensated PLL operating at 1 GHz 1 GHz reference modulated at 100 MHz and 333 MHz . . . . . . . Mixed signal model of PLL . . . . . . . . . . . . . . . . . . . . . . 100 MHz reference modulated at 33 MHz and 50 MHz in verilog-A model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mathematical modelling of PLL operating at 1 GHz in verilog-A . Pole at VCO for Vctrl from storage cells . . . . . . . . . . . . . . . Pole at VCO for Vctrl from charge pump . . . . . . . . . . . . . . . Charge pump resistor scaling . . . . . . . . . . . . . . . . . . . . . REFCUR resistor scaling . . . . . . . . . . . . . . . . . . . . . . . Schematic of charge pump capacitor scaling . . . . . . . . . . . . . Charge pump capacitor scaling . . . . . . . . . . . . . . . . . . . . Scaling of VCO proportional part . . . . . . . . . . . . . . . . . . . Mathematical modelling of PLL operating at 100 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mathematical modelling of PLL operating at 1 GHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 MHz reference modulated at 10 MHz and 25 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GHz reference modulated at 100 MHz and 250 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mathematical modelling of PLL operating at 100 MHz in weak process Mathematical modelling of PLL operating at 700 MHz in weak process Mathematical modelling of PLL operating at 100 MHz in strong process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mathematical modelling of PLL operating at 1 GHz in strong process A.1 Uncompensated PLL in strong process A.2 Uncompensated PLL in weak process . A.3 Compensated Icp in nominal process . A.4 Compensated Ko in nominal process . A.5 Compensated Kp in nominal process . A.6 Compensated Icp in strong process . . A.7 Compensated Ko in strong process . . A.8 Compensated Kp in strong process . . A.9 Compensated Icp in weak process . . . A.10 Compensated Kp in weak process . . . A.11 Compensated Ko in weak process . . . A.12 Compensated PLL in strong process . A.13 Compensated PLL in weak process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 57 58 59 60 61 62 63 64 65 66 67 68 68 69 70 71 72 72 74 75 76 77 . . . . . . . . . . . . . 83 84 85 85 86 86 87 87 88 88 89 90 91 B.1 Icp measurement for PLL operating at 100 MHz in nominal process 92 Contents 3 Ko measurement for PLL operating at 100 MHz in nominal process Kp measurement for PLL operating at 100 MHz in nominal process 100 MHz reference modulated at 7 MHz in nominal process . . . . 100 MHz reference modulated at 25 MHz in nominal process . . . 100 MHz reference modulated at 50 MHz in nominal process . . . dt measurement for PLL operating at 1 GHz in nominal process . Icp measurement for PLL operating at 1 GHz in nominal process . Ko measurement for PLL operating at 1 GHz in nominal process . 1 GHz reference modulated at 20 MHz in nominal process . . . . . 1 GHz reference modulated at 100 MHz in nominal process . . . . 1 GHz reference modulated at 200 MHz in nominal process . . . . 93 93 94 95 95 96 96 97 98 99 99 C.1 1 GHz reference modulated at 50 MHz in mixed simulation . . . . C.2 1 GHz reference modulated at 100 MHz in mixed simulation . . . . C.3 1 GHz reference modulated at 33 MHz in mixed simulation . . . . C.4 B < 13 >, modulated at 10 MHz for pole measurement . . . . . . C.5 B < 13 >, modulated at 200 MHz for pole measurement . . . . . . C.6 B < 13 >, modulated at 300 MHz for pole measurement . . . . . . C.7 Prop, modulated at 5 MHz for pole measurement . . . . . . . . . . C.8 Prop, modulated at 200 MHz for pole measurement . . . . . . . . . C.9 Prop, modulated at 300 MHz for pole measurement . . . . . . . . . C.10 dt measurement for PLL operating at 100 MHz in nominal process C.11 Kp and Ko measurement for PLL operating at 100 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.12 dt measurement for PLL operating at 1 GHz in nominal process . C.13 Kp and Ko measurement for PLL operating at 1 GHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.14 dt measurement for PLL operating at 500 MHz in nominal process C.15 Kp and Ko measurement for PLL operating at 500 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.16 dt measurement for PLL operating at 300 MHz in nominal process C.17 Kp and Ko measurement for PLL operating at 300 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.18 dt measurement for PLL operating at 200 MHz in nominal process C.19 Kp and Ko measurement for PLL operating at 100 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.20 Mathematical modelling of PLL operating at 200 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.21 Mathematical modelling of PLL at operating 300 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.22 Mathematical odelling of PLL at operating 500 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.23 200 MHz reference modulated at 20 MHz and 50 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C.24 300 MHz reference modulated at 30 MHz and 75 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 105 105 106 107 107 108 109 109 110 B.2 B.3 B.4 B.5 B.6 B.7 B.8 B.9 B.10 B.11 B.12 110 111 111 112 112 113 113 114 114 115 116 117 118 118 4 Contents C.25 500 MHz reference modulated at 50 MHz and 125 MHz in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 C.26 Mathematical modelling of PLL operating at 200 MHz in weak process120 C.27 Mathematical modelling of PLL operating at 300 MHz in weak process121 C.28 Mathematical modelling of PLL operating at 300 MHz in strong process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 C.29 Mathematical modelling of PLL operating at 500 MHz in strong process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 List of Tables 4.1 4.2 4.3 4.4 4.5 4.6 PLL parameters in nominal process . . . . . . . . . Uncompensated PLL parameters in strong process Uncompensated PLL parameters in weak process . Compensated PLL parameters in nominal process . Compensated PLL parameters in strong process . . Compensated PLL parameters in weak process . . . . . . . . . . . . . . . . . . . . . . . . . . 40 42 42 44 44 44 5.1 5.2 5.3 5.4 Parameters of PLL operating at 100 MHz in nominal process Bandwidth test for PLL operating at 100 MHz . . . . . . . . Parameters of PLL operating at 1 GHz in nominal process . . Bandwidth test for PLL operating at 1 GHz . . . . . . . . . . . . . . . . . . . . . . 51 51 51 53 6.1 6.2 6.3 6.4 6.5 Parameters of PLL operating at 1 GHz in verilog-A model . . . . . Bandwidth test for PLL operating at 1-GHz in verilog-A . . . . . . Pole frequency measurement for Vctrl from storage cells . . . . . . Pole frequency measurement for Vctrl from charge pump . . . . . . PLL parameters measured for different reference frequency in nominal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL parameters measured for different reference frequency in weak process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL parameters measured for different reference frequency in strong process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured jitter and power . . . . . . . . . . . . . . . . . . . . . . . 61 63 64 65 6.6 6.7 6.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 73 73 73 Contents 5 List of Abbreviations Abb. Spell-out Explanation Ref PLL Phase-Locked Loop A device which generates a signal which is in phase and frequency with the reference signal. Ch. 1 PFD Phase-Frequency Detector A device which compares the phase of two input signals. Ch. 1 VCO Voltage Controlled Oscillator A device to control the oscillation frequency by a voltage input. Ch. 2 CP Charge Pump A device which create either a higher or lower voltage power source by using capacitors as storage elements. Ch. 2 CMOS Complementary Metal Oxide Semiconductor A technology for making lowpower integrated circuits. Ch. 3 NMOS N-Type CMOS N-type MOS to implement logic gates and other digital circuits. Ch. 3 PMOS P-Type CMOS P-type MOS to implement logic gates and other digital circuits. Ch. 3 W Width Width of the MOSFET gate. Ch. 6 L Length Length of the MOSFET channel. Ch. 6 Chapter 1 Background Theory The phase-locked loop (PLL) [5], [6] generates the well-timed on-chip clocks for various applications such as clock and data recovery, microprocessor clock generation and frequency synthesizer. The basic concept of the phase locking has remained the same, since its invention in the 1930’s. However, the design and the implementation of the PLL continue to be challenging as the design requirements of a PLL system such as clock timing uncertainty, power consumption and area become more stringent. A phase-locked loop (PLL) is a control system which generates the signal, which is in phase and frequency with the input reference signal. The frequency generated from the PLL will be same as the input frequency or it is N times higher than the input frequency. The following section describes the PLL building blocks and its operation. The new PLL architecture is also described briefly. 1.1 Conventional PLL architecture The PLL consists of the phase-frequency detector, the charge pump, the loop filter, the voltage controlled oscillator (VCO) and the divider. The conventional PLL architecture is shown in Figure 1.1. The block 1/s represents the integration. The phase of the signal can be obtained by integrating its frequency. The following section explains each block of PLL. 1.1.1 Phase-Frequency Detector The phase-frequency detector (PFD) [4] compares the rising edge of the reference signal, φref to the feedback signal, φout and gives the difference as a phase difference, ∆t. The phase difference depends upon the lag or lead of the feedback signal with the reference input. If it is lag, it generates an UP pulse and if it is lead means, it generates a DOWN pulse. The conversion gain of the PFD is denoted by Kd . The operation of the PFD is shown for two cases: (a) the two input signals have the same frequency, and (b) one input has higher frequency than another input in Figure 1.2. 7 8 Background Theory Figure 1.1. Conventional PLL architecture 1.1.2 Charge Pump Based on the phase difference from the phase-frequency detector, the charge pump [4] pumps in or out the current in the loop filter. During the UP pulse, the charge pump charges the capacitor in the loop filter and during DOWN pulse, vice versa. 1.1.3 Loop Filter The loop filter converts the digital output of the phase-frequency detector to the DC control voltage, Vctrl for the VCO. The loop filter plays a main role for the PLL bandwidth. The filter can be active or passive. It can be any order based on the PLL application. 1.1.4 VCO The voltage controlled oscillator is the heart of the PLL. With a zero control voltage, the VCO generates a free running frequency, fo . The gain of the VCO is denoted as Ko . If the control voltage, Vctrl is high, the frequency increases and if the control voltage is low, the frequency decreases. Once, the PLL locks, the output frequency is constant. The VCO can be tuned based on the control voltage. The function of the VCO can be expressed as. fout = f0 + (Ko · Vctrl ) (1.1) Hence, the frequency change of the VCO depends on the change of the control voltage. 1.1.5 Divider If the output of the VCO is higher than the reference frequency, then it must be divided by N times and is fed back as one of the input to the phase detector. If the division ratio is 1, then the PLL tracks the input frequency and acts as a buffer. 1.2 PLL operation 9 Figure 1.2. PFD operation: (a) fref =fCLK and (b) fref > fCLK 1.2 PLL operation The PLL [6] is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO). The input reference signal is applied to one input of the phase-frequency detector. The other input is connected to the output of a divide by N counter. Normally, the frequency of both signals will be same, when the PLL is locked. The output of the phase-frequency detector is a pulse proportional to the phase difference between the two inputs. This signal is applied to the loop filter. It is the loop filter that determines the dynamic characteristics of the PLL. The filtered signal controls the oscillator. Note that the output of the VCO is at a frequency that is N times frequency of the reference input. The frequency range by which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal, the range of frequencies that the PLL will follow is called the tracking range. The loop filter also determines how fast the signal frequency can change and still maintains lock. This maximises the slewing rate. 1.3 New PLL architecture In the conventional PLL architecture, there is a big capacitor in the loop filter, which cannot be integrated. In the new architecture, this big capacitor is divided into N storage cells, which has the two advantages. 1. The tuning information can be stored in the storage cells, when the cell is not active. 2. Analogue tuning can be implemented, when the cell is active. In the conventional PLL architecture, the damping is usually achieved using either a resistor or a capacitor. The charge pump in the new PLL architecture provides a new active proportional damping to the VCO, which results in a very high damping factor and less peaking to achieve the right frequency to lock. The 10 Background Theory REFCUR block mirrors the current to the N storage cells based on the outputs from the PFD. The other blocks of the PLL like, the phase-frequency Detector, the divider, and the VCO are implemented as conventional ones. The divider is used in low bandwidth PLL applications. Here, the main focus is to design a high bandwidth PLL. So, the divide ratio is 1 or no divider is implemented. The new PLL architecture is shown in Figure 1.3. In the new architecture [1], [2], the phase-frequency detector produces four out- Figure 1.3. New PLL architecture puts. The UP and DOWN are the same signals as in the conventional PFD. The UPB and DOWNB are just the inversion of UP and DOWN. All the four signals are given to the charge pump and the REFCUR. Additionally, the reference CLK and feedback signal is also connected to the charge pump. This is to ensure that when both the signals are zero, the voltage at the capacitor is pulled back to V dd/2 (Active Damping). Depending on the DOWN and UP pulse, the charge pump pumps current to the capacitor. The output of charge pump, prop is the proportional damped signal given to one input of VCO. The other input to the VCO is from the N storage cells, B < 1 : N >. The signal INIT is to reset all the node voltages in the PFD to zero and is also given to N storage cells, to initialise all the capacitors to Vdd. Based on the UP and DOWN pulse from the PFD, the capacitor in the storage cells starts discharging or charging one by one. This leads to either filling 0’s or 1’s in the storage cell one by one. Based on the filling, the frequency of the VCO gets increased or decreased. This helps in frequency tuning of the VCO. Thus, there will be two VCO gains respective to its two control voltages, Vctrl . One is the proportional gain, Kp from the output of charge pump and the other is the step gain, Ko being the frequency difference of one more storage cell being switched on. A five stage differential ring oscillator is implemented here. This 1.3 New PLL architecture 11 architecture is implemented for an operating range of 100 MHz to 1 GHz with a PLL bandwidth of (1/4)th of input frequency. The mathematical modelling of the new architecture is performed in z-domain, since PLL is a time discrete system. The results of the simulation are also matched with the mathematical modelling of the new architecture. Chapter 2 Mathematical Modelling of the PLL In this chapter, the conventional PLL is modelled using the z-domain. It is then modified to the new PLL architecture. Generally, the PLL is modelled using the s-domain. The s-domain modelling updates the information continuously for all the time, which is useful for a time-continuous system. Since, the PLL is a timediscrete system; each block of PLL can be accurately modelled in the z-domain. The z-domain modelling updates the information only at the edges of the signal. For example, in a PLL, we need information only at the rising edge of the reference clock i.e., 0, 2π, 4π, 6π,...., 2nπ. The model includes frequency and phase of the signals, thus reflects both, frequency and phase behaviour of the PLL. 2.1 Z-Domain model of a conventional PLL The conventional architecture of the PLL consists of the phase-frequency detector, the charge pump, the loop filter, the voltage controlled oscillator and the frequency Divider. Each component of the PLL is described by its transfer function to obtain an overall input-output behaviour for the frequency and phase domain. 2.1.1 Z-Domain model of frequency to phase transfer The frequency to phase transfer converts frequency information into phase information evaluated at discrete time stamps, Tref . The input to the frequency to phase converter is a signal with frequency f(t) and time period, Tref . The phase of the signal can be obtained by integrating the frequency of the signal and it is given as. Z Φ(t) = f(t) dt (2.1) The integration in the z-domain is the accumulation of Tref with respect to previous Tref . So, at the ith time period, the time is sum of all the periods before i 13 14 Mathematical Modelling of the PLL and it is given as. t(i) = i X Tj (2.2) j=0 This can be implemented in the z-domain with an adder and a delay element as the following equation and it is also shown in the Figure 2.1, where z(s) = exp (−s · Tref ). t(i) = Ti + t(i-1) (2.3) Figure 2.1. Z-Domain model of frequency to phase transfer 2.1.2 Z-Domain model of phase-frequency detector The PFD detects the phase difference between the feedback signal and the reference signal. Using the frequency to phase transfer, the phases are applied as an input to the PFD. So, the PFD can be modelled as a subtractor in the z-domain and it is shown in the Figure 2.2. Figure 2.2. Z-Domain model of phase-frequency detector 2.1 Z-Domain model of a conventional PLL 2.1.3 15 Z-Domain model of capacitor and resistor in loop filter The PFD generates the phase difference ∆t as a pulse, and the charge pump pumps the current during the time period ∆t. This current is deposited as a charge of size, Q(i) in the capacitor. Q(i) = Icp · ∆t (2.4) The same size of charge is deposited to the capacitor for each update pulse from the PFD. So, after the n update pulse of ∆t, the total charge deposited is given as. n X Q(n) = Icp · ∆t (2.5) i=0 The voltage across the capacitor is V = Q/C. So, the capacitor translates the charge into voltage, Ustored . Hence, the capacitor along with the charge pump can be modelled in the z-domain is shown in Figure 2.3. U(n) = n X Icp · ∆t i=0 C (2.6) In case of a damping resistor, during the pulse ∆t, the charge pump current causes Figure 2.3. Z-Domain model of capacitor and charge pump a voltage drop across it with a size of V(i) = R·Icp . In the rest of update period Tupdate , no voltage drop is produced across the damping resistor. So, the average voltage drop is given as. Uprop (i) = ∆ti · R · Icp Tupdate (2.7) Hence, the resistor along with charge pump can be modelled in the z-domain as shown in the Figure 2.4. 16 Mathematical Modelling of the PLL Figure 2.4. Z-Domain model of resistor and charge pump 2.1.4 Z-Domain model of VCO The transfer function of voltage controlled oscillator is Fout = K · Vctrl . The time period is given by 1/Fout , Tout = 1/(K · Vctrl ). The frequency range of the VCO must be linear with respect to the control voltage. For linearization, the time Tout can be written as. dTout T = Tout |ctrl0 + · (Vctrl − Vctrl0 ) (2.8) dVctrl ctrl0 Differentiate Tout w.r.t Vctrl . δTout −1 = δVctrl K · (Vctrl )2 (2.9) Hence, the VCO can be modelled in the z-domain based on above equation. 2.1.5 Z-Domain model of conventional PLL Each component of the PLL is modelled in the z-domain. The frequency divider is implemented as a multiplier in the time domain. The complete z-domain model of the PLL is shown in the Figure 2.5. The block 1/z(s) before the charge pump, Icp is to ensure the one time period delay between the feedback signal and reference CLK. 2.2 Z-Domain model of new PLL architecture 17 Figure 2.5. Z-Domain model of conventional PLL 2.2 Z-Domain model of new PLL architecture In the new PLL architecture [2], the capacitor in the loop filter is divided into many storage cells. Each storage cell is used for tuning the oscillator. Once, the capacitor in the storage cell starts to discharge/charge below/above V dd/2, it activates the next storage cell. When, the capacitor discharges, it increases the frequency of the VCO and when the capacitor charges, it decreases the frequency of the VCO. The step change from one storage cell to another cell is given as dt. This makes a change in frequency by a step in the oscillator. The total control voltage to the oscillator is given as. Ucontrol (n) = Ustored (n) + Uprop (n) (2.10) The frequency change in the oscillator can be written as a gain Ko , times the Ucontrol (n). f(n) = Ko · Ucontrol (n) (2.11) The Uprop (n) is the voltage drop across the periodically charged capacitor. Uprop (n) should be multiplied by the VCO gain, Kprop to change the frequency of the VCO. Ustored (n) is obtained from both the active and non-active storage cells. At a particular time, two consecutive storage cells X and X+1 are active. Hence, it is given as Kstep positive during the UP pulse and negative during the DOWN pulse. n X U< x >(n) = active U< x + 1 >(n) = Icp · ∆ti C i=0 n X active Icp · ∆ti C i=0 (2.12) (2.13) 18 Mathematical Modelling of the PLL The storage cell next to the active cell gets activated only when the current storage cell discharges below V dd/2. Ustored (n) should be multiplied by the VCO gain, Kstep to change the frequency of the VCO. Hence, the frequency change in the oscillator is given as. non−active(B=0) f(n) = Kprop · Uprop (n) + X Kstep + Kstep · i 2 · Icp · ∆ti Vdd · C 2activebit (2.14) The frequency change in the oscillator caused by the step change, dt from the storage cells is given as. dtstep = 2 · Icp Vdd · C (2.15) Hence, finally the frequency change of the oscillator can be re-written as. non−active(B=0) f(n) = Kprop · Uprop (n) + X i Kstep + Kstep · ∆ti (2.16) dtstep 2activebit The z-domain model of the new PLL architecture is shown in the Figure 2.6. Figure 2.6. Z-Domain model of new PLL architecture 2.3 Transfer function of new PLL architecture 2.3 19 Transfer function of new PLL architecture From the Figure 2.6, the transfer function of the output to the input can be obtained from forward path and feedback path. So, the whole PLL can be described like a linear loop and its transfer function is given by. F orward(z) OU T = IN 1 + (F orward(z) · F eedback(z)) (2.17) Forward(z) is the path from the output of the PFD to the input of the PFD. It is obtained by multiplying the gain of each block placed in the path. The forward path consists of the proportional part, the storage cells, the VCO, and the feedback divider. The forward path is shown in the Figure 2.7. From the Figure 2.7, the Figure 2.7. Z-Domain model of PLL forward path Forward(z) is given as. Tsys = ( Kstep Kprop Icp 1 N + · 1 · f 2 · dt ) · f2 C 1 − z(s) z(s)(1 − z1 ) (2.18) Since, the divider is included in the forward path of the transfer function, the feedback(z) is considered as a unity gain feedback. Hence, the transfer function of the new PLL architecture is given as. ( Kprop f2 H(Z) = 1+( Icp · C + Kprop f2 1 1− Icp · C + 1 · z(s) 1 1 1− z(s) Kstep N )· f 2 ·dt z(s)(1− z1 ) · Kstep N )· f 2 ·dt z(s)(1− z1 ) (2.19) The transfer function is used for the mathematical modelling of the PLL [2]. The parameters used for designing the PLL is the digital step dt, the charge pump current Icp , the proportional gain Kp , the step gain Ko , the divide ratio N , the input 20 Mathematical Modelling of the PLL update frequency, Fref and the damping capacitor C. The mathematical modelling is performed using Mathcad . From the PLL transfer function, magnitude and phase response of the PLL can be obtained. For example, the magnitude and the phase response of the PLL operating at 500 MHz is shown in the Figure 2.8. 2.3 Transfer function of new PLL architecture Figure 2.8. Magnitude and phase plot of PLL operating at 500 MHz 21 Chapter 3 Design of PLL blocks The design of the new PLL blocks at 150 nm CMOS process with a supply voltage of 1.5 V is described in this chapter. 3.1 PFD The phase detector compares the phase difference between the reference CLK and the feedback CLK and produces the error as a phase difference (δT ). But when the frequency difference between the two signals is very high, the phase detector alone cannot generate the exact phase error. This kind of phase error accumulates and results in phase oscillation between > 180◦ and < 180◦ from cycle to cycle. Since the phase detector is insensitive to frequency difference at the input, the PLL may fail to lock. To overcome this problem, the phase-frequency detector (PFD) is used to detect both phase and frequency difference of the input signals. The phase-frequency detector [4], [8] uses two D-flip flops and one NAND gate to detect both the phase and frequency. The design and operation is explained in the following section. 3.1.1 D-flip flop The D-flip flop takes CLK, CLR, CLRZ as inputs and Q and Qz as outputs. The schematic of D-flip flop is shown in the Figure 3.1. Let’s consider the case, when CLK is high and CLR input is low. Initially, the wire Q1 is set to zero. The inverted CLK signal, CLKZ turns on the transistor MP7 and transistor MP6 is already activated due to wire Q1. This results in the output Q to be pulled to Vdd. The signal Q gets inverted by an inverter, which generates the output Qz. In each time period, the signal Q1 and Q are passed into the buffers connected with the wires. If CLR input is high, the inverted CLR signal, CLRz activates the transistor XP46, which results in signal Q1 to be pulled to VDD. The CLR signal activates the transistor MN6, which pulls back the output Q to zero. Thus, the output of the D-flip flop get resets to zero, when CLR signal is high. 23 24 Design of PLL blocks Figure 3.1. Schematic of D-flipflop 3.1.2 NAND gate The NAND gate generate the output as high, when both of its inputs are zero and generate the output as low, when both of its inputs are high. When the INIT signal is high, it enables the transistor XN32 and the output Y is pulled back to zero. This happens even when both the input signals A and B are high at the same time. This helps in resets the PFD, when both UP and DOWN pulse are high at the same time. The schematic of the NAND gate is shown in the Figure 3.2. 3.1.3 PFD schematic The inputs to the two D-flip flops are reference clock signal and feedback signal. INIT signal is an initialization signal, which resets all the node voltages and output of PFD to zero at the start. The D-flip flop generates two outputs, Q and Qz. Qz is complement of Q. One of the outputs of D-flip flop, Q is connected to a NAND gate, which is used to reset the flip-flops, when the output Q from both the D-flip flop are high at the same time. Thus, both the signals cannot be high at the same time. This means the PFD generates either an UP or DOWN pulse but not both. The phase difference between the REFCLK and SYSCLK is measured by whichever rising edge occurs first. The complemented outputs Qz of each flip-flop are inverted and taken as UP and DOWN signals for Charge Pump and REFCUR block. The schematic of PFD is shown in Figure 3.3. The PFD circuit can be analyzed in two different ways: one way in which REFCLK leads SYSCLK and the other is SYSCLK leads REFCLK. The first scenario is when REFCLK leads SYSCLK. At this stage, an UP pulse is generated. This UP pulse is the phase difference between the phases of the two clock signals. 3.1 PFD 25 Figure 3.2. Schematic of NAND gate Figure 3.3. Schematic of PFD This UP pulse indicates to the rest of the circuit that the SYSCLK needs to speed up or increase the frequency. This scenario is shown in the Figure 3.4. In other scenario, DOWN pulse is generated and this will indicate that SYSCLK needs to slow down or decrease the frequency. This scenario is shown in the Figure 3.5. 26 Design of PLL blocks Figure 3.4. REFCLK leads SYSCLK Figure 3.5. SYSCLK leads REFCLK 3.2 Charge Pump The charge pump [1] pumps in or out the current from the damping capacitor. When the PFD generates an UP pulse, the charge stored in the capacitor starts discharging. When a DOWN pulse is generated, the capacitor starts to charge. The frequency of the VCO decreases/increases based on the capacitor being dis- 3.2 Charge Pump 27 charges/charges. Additionally, the reference clock and the feedback signal is also connected to the charge pump to ensure the active damping. Whenever these two signals are zero at the same time, the voltage in the capacitor should be pulled back to V dd/2. At this stage, the PLL is in locked state. The damping used here results in very high damping factor, which in turn results in less peaking to achieve the lock frequency. The schematic of charge pump is shown in Figure 3.6. When the PFD generates an UP pulse, the transistor MN8 gets turned on. The Figure 3.6. Schematic of charge pump transistor MN7 mirrors the current from the transistor MN6, which results in a path from CP1 to GND. Hence, the capacitor started discharging until the pulse width of UP. The UPB enables the transistor MN9, which maintains the transistor MN7 to be in saturation for the time of UPB pulse. When the PFD generates the DOWN pulse, the transistor MN0 gets turned on. The transistor MN2 mirrors the current from the transistor MN6, which is same as the UP current. The transistor MP4 again mirrors the DOWN current, which result in charging path from Vdd to the CP1. Hence, the capacitor started charging until the pulse width of DOWN. Similar to UPB, DOWNB turns on the transistor MN1 to maintain the transistor MN2 to be in saturation for all the time of DOWNB pulse. When the PLL is in the locked state, both UP and DOWN currents flowing out and in to the capacitor should be same. At the same time, the output of NAND gate will be 1, when reference clock and feedback signal goes to zero. This results in transistor MN13, MP8 to be turned on, which leads to pull back the capacitor voltage, CP1 to V dd/2. So, the charge pump is switched off and the voltage settles at V dd/2. The proportional voltage at the ith update is given as. 28 Design of PLL blocks Vprop (i) = Icp · ∆Ti C (3.1) Where, Icp - Charge Pump current (CP1) C - Effective damping capacitor ∆Ti - Phase Difference of the ith update at the PFD inputs 3.3 Storage cell and Reference current The storage cell [1], [2] is the important part of this PLL architecture. It is used to tune the frequency of the voltage controlled oscillator. The tuning range of the VCO is divided into N steps and the N storage cells are used for that N steps. Each storage cell has a capacitor to charge and discharge. This changes the control voltage of the VCO. The storage cells has two advantages: 1. It is used to for analogue tuning of the VCO from one step to another step, when a cell is active. 2. It is used to store the digital tuning information, when a cell is inactive. The N Storage cells are connected in a fashion as shown in Figure 3.7. The inputs LEFT and RIGHT are connected to the A outputs of the left and right neighbouring storage cells. So, at the same time, two storage cells are active and remaining storage cells are inactive. The B outputs of the storage cells are used for step tuning the VCO. From the outputs of the PFD, FAST and SLOW signals are generated from REFCUR, which generates the current for the storage cells. 3.3.1 Reference current block The schematic of the REFCUR is shown in the Figure 3.8. When the PFD generates an UP signal, it enables the transistor, MN0. When the transistor, MN0 is enabled, fast signal is mirrored to the storage cell. And, when PFD generates a DOWNB signal, it enables the transistor, MP13. Then the slow signal is mirrored to the storage cell. Based on the fast and the slow signal, the storage cell output B is either low or high. When an UP pulse enables the transistor, MN0 the voltage at the drain of the transistor, MN3 starts building up. The transistor MN13 is also used to pull the voltage at the drain of MN3 to a suitable level to trigger the transistor MN1 at the storage cell. The transistor MN8 is used to pull back the voltage at the drain of MN3 to zero, when PFD generates the UPB signal. Similarly for the DOWN signal from PFD, the transistor MP14 is used to pull down the voltage at the drain of transistor MP0, and transistor MP9 is used to pull back the voltage to Vdd. 3.3 Storage cell and Reference current 29 Figure 3.7. Block diagram of N storage cell Figure 3.8. Schematic of REFCUR 3.3.2 Storage cell block The schematic of single storage cell is shown in the Figure 3.9. Initially, each capacitor in the storage cell is initialized to Vdd by turning on the transistor MP5 using INI signal. This makes the voltage at B to Vdd and zero at A. The LEFT signal of the first storage cell is connected to Vdd. This enables the transistor 30 Design of PLL blocks MN0 and disables the transistor MP0 for the first storage cell. The RIGHT signal is connected to the A output of the neighbouring cell. This enables the transistor MP4 and disables MN2 for the first storage cell. During a fast signal from REFCUR, the transistor MN1 gets enabled and the Figure 3.9. Schematic of single storage cell charged capacitor started discharging. Once, the voltage at B started to decrease, the voltage at A started to increase. When A increases above V dd/2, transistor MN2 turns on and pulled down the voltage at B to zero. This turns on the pmos transistor in proportional part of VCO, which results in frequency increase. During a slow signal from REFCUR, the transistor MP3 turns on and pulls up the voltage at B to Vdd which results in frequency decrease of VCO. The charging and discharging time depends on the current mirror ratio from the REFCUR to Storage cell. All the B output of the storage cell is connected to the pmos transistor in the VCO. So at the start, the VCO is operating at the lowest frequency, because all the B output of the storage cells is high. B[1:N]i = Vdd (3.2) A[1:N]i = 0 (3.3) When the PLL tries to lock the phase of the output signal to the input signal, the PFD generates a wide UP pulse. The REFCUR generates the FAST signal of same width as UP and copies the FAST signal to the storage cells. This turns on the transistor MN1 in S1. So, the capacitor in S1 starts discharging during the width of the UP. However, the capacitor in S2..SN, remains at Vdd, because the LEFT input of S2..SN is connected to A output of previous storage cells. Once, 3.3 Storage cell and Reference current 31 the voltage at B1 decreases below V dd/2, voltage at A1 starts to increase. This turns on the second storage cell S2 and the capacitor in S2 starts discharging. By this time, the RIGHT signal in S1 pulls down the B1 to zero and inactivates S1. When B2 is pulled down below V dd/2, S3 gets enabled and it becomes active. So, at a particular time, only two storage cells are active and all other storage cells are inactive. Thus, the PLL starts filling 0 in the capacitor from S1..SN. At the same time, the frequency controlling pmos transistors in VCO turns on one by one. This results in the increasing current flow in the oscillator and frequency gets increased. At the lock stage of PLL, when B is low, X-1 storage cells are inactive and when B is high, N-(X+1) are inactive. Storage cells with B(X:X+1) are active. This means for the length of ∆T of the ith UP or DOWN pulse charge will be dumped at C1. B[1:(X-1)i ] = 0 (3.4) B[(X+2)i :N] = Vdd (3.5) The whole process of the storage cells is shown in the Figure 3.10. Depending on Figure 3.10. Process of storage cells the current mirror ratio in REFCUR and the capacitor in the storage cell, it would take a pulse of length dt to change the voltage from Vdd to Gnd. X X ∆ti ∆ti B[m]i = Vdd · ( − ) dt dt B[m]active ,Down B[m]active ,Up (3.6) 32 Design of PLL blocks X B[m+1]i = Vdd · ( B[m+1]active ,Down f(i)=Kprop · Vprop (i) + m−1 X Kstep + Kstep · j=1 ∆ti − dt X B[m+1]active ,Up ∆ti ) dt (3.7) vdd-B[m+1]i vdd-B[m]i + Kstep · (3.8) vdd vdd Where, f(i) - average VCO frequency during ith update Kprop - VCO proportional gain Vprop (i) - average voltage at PROP during ith update pulse Kstep - Frequency change per digital step dt - Digital Step 3.4 Voltage Controlled Oscillator The voltage controlled oscillator [11] is a differential oscillator. The high bandwidth PLL needs a good oscillator in terms of the duty cycle. This leads to a symmetric differential design. 3.4.1 Single stage of VCO Each stage of VCO is a differential stage ring oscillator. It has two inputs which are differential to each other. It produces two outputs complement of each other. Both the outputs are connected to a buffer and the output of the buffer is given as input to next stage. The control voltage of each stage is applied through array of pmos and nmos transistors. The schematic of the single stage ring oscillator is shown in the Figure 3.11. The differential inputs are INN and INP. The input INN is given to the transistors MN1, MP1 and INP is given to the transistors MN2, MP2. When the input INN is high, transistor MN1 is turned on. These results in output node OSCP to pulled down to zero by the transistors MN15, MN1 and array of nmos transistors M N < 1 : N >. When the input INN is low, OSCP is pulled up to Vdd by transistors MP16, MP1 and array of pmos transistor M P < 1 : N >. The same procedure happens for the other input INP. Since both INN and INP are complementary to each other, output OSCP and OSCN are also complementary to each other. The array of transistor M P < 1 : N > and M N < 1 : N > controls the frequency of the oscillation. This array of transistors has one transistor for proportional part biased to V dd/2 by the capacitor in the charge pump. The gate voltage of all other transistors are connected to the B < 1 : N > outputs of the N storage cell. Basically, the control signal V n < 1 : N > is just a mirror of the control signal V p < 1 : N >. When all the transistors < 1 : N > are turned on, this results in more current flow in the oscillator results in the highest frequency of oscillations. When all the transistors < 1 : N > are turned off, this leads to less 3.4 Voltage Controlled Oscillator 33 Figure 3.11. Schematic of VCO single cell current flow, which results in lowest frequency of oscillations. The schematic of 5 stage differential ring oscillator is shown in the Figure 3.12. The frequency range Figure 3.12. Schematic of five stage VCO of oscillations is shown in the Figure 3.13. 34 Design of PLL blocks Figure 3.13. Frequency range of oscillator Chapter 4 Measuring PLL parameters The schematic of the PLL [1], [2] is shown in the Figure 4.1. It consists of the PFD, the charge pump, the VCO, and the storage cells. The frequency of VCO is tuned by the B 0 s output of the storage cells. The output of the VCO is passed into the buffer and is given back to the PFD as feedback signal. The PFD generates four outputs UP, UPB, DOWN and DOWNB. All the four outputs are given to charge pump and the REFCUR. The prop signal from the charge pump is used for the proportional damping of the PLL. For example, given operation at 500 MHz, the reference signal, CLK should be with a period of 2 ns and a pulse width of 1 ns to achieve a 50 % duty cycle. The rise time and fall time of the reference signal is given as 50 ps. Initial signal is given to the storage cell for a time of 10 ns to initialize all the capacitor in storage cell to Vdd. It is also given to PFD to stop generating UP or DOWN pulse until all the capacitor in storage cell get initialized. The whole setup is simulated in spice in a nominal process. The phase and frequency lock of the feedback signal, SYSCLK and the reference signal, CLK is shown in the Figure 4.2. There is an offset of 14 ps between SYSCLK and CLK. The time it takes to lock is 1.1 µs and the number of storage cells required for tuning the VCO to 500 MHz is 10. The PLL bandwidth achieved in the simulation results should be matched with mathematical modelling. The closed loop transfer function calculated in the equation 2.19, is used to obtain the magnitude plot of the PLL. The mathematical modelling of the PLL operating at 500 MHz is shown in the Figure 4.3. From the Figure 4.3, Hz (s) is the magnitude plot and Ez (s) is the error function from the VCO output to the VCO input. To verify the bandwidth obtained in the mathematical modelling with the simulation results, the following parameters must be measured. 1. Ko , Step gain of VCO. 2. Kp , Proportional gain of VCO. 35 36 Measuring PLL parameters Figure 4.1. Schematic of PLL operation at 500 MHz Figure 4.2. Phase and frequency lock of PLL operating at 500 MHz 3. dt, time taken to step from one storage cell to another storage cell. 4. Icp , current drawn by charge pump during UP and DOWN pulse. The measured parameters are substituted in the mathcad sheet to verify the sim- 4.1 Setup for measuring PLL parameters 37 Figure 4.3. Mathematical modelling of PLL operating at 500 MHz ulation results. 4.1 Setup for measuring PLL parameters To measure the PLL parameters, separate simulation to be performed, which has the same behaviour as in the PLL simulation. 4.1.1 VCO proportional gain measuring setup The proportional gain is the measurement of change in frequency of VCO for a change in the proportional control voltage. It has almost the same setup like step gain measurement. From the PLL simulation, at the lock state, the variation of the prop signal is from 0.73 to 0.8. Hence, the prop signal is ramped from 0.7 to 0.9 and the respective B 0 s should be turned on by the corresponding DC source to achieve 500 MHz signal. This setup is shown in Figure 4.4. From Figure 4.5, the frequency change with respect to change in control voltage is measured, df /dv. The prop voltage is pulled back to V dd/2, when CLK and feedback signal are zero 38 Measuring PLL parameters at the same. Since, the proportional gain, Kp is seen only for half of the time period, it should be divided by 2, hence Kp = Kp /2. Figure 4.4. Proportional gain measuring setup Figure 4.5. Kp , Proportional gain 4.1 Setup for measuring PLL parameters 4.1.2 39 Charge pump current measuring setup The current, Icp can be measured in two ways. One is directly plotting the drain current of transistor MN8 and MP4 of the charge pump, Figure 3.6. The other way is measuring the change in the voltage of prop signal with respect to an UP or DOWN signal and then multiplying the slope with the capacitor gives the current, Icp . It is given as. Icp = C · dv dt (4.1) The Figure 4.6 shows the second way of measuring Icp from the PLL simulation. Figure 4.6. Icp , Charge pump current 4.1.3 Digital step measuring setup The digital step, dt is the time taken for an inactive cell to become active cell. This can be measured by applying a constant UP pulse to the REFCUR block. This will generate a constant FAST pulse, which leads to discharging the capacitor one by one. The measuring set up for dt is shown in the Figure 4.7. 4.1.4 VCO step gain measuring setup The step gain is the measurement of change in frequency of VCO per digital step. It is measured by simulating the VCO alone with a constant DC source of V dd/2 for the proportional part. From the PLL simulation, the number of storage cells 40 Measuring PLL parameters Figure 4.7. dt, Digital step required to achieve 500 MHz is 10. So, in the control signal of VCO from storage cell B < 1 : 28 >, a DC source of zero is given to B < 1 : 9 > and Vdd is given to B < 11 : 28 >. The remaining one control signal B < 10 > is ramped from Vdd to zero. This setup is shown in Figure 4.8. From the Figure 4.9, the frequency change with respect to change in control voltage is measured, df /dv. This is the step gain Ko . The parameters measured for the PLL operating at 500 MHz under nominal process are shown in the Table 4.1. All the measured parameters are applied in the Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt, Digital Step Values 1.5 25◦ C 60 MHz 53 MHz 420 µA 34 ns Table 4.1. PLL parameters in nominal process mathematical modelling and the resulting magnitude plot of the transfer function is shown in the Figure 4.3. It shows the -3 dB bandwidth of the PLL operating at 500 MHz is greater than 1/10th of the input frequency (i.e) 50 MHz. 4.2 Bandwidth test 41 Figure 4.8. Ko , Step gain measuring setup Figure 4.9. Ko , Step gain 4.2 Bandwidth test To verify the bandwidth of the PLL operating at 500 MHz, the reference signal CLK should be modulated by the corresponding modulating frequency. The PLL 42 Measuring PLL parameters operating at 500 MHz with the same setup as in the Figure 4.1 is simulated with a modulated CLK at 5 MHz and 50 MHz with 500 MHz as carrier frequency. In each simulation, the output signal SYSCLK follows the modulated CLK. So, how much the modulated SYSCLK gets deviated from the modulated CLK can be calculated using ∆fSY SCLK ) (4.2) s=20 · log( ∆fCLK s=-3 dB, implies the -3 dB bandwidth of the PLL, which is at 50 MHz. Hence, the same bandwidth of 50 MHz in the mathematical modelling is achieved in simulation too. 4.2.1 Process corners compensation The PLL shown in the Figure 4.1 is simulated in nominal process with Vdd = 1.5 V. The same setup has to be simulated under different process variations like strong and weak process. In strong process, the Vth of transistors gets reduced, which results in very fast switching and in weak process the vice versa. The uncompensated PLL operating at 500 MHz is simulated under strong and weak process conditions. During strong simulations, the temperature of the simulation must be changed to −40◦ celsius and the supply voltage should be 1.6 V. During weak simulations, the temperature should be +125◦ celsius and Vdd should be 1.4 V. The measured parameters values for strong simulation is shown in the Table 4.2 and for weak simulation is shown in the Table 4.3. From the table, Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt, Digital Step Values 1.6 −40◦ C 110 MHz 90 MHz 634 µA 32ns Table 4.2. Uncompensated PLL parameters in strong process Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt, Digital Step Values 1.4 125◦ C 13 MHz 45 MHz 360 µA 33ns Table 4.3. Uncompensated PLL parameters in weak process 4.2 Bandwidth test 43 it can be realized that the proportional gain, the step gain and the charge pump current for strong process simulation, has increased by approximately 50% from the nominal process values. These results in a very high bandwidth above than the bandwidth achieved for the nominal process. For the weak process simulation, the parameters have been decreased. This results in a very low bandwidth than nominal process. The parameters measured in both strong and weak process are substituted in the mathematical modelling and the resulting bandwidth are shown in the Appendix A. The PLL should be compensated for all the process corners. The compensation is applied in the proportional part of the VCO. The compensated proportional part of the VCO is shown in the Figure 4.10. Based on the process, the number of storage cells required to achieve the lock frequency differs. From the Figure 4.10, the transistors V BP < 7 : 14 > gets activated based on the number of active storage cells. This in turn increases the proportional gain of the VCO. This results in achieving the same bandwidth as achieved in the nominal process of the PLL operating at 500 MHz. The compensated PLL parameters under all the three Figure 4.10. Compensated proportional part of VCO process are shown in the Table 4.4, Table 4.5 and Table 4.6. The measured compensated PLL parameters are substituted in the mathematical modelling and the resulting bandwidth for the nominal process is shown in Figure 4.11. The PLL parameters measuring graphs for the compensated PLL operating at 500 MHz in all the process corners are shown in the Appendix A. 44 Measuring PLL parameters Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt,Digital Step Values 1.5 25◦ C 95 MHz 100 MHz 290 µA 34ns Table 4.4. Compensated PLL parameters in nominal process Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt,Digital Step Values 1.6 −40◦ C 31 MHz 123 MHz 344 µA 30ns Table 4.5. Compensated PLL parameters in strong process Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt,Digital Step Values 1.4 125◦ C 53 MHz 38 MHz 188 µA 33ns Table 4.6. Compensated PLL parameters in weak process 4.2 Bandwidth test Figure 4.11. Compensated PLL in nominal process 45 Chapter 5 PLL operating range The operating range of the PLL is from 100 MHz to 1 GHz. The bandwidth of the PLL over the large range should be more than 1/10th of the reference frequency. Two separate PLL are designed at extreme operating frequency range in this chapter. Then finally in the chapter 6, two PLL’s are combined in a single PLL schematic to operate all over the frequency range. The REFCUR block is also modified in this chapter to make sure that the final PLL schematic operates all over the range from 100 MHz to 1 GHz. 5.1 Modified REFCUR block To make the PLL to operate from 100 MHz to 1 GHz range, the digital step, dt should vary for a range of values. This can be achieved by varying the current copied from the REFCUR block to the storage cells. The REFCUR in the Figure 3.8 is not flexible with the change of current copying to storage cells when the value of the resistor gets changed. Because even when the value of resistance is changed, same current flows through the transistors MP12 and MP11 and gets copied to FAST and the same for the SLOW. Hence a REFCUR block, which is very much flexible with the resistance, is designed. It is shown in the Figure 5.1. It works exactly the same manner as the previous REFCUR and is also flexible with the value of resistance. When the PFD generates an UP pulse, it enables the transistor MN3 and the current gets copied by the transistor MP5. This will start build up the voltage at the drain of transistor MN4, which enables the corresponding transistor in the storage cell. During an UPB pulse from the PFD, the FAST voltage gets pulled down to zero by transistor MN5. The same concept applies for the SLOW pulse. 47 48 PLL operating range Figure 5.1. Schematic of modified REFCUR Figure 5.2. Schematic of PLL operating at 100 MHz 5.2 PLL operating at 100 MHz At 100 MHz as the input reference frequency, the resistor in the charge pump has a value of 40 KΩ, to achieve a charge pump current of 90 µA. The resistor in the REFCUR block has a value of 40 KΩ to get a digital step value, dt as 40 ns. The schematic of the PLL operating at 100 MHz as the input frequency is shown in the Figure 5.2. The VCO has the respective step gain and the proportional gain to achieve the respective lock frequency. The number of storage cells required to tune the PLL to 100 MHz is 3. The phase and frequency lock of the PLL operating 5.2 PLL operating at 100 MHz 49 at 100 MHz is shown in the Figure 5.3. It has a phase offset of 91 ps and the lock time is 200 ns. The measurement graphs for the PLL parameters like Ko , Kp , Icp and dt are shown in the Appendix B. The measured parameters under the nominal process are shown in the Table 5.1. Figure 5.3. Frequency and phase lock of PLL operating at 100 MHz The measured parameters are substituted in the mathematical modelling and the resulting bandwidth is greater than 50 MHz. The maximum modulation frequency of a signal is fsignal /2. The maximum modulating frequency is 50 MHz for the reference frequency of 100 MHz. Hence, the bandwidth achieved in the PLL operating at 100 MHz is very high bandwidth. So, it can transfer all the signals from the input to output with a offset of 91 ps. The description of the PLL is shown in the Figure 5.4. 5.2.1 Bandwidth test of PLL operating at 100 MHz To test the bandwidth of the PLL operating at 100 MHz, the reference signal is modulated at certain modulating frequency with 100 MHz as a carrier signal. 50 PLL operating range Figure 5.4. Mathematical modelling of PLL operating at 100 MHz The output of the PLL follows the input modulated signal. The magnitude of the deviation of the output to the input frequency of the modulated signals is shown in the Table 5.2. The measurement graphs for the modulated signals with 100 MHz as carrier frequency are shown in the Appendix B. Hence, the values of the modulated frequencies are roughly matched with the description in the Figure 5.4. 5.3 PLL operating at 1 GHz At 1 GHz as the input frequency to the PLL, the resistor in the charge pump and REFCUR should be changed to 1 KΩ to obtain the charge pump current of 670 µA and the digital step, dt as 15 ns. The VCO has the respective proportional and step gain to achieve damping and frequency. The number of storage cells required to achieve the right frequency is 13. The phase and frequency lock of PLL at 1 GHz is shown in Figure 5.5. It has a phase offset of 67 ps and lock time as 2 µs. The measurement graph for all the PLL parameters is shown in the Appendix B. The measured parameters under nominal process are shown in the 5.3 PLL operating at 1 GHz Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp ,Charge Pump current dt,Digital Step 51 Values 1.5 25◦ C 90 MHz 10 MHz 90 µA 40ns Table 5.1. Parameters of PLL operating at 100 MHz in nominal process Modulation Frequency (MHz) 2 7 13 25 50 ∆fout 20 · log( ∆f ) ref 0 1.1 1 -0.2 -0.8 Table 5.2. Bandwidth test for PLL operating at 100 MHz Table 5.3. As usually, the measured parameters are substituted in the description Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp ,Charge Pump current dt,Digital Step Values 1.5 25◦ C 409 MHz 28 MHz 672 µA 15ns Table 5.3. Parameters of PLL operating at 1 GHz in nominal process and the resulting -3 dB bandwidth is 100 MHz. The mathematical modelling of PLL at 1 GHz is shown in the Figure 5.6. 5.3.1 Bandwidth test of PLL operating at 1 GHz To test the bandwidth of the PLL operating at 1 GHz, the reference signal is modulated at certain modulating frequency with 1 GHz as a carrier signal. The magnitude of output to input frequency deviation of the signals modulated at 10 MHz, 20 MHz, 50 MHz, 100 MHz and 200 MHz is shown in Table 5.4. The measurement graphs for the modulated signals with 1 GHz as carrier frequency are shown in the Appendix B. The values obtained in the simulation for the particular modulated signal is not matched with the description in the Figure 5.6 52 PLL operating range Figure 5.5. Frequency and phase lock of PLL operating at 1 GHz for frequency higher than 100 MHz. At higher frequencies, the curve is steeper. So, there may be an extra pole occurs at the higher frequency. This is discussed more in the Chapter 6. 5.3 PLL operating at 1 GHz 53 Figure 5.6. Mathematical modelling of PLL operating at 1 GHz Modulation Frequency (MHz) 10 20 50 100 200 ∆fout 20 · log( ∆f ) ref 0 0 0 1.3 -8.9 Table 5.4. Bandwidth test for PLL operating at 1 GHz Chapter 6 Mixed signal and process corner simulation of PLL The PLL has to operate for a range of 100 MHz to 1 GHz with a high bandwidth of more than 1/10th of input frequency. It has been checked already that the PLL can operate at both extremes. It is also checked that the description is matched with PLL at 100 MHz and not matched with PLL at 1 GHz. To make it work for all frequencies within the range, the following three things should be varied dynamically. 1. Current from charge pump. 2. Current copied from REFCUR. 3. Proportional part of the VCO. The number of storage cells required to tune the VCO for particular operating frequency is different. This is the key to vary the above mentioned parameters dynamically. With the use of the A < 1 : N > outputs from the storage cells, a breeching resistor architecture is used in the charge pump and the REFCUR. The single resistor is replaced by the breeching resistors as shown in the Figure 6.1. The A < 1 : N > outputs of storage cell is inverted and is applied to the pmos transistors to breech resistors. From the Chapter 5.2, it known that the charge pump and REFCUR block needs 40 KΩ of resistance for PLL operating at 100 MHz. If the PLL is operating at 100 MHz, it takes 3 storage cells to achieve lock. This will breech first three pmos transistors and the charge pump or the REFCUR block will see a 40 KΩ of resistance. The same procedure occurs for each operating frequency. Similarly, the proportional part of the VCO needs to be compensated to provide appropriate gain at each operating frequency. It is almost the same procedure used in the process compensation for the PLL operating at 500 MHz in the Chapter 4.2.1. For the particular operating frequency, the number of storage cells required to achieve lock is different. Based on this, the transistors turns ON and increases 55 56 Mixed signal and process corner simulation of PLL Figure 6.1. Architecture of resistor breech the proportional part of the oscillator. The compensation of oscillator is shown in the Figure 6.2. Figure 6.2. Frequency compensation of proportional part of VCO Reference CLK at 100 MHz The frequency compensated PLL is simulated with 100 MHz as input frequency. The frequency and phase lock of the PLL at 57 100 MHz is shown in the Figure 6.3. The modulated signal is also applied at the input frequency with carrier at 100 MHz. The output frequency deviation of the modulated signals at 33 MHz and 50 MHz is shown in the Figure 6.4. It can be seen that, it has a strange behaviour at those modulation frequencies. But these strange behaviours are not reflected in the description too, in the Figure 5.4. This problem will be addressed in the Section 6.2. Figure 6.3. Frequency and phase lock of compensated PLL operating at 100 MHz Reference CLK at 1 GHz The PLL with the same setup is simulated with 1 GHz as input frequency. The frequency and phase lock of PLL operating at 1 GHz is shown in the Figure 6.5. The reference signal is also modulated at 100 MHz and 333 MHz with 1 GHz as a carrier frequency and the result is shown in the Figure 6.6. It is clear that at 100 MHz modulation signal, again a strange behaviour occurred. In description, it is stable, but in the simulation it results in ringing. 58 Mixed signal and process corner simulation of PLL Figure 6.4. 100 MHz reference modulated at 33 MHz and 50 MHz 6.1 Verilog-A model of charge pump and REFCUR The strange behaviour occurred in both the extreme operating frequencies. Replacing the charge pump and the REFCUR with verilog-A model leads to better understanding of these strange behaviours and to cross check the behaviour occurs at with ideal components. 6.1.1 Verilog-A model of charge pump The basic function of the charge pump is to charges/discharges the capacitor. The verilog-A model of the charge pump is shown in the Appendix C. In the model, if the PFD generates an UP pulse, a variable called state is set to 1 and it is set to 0, when DOWN pulse is generated by the PFD. So, based on the value of variable, the current starts flowing in particular direction. Here, for an UP pulse a current flows in the positive direction and for the DOWN pulse, vice-versa. The time, when both the reference clk and the feedback signal are zero, the current flow should be stopped and voltage at the capacitor should be pulled back to V dd/2. The current flowing from charge pump is set to 1400 µA for PLL operating at 6.1 Verilog-A model of charge pump and REFCUR 59 Figure 6.5. Frequency and phase lock of compensated PLL operating at 1 GHz 1 GHz and 80 µA at 100 MHz. 6.1.2 Verilog-A model of REFCUR The REFCUR block is to supply current to the storage cells depending on the operating frequency of the PLL. It is known that the current copied into the storage cells for PLL operating at 100 MHz is 17 µA and at 1 GHz is 50 µA. The modelling is similar to the charge pump that when an UP pulse is generated, current flows in the positive direction and for DOWN its vice-versa. The way of connecting each storage cell is shown in the Figure 3.7. This will result in the two active storage cell at all the time. The capacitor is connected at the output port of each storage cell. The verilog-A model of the REFCUR is also shown in the Appendix C. 60 Mixed signal and process corner simulation of PLL Figure 6.6. 1 GHz reference modulated at 100 MHz and 333 MHz 6.2 Mixed signal model of PLL In the frequency compensated PLL, the charge pump and the storage cells are replaced by its verilog-A model. The mixed signal model of the PLL is shown in the Figure 6.7. At the first step, only the charge pump is replaced with its verilog-A model and is simulated with a modulated signals at 100 MHz as carrier. The large peaking occurred in the Figure 6.4 does not occurred using the verilog-A model of the charge pump with a current of 80 µA, but the zig-zag behavior remains the same. When the storage cells is also replaced with verilog-A model with a current of 17 µA, the zigzag pattern also disappeared and the resulting waveforms at the respective modulation frequencies are shown in the Figure 6.8. So, there needs to adjust the breeching resistors for PLL operating at 100 MHz. To achieve the same response in the schematic, the resistance required for the charge pump and the REFCUR should be different. The resistance should be 86 KΩ for the charge pump and 60 KΩ for the REFCUR. The same setup is also simulated with the modulated signals at 1 GHz as car- 6.2 Mixed signal model of PLL 61 Figure 6.7. Mixed signal model of PLL rier and the resulting waveforms are showed in the Appendix C. The measured parameters with the mixed signal simulation of the PLL operating at 1 GHz is shown in the Table 6.1. The resulting mathematical modelling of the PLL operating at 1 GHz is shown in the Figure 6.9. The magnitude of output to input frequency deviation of the modulated signals are shown in the Table 6.2. It is clearly seen that still it is not matched with the description at higher frequencies. So, the problem may be from the VCO. There may be one more extra pole in the operating range of the PLL. To verify this, the bandwidth of VCO should be checked, because in the mathematical description it is assumed that VCO has infinite bandwidth. Parameters Vdd Temperature Kp , Proportional Gain Ko , Step Gain Icp , Charge Pump current dt,Digital Step Values 1.5 25◦ C 256 MHz 28 MHz 1400 µA 15 ns Table 6.1. Parameters of PLL operating at 1 GHz in verilog-A model 62 Mixed signal and process corner simulation of PLL Figure 6.8. 100 MHz reference modulated at 33 MHz and 50 MHz in verilog-A model 6.3 Poles in VCO The voltage controlled oscillator has one input from the storage cells, B < 1 : N > and another input from the charge pump, prop. So, there is a need to determine the bandwidth of the VCO from both the inputs. The frequency deviation occurred at the output of the VCO is measured at different frequencies of the input. The frequency deviations are converted into decibels, and the -3 dB bandwidth is measured. The bandwidth curve looks like a response of low-pass filter with single pole. Using the measured pole frequency, the time constant, τ can be measured from the equation. τ= 1 2πf (6.1) The measured pole should be included in the transfer function by multiplying the transfer function with. 6.3 Poles in VCO 63 Modulation Frequency (MHz) 50 100 333 ∆f ) 20 · log( ∆fref out -1.6 -4.5 -15.6 Table 6.2. Bandwidth test for PLL operating at 1-GHz in verilog-A Figure 6.9. Mathematical modelling of PLL operating at 1 GHz in verilog-A 1 1 + (s · τ ) (6.2) The pole frequency should be measured from both the inputs of the VCO. At first, the pole frequency is measured for the control signal from the storage cells. Since, there are no match between the description and the simulation for the PLL operating at 1 GHz, the number of storage cells required to achieve 1 GHz, frequency lock is 13. Therefore, B < 1 : 12 > should be hardwired to zero and the rest, B < 14 : N > should be hardwired to Vdd. A sinusoidal signal of certain frequency is applied at B < 13 > with V dd/2 as DC voltage. The input sinusoidal 64 Mixed signal and process corner simulation of PLL signal with different frequencies and its output frequency deviation of the VCO is tabulated in the Table 6.3. The measurement graphs for the frequency deviation are shown in the Appendix C. The pole frequency of the VCO with modulated input from the storage cells is Sinusoidal signal frequency (MHz) 10 100 200 300 400 500 Frequency Deviation (MHz) 35 35 32 27 22 19 Magnitude 0 -0.7 -2.2 -4 -4.03 -5.3 Table 6.3. Pole frequency measurement for Vctrl from storage cells occurred at 280 MHz. Using the equation 6.1, the time constant, τ is obtained as 568 ps. The -3 dB bandwidth of the VCO for the modulated B < 1 : N > are shown in the Figure 6.10. Finally, the pole frequency for the signal from the Figure 6.10. Pole at VCO for Vctrl from storage cells charge pump is to be measured. For this, the number of B < 1 : N > required to achieve the respective frequency is hardwired. Prop signal should be hardwired by a sine wave with V dd/2 as a DC voltage. Different frequencies are applied at prop, and the frequency deviation is tabulated in the Table 6.4. The graphs for measuring -3 dB point are shown in the Appendix C. The pole frequency occurred at approximately 300 MHz and the obtained time constant is 530 ps. The -3 dB bandwidth of the VCO for the modulated prop signal are shown in the Figure 6.11. From the bandwidth of VCO, two poles are present at a frequency of 300 MHz. So, the transfer function of PLL should be 6.4 Exponential scaling 65 Sinusoidal signal frequency (MHz) 5 10 100 200 300 Frequency Deviation (MHz) 133 133 125 105 96 Magnitude 0 -0.5 -2.05 -2.8 -4.2 Table 6.4. Pole frequency measurement for Vctrl from charge pump Figure 6.11. Pole at VCO for Vctrl from charge pump modified as ( Kprop H(z) = 1+( f2 Icp · C · Kprop f2 1 1+(s·p1) Icp · C · + 1 1+(s·p1) 1 1− + · 1 z(s) 1 1− 1 z(s) Kstep · f 2 ·dt · 1 ) 1+(s·p2) Kstep · f 2 ·dt · 1 ) 1+(s·p2) N z(s)(1− z1 ) · N z(s)(1− z1 ) (6.3) When the poles are included in the transfer function, the description and the simulation results of the PLL simulation at 1 GHz is roughly matching with ±1 dB deviation as shown in the Figure 6.18. 6.4 Exponential scaling The operating range of the PLL is from 100 MHz to 1 GHz under nominal process. In the Chapter 5, the resistance in the charge pump and the REFCUR is replaced by a breeching architecture to provide a suitable current for all the input frequency from 100 MHz to 1 GHz. Currently, the resistors are scaled in a linearly decreased fashion. But in reality it should decrease approximately like an 66 Mixed signal and process corner simulation of PLL exponential fashion. 6.4.1 Charge pump and REFCUR resistor scaling From the mixed signal simulation, it is known that at 100 MHz input frequency, resistance required for charge pump is 86 KΩ and 1 KΩ at 1 GHz input frequency. The number of storage cells required for 100 MHz is 3 and 13 storage cells for 1 GHz. The total number of steps is 10. Hence, the exponential scaling of resistance is given by. 86K · e(−x·10) = 1K (6.4) By solving it, we get x=0.4454. By using the equation 6.5, the resistance seen by the charge pump at each step and the value of resistance between the step is shown in the Figure 6.12. 86k · e(−0.4454·STn ) (6.5) For the REFCUR, it is known that at 100 MHz resistance required is 60 KΩ and Figure 6.12. Charge pump resistor scaling 1.3 KΩ at 1 GHz. Similarly as above, the exponential scaling of the resistance is given by. 60K · e(−x·10) = 1.3K By solving it, we get x = 0.383. (6.6) Substituting x in the equation gives 60k · 6.4 Exponential scaling 67 e(−0.383·STn ) and the resistance seen by the REFCUR at each step and the value of resistance between the step is shown in the Figure 6.13. Figure 6.13. REFCUR resistor scaling 6.4.2 Charge pump capacitor scaling From the current equation of the capacitor, the capacitance and the current are inversely proportional to each other. Using that, when the PLL is operating at higher frequencies at 1 GHz, less capacitance should be connected to the charge pump output and at low frequencies its vice-versa. This leads to the scaling of the capacitor and the schematic is shown in the Figure 6.14. The A < 1 : N > output from the storage cells are used to connect and disconnect the capacitor based on the number. Initially, all the A < 1 : N > output from the storage cells were zero and hence all the capacitors are connected to the charge pump output, cp1. Depends on the input frequency, certain number of A < 1 : N > will be pulled up to Vdd and some capacitors gets disconnected from cp1. This leads to a high current flow at the higher frequencies than at the lower frequencies. The capacitor scaling is also done in the exponential manner as follows. 1.1 p · e(−10·x) = 0.001 p (6.7) Solving the equation, we get x = 0.7003. The equation should be differentiated with respect to STn , because the value of capacitance should get accumulated with the number of A < 1 : N >. Hence, the equation becomes. 0.77033 · e(−0.7003·STn ) (6.8) 68 Mixed signal and process corner simulation of PLL Figure 6.14. Schematic of charge pump capacitor scaling The value of capacitor between each step is shown in the Figure 6.15. Figure 6.15. Charge pump capacitor scaling 6.5 Process corner simulations 6.4.3 69 Transistor scaling of proportional part of VCO The proportional part of the VCO also needs to be scaled up exponentially. The procedure is same like the capacitor scaling. The resulting exponential increase in the W/L of the transistors are shown in the Figure 6.16. Figure 6.16. Scaling of VCO proportional part 6.5 Process corner simulations The PLL is simulated for different reference frequency under nominal process with 25◦ C temperature and 1.5 V supply voltage. The PLL parameters measured for different input frequencies ranging from 100 MHz to 1 GHz are shown in the Table 6.5. The measurement graphs for all PLL parameters in nominal process are shown in the Appendix C. The mathematical description for PLL operating at 100 MHz input frequency is shown in the Figure 6.17 and at 1 GHz is shown in the Figure 6.18. The mathematical description for other reference frequencies are shown in the Appendix C. The bandwidth test for the PLL is simulated at 1/10th and 1/4th of input frequency to test the matching between the simulation results and the description. The simulation results for bandwidth test at 100 MHz input frequency are matching with description as shown in the Figure 6.19 and at 1 GHz in the Figure 6.20. The bandwidth test for other frequencies are shown in the Appendix C. The achieved bandwidth is 1/4th of the reference frequency for the whole range from 100 MHz to 1 GHz in nominal process. 70 Mixed signal and process corner simulation of PLL Input Frequency (MHz) 100 200 300 400 500 900 1000 dt (ns) 55 41 32 26 24 20 15 Ko (MHz) 24 119 96 106 70 60 18 Kp (MHz) 141 154 176 215 225 276 250 Icp µA 61 120 170 213 316 700 1000 C (pF) 1.2 0.768 0.58 0.487 0.442 0.360 0.420 Table 6.5. PLL parameters measured for different reference frequency in nominal process Figure 6.17. Mathematical modelling of PLL operating at 100 MHz in nominal process 6.5.1 Weak and strong corners The PLL with the same setup is simulated for different process corners. The following tables show the parameters measured for different process corners. The mathematical description for 100 MHz input frequency for weak corner is shown the Figure 6.21 and for 700 MHz is shown in the Figure 6.22. The mathematical description for 100 MHz input frequency for strong corner is shown in the Fig- 6.5 Process corner simulations 71 Figure 6.18. Mathematical modelling of PLL operating at 1 GHz in nominal process ure 6.23 and for 1 GHz is shown in the Figure 6.24. The description for other frequencies in the weak and strong corners are shown in the Appendix C. It is understood that for weak corner, the PLL cannot operate above 700 MHz because of the limitations with the VCO. At extreme frequency, the description is roughly matching with the simulation results, because of the poles occurring in the operating frequency of PLL. It is not good to have pole frequencies within the operating frequency of the PLL. The PLL bandwidth should depend on the PLL parameters rather than pole frequency. So, there is a need to move these two poles away from our operating frequency. The pole occurred in the proportional signal is very sensitive with the bandwidth. So, to increase the pole frequency, the resistance should be decreased. In the VCO, the control signal is given to pmos transistors and then it is mirrored to nmos transistors to achieve the symmetrical oscillations. Hence, to move the poles, the transistor sizes are increased in the path of prop signal. But this does not affect the pole, because of the diodes present in the inverter of single VCO cell in the Figure 3.11. So, when those diodes were not there, the pole is moved to higher frequency and at the same time maximum frequency of oscillation is moved to 3 GHz. 72 Mixed signal and process corner simulation of PLL Figure 6.19. 100 MHz reference modulated at 10 MHz and 25 MHz in nominal process Figure 6.20. 1 GHz reference modulated at 100 MHz and 250 MHz in nominal process 6.6 Jitter and Power measurement The jitter is measured by simulating the PLL along with the transistor noises. The main contribution for jitter is from VCO. The period jitter measured with differential VCO is very high compared to the single ended VCO. The measured 6.6 Jitter and Power measurement Input Frequency (MHz) 100 200 300 700 dt (ns) 60 38 33 28 73 Ko (MHz) 5 60 65 17 Kp (MHz) 122 128 152 231 Icp µA 60 122 161 1066 C (pF) 0.8 0.621 0.509 0.448 Table 6.6. PLL parameters measured for different reference frequency in weak process Input Frequency (MHz) 100 300 500 1000 500 900 1000 dt (ns) 58 38 28 16 24 20 15 Ko (MHz) 26 165 150 104 70 60 18 Kp (MHz) 161 168 240 340 225 276 250 Icp µA 92 200 230 700 316 700 1000 C(pF) 1.5 0.6 0.5 0.5 0.442 0.360 0.420 Table 6.7. PLL parameters measured for different reference frequency in strong process jitter for two different VCO is shown in Table 6.8. The power consumed by the PLL is also high for differential VCO compared to Single ended VCO and it is also shown in Table 6.8. Differential VCO Single Ended VCO Jitter 100 MHz 150 65 (ps) 1 GHz 25 12 Power (mW) 100 MHz 1 GHz 13 33 12 24 Table 6.8. Measured jitter and power 74 Mixed signal and process corner simulation of PLL Figure 6.21. Mathematical modelling of PLL operating at 100 MHz in weak process 6.6 Jitter and Power measurement 75 Figure 6.22. Mathematical modelling of PLL operating at 700 MHz in weak process 76 Mixed signal and process corner simulation of PLL Figure 6.23. Mathematical modelling of PLL operating at 100 MHz in strong process 6.6 Jitter and Power measurement 77 Figure 6.24. Mathematical modelling of PLL operating at 1 GHz in strong process Chapter 7 Conclusion and Future work 7.1 Conclusion The new PLL architecture with very high bandwidth is implemented in a 150 nm CMOS process. The operating range of the PLL is from 100 MHz to 1 GHz. The new PLL architecture is also mathematically modelled in the z-domain. The architecture implements a new active proportional damping, which results in a less update jitter and very fast to achieve desired (lock) frequency. The N storage cells had an advantage of analogue tuning with the oscillator and also storing the tuning information digitally. Overall, the bandwidth achieved is 1/4th of the input frequency for the whole operating range in the nominal and strong process. Because of the limitation with the VCO, the PLL cannot operate above 700 MHz for weak process, but it achieves the above mentioned bandwidth until it operates. The power consumed by the design at high frequency (1 GHz) is 33 mW , which is not very much low power, since a lot of power is consumed by the oscillator. Finally, the simulation results are also matched with the mathematical modelling. 7.2 Future work 1. The bandwidth of the PLL can be increased to 1/2th of input frequency. So, that it can pass all the modulating frequencies. 2. The jitter and power can be improved by designing the VCO better than the architecture used here. 3. The high bandwidth semi-digital PLL can be implemented in the silicon and it can be verified with the results obtained from the hardware. 79 Bibliography [1] M. Dietl and P. Sareen, Low Power, small die-size PLL using semi-digital storage instead of big loop filter capacitance, NESEA IEEE Conference, 2010. [2] M. Dietl and P. Sareen, A New Low Power and Area Efficient Semi-Digital PLL Architecture for Low Bandwidth Applications, GLSVLSI IEEE Conference, 2011. [3] B.Razavi, Design of Analog CMOS Integrated Circuits, 3rd ed. TATA McGRAW-HILL, 2009. [4] L. Won-Hyo, L. Sung-Dae, Jun-Dong, A High Speed and Low Power PhaseFrequency Detector and Charge-pump, Design Automation Conference, 1999. PP. 269-272. [5] J.G. Maneatis, Low-jitter and process independent DLL and PLL based on self biased techniques, Solid-State Circuits Conference, 1996. Digest of Technical Papers, 42nd ISSCC. [6] B. Zhang, P.E. Allen, J.M. Huard, A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-?m CMOS, Solid-State Circuits, IEEE Journal of 2003, Volume : 38 , Issue:6 , pp. 855 865. [7] Cardinal Components Inc., Phase-Lock Loop basics, Applications Brief No. A.N. 1007., http://www.cardinalxtal.com/docs/notes/cardinal_ phase_lock_loop_basics.pdf [8] M. Mozhgan, Low-Power Low-Jitter On-Chip Clock Generation, PHD Thesis at University of California, 2003. 81 82 [9] F. Dennis, Practical Tips //www.delroy.com, 2007. Bibliography for Phase Lock Loop Design, http: [10] T.M. Almeida, M.S. Piedade, High Performance Analog and Digital PLL Design, Circuits and Systems, 1999. ISCAS ’99. Proceedings of the 1999 IEEE International Symposium, Page(s): 394 - 397 vol.4. [11] Sai, A. Yamaji, T. Itakura, A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop, Solid-State Circuits, Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, pp. 98 - 100, 2011. Appendix A PLL parameters measuring graphs 1. The following figures show the mathematical modelling of the uncompensated PLL in strong and weak process. Figure A.1. Uncompensated PLL in strong process 83 84 PLL parameters measuring graphs Figure A.2. Uncompensated PLL in weak process 85 2. The following figures depicts the graphs for measuring the compensated PLL parameters in all the process corners. Figure A.3. Compensated Icp in nominal process Figure A.4. Compensated Ko in nominal process 86 PLL parameters measuring graphs Figure A.5. Compensated Kp in nominal process Figure A.6. Compensated Icp in strong process 87 Figure A.7. Compensated Ko in strong process Figure A.8. Compensated Kp in strong process 88 PLL parameters measuring graphs Figure A.9. Compensated Icp in weak process Figure A.10. Compensated Kp in weak process 89 Figure A.11. Compensated Ko in weak process 90 PLL parameters measuring graphs 3. The following figures explains the mathematical modelling of the compensated PLL in weak and strong process. Figure A.12. Compensated PLL in strong process 91 Figure A.13. Compensated PLL in weak process Appendix B Simulations for PLL operating range 1. The following figures shows the parameter measuring graphs for the PLL operating at 100 MHz in the nominal process. Figure B.1. Icp measurement for PLL operating at 100 MHz in nominal process 92 93 Figure B.2. Ko measurement for PLL operating at 100 MHz in nominal process Figure B.3. Kp measurement for PLL operating at 100 MHz in nominal process 94 Simulations for PLL operating range 2. The following figures shows the bandwidth test for the PLL operating at 100 MHz reference modulated at 7 MHz, 25 MHz and 50 MHz in the nominal process. Figure B.4. 100 MHz reference modulated at 7 MHz in nominal process 95 Figure B.5. 100 MHz reference modulated at 25 MHz in nominal process Figure B.6. 100 MHz reference modulated at 50 MHz in nominal process 96 Simulations for PLL operating range 3. The following figures shows the parameter measuring graphs for the PLL operating at 1 GHz in the nominal process. Figure B.7. dt measurement for PLL operating at 1 GHz in nominal process Figure B.8. Icp measurement for PLL operating at 1 GHz in nominal process 97 Figure B.9. Ko measurement for PLL operating at 1 GHz in nominal process 98 Simulations for PLL operating range 4. The following figures shows the bandwidth test for the PLL operating at 1 GHz reference modulated at 20 MHz, 100 MHz and 200 MHz in the nominal process. Figure B.10. 1 GHz reference modulated at 20 MHz in nominal process 99 Figure B.11. 1 GHz reference modulated at 100 MHz in nominal process Figure B.12. 1 GHz reference modulated at 200 MHz in nominal process Appendix C Simulations for process corners 1. The following section describes the verilog-A model of the charge pump and the storage cell. Verilog-A Model of Charge Pump module cp1 (out, up, dn, clk, sysclk); inout input input input input out; electrical out; up; voltage up; dn; voltage dn; clk; voltage clk; sysclk; voltage sysclk; // current output // positive input (edge triggered) // inverting input (edge triggered) parameter real iout_up = 80u; parameter real iout_dn = 80u; // maximum output current parameter real vh= 1.5; parameter real vl=0; parameter real vth=(vh+vl)/2; // input voltage in high state // input voltage in low state // threshold voltage at input integer state_up,state_dn,en; analog begin @(cross(V(up)-vth, 1)) state_up = 1; @(cross(V(up)-vth, -1)) state_up = 0; 100 101 @(cross(V(dn)-vth, 1)) state_dn = -1; @(cross(V(dn)-vth, -1)) state_dn = 0; // Implement charge pump if ((V(clk)<0.75) && (V(sysclk)<0.75)) begin if(V(out) < 0.75) begin I(out) <+ -10m; if(V(out) == 0.75) I(out) <+ 0; end else if(V(out) > 0.759999) begin I(out) <+ 10m; if(V(out) == 0.75) I(out) <+ 0; end else if((V(out)>=0.75) && (V(out)<=0.759999)) V(out) <+ 0.75; end else if((V(clk)>=0.75 && V(sysclk)<=0.75)||(V(clk)<=0.75 && V(sysclk)>=0.75 begin if(V(out)<=0.1) V(out) <+ 0.1; else if(V(out)>=1.4) V(out) <+ 1.4; else if((V(out)>0.1) && (V(out)<1.4)) I(out) <+ (iout_up * state_up) + (iout_up * state_dn); end end module 102 Simulations for process corners Verilog-A Model of Storage Cell module tuning (fast,slow,left,right,b,a); input input input input fast; voltage fast; slow; voltage slow; left; voltage left; right; voltage right; inout b; electrical b; inout a; electrical a; parameter real ifast = 17u; parameter real islow = 17u; parameter real vh =1.5; parameter real vl = 0; parameter real vth = 0.75; integer state_up,state_dn; analog begin @(cross(V(fast)-vth, state_up = 1; @(cross(V(fast)-vth, state_up = 0; @(cross(V(slow)-vth, state_dn = -1; @(cross(V(slow)-vth, state_dn = 0; 1)) -1)) 1)) -1)) I(b) <+ (ifast * state_up) + (ifast * state_dn); if(V(b)>1.5) I(b) <+ 0; if((V(left)>0.75) && (V(right)>0.75)) V(b) <+ vl; else if((V(left)<0.75) && (V(right)<0.75)) V(b) <+ vh; else if(V(left)<0.75 && V(right)>0.75 && V(left)>0.75 && V(right)<0.7 I(b) <+ 0; 103 if(V(b)<=0.75) V(a) <+ vh; else V(a) <+ vl; end endmodule 104 Simulations for process corners Simulation Results 2. The following figures shows the bandwidth test for the PLL operating at 1 GHz reference modulated at 50 MHz, 100 MHz, and 333 MHz in the mixed signal simulation. Figure C.1. 1 GHz reference modulated at 50 MHz in mixed simulation 105 Figure C.2. 1 GHz reference modulated at 100 MHz in mixed simulation Figure C.3. 1 GHz reference modulated at 33 MHz in mixed simulation 106 Simulations for process corners 3. The following figures shows the VCO pole frequency measuring graphs due to storage cells. The poles due to the control voltage from the storage cells is measured by modulating the respective cell at 10 MHz, 200 MHz, and 300 MHz. Figure C.4. B < 13 >, modulated at 10 MHz for pole measurement 107 Figure C.5. B < 13 >, modulated at 200 MHz for pole measurement Figure C.6. B < 13 >, modulated at 300 MHz for pole measurement 108 Simulations for process corners 4. The following figures shows the VCO pole frequency measuring graphs due to the proportional voltage. The poles due to the control voltage from the charge pump is measured by modulating the proportional voltage at 5 MHz, 200 MHz, and 300 MHz. Figure C.7. Prop, modulated at 5 MHz for pole measurement 109 Figure C.8. Prop, modulated at 200 MHz for pole measurement Figure C.9. Prop, modulated at 300 MHz for pole measurement 110 Simulations for process corners 5. The following figures shows the parameter measuring graphs for the PLL operating at 100 MHz in the nominal process. Figure C.10. dt measurement for PLL operating at 100 MHz in nominal process Figure C.11. Kp and Ko measurement for PLL operating at 100 MHz in nominal process 111 6. The following figures shows the parameter measuring graphs for the PLL operating at 1 GHz in the nominal process. Figure C.12. dt measurement for PLL operating at 1 GHz in nominal process Figure C.13. Kp and Ko measurement for PLL operating at 1 GHz in nominal process 112 Simulations for process corners 7. The following figures shows the parameter measuring graphs for the PLL operating at 500 MHz in the nominal process. Figure C.14. dt measurement for PLL operating at 500 MHz in nominal process Figure C.15. Kp and Ko measurement for PLL operating at 500 MHz in nominal process 113 8. The following figures shows the parameter measuring graphs for the PLL operating at 300 MHz in the nominal process. Figure C.16. dt measurement for PLL operating at 300 MHz in nominal process Figure C.17. Kp and Ko measurement for PLL operating at 300 MHz in nominal process 114 Simulations for process corners 9. The following figures shows the parameter measuring graphs for the PLL operating at 200 MHz in the nominal process. Figure C.18. dt measurement for PLL operating at 200 MHz in nominal process Figure C.19. Kp and Ko measurement for PLL operating at 100 MHz in nominal process 115 10. The following figures shows the mathematical modelling of the PLL operating at 200 MHz, 300 MHz and 500 MHz in the nominal process. Figure C.20. Mathematical modelling of PLL operating at 200 MHz in nominal process 116 Simulations for process corners Figure C.21. Mathematical modelling of PLL at operating 300 MHz in nominal process 117 Figure C.22. Mathematical odelling of PLL at operating 500 MHz in nominal process 118 Simulations for process corners 11. The following figures shows the bandwidth test for the PLL operating at 200 MHz, 300 MHz and 500 MHz modulated at 1/10th and 1/4th of the operating frequency in the nominal process. Figure C.23. 200 MHz reference modulated at 20 MHz and 50 MHz in nominal process Figure C.24. 300 MHz reference modulated at 30 MHz and 75 MHz in nominal process 119 Figure C.25. 500 MHz reference modulated at 50 MHz and 125 MHz in nominal process 120 Simulations for process corners 12. The following figures shows the mathematical modelling of the PLL operating at 200 MHz and 300 MHz in the weak process. Figure C.26. Mathematical modelling of PLL operating at 200 MHz in weak process 121 Figure C.27. Mathematical modelling of PLL operating at 300 MHz in weak process 122 Simulations for process corners 13. The following figures shows the mathematical modelling of the PLL operating at 300 MHz and 500 MHz in the strong process. Figure C.28. Mathematical modelling of PLL operating at 300 MHz in strong process 123 Figure C.29. Mathematical modelling of PLL operating at 500 MHz in strong process

Institutionen För Systemteknik Department Of Electrical Engineering Low Power And Area Efficient

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