Institutionen För Systemteknik Department Of Electrical Engineering Examensarbete

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Institutionen för systemteknik Department of Electrical Engineering Examensarbete Designing a Low Power Regulator for Smart Dust Examensarbete utfört i ämnet Elektroniksystem vid Tekniska högskolan vid Linköpings universitet av Mohamed Lababidi LiTH-ISY-EX--12/4643--SE Linköping 2011 Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Linköpings tekniska högskola Linköpings universitet 581 83 Linköping Designing a Low Power Regulator for Smart Dust Examensarbete utfört i ämnet Elektroniksystem vid Tekniska högskolan i Linköping av Mohamed Lababidi LiTH-ISY-EX--12/4643--SE Handledare: Joakim Alvbrant isy, Linköpings universitet Examinator: Dr. J Jacob Wikner isy, Linköpings universitet Linköping, 19 September, 2011 Avdelning, Institution Division, Department Datum Date Division of Electronics Systems Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden Språk Language Rapporttyp Report category ISBN  Svenska/Swedish  Licentiatavhandling ISRN  Engelska/English    Examensarbete  C-uppsats  D-uppsats   Övrig rapport 2011-09-19 — LiTH-ISY-EX--12/4643--SE Serietitel och serienummer ISSN Title of series, numbering —  URL för elektronisk version http://www.es.isy.liu.se/ http://www.ep.liu.se Titel Title Designa en Låg Effekt Regulator för Smart Dust Designing a Low Power Regulator for Smart Dust Författare Mohamed Lababidi Author Sammanfattning Abstract The revolutionary progress that happened recently in the micro-electro mechanical systems (MEMS) field and the complementary metal-oxide-semiconductor (CMOS) integrated circuits has made it possible to produce low-cost, low-power and small size processing circuits. Utilizing wireless communication theory allows those circuits to send their data over a network. This wireless sensor network is known as "Smart Dust". Each wireless sensor node in the network is indicated as "mote". It consists of several components: sensors, micro-processors, radio transceivers and a power management unit. The power management unit can be divided into several parts including battery, power control and regulator. The purpose of the regulator is to supply a constant reliable voltage to the other parts in the mote as most of the devices have voltage limits that need to be considered to guarantee producing a robust long-life mote. In this thesis designing a low-power regulator is investigated. The goal of the thesis is to design a regulator that can handle the high-voltage acquired from an energy harvest unit using only 65-nm core transistors. This allows an easier production process that results in a low-cost fully-integrated chip. The regulator architecture to be used is a simple linear regulator. The report highlights the theoretical background, the challenges of the analog design and presents the results of the simulation that were ran using cadence design system software on schematic level. Nyckelord Keywords communication, electronics, smartdust, regulator, low power, 65-nm Abstract The revolutionary progress that happened recently in the micro-electro mechanical systems (MEMS) field and the complementary metal-oxide-semiconductor (CMOS) integrated circuits has made it possible to produce low-cost, low-power and small size processing circuits. Utilizing wireless communication theory allows those circuits to send their data over a network. This wireless sensor network is known as "Smart Dust". Each wireless sensor node in the network is indicated as "mote". It consists of several components: sensors, micro-processors, radio transceivers and a power management unit. The power management unit can be divided into several parts including battery, power control and regulator. The purpose of the regulator is to supply a constant reliable voltage to the other parts in the mote as most of the devices have voltage limits that need to be considered to guarantee producing a robust long-life mote. In this thesis designing a low-power regulator is investigated. The goal of the thesis is to design a regulator that can handle the high-voltage acquired from an energy harvest unit using only 65-nm core transistors. This allows an easier production process that results in a low-cost fully-integrated chip. The regulator architecture to be used is a simple linear regulator. The report highlights the theoretical background, the challenges of the analog design and presents the results of the simulation that were ran using cadence design system software on schematic level. v Acknowledgments I would like to thank God that I was fortunate enough to have the opportunity to study this master program at Linköping University. A lot of people in different parts of the world are not able to do that because of their bad circumstances. So I am, as always, very grateful. Then I would like to thank My parents: My father who did everything he could, on both economical and motivational sides, to make me study this master program and finish my thesis work, and my mother who kept pushing me forward, even during the hardest times, towards reaching my goals and dreams. A big thanks to My examiner Dr.Jacob Wikner, who also suggested me this challenging topic, for his unconditional support and incredible patience during this thesis work. I could not ask for any better mentoring. I have certainly learned a lot during this thesis work and I am very thankful to you Jacob for all the support you have provided. My supervisor Joakim Alvbrant who answered all my questions regarding the analog design, thanks a lot Joakim. Many thanks to PhD student Ekhiotz Vergara who helped me a lot to improve my thesis report. Also Markus Keller who gave me a great feedback through his opposition, Blerina Hasa and Hani Kamal who put an effort to help me fixing the mistakes in the report. My siblings, friends and lab mates who are all part of my success in one way or another. I thank you all and wish you the best in the bright future ahead of you. I will do my best to support or help you whenever I am needed. Finally, I hope that this report will add some knowledge to the readers and will help students who are doing their thesis in the analog design to complete their work or report in a good way. vii Contents 1 Introduction 1.1 Smart Dust . . . . . . . . . . . . . . . . . . . . . 1.1.1 What is Smart Dust? . . . . . . . . . . . 1.1.2 A Brief History . . . . . . . . . . . . . . . 1.1.3 Smart Dust at Linköping University (LiU) 1.2 Thesis Scope . . . . . . . . . . . . . . . . . . . . 1.3 Thesis Outline . . . . . . . . . . . . . . . . . . . 1.3.1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 6 8 9 9 2 Introduction to Regulators 2.1 What is a Regulator? . . . . 2.2 Regulator Types . . . . . . 2.2.1 Switching Regulators 2.2.2 Linear Regulators . 2.3 Selecting the Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 14 16 19 3 Theory Background for Analog Design 3.1 Modeling the Short Channel MOSFET . . . . . . . . . . 3.2 Core Transistors and I/O Transistors . . . . . . . . . . . 3.3 Operational Amplifier . . . . . . . . . . . . . . . . . . . 3.3.1 Two-Stage Operational Amplifier . . . . . . . . . 3.3.2 Cascode Operational Amplifier . . . . . . . . . . 3.3.3 Folded-Cascode Operational Amplifier . . . . . . 3.3.4 Current-Mirror Operational Amplifier . . . . . . 3.3.5 Operational Transconductance Amplifier (OTA) 3.3.6 Selecting a suitable Operational Amplifier . . . . 3.4 Current Mirrors Techniques . . . . . . . . . . . . . . . . 3.4.1 Basic Current Mirrors . . . . . . . . . . . . . . . 3.4.2 Cascode Current Mirrors . . . . . . . . . . . . . 3.4.3 Wide-Swing Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 22 26 27 27 27 30 31 33 34 34 34 37 4 Designing the Regulator 4.1 The Resistors Ladder and the Transmission Gates . . . . . . . . . 4.2 Designing the OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Cascading the OTA . . . . . . . . . . . . . . . . . . . . . . 41 43 45 47 . . . . . . . . . . . . . . . ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x Contents 4.3 4.4 4.5 The Pass Transistor . . . . . . . . . . . . 4.3.1 Biasing the Cascoding Transistors The OTA Test-Bench . . . . . . . . . . . The Regulator Test-Bench . . . . . . . . . 5 Simulation Results 5.1 Voltage Drop Simulations . . . . . 5.2 DC Load Simulations . . . . . . . 5.3 AC Load Simulations . . . . . . . . 5.4 Transient Response Simulations . . 5.5 Temperature Changes Simulations 5.6 Ctrl-bit Settings Simulations . . . 5.6.1 0.5 V Output . . . . . . . . 5.6.2 0.6 V Output . . . . . . . . 5.6.3 0.7 V Output . . . . . . . . 5.6.4 0.8 V Output . . . . . . . . 5.7 Sleep Mode Simulations . . . . . . 5.8 Power Down Simulations . . . . . . 5.9 Corner Analyze Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 51 52 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 55 57 60 64 67 70 70 72 73 74 76 78 79 6 Conclusion 85 7 Future Work 87 Bibliography 89 A Permission of using the photo of the Mica mote 91 List of Figures 1.1 1.2 2.1 2.2 2.3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 5.4 5.5 5.6 The Mica mote combines sensing, power, computation, and communication into one package using off-the-shelf components. . . . . Outline of smart dust model. . . . . . . . . . . . . . . . . . . . . . 7 8 Single-ended PWM DC-DC converters. . . . . . . . . . . . . . . . . 15 Basic circuits of linear voltage regulators (a) Series voltage regulator (b) Shunt voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 17 The selected voltage regulator architecture for the smart dust mote. 19 A two-stage operational amplifier circuit. . . . . . . . . . . . . . . A cascode (telescopic) operational amplifier circuit. . . . . . . . . . A folded-cascode operational amplifier circuit. . . . . . . . . . . . . A current-mirror operational amplifier circuit. . . . . . . . . . . . . A simple current-mirror operational transconductance amplifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A cascode current-mirror operational transconductance amplifier circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) A simple current-mirror. (b) A small-signal model of the currentmirror circuit shown in (a). . . . . . . . . . . . . . . . . . . . . . . A cascode current-mirror circuit. . . . . . . . . . . . . . . . . . . . A wide-swing current-mirror circuit. . . . . . . . . . . . . . . . . . 28 29 30 31 The voltage regulator circuit. . . . . . . . . . . . . . . . (a) The resistor ladder for several output values. (b) The sion gate placing in the regulator circuit. . . . . . . . . . The transmission gate circuit. . . . . . . . . . . . . . . . A simple current-mirror PMOS-input circuit. . . . . . . A circuit to increase the input level. . . . . . . . . . . . The cascoded bias current circuit of the OTA. . . . . . . The final circuit of the cascoded OTA. . . . . . . . . . . The test bench circuit of the OTA. . . . . . . . . . . . . The test bench circuit of the regulator. . . . . . . . . . . 42 . . . . . . transmis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The voltage drops on all the transistors of the OTA when the maximum current is pulled by the load. . . . . . . . . . . . . . . . . . . The voltage drops on all the transistors of the OTA when there is no current pulled by the load. . . . . . . . . . . . . . . . . . . . . . The output error for all unregulated voltage values and maximum DC load current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output error variation against DC load current for 1.8 to 2.1 V unregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . The output error variation against DC load current for 2.2 to 2.5 V unregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . The output error variation against DC load current for 2.6 to 2.9 V unregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 33 35 36 38 44 45 46 47 49 50 52 53 56 56 57 58 58 59 2 Contents 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25 5.26 5.27 5.28 5.29 5.30 The output error variation against DC load current for 3 to 3.3 V unregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . The output error variation against DC load current for 3.4 to 3.6 V unregulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . The AC current load on the regulator output. . . . . . . . . . . . . The output error for all unregulated voltage values and AC current load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output voltage for 1.8 V unregulated voltage and AC current load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output voltage for 2.7 V unregulated voltage and AC current load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output voltage for 3.3 V unregulated voltage and AC current load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The output voltage for 3.6 V unregulated voltage and AC current load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The vpwl signal used to cause load transient. . . . . . . . . . . . . The output voltage load transient response for 1.9 V, load changes from half-load to full-load. . . . . . . . . . . . . . . . . . . . . . . . The output voltage load transient response for 3.3 V, load changes from half-load to full-load. . . . . . . . . . . . . . . . . . . . . . . . The output voltage load transient response for 1.9 V, load changes from half-load to no-load. . . . . . . . . . . . . . . . . . . . . . . . The output voltage load transient response for 3.3 V, load changes from half-load to no-load. . . . . . . . . . . . . . . . . . . . . . . . The output error for temperatures between -20-70 C and input voltages between 1.8-3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . The output error for temperatures between -20-70 C and DC-load between 0-50 uA ,1.8 V input voltage. . . . . . . . . . . . . . . . . The output error for temperatures between -20-70 C and DC-load between 0-50 uA, 2.7 V input voltage. . . . . . . . . . . . . . . . . The output error for temperatures between -20-70 C and DC-load between 0-50 uA, 3.6 V input voltage. . . . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.6 V and full DC load, 0.5 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . The output error for input voltages between 1.8-3 V and DC-load between 0-50 uA, 0.5 V regulated voltage. . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.6 V and full DCload, 0.6 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.2 V and DC-load between 0-50 uA, 0.6 V regulated voltage. . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.6 V and full DCload, 0.7 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.3 V and DC-load between 0-50 uA, 0.7 V regulated voltage. . . . . . . . . . . . . . . The output error for input voltages between 1.8-3.6 V and full DCload, 0.8 V regulated voltage. . . . . . . . . . . . . . . . . . . . . . 59 60 61 61 62 62 63 63 64 65 65 66 66 68 69 69 70 71 71 72 72 73 73 74 Contents 5.31 The output error for input voltages between 1.8-2.1 V and DC-load between 0-50 uA, 0.8 V regulated voltage. . . . . . . . . . . . . . . 5.32 The output error for input voltages between 2.1-3.4 V and DC-load between 0-50 uA, 0.8 V regulated voltage. . . . . . . . . . . . . . . 5.33 The current consumption for the regulator when Ctrl equals VDD. 5.34 The current consumption for the regulator in sleep mode. . . . . . 5.35 The output voltage versus time during periodic VDD change every 10µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.36 The output voltage versus time during VDD change with period of 200µs and a pulse width of 1µs. . . . . . . . . . . . . . . . . . . . . 5.37 The output error for full DC load in corner analyze typical case. . 5.38 The output error for full DC load in corner analyze fast-fast-fast case. 5.39 The output error for full DC load in corner analyze slow-slow-slow case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.40 The output error for full DC load in corner analyze fast-slow-typical case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.41 The output error for full DC load in corner analyze slow-fast-typical case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.42 The output error for full DC load in corner analyze fast-slow-slow case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.43 The output error for full DC load in corner analyze slow-fast-slow case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.44 The output error for full DC load in corner analyze fast-slow-fast case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.45 The output error for full DC load in corner analyze slow-fast-fast case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 75 75 77 77 78 79 80 80 81 81 81 82 82 82 83 List of Tables 1.1 Requirement specifications of the regulator. . . . . . . . . . . . . . 11 2.1 Comparison between switching and linear regulators features and the requirements and preferences for the smart dust project. . . . . 20 3.1 The tolerable voltages regarding the affecting lifetime mechanisms for a typical 65-nm CMOS technology. . . . . . . . . . . . . . . . . 25 5.1 The DC-load range where the regulator supplies a regulated output for different input voltages. . . . . . . . . . . . . . . . . . . . . . . A summary of the transient response simulation results. . . . . . . The maximum input voltage versus the output voltage for which the regulator is still able to provide a good output regulated voltage. The corner cases and the respective input voltage range for which the regulator is still able to provide a good output regulated voltage. 5.2 5.3 5.4 60 67 76 83 4 Contents 6.1 The simulation type and the respective input voltage range for which the regulator is still able to provide a good output regulated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter 1 Introduction The revolutionary improvements in the Micro Electro Mechanical Systems (MEMS) field, which have recently evolved following Moore’s Law, have pushed the industry towards producing microsensors that consume less power and cost less [1]. Furthermore Moore’s law has continued to correctly estimate the improvements in the complementary metal-oxide-semiconductor (CMOS) integrated circuits, leading to the possibility of producing 'tiny' low-cost processing circuits. Combining the former two technologies with the wireless communication theory allows for producing a low-cost, low-power and a small size chip that can sense, compute and send data over a network. This wireless sensor network is usually referred to as Smart Dust [2]. 1.1 1.1.1 Smart Dust What is Smart Dust? The Smart Dust term is used to refer to a broad range of tiny hardware that forms a wireless sensors network. Those wireless sensor nodes, also called motes, are spread around a large area and can communicate with each other in an ad-hoc network. Each dust mote is made up mainly from one or more sensors, a data processing unit, a transceiver for communicating with other motes in the network, and a power supply [2]. 1.1.2 A Brief History In 1992 the idea of Smart Dust was visualized as a future technology by Kris Pister during a workshop at RAND Corporation. Two years later, he found out that it could be implemented sooner than he had thought. Therefore, he continued his research and started publishing papers to present that technology [3]. The idea was to create tiny wireless sensors that are distributed randomly over a big area to make a network that acts as one intelligent system. 5 6 Introduction Those sensor nodes have got the ability to sense sound, light, temperature, moisture, vibrations or chemicals, and then send the information to a distanced main unit. A typical application for the Smart Dust is in the military, where the motes could be spread in the desert sands and be used to detect the sound of a passing tank or the metal of the weapons of passing soldiers. Once the sensors detect a signal they send an alarm and they can be even used to track the enemy’s movements. With such possible applications, Smart Dust attracted the US Defense Advanced Research Projects Agency (DARPA) to support Pister’s research. DARPA’s support has helped Pister to implement the first Smart Dust hardware in 1998. The third-generation hardware, known as the Rene mote, was developed in 2001 by the Pister’s lab. The mote had the size of a matchbox and the battery set was a few times bigger. But the battery voltage affected the mote’s performance in a direct way. Overall, the Rene motes did not function with high credibility. Meanwhile, there were efforts to move further on the software side. At Berekley, a software engineer named David Culler was working on building a bare-bones operating system flexible for implementation in many different electronics. Jason Hill, a smart dust software consultant, combined the two projects together by editing the circuit design of the mote and embedding the operating system, named TinyOS. Hill’s efforts’ outcome was called the Mica mote. The operating system (OS) preserved power by controlling the hardware to execute only vital operations. Thanks to those improvements the Mica mote needed just a couple of AA batteries to function, which made the whole device’s size equivalent to the new pagers size [2]. Figure 1.1 shows the Mica mote. Mica was selected by the defense agency for the Network Embedded Systems Technology (NEST) project, making the mote an interest for a lot of labs, and with corporation between Berkeley and Crossbow Technology the motes have been commercialized within affordable prices. The success that Mica showed in the first few months of NEST encouraged Hill and Pister to bring this new technology to the market, as a result "Dust, Inc" was established by Hill and Pister in 2002. Being financially supported helped developing a smaller mote. The mote was named Spec, and it was the first mote to implement radio frequency communication with adopted circuits running on TinyOS. The size of the mote was roughly equal to the size of a piece of glitter. Spec being much smaller than Mica indicates that Smart Dust has the potential to reach the size of the real dust, however this is related to the evolution of battery technology [3]. 1.1.3 Smart Dust at Linköping University (LiU) As mentioned at the beginning of chapter 1, the revolutionary progress in CMOS and MEMS manufacturing joined by the motivation to produce costless longlife units are pushing the evolution of system on chip (SoC) solutions towards 1.1 Smart Dust 7 Figure 1.1. The Mica mote combines sensing, power, computation, and communication into one package using off-the-shelf components [2]. producing motes within cubic centimeter scale and fewer off-chip components. Here, at the division of Electronics systems, Department of Electrical Engineering at Linköping University, a recent Smart Dust research has been launched under the supervision of Dr. Jacob Wikner and the contribution of researchers, Phd students and Master Students. The aim of the project is mainly to achieve an extreme low power consumption and to digitize the components in order to achieve a better performance. The project gives the chance for the master students to work in an industrial fashion, where each student is responsible for building a particular block while working along with other students and researchers to complete the whole project. The outline of the mote is illustrated in Figure 1.2. Different blocks shown in the figure can be briefly presented as the following: The sensor can vary depending on the application that the mote is intended to be used for, it can be a microphone, thermometer, smoke sensor, etc. For some applications, there could be more than one sensor. The transceiver is used for communication with the other motes in the network. The energy harvest, energy storage, supply regulator and control unit blocks shown in figure 1.2 represent the mote’s power supply system. The energy harvest block can acquire energy from the surrounding environment. The energy storage block is usually a battery that is responsible for maintaining the energy. The regulator block is responsible for supplying suitable voltages required for different blocks in the mote. The control block is responsible for administrating the available power in an efficient way. The micro processor unit’s main responsibility 8 Introduction Figure 1.2. Outline of smart dust model. is to manage the data between the transceiver and the sensors. Producing motes with long lifetimes is demanded for most applications of the smart dust. Even though harvesting energy from the surrounding environment increases the mote’s life time, since energy is not limited, a battery unit might still be needed for maintaining the harvested energy. Batteries can usually live in the range of one to ten years, which indicates that the power dissipation of a mote, sized within an inch range, must be in the order of tens to hundreds of microwatts on average per day, according to typical batteries’ capacity. 1.2 Thesis Scope The demand for higher level of integration, low cost and high speed are dragging CMOS technology towards the dimension of 65nm and less. In order to guarantee a good performance of these 65nm devices, the supply voltage should be less than 1 V. However, the drawback of such a low supply voltage is that it increases the power consumption of many analog devices [4]. In CMOS circuits the power dissipation is proportional to the minimum feature size. Therefore using only core transistors in the regulator circuit while supplying high voltages will result in an extreme low power consumption. However, applying high voltages on core transistors posses a big challenge since it shortens the devices’ 1.3 Thesis Outline 9 lifetime. The scope of this thesis is investigating a method to apply voltages higher than the nominal supply voltage of 65-nm devices while keeping the lifetime unaffected. In particular, this thesis studies the feasibility of designing a regulator with 65-nm core transistors that has an input voltage much higher than the nominal supply of core transistors. 1.3 Thesis Outline In this thesis a regulator is designed, which supplies a regulated voltage to the digital and analog parts of the mote. The regulator is required to consume low power. Moreover, it is requested to be built using 65-nm core transistors only. The report, which covers work that has been done in this thesis, is divided into the following chapters: • Chapter 1 introduces the reader to the smart dust project and the work that needed to be done in this thesis. • Chapter 2 includes a brief introduction of some regulator types, such as linear regulators and switched regulators. The advantages and disadvantages of those regulator types are shown. The chapter ends with a discussion about choosing a suitable architecture for the project. • Chapter 3 presents some theoretical background about analog design and the challenges for analog designers in low voltage devices. • Chapter 4 explains the regulator design of this project and the problems that have been faced to meet the requirements in the design. • Chapter 5 shows the simulation results that have been executed on a schematic level of the designed regulator circuit. • Chapter 6 concludes the work that has been done during this thesis, based on the achieved results. • Chapter 7 presents some of the future work to be done towards the production of the mote’s chip. 1.3.1 Specifications The requirement specifications for the regulator design are shown in table 1.1. The input voltage represents the unregulated supply voltage. Achieving a 5µA current consumption is targeted for active mode, while the current consumption should reach a minimum value during sleep mode. The regulated output voltage can be tuned to one of the voltage levels shown in the table. The load current 1 is assumed to be a Direct Current (DC) current for the analog parts in the mote while load current 2 is assumed for the digital parts in the mote. The current consumed by the digital parts is pulse Alternative Current (AC) current. The 10 Introduction response time of the regulator to changes in the load should not exceed 10µs. The operating temperature is ranging between -20 and 70 C. The area and the bias currents are decided at later stages in the design. However, minimal values are targeted. Finally, the technology used is STM 65-nm core devices. The usage of core devices in combination with the requirements for the input voltage range poses the greatest challenge for the design. 1.3 Thesis Outline 11 Item Unit Min Type Max Input Voltage V 1.8 2.7 3.6 Current Consumption Amp 0µ Output Voltage level 1 V 0.85 0.9 0.95 Output Voltage level 2 V 0.75 0.8 0.85 Output Voltage level 3 V 0.65 0.7 0.75 Output Voltage level 4 V 0.55 0.6 0.65 Output Voltage level 5 V 0.45 0.5 0.55 Load Current 1 Amp 0µ 50µ Load Current 2 Amp 0µ 100µ Transient Response Sec 5µ 10µ SleepMode Yes Temp C -20 70 Process nm 65 Area mm TBD Bias Currents Amp TBD Table 1.1. Requirement specifications of the regulator. Chapter 2 Introduction to Regulators As we are heading towards nano meter scales in size and GHz frequency ranges in operating frequencies used, the problems of obtaining reliable power sources are becoming more significant. Supplying a clean power in the integrated circuits became more challenging with the frequency increment and the rise of using mixed-signal systems. Inefficient management of power leads to poor chip performance, larger area utilization and causes the design to function improperly. For this reason, managing the power consumption is vital since it has an important effect on the Integrated Circuit’ (IC) performance. Most of the computing systems contain voltage regulators which are necessary to hand over the power from the source to several integrated circuits. They can handle either constant or time-varing voltage levels. The regulator is responsible for supplying a constant proper voltage level to the electronic components which enables them to function properly. In addition, the regulator should be able to control power fluctuations and protect loads connected to the supply from damage [5]. 2.1 What is a Regulator? Generally, a voltage regulator is a circuit that provides a constant voltage supply for the electrical or the electronic devices that are connected to it. The regulator circuit is used in order to protect those devices from damage due to voltage changes, since most of the devices have voltage limits. It is one of the main power supply blocks for every electronic or electrical device. Furthermore, regulators can be used to supply voltages to the connected devices that are within the operating ranges of those devices. Usually electronic devices work in low voltages, and providing a voltage higher than the maximum acceptable voltage causes a damage in the device. On the other hand, providing a very low voltage can cause the device to disfunction or work inappropriately. Therefore we need to guarantee an acceptable voltage sup13 14 Introduction to Regulators ply range for the device, and the purpose of the regulators is to supply a voltage within that range. In most of the cases, the regulators down-convert the voltage from a higher voltage to a lower one [6]. Since the regulator is designed to keep the output voltage constant in spite of changes in the input voltage or the load current, the regulator’s performance is often specified with the following parameters [7]: Dynamic load response time is the time slot needed for the regulator to set the output voltage withing the acceptable range when there is a step change in the load current [8]. Line regulation is indicating how much the output voltage changes when the input voltage changes, in percentage [8]. LineReg = Vo,(hi,in) − Vo,(lo,in) · 100(%) Vo,(nom,in) (2.1) Load regulation is indicating, in percentage, how much the output voltage changes when the load current changes from the no load current to full load current condition [8]. LoadReg = Vo(no−load) − Vo(f ull−load) · 100(%) Vo(f ull−load) (2.2) Overall efficiency is the percentage of the output power to the input power ratio, and it helps specifying the heat produced in the regulator [8]. ef f ic. = 2.2 Pout · 100(%) Pin (2.3) Regulator Types There are plenty of voltage regulators types, but the most common ones for implementing on-chip are linear and switching regulators. Each of those types has its advantages and disadvantages depending on the design of the IC [5]. Linear and switching regulators are also divided into different categories. The main two categories of linear regulators are shunt regulators and series regulators, while the main switching regulator types are Pulse-Width Modulated (PWM), resonant regulators and switched-capacitor regulators. 2.2.1 Switching Regulators Also known as DC-DC converters, the switching-mode regulators employ transistors as switches. The voltage drop across the transistors and the conducted current are inversely proportional which enables this regulators type to offer low conduction losses and a high efficieny. However the conduction losses increase by 2.2 Regulator Types 15 increasing the switching frequency which leads to less efficiency. The pulse-width modulated regulators are very popular between the switching regulators. Figure 2.1 shows some of the common topologies of single-ended PWM switching regulators. Figure 2.1. Single-ended PWM DC-DC converters. The switching regulators function with a method that can be explained in a simplified way. As mentioned before, the power transistors of the PWM switching regulators are working as switches, i.e. saturation and cutoff regions. The voltampere product in the power transistors is low during these states (low voltage and high current in saturation mode and high voltage no current in cutoff mode). The volt-ampere product in the power transistors represents the loss in the power device (the regulator). The highly efficient functioning of the switching regulators is obtained by cutting the DC input voltage into pulses. The magnitude of the input voltage decides the amplitude of the pulse while the regulator controller part is controlling the duty cycle of the pulse. By transforming the input voltage to an AC rectangular waveform, several operations can be performed to get the desired output voltage. Stepping the input voltage up or down is done by changing the amplitude of the pulse using a transformer, also by adding secondaries to the transformer several output voltages can be obtained. Eventually, the DC output voltages are derived by filtering the AC waveforms. Similar to the linear regulator controller, the switching regulator controller is re- 16 Introduction to Regulators sponsible for keeping a regulated output voltage. This means that the functional blocks, voltage reference and error amplifier are staged in the same way of the linear regulators. However, in the switching regulators a voltage-to-pulsewidth converter stage is following the error amplifier, whereas in the linear regulators the output voltage of the error amplifier (the error voltage) is driving the power transistors. The main functional types of switching regulators are the forwardmode converter and the boost-mode converter, each has its advantages depending on the applications to be used [8]. Advantages and Disadvantages The switching regulators contain a low loss inductor which provides more efficient power conversion, it also provides the regulator with the ability to transmit the energy from the input to the output and finally it filters the output from switching signals. In addition, the switching regulators has the ability to create several output voltages from one input voltage and to step up the voltage. The duty cycle of the switch decides the amount of charge transmitted to the load. However, as typical switching regulators work in low switching frequency ranges and contain filter components like inductors or capacitors, they are usually implemented off-chip. Hence problems like slow responses to the variations in the load current transients and parasitic components in the circuitry between the regulator and the load are introduced. Nevertheless, recently the focus was to implement on-chip switching regulators which provides faster response to voltage transitions but demands smaller size filter components and higher operating frequencies which affect the power conversion efficiency [5]. 2.2.2 Linear Regulators Linear regulators can be specified as shunt or series regulators, depending on where the control element (usually a transistor) is situated in the circuit [7]. Figure 2.2 shows two basic circuits of series linear regulator and shunt linear regulator. The general principle of the linear regulators is based on comparing a feedback signal with a reference voltage and amplifying the error signal. The output of the error voltage amplifier is controlling the current flow of the power transistor that controls the load. Linear regulators usually have got a higher input voltage magnitude than the output and a low output impedance [9]. Usually, the shunt regulators contain a small resistor that is placed in series between the load and the input voltage. The resistor value should be low enough to always allow enough current to the load. The control element is set in parallel with the load and maintains a constant voltage over the load [7]. The control element is mainly a transistor which maintains a constant output voltage by changing its current when the input voltage or the load current changes. The shunt transistor works like a variable resistor. Decreasing the output voltage causes the amplifier output voltage to decrease, which results in less conduction 2.2 Regulator Types 17 Figure 2.2. Basic circuits of linear voltage regulators (a) Series voltage regulator (b) Shunt voltage regulator. 18 Introduction to Regulators by the transistor, thus, increasing the resistance. As a consequence, more current will be directed to the load, resulting the load current and the output voltage to increase. For a constant input voltage the input current remains constant when there is a change in the load current. This means that the transistor current changes, causing the voltage drop on the shunt transistor to change in order to keep the output voltage fixed. Shunt regulators are immune to short-circuits, however they are less efficient than series regulators because of the losses in the series resistor and the shunt transistor. They have better line transient response than the series regulators but input overvoltage can damage the shunt voltage regulator [10]. In series regulators, the transistor is set in series with the load and the input voltage. A constant voltage over the load is maintained by controlling the current through the transistor. This is done by employing a feedback to compare the output voltage to a reference voltage using an amplifier which drives the transistor’s current [7]. The voltage drop on the pass transistor varies in a similar way as the input voltage does. Therefore the pass transistor is considered to act like a variable resistor. This variable resistor together with the load resistor form a voltage divider. A reduction in the input voltage causes a decrement in the variable resistance which in turn causes an increment in the output voltage, and vice versa. The amplifier should work in the linear region in order to control the circuit correctly, if the input voltage value gets very low the amplifier will be in saturation and the series regulator will not operate correctly. The deviation between the lowest input voltage value, for which the regulator stops to work for lower values Vi,min , and the regulated output voltage Vo is called the drop-out voltage Vdo = Vi,min − Vo . The drop-out voltage value can be very low, in that case the regulator is called low drop-out (LDO) voltage regulator, generally the utilized pass transistor is NMOS or pnp bipolar transistor for LDO regulators [10]. Advantages and Disadvantages The linear regulators are easier to implement on-chip, have smaller size and cost less than switching regulators. In addition, they provide a good response to the changes in load current and offer a low noise clean output. Hence, they are more appropriate for designs that demand fast input-output reaction and output with low noise. One of the disadvantages of using linear regulators is the low efficient power . In conversion which decreases, in a linear proportional way, with the ratio VVout in addition, the linear regulators cannot create several output voltages and cannot up-convert the voltage [5]. 2.3 Selecting the Architecture 2.3 19 Selecting the Architecture Selecting the architecture is usually based on the specifications and the requirements needed. Comparing the advantages and the disadvantages of different topologies helps choosing a suitable architecture. Regarding this project, table 2.1 shows the features of switching and linear regulators in comparism with the requirements or preferences for the smart dust project. Considering the main challenge in this thesis, which is how to deal with high voltages using 65-nm core transistors, makes circuits of simpler architecture highly desirable. A look back on the table shows that linear regulators are more suitable for this project. To avoid shunt regulators faults mentioned in 2.2.2 the series voltage regulator shown in figure 2.3 is used. Figure 2.3. The selected voltage regulator architecture for the smart dust mote. 20 Introduction to Regulators Linear Regulators Switching tors Regula- The Requirements and preferences for this project smaller size and cost, easier to implement on-chip usually need some offchip components and more complicated architecture the regulator is going to be implemented in a mote which makes the fully on-chip implementation preferable fast transient response slower transient sponse re- fast transient response is preferred cannot step up the input voltage able to step up voltages stepping up voltages is not needed low efficiency more efficient power conversion since the energy will be harvested from the surrounding environment power loss is not the main concern rather than supplying a regulated desired voltage level low-noise output contains filter components which produce noise low-noise output supply is preferred since there are digital and analog components cannot create several output voltages several output voltages can be created from one input voltage several output voltages at the same time are not required. However, the output voltage level is programmable and can be changed Table 2.1. Comparison between switching and linear regulators features and the requirements and preferences for the smart dust project. Chapter 3 Theory Background for Analog Design During this chapter, major aspects of the analog design in general, and the regulator in particular, are discussed. The short channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) model, the difference between I/O and core transistors and the main lifetime affecting mechanisms are explained. Furthermore several operational amplifiers are discussed towards choosing the most suitable amplifier architecture for the regulator. Finally, useful current mirror topologies and other operating condition issues are shown. 3.1 Modeling the Short Channel MOSFET Recently, the new CMOS transistors process has a minimum length much smaller than 1µm, more specifically, in the nano-meter range. The square-law currentvoltage relation which was based on the gradual channel approximation can not hold for short channel devices, since it can not be assumed anymore that the electric field under the gate oxide is one dimensional. Also, the potential of the carriers that are moving between the channel and the drain could reach saturation, causing an effect called carrier velocity saturation νsat , where the velocity of the carriers refrain from incrementing with the increment of the applied electric field. The electron mobility µn is the electron drift velocity divided by the applied electric field [11] ν µn = (3.1) E The current-voltage relation becomes in the saturation region of short channel devices as the following: 0 ID = W · νsat · Cox (VGS − VT HN − VDS,sat ) (3.2) Taking into consideration that, for high electric fields, the mobility can be written as: µn = νsat E and V (L) = VDS,sat when the MOSFET is in the saturation region. 21 22 Theory Background for Analog Design It is also worth mentioning that VDS,sat for long-channel transistors can be found using the equation VDS,sat = VGS − VT HN while this equation does not hold for short channel MOSFET transistors. VDS,sat for short channel devices is the drain-source voltage drop VDS when the transistor is in the saturation region and VGS − VT HN is denoted as the gate overdrive voltage Vovn . Vovn = VGS − VT HN 6= VDS,sat (3.3) From equation 3.2 it can be seen that the drain current is linearly proportional to the gate-source voltage VGS for short channel transistors working in the saturation region. While for long-channel MOSFET transistors it is known that the drain current is proportional to the square of VGS . Equation 3.4 shows the drain current of long-channel transistors operating in the saturation region: ID,sat = K · Pn W · · (VGS − VT HN )2 2 L (3.4) Finally, another usable expression for the short channel MOSFET transistors is the drive current per width Ion or Idrive which is defined as: 0 Ion = Idrive = νsat · Cox (VGS − VT HN − VDS,sat ) . . . µA/µm (3.5) Even though the drive current for short channel devices can be approximated using the previous equations, it is usually measured [11]. 3.2 Core Transistors and I/O Transistors The evolution of CMOS technology yields smaller transistors that are faster and more economical in terms of area and power consumption. However, since transistors have scaled down to nanometer dimensions, decreasing the power supply has become essential in order to keep a reliable performance and a longer life time. With the consideration of lower cost and higher speed, a highly integrated system on chip is desired for most of the portable devices. Using 65-nm and 45-nm core transistors allows for more functions to be implemented in the unit area. The nominal power supply for 65-nm transistors is 1.2 V and it is reduced further for 45-nm transistors. For digital circuits, the lower power supply voltage reduces the power consumption according to the following formula: 2 P ∼ af CVDD ; a: activity factor, C: total node capacitance, f : operating frequency. For some analog circuits higher power supply reduces the power consumption [4]. In the smart dust project, the 65-nm core transistors are used to build the regulator, for which the unregulated power supply can range between 1.8 to 3.6 V. This posses a challenge on how to deal with voltage drops higher than the nominal supply voltage of the 65-nm transistors without affecting the lifetime [4]. Several solutions exist to overcome this issue: 3.2 Core Transistors and I/O Transistors 23 - One possible solution is to produce transistors that can tolerate high voltages through technological solutions such as multiple gate oxides. The main drawback of this solution is the cost, since more processing steps and masks are required. - Another solution is to use extended-drain transistors which does not require extra processing steps but affects the performance-per-area. - Finally, solutions to use only core transistors can be achieved through advanced circuit solutions, which limit the voltage drops on each transistor to tolerable values that guarantee adequate lifetime [12]. For MOS transistors, the lifetime is related to the strength of the electric field in the device. Transistors that have minimum length can work for at least the nominal lifetime when the nominal supply voltage is applied [12]. Restraining the electric field on transistors with low voltage tolerance is vital for the lifetime when they are used in circuits with high voltages. This is usually done by sacrificing more area. The most vital electric fields that affects the lifetime of the transistors are the vertical, the lateral and the electric fields across junctions. The representing mechanisms of those electric fields which affect the life-time are respectively: oxide breakdown, hot-carrier degradation and junction breakdown [12]. Oxide Breakdown: When applying an exaggerated electric field over the oxide, a decay of oxide happens as a consequence of the currents that flow across the oxide. When the capacity of charges exceeds a limit in a specific area of the oxide it will be destroyed, meaning that an oxide breakdown has happened. When the gate oxide is broken, the gate current will increase and the device becomes uncontrollable by the gate voltage. The oxide breakdown is also called Time Dependent Dielectric Breakdown (TDDB) [4]. The lifetime of the transistor is greatly affected by the oxide current that is generated by the electric field applied over the oxide. It has been shown that by limiting the electric field over the oxide to 5.5 MV/cm an adequate oxide lifetime could be achieved. This value usually means that the oxide voltage tolerated can be up to 20% higher than the nominal supply voltage of the process. The source-gate voltage Vsg is equal to the oxide voltage at the source. Similarly, the drain-gate voltage Vdg equals the oxide voltage at the drain side of the transistor. When the transistor is ON, the oxide voltage in the area between the drain and the source is between Vdg and Vsg . When the transistor is OFF a bulk-gate voltage is applied and partly divided across the gate oxide and a depletion layer in the silicon, a big part of the voltage is applied over the depletion layer [12]. Hot-Carrier Degradation: The second lifetime affecting mechanism is the hot-carrier degradation or hot carrier injection (HCI). It occurs when the transistor is in the saturation region and the drain-source voltage is big, which will give a high energy to the carriers moving from source to drain and cause them to turn 24 Theory Background for Analog Design hot near the drain zone. The transistor performance is affected from the hot carriers that cause slow degradation in the gate oxide. The slow degredation happens when the hot carriers get into the gate oxide zone near the drain during their collision with the silicon lattice. The HCI results in a small variation in the threshold voltage of the transistor [4]. The magnitude of the hot-carrier degradation effect primarily depends on the transistor’s length and the biasing conditions. [12]. • The lifetime is exponentially related to the drain-source voltage Tlif e ∝ exp(A/Vds ). For deep submicron processes A = 80-120 V, Vds should be according to the worst case settings. • The length does not affect the lifetime strongly, the relation can be approximated by: Tlif e ∝ LB ; B = 1-5. • The lifetime has got a more complicated relation with the gate-source voltage. When the gate-source voltage is low, the transistor is turned off leading to a zero drain-source current which in consequence means no hot carriers. Furthermore when the gate-source voltage is very high and the drain-source voltage is constant there will be no hot carriers since the transistor is operating in the linear region. However, the hot-carrier degradation becomes maximum for the region where the drain current is large and the transistor is well in the saturation region, resulting in a minimum lifetime. Junction Breakdown: The junction breakdown happens when applying voltages that are at least several times larger than the nominal supply voltage for the new CMOS processes. For this reason there is no need to care much about it for circuits that work at voltages that are 2.5 times higher than the nominal supply voltage. Nonetheless, the junction weakly collapses when applying reverse voltages that are higher than the nominal supply voltage. Incrementing the reverse bias voltage level causes the reverse diode current (the leakage current) to increase. Another mechanism that affects the lifetime is PMOS Negative Bias Threshold Instability (NBTI). NBTI is a serious issue for thin oxide PMOS. When the negative gate-source voltage pressures the PMOS, the threshold voltage is increased causing a decrement in the drain current and a decreased transconductance. The effect of NBTI becomes worse for shorter channel lengths and higher temperatures. Achieving a longer life time demands reducing the effect of NBTI. This is done by keeping the transistor in the dynamic condition, where biasing the gate is varied between high and low cases, compared to the NBTI effect in the static condition [12]. Table 3.1 shows a comparison between 65-nm thin oxide (core) transistors and 0.25µm thick oxide (IO) transistors regarding the different reliable voltages that assure a sufficient lifetime. 3.2 Core Transistors and I/O Transistors IO Oxide Breakdown or TDDB NMOS 3.8 V PMOS 4.1 V NMOS 1.7 V PMOS 1.7 V NMOS 3.0 V PMOS 3.3 V NMOS 1.4 V PMOS 1.4 V IO PMOS 4.0 V Core PMOS 1.4 V Core IO Hot-carrier degradation or HCI NBTI 25 Core Table 3.1. The tolerable voltages regarding the affecting lifetime mechanisms for a typical 65-nm CMOS technology [4]. 26 Theory Background for Analog Design The maximum supply voltage tolerated for 65-nm core transistors is 1.4 V in order to assure the desired lifetime, as shown in table 3.1. The voltage is limited by the PMOS NBTI and MOS HCI [4]. 3.3 Operational Amplifier A lot of analog and mixed-signal circuits contain an operational amplifier (op amp). Operational amplifiers have got various applications. Ranging from simple to more complex designs, op amps are used for different purposes such as filtering, generating DC bias or amplifying signals. While CMOS technologies are scaled down and the demand for less power consumption is increased, the design of the op amp presents a big challenge for analog and mixed-signals designers [13]. Generally in the regulator, the driver stage (usually an op amp) is the most vital part of the regulator. It is very critical for the regulator design to build a high performing amplifier so the desired load and line regulations are met. In addition, high performance for various temperatures is achieved by designing a good amplifier. Each of the amplifier specifications play a role in the performance of the regulator, such as the DC gain, the bandwidth, the phase margin, etc. It is usually desired for amplifiers to have a significant DC gain, a sufficient bandwidth in order to attain a good transient response and a good phase margin (typically larger than 45 degrees) to obtain stability for the closed loop circuit. General Considerations: The operational amplifier in general is a differential amplifier with a high-gain. It is relative how high the amount of gain can be, but it should be a sufficient value for a specific application. The op amps are mainly used with a feedback system and the open-loop gain is decided by the desired accuracy of the closed-loop circuit [13]. Previously, op amps were designed more standardly to fulfill a lot of application requirements, e.g. building op amps with a very high voltage gain and a high input impedance to achieve a close to "ideal" op amp. However, this was possible by sacrificing other performance features such as speed and power consumption. On the contrary nowadays, designing the op amp is done by taking into account the trade-offs between the parameters and the need for optimization in order to achieve a sufficient performance. Therefore, it is very important to decide the sufficient value for each parameter and to choose the suitable topology according to the requirements of the application [13]. Since the design of the op amp contains a lot of transistors and a big number of parameters that affect the performance. It is usually difficult to know where to start from and how to select the values for the design parameters. Actually in practice, the method of designing an amplifier mainly relies on the requirements of the circuit, i.e. the method to design a high-gain op amp could be very dif- 3.3 Operational Amplifier 27 ferent from the method to design a low-noise op amp. Thus, the most important parameters for the performance will decide the design procedure [13]. Several op amp topologies will be briefly explained in the following sections. 3.3.1 Two-Stage Operational Amplifier The two-stage op amp is a very popular topology that has been widely used for bipolar and CMOS op amps [14]. It is usually used to obtain a high-gain and a wide output swing. The high gain is provided by the first stage of the amplifier and the large output swings by the second stage [13]. However, the two-stage op amp is, by some means, more appropriate for resistive loads [14]. Typically, the first stage has a differential-input and single-ended output. This stage could be any topology of amplifier, while the second stage is usually a common-source gain stage that grants the largest output swings. The commonsource stage is connected to an active load. The first stage could also be fully differential if a two-stage fully differential amplifier is desired. Furthermore the first stage could be differential while converting the differential output stage to a single-ended output in the second stage. Figure 3.1 shows a two-stage op amp. 3.3.2 Cascode Operational Amplifier The differential cascode amplifier can be used to acquire higher gain. Figure 3.2 shows an example of a differential cascode op amp topology. This circuit is also called "telescopic" cascode op amp. 

 2 2 The circuit gain could be estimated to be in the class of gmN · gmN · rON k gmP · rOP . However, the main disadvantages of using the telescopic op amp is the limited output swing and the complexity when connecting the output to the input to build a buffer. To overcome those issues the folded-cascode op amp could be used [13]. 3.3.3 Folded-Cascode Operational Amplifier The main concept of the folded-cascode op amp is to cascode the differential input transistors using a different type of transistors than the input pair transistors. i.e. using PMOS transistors to cascode NMOS differential input transistors and vice versa. The compromise of using different type transistors gives an ability to the output signal to reach the same level of the input signal at the same bias voltage levels. Since the cascode methodology is used, a high output impedance is achieved. Consequently a good amount of gain is achieved because the product of the input transconductance and the output impedance decides the gain. The gain could be in the range of 700 to 3000. Figure 3.3 shows an example of a folded-cascode op amp circuit. 28 Theory Background for Analog Design Figure 3.1. A two-stage operational amplifier circuit [14]. 3.3 Operational Amplifier Figure 3.2. A cascode (telescopic) operational amplifier circuit [13]. 29 30 Theory Background for Analog Design Figure 3.3. A folded-cascode operational amplifier circuit [14]. 3.3.4 Current-Mirror Operational Amplifier The current-mirror op amp is also a very common topology that is widely used for on chip applications which do not have resistive loads. A decent gain could be achieved by designing current mirrors that have high output impedance. Figure 3.4 shows a current-mirror op amp circuit where K is the rate between the output current and the input mirrored current. Using higher mirror rate increases the op amp transconductance which causes the unity gain frequency to increase. The load capacitance plays a main role in limiting the unity gain frequency instead of the high frequency poles. Increasing K to very high values makes it necessary to increase the load capacitance in order to keep the circuit stable. Also, in some cases, a higher mirror rate causes the bandwidth to drop to smaller values depending on the dominant poles. Since high speed is important, K should be small if the load capacitance is small and the second pole is dominant. The current-mirror op amp performance, regarding slew rate and bandwidth, is much better comparing to the folded-cascode op amp. This makes it more desirable. 3.3 Operational Amplifier 31 Figure 3.4. A current-mirror operational amplifier circuit [14]. 3.3.5 Operational Transconductance Amplifier (OTA) An amplifier is called operational transconductance amplifier (OTA) when all the internal nodes (all the nodes in the circuit excluding the input and output nodes) of the amplifier have low impedances. It is normally more suitable to be used for driving capacitive loads. Nevertheless, OTA could be used to drive resistive loads by introducing a buffer stage. A good example of an OTA is the current-mirror amplifier shown in Figure 3.5. As seen in Figure 3.5, all the internal nodes have low impedances, some of the nodes are diode connected devices and the others have a source connected to them. The highest value that the output current can achieve is K · Iss where K is the mirror rate. This explains the slew-rate issues when the OTA is used as a first stage in an op amp. The output impedance of the ideal OTA should be infinite, meaning that all of the output current proceeds in the capacitive load and no current proceeds in the output impedance of the OTA. An ideal OTA can be represented with a voltagedependent current source, it is sometimes called a GM stage [13]. The previous OTA output impedance could be increased by cascoding the current mirrors. Figure 3.6 shows the suggested circuit to increase the output 32 Theory Background for Analog Design Figure 3.5. A simple current-mirror operational transconductance amplifier circuit [11]. 3.3 Operational Amplifier 33 impedance. Also, the tail current source has been changed to four transistors instead of two. Figure 3.6. A cascode current-mirror operational transconductance amplifier circuit [11]. The unity gain frequency is reduced when the load capacitance is increased, resulting in a better stability. The OTA gains more stability by increasing the load capacitance, contrarily to the two-stage op amp where big load capacitance causes stability problems. In addition, the phase margin improves with larger load capacitance. Moreover, the OTA has a first-order step response. All of the those features make the OTA suitable for a lot of on chip applications, when it is configured in a closed-loop circuit. 3.3.6 Selecting a suitable Operational Amplifier As mentioned in section 3.3, when designing an amplifier, the designer bumps mainly into the problem of where to start from since there is a lot of effecting parameters. Therefore a general guideline is to go through the needed requirements in order to select a suitable architecture. 34 Theory Background for Analog Design The DC-gain, the bandwidth, the phase margin and the power consumption are the main features to consider in the op amp performance when it comes to the regulator design. Different op amp topologies have been shown, their advantages and their drawbacks have been briefly mentioned. It has been concluded that the current mirror OTA shown in Figure 3.5 is the most suitable architecture to be implemented in the regulator circuit, since the current mirror OTA is able to supply the required DC-gain, bandwidth, etc. And it is more suitable for on chip applications that have capacitive loads. In the regulator circuit, the output of the amplifier will be connected to the gate of an NMOS which requires a high output impedance. However, the amplifier needs to deal with supply voltages that are higher than the nominal supply voltages of the used transistors. Moreover, obtaining a decent amount of DC gain is needed. Therefore, cascoding the current mirrors in Figure 3.5 is required. The design of the amplifier will be discussed in chapter 4 while the next section will briefly present some current mirror techniques. 3.4 3.4.1 Current Mirrors Techniques Basic Current Mirrors Figure 3.7(a) shows a basic current mirror circuit. Assuming that both transistors are equal in size and are operating in the saturation region then the current going through Q1 ,Iin , should be equal to the current going through Q2 ,Iout , since both transistors have the same gate-source voltage Vgs . It has also been assumed that the transistors’ output impedance is infinite. This means that the input current has been mirrored or copied to the output branch. The current values are sligthly different when considering again the precise output impedances of the transistors. The transistor with the higher drain-source voltage drop will have the higher current. Furthermore, the fact that the transistors’ output impedances are not infinite means that the the current mirror’s smallsignal output impedance is also confined. The current mirror’s small-signal output impedance is the small-signal impedance seen from the drain of Q2, like shown in Figure 3.7 (b) The value of this impedance is estimated to be rds2 after approximating Q1 output impedance to 1/gm1. In order to obtain a higher output impedance and eventually a more 'ideal' current mirror, other techniques such as cascode current mirrors are used [14]. 3.4.2 Cascode Current Mirrors As mentioned in the previous section, cascode current mirrors have a higher smallsignal output impedance. Figure 3.8 shows an example of a cascode current mirror circuit. Similarly to the basic current mirrors, the output impedance seen from the drain of Q2 is rds2 . Assuming Q4 is a current source with a source-degeneration1 1 basic current mirror that has resistors connected to the source of the transistors 3.4 Current Mirrors Techniques 35 Figure 3.7. (a) A simple current-mirror. (b) A small-signal model of the current-mirror circuit shown in (a) [14]. 36 Theory Background for Analog Design resistor rds2 , the output impedance can be written as: rout = rds4 [1 + rds2 (gm4 + gs4 + gds4 )] ∼ = rds4 (rds2 · gm4 ) (3.6) Figure 3.8. A cascode current-mirror circuit. This means that the output impedance of the cascode current mirror is larger than that of the basic current mirror with a factor of gm4 · rds2 . This value is the maximum gain that can be achieved by a single-transistor gain stage. It can range from 10 to 100, determined by the transistors dimensions, currents and the used technology. The main drawback of the cascode current mirror is that it lowers the available upper-limit which the output-signal swing can reach while keeping the transistors in the saturation region. It is known that in order to let NMOS operate in the saturation region, the drainsource voltage should be: Vds > VGS − Vtn = Vef f . Therefore the minimum output voltage that both transistors Q4 and Q2 can still operate in the saturation region with is Vout = 2Vef f , assuming equal dimensions and gate-source voltages for both transistors. However, the minimum allowed voltage for Vout is Vout = 2Vef f +Vtn which is a Vtn higher than the usual minimum 3.4 Current Mirrors Techniques 37 value. This problem becomes severe for technologies that have relatively small power supply voltages. 3.4.3 Wide-Swing Current Mirrors As seen in section 3.4.2, cascode current mirrors are required to obtain a higher output impedance, especially when it comes to designing an operational amplifier using recent transistor-technologies with short channel lengths. The output impedance is reduced proportionally with the channel length which makes the design of an amplifier with decent gain a big challenge. On the other hand, employing typical cascode current mirrors such as illustrated in Figure 3.8 reduces the possible signal swings. This presents another problem, namely that the power supplies of new technologies are reduced proportionally as well. To overcome this problem another current mirror technique known as "Wide-swing cascode current mirror" is used. Figure 3.9 shows a wide-swing current mirror circuit. This circuit does not reduce the signal swing like the cascode current mirror shown in figure 3.8. The main principle of this technique is to set Vds of Q2 and Q3 to the lowest value where the transistors are still in the saturation region. In this architecture Q3 and Q4 behave like one diode-connected transistor for biasing VGS of Q3. The purpose of using Q4 in this architecture is to equal the drain-source voltages of Q2 and Q3 and thus having equal input and output currents. The output current value would be less than the input current in case Q4 was not used because the output impedance of Q2 and Q3 is not infinite. In addition, Q4 has a small contribution on the circuit’s function. The lowest output voltage tolerated for the wide-swing current mirror circuit shown in figure 3.9, before the transistors move to the linear region, is: Vout > (n + 1)Vef f (3.7) where n is a number used for the transistors sizes as seen in Figure 3.9. By choosing n value to be 1, the minimum output voltage becomes: Vout > 2Vef f . Some points regarding the circuit shown in Figure 3.9 are presented as follows: The dimensions of Q5 are usually chosen slightly smaller than the value shown in Figure 3.9 by experienced designers. The reason is to set Vds of Q2 and Q3 to a value that is a little bit higher than the minimum value which is needed to let the transistors operate in the saturation region. The higher voltage is desirable when taking into account practical issues such as the gradual move for real transistors from linear to saturation regions, also it is done to shift second-order effects caused by the body of transistors Q1 and Q4. The circuit’s part of Ibias and Q5 could be adjusted to reduce the current going through that branch while maintaining the same current density, hence the same gate-source voltage, in order to reduce the power consumption. Another typical adjustment is to select the value of the transistors’ length so that Vds is minimized, except for Q1 and Q4 for which the channel length value is usually selected to be twice the lowest available channel length. This is done because 38 Theory Background for Analog Design Figure 3.9. A wide-swing current-mirror circuit. 3.4 Current Mirrors Techniques 39 those transistors usually handle higher voltage drops. In addition, it helps getting rid of short channel effects. Selecting the lowest channel length value for Q2 and Q3 results in a better frequency response. In conclusion, this current mirror technique is the most preferred one to be used nowadays in CMOS analog circuits. Chapter 4 Designing the Regulator This chapter handles the design of the regulator, including the design considerations, calculations and the test benches used for simulation. Before discussing the design, figure 4.1 previews the general regulator circuit that was selected in section 2.3. The voltage supply is in the range between 1.8 to 3.6 V while the regulated output voltage is a selectable voltage between the following outputs [0.9, 0.8, 0.7, 0.6, 0.5 V]. The values of the resistors and the reference voltage have not been specified yet. A reference voltage is needed in order to achieve a regulated output. The reference voltage is obtained from a band-gap reference circuit. It is ideally constant and independent of both, power supply and temperature changes. For an ideal constant reference voltage, the output regulated voltage will be independent from process and temperature variations, since it is related to the resistors proportion which is invariant with temperature and process fluctuations of the resistors. Also, it is invariant with the amplifier open-loop gain which is stabilized using a feedback [11]. Considering an ideal amplifier (with infinite gain), the regulated output voltage is given by the following equation: VOU T = VREF · (1 + R1 ) R2 (4.1) Considering again a non-ideal amplifier, meaning that v + 6= v − and assuming the value of the amplifier open-loop gain equals to A, then VOU T can be written as: VOU T = Vamp,out − VGS ⇒ VOU T = A · (v + − v − ) − VGS but v + = VREF and v − = VOU T · R2 R1 +R2 ⇒ VOU T = A · (VREF − VOU T · 41 R2 R1 +R2 ) − VGS 42 Designing the Regulator Figure 4.1. The voltage regulator circuit. 4.1 The Resistors Ladder and the Transmission Gates ⇒ VOU T = A · VREF − VGS 2 1 + A · R1R+R 2 43 (4.2) For very large values of A, equation 4.2 becomes equal to equation 4.1. This result shows that designing an amplifier is very critical for the regulator. The more 'ideal' the amplifier is, the better output regulated voltage is achieved [11]. Back to equation 4.1, the highest output voltage required in the specification is 0.9 V, while the lowest output voltage required is 0.5 V. In the case of an ideal amplifier, the node between R1 and R2 has a voltage that is equal to the reference voltage. Therefore the reference voltage value should be selected to be less than 0.5 V. By selecting the value of VREF = 0.3 V and assuming that the current going through the resistors is 0.3µA, then the value of the resistor R2 becomes: VREF − 0 = 1M Ω (4.3) 0.3 · 10−6 Hence, the value of R1 is decided according to the selected output regulated voltage. For 0.9 V output R1 is calculated according to equation 4.1 [11]. R2 = R1 = R2 · ( 4.1 VOU T 0.9V − 1) = 2M Ω − 1) = 1M Ω · ( VREF 0.3V (4.4) The Resistors Ladder and the Transmission Gates As mentioned previously, the value of R1 varies with the output voltage, since five different output voltages are required, there will be five corresponding values for the resistor R1 . The values of R1 are calculated as follows: R1,0.9V = 2M Ω R1,0.8V = 1M Ω · ( 0.8 0.3 − 1) = 1.667M Ω R1,0.7V = 1M Ω · ( 0.7 0.3 − 1) = 1.333M Ω 0.6 R1,0.6V = 1M Ω · ( 0.3 − 1) = 1M Ω R1,0.5V = 1M Ω · ( 0.5 0.3 − 1) = 0.667M Ω One possible solution to get all of the required output voltages is to divide R1 into several resistors connected in series with each other. Where the sum of all the resistors is the highest required value of R1 . i.e: R1 is selected to be 2M Ω and divided into the following series resistors [0.667, 0.333, 0.333, 0.334, 0.333M Ω]. Figure 4.2(a) illustrates the resistors connection. However, when selecting an output voltage less than 0.9 V, one or more resistors need to be shortcut to avoid increasing the load resistance. Therefore, transmission 44 Designing the Regulator gates are used in order to shortcut the undesired resistors for the output voltage values less than 0.9 V. Each resistor is connected in parallel with a transmission gate. The transmission gate is controlled by a control signal (ctrl) that is connected to a multiplexer for selecting the desired output voltage. Figure 4.2(b) shows the connection of the transmission gates with the resistors. Figure 4.2. (a) The resistor ladder for several output values. (b) The transmission gate placing in the regulator circuit. The transmission gate works as a switch which is controlled by a control signal, i.e. it behaves like an open circuit or a shortcut, depending on the control signal. Each transmission gate consists of two transistors, an NMOS and a PMOS. Those transistors are always in the same state, either 'on' or 'off'. This can be done by biasing the gates of the transistors in an opposite way, i.e. when one of the transistors has a 'high' signal applied on its gate, a 'low' signal is applied on the gate of the other transistor. This can be achieved with the same ctrl signal using an inverter. When the ctrl signal is 'high' the NMOS state is 'on' and the PMOS is also biased to be in the state 'on' due to the inverted ctrl signal applied on its gate. This yields a very small on-resistance, i.e. the switch is closed. Meaning that all the signal passes through the transmission gate. Hence, the parallel resistor is 4.2 Designing the OTA 45 shortcut. When the ctrl signal is 'low' then both transistors are 'off' in the same manner. This results into an almost infinite high-impedance by the transistors, i.e. the switch is open. Meaning that all the signal passes through the resistor in parallel with the transmission gate [15]. Figure 4.3 illustrates the whole transmission gate circuit, taking into consideration that the 'IN' and 'OUT' nodes are connected in parallel with the resistors as shown in figure 4.2(b). Figure 4.3. The transmission gate circuit [15]. The transistors sizes were selected to be of minimum size, i.e. the length is 0.06µm and the width is 0.675µm. Since the transmission gates are connected in parallel with relatively large resistors, it was possible to achieve a good performance without needing to change the transistors dimensions. Simulations have been done to verify the performance of the transmission gates. 4.2 Designing the OTA As mentioned at the beginning of chapter 4, designing the OTA is the most critical part of the regulator design. Building a good regulator circuit requires building a high performance amplifier. 46 Designing the Regulator In this project, the requirements which needed to be fulfilled by the OTA were to supply a minimum DC gain of 30 dB and a phase margin larger than 45 degrees for the whole input voltage range, using only core transistors. The main two points which had to be considered during the design were: • The voltage drop on each core transistor should not exceed 1.4 V, in order to guarantee a sufficient life-time. • The input supply voltage is in the range 1.8 to 3.6 V. This means that the supply voltage can get to its double minimum value. Obtaining the desired DC gain and phase margin for such a relatively wide input range becomes a challenge. The primary selected architecture that was used is the current mirror OTA shown in figure 3.5. However, some modifications were required in order to make it suitable for the design. Cascade current-mirrors were used to contain the voltage drops and to achieve a higher gain. The input transistors should always be in the state 'on'. Since the input voltages are relatively low (0.3 V), an OTA with PMOS inputs had to be used. Figure 4.4 shows the simple uncascoded OTA architecture with PMOS input. Figure 4.4. A simple current-mirror PMOS-input circuit. 4.2 Designing the OTA 47 The low level of the input voltages makes it very difficult to operate the input transistors in the 'saturation' region for higher supply voltages, which directly affects the DC gain. Therefore, the input levels were increased by using the circuitry shown in figure 4.5. Figure 4.5. A circuit to increase the input level. All transistors’ lengths were chosen to be 1µm in order to minimize the short channel effect. Handling the high voltage drops will be explained in the next section. 4.2.1 Cascading the OTA Cascading the amplifier, as mentioned in section 3.4.2, maximizes the gain that can be achieved by a single-transistor gain stage. Moreover, using cascoded current mirrors increases the number of transistors in the same branch which is needed for handling high supply voltages, since the voltage drop is divided over several transistors. The maximum supply voltage is 3.6 V while the maximum voltage drop on each core transistor is 1.4 V. This means that the minimum number of transistors in 48 Designing the Regulator one branch should be three. The output of the amplifier is connected to the gate of the driving transistor. The driving transistor source voltage is the output regulated voltage which has maximum value of 0.9 V. It is known that Vgs should be larger than Vth in order to have the transistor ON. For the core transistors used in this thesis, the threshold voltage for NMOS is approximately 0.3 V which means that the output of the amplifier should be at least 1.2 V in the case of 0.9 V output. This indicates that the maximum voltage drop on the PMOS transistors in the output branch of the amplifier is 2.4 V, which requires minimally two PMOS transistors to handle that voltage drop. As mentioned in section 4.2, the input voltage levels are relatively low since the bandgap reference voltage is 0.3 V. The added level shifter circuitry seen in figure 4.5 increases the voltage level up to approximately 0.7 V, this makes the voltage on the drain of the bias transistor equals to maximally 2.1 V. The bias current used is assumed to be 0.5µA in order to minimize the current consumption. The current mirror principle, as explained in section 3.4, depends on a diodeconnected transistor, i.e. the gate and drain of the mirroring transistor are connected together. For the same source, the drain voltage of the mirrored transistor tends to equal the drain voltage of the mirroring transistor, making the transistor operate in the saturation region. Based on the previous fact and the fact that the maximum voltage on the source of the input transistors is 2.1 V, it has been decided that cascading the bias current circuit is necessary. By tuning the sizes of the transistors and running simulations it has been found that three PMOS transistors are needed for the bias circuit. The bias current circuit that consists of three cascoded current mirror PMOS transistors is shown in figure 4.6. The bias current which is needed in the mirrored branch is 25µA, 50 times greater than the current source used. This means that the mirror rate should be 50 in the ideal case, however, simulation results have shown that the required mirror rate is 84. The current passing through the mirrored bias branch is equally divided into the input branches. Each branch of the input transistors has 12.5µA current going through it. The current going through the output branch is decided to be 50µA, that is in order to guarantee enough current is supplied to the load in case of unexpected drops in the input voltage. This means that the mirror rate from the right input branch (the positive input) to the output branch is four. The left input branch current is mirrored to the output branch on two levels. First, it is mirrored to the left branch which is parallel to the output branch, then it is mirrored to the output branch. The combination of both mirror rates should be four. The mirror rate of the left input branch is decided to be one, making the upper 4.2 Designing the OTA 49 Figure 4.6. The cascoded bias current circuit of the OTA. right mirror rate, from the left branch to the output, equals to four. Considering the required output voltage and the fact that the value of the diode connected transistor’s drain voltage is equal to the mirrored transistor’s drain voltage, it can be seen that three PMOS cascode transistors are needed in every branch. This was concluded in a similar manner to the bias current mirror design. When tuning the sizes of the transistors in order to achieve the desired voltages, it should be taken into consideration that the drain source voltage drop on the transistor is minimized when the transistor is ON and vice versa. Also, as it is known, the PMOS transistors are ON when the voltage applied on the gate is minimum while the NMOS transistors are ON when the gate voltage is maximized. In order to balance the voltage drop on the transistors in the output and its parallel branch, a third NMOS cascode level has been added to those branches. The voltage between the PMOS and NMOS transistors in the parallel branch is applied to the gates of those added transistors. Figure 4.7 shows the final design of the cascoded OTA used for the regulator. 50 Designing the Regulator Figure 4.7. The final circuit of the cascoded OTA. 4.3 The Pass Transistor The pass transistor is the NMOS that has its gate connected to the output of the OTA, as shown in the general circuit of the regulator in figure 4.1. The output of the regulator is the source of this NMOS and has a minimum value of 0.5V and a maximum value of 0.9V . The drain is connected to the unregulated supply voltage which can be in the range of 1.8 to 3.6V . This means that the minimum drain-source voltage drop for this transistor is 1.8 − 0.9 = 0.9V , while the maximum voltage drop is 3.6 − 0.5 = 3.1V . Therefore, cascode transistors are required in order to handle the high voltage drop on the pass transistor which guarantees a sufficient life time. The maximum voltage drop, as calculated at the beginning of this chapter, is 3.1V which requires three core transistors to handle it. One of the three transistors is biased by the OTA output and the remaining two cascoding transistors need to be biased in a proper way. 4.3 The Pass Transistor 4.3.1 51 Biasing the Cascoding Transistors The drain-source voltage drop across NMOS transistors can vary depending on the gate voltage. For a fixed current, biasing the NMOS transistors with a high voltage leads to a low drain-source voltage and vice versa. The drain source voltage drop on the two cascoding transistors should be minimum 1.7V , when the input voltage is 3.6V and the output regulated voltage is 0.5V . The threshold voltage for the used NMOS core transistors is around 0.3V . This means that the minimum voltage at the drain of the pass transistor is Vs + Vth = 0.9 + 0.3 = 1.2V . Hence the maximum drain source voltage drop across the two cascoding transistors is 0.6V , in the case of 1.8V input voltage and 0.9V output. This causes a voltage headroom issue which needs to be considered during the design. To overcome this problem, the cascoding transistors should be biased with voltages that vary with the input voltage, making their source-drain voltage vary accordingly to fulfill the previous conditions. However, this means that the biasing voltages should be decreased when the input voltage increases. Simulations have shown that this condition is not possible to achieve for the given parameters. The simulations have been done by biasing the transistors with the OTA output voltage and introducing a level-shifter for each cascoding transistor, making the highest voltage drop across the lowest transistor. The result, for the case of 1.8V input voltage and 0.9V output voltage, has shown that the cascoding transistors must be biased with voltages higher than the power supply. This is not possible in reality. Another possible solution is to make the drain voltage of the pass transistor 1.2V constantly, making the voltage drop across the cascoding transistors ranging between 0.6 and 2.4V , depending on the input voltage. However, providing a constant 1.2V voltage implies that a regulated or a referenced voltage needs to be obtained somehow. This might be possible to achieve theoretically by building another bandgap reference or regulator circuit which supplies this voltage constantly. However, the design area, power consumption and other parameters are affected significantly. Therefore, the goals and requirements of the general project need to be reconsidered before considering this as a proper solution. Other solutions for this problem could exist but considering the limited time for the research of this thesis, the core pass transistor was substituted with a thickoxide NMOS which can handle the maximum voltage drop temporarily. All the simulation results presented in chapter 5 were obtained from simulations including a thick-oxide pass transistor. 52 4.4 Designing the Regulator The OTA Test-Bench Figure 4.8 shows the testbench of the OTA. The SignalToDiff box is used to generate one signal on both ends so the OTA inputs are fed with a common signal, the load capacitance is 1pF , the VDD voltage source is the unregulated supply voltage which ranges between 1.8 and 3.6V . The reference current IREF has a value of 500nA. Figure 4.8. The test bench circuit of the OTA. 4.5 The Regulator Test-Bench Figure 4.9 shows the testbench used for running simulations of the regulator circuit. A 100pF capacitor is added to the output as a load capacitance, since the output of the regulator is connected to many devices in the mote. The VDD voltage source is the unregulated supply voltage which ranges between 1.8 and 3.6V . The reference voltage VREF is the bandgap reference voltage. The pulled current by the load is simulated using a PVCCS2 device which is obtained from CADENCE’s analog library. This device pulls current according to the voltage VLOAD as seen in the figure. The maximum voltage that can be pulled is selected to be 50µA direct current and 100µA pulse-wave current, as has been specified in the requirements. When VLOAD is 1V the maximum specified current is pulled and when VLOAD is 0V no current is pulled. 4.5 The Regulator Test-Bench Figure 4.9. The test bench circuit of the regulator. 53 Chapter 5 Simulation Results This chapter shows the performance of the regulator through simulations which were done using CADENCE. The results for various cases of simulations show wether the design is able, or close, to meet the requirements using a thick-oxide transistor as the regulator’s pass transistor. 5.1 Voltage Drop Simulations During the design it was considered that each branch in the OTA should contain enough transistors in order to handle the maximum input voltage. However, the voltage drop is not equally distributed on all the transistors in a branch. This means that some transistors can have voltage drops higher than their tolerable voltage. There are several ways to change the voltage drop on a transistor, e.g. changing the dimensions of a transistor. It should be taken into consideration that changing one parameter can affect the whole circuit. Therefore the voltage drops on every transistor should be looked at during the simulations. Many simulations were executed to assure that the voltage drop on each transistor will never exceed 1.4 V. Figure 5.1 shows the voltage drops on all the transistors of the OTA during the simulation of the regulator. The simulation is done for the highest unregulated voltage which is 3.6 V and with maximum current pulled by the load. Changing the load current can affect the voltage drops in some cases. Figure 5.2 shows the simulation results when the unregulated voltage is 3.6 V and there is no current pulled by the load. It can be seen that the voltage drops on the transistors of the OTA are slightly different from the full-load case shown in figure 5.1. 55 56 Simulation Results Figure 5.1. The voltage drops on all the transistors of the OTA when the maximum current is pulled by the load. Figure 5.2. The voltage drops on all the transistors of the OTA when there is no current pulled by the load. 5.2 DC Load Simulations 5.2 57 DC Load Simulations According to the requirements, the regulator should be able to handle the DC load current changes between 0 and 50µA. Usually, changes in the load current cause changes in the output regulated voltage. In order to capture the output voltage changes, the output error has been calculated during simulations. It generally indicates the error percentage in the output voltage which is introduced due to changes in some parameters. For the simulations that have been executed, the bandgap reference voltage used is an ideal voltage source. In practice, the reference voltage is obtained from a bandgap reference circuit which usually introduces an error in the output voltage. Most of the devices can handle 10% error from their nominal supply voltage. Therefore, the error in the output voltage level generated by the regulator which can be tolerated is decided to be maximally 5%. The output error for 0.9 V output voltage is defined in the following equation: p (Vout − 0.9)2 · 100 (5.1) OutputError[%] = 0.9 Figure 5.3 shows the output error for the unregulated voltages in the range 1.8 to 3.6 V, where the DC load is 50µA. Figures 5.4 to 5.8 shows the variations of the Figure 5.3. The output error for all unregulated voltage values and maximum DC load current. output error with the load current changes for all possible unregulated voltages. All the simulations are done for the output voltage case of 0.9 V. It can be seen from the figures that the output error varies differently for different input voltages. Furthermore, simulations have shown that the output voltage increases when the DC load decreases. As seen in figures 5.4 and 5.8, the output voltage error exceeds the tolerable limit for the input voltages of 1.8 V and 3.6 V. Table 5.1 summarizes the simulation results seen by the previous figures. The table shows the DC load that was handled by the regulator, where the output voltage error is less than 5%, for each input voltage. 58 Simulation Results Figure 5.4. The output error variation against DC load current for 1.8 to 2.1 V unregulated voltage. Figure 5.5. The output error variation against DC load current for 2.2 to 2.5 V unregulated voltage. 5.2 DC Load Simulations 59 Figure 5.6. The output error variation against DC load current for 2.6 to 2.9 V unregulated voltage. Figure 5.7. The output error variation against DC load current for 3 to 3.3 V unregulated voltage. 60 Simulation Results Figure 5.8. The output error variation against DC load current for 3.4 to 3.6 V unregulated voltage. It can be seen from the table that the regulator is able to supply a proper output voltage for the required DC load currents within the input voltage range 1.9 to 3.3 V. Input Voltage 1.8 V 1.9 V 2.0 V 2.1 V 2.2 V 2.3 V 2.4 V 2.5 V 2.6 V 2.7 V Load Current Ca∼ 0 to 15 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA Input Voltage 2.8 V 2.9 V 3.0 V 3.1 V 3.2 V 3.3 V 3.4 V 3.5 V 3.6 V Load Current 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA 0 to 50 µA Ca∼ 13 to 50 µA Ca∼ 38 to 50 µA Not available Table 5.1. The DC-load range where the regulator supplies a regulated output for different input voltages. 5.3 AC Load Simulations The regulator’s AC load is represented by the digital circuits in the mote, their consumed current is in the form of periodic spikes. The consumed current ranges between 0 and 100µA. The digital circuits in the mote are assumed to operate in a relatively low frequency. A load current with 100µA spikes is added to the output of the regulator for simulations, the spikes period is 50µs and the simulations are done with no DC 5.3 AC Load Simulations 61 load. Figure 5.9 shows the AC load current used during the simulations. The Figure 5.9. The AC current load on the regulator output. output error that is defined in equation 5.1 is used to show the AC load effect on the output regulated voltage. Figure 5.10 shows the output error for the unregulated voltages in the range 1.8 to 3.6 V, where the load current applied is the AC current shown in figure 5.9. As seen in the figure, the output error exceeds 5% for input voltages higher than Figure 5.10. The output error for all unregulated voltage values and AC current load. 3.3 V. Transient simulations have been done also for several input voltages to see the output voltage signal form. Figures 5.11 to 5.14 show the transient response 62 Simulation Results for 0.9 V output voltage and 1.8, 2.7, 3.3, 3.6 V input voltages respectively. Figure 5.11. The output voltage for 1.8 V unregulated voltage and AC current load. Figure 5.12. The output voltage for 2.7 V unregulated voltage and AC current load. As seen in the previous figures, the voltage level slightly drops at the spikes positions for 1.8, 3.3 and 3.6 V, while it seems like it oscillates for the 2.7 V. 5.3 AC Load Simulations 63 Figure 5.13. The output voltage for 3.3 V unregulated voltage and AC current load. Figure 5.14. The output voltage for 3.6 V unregulated voltage and AC current load. 64 Simulation Results The change in the voltage level is maximally 0.002 mV for all tested input voltages which is extremely small and has no effect on the performance of digital parts in the mote. It can be concluded that the regulator is able to supply a proper output regulated voltage for the required AC load current in the input voltage range 1.8 to 3.3 V. 5.4 Transient Response Simulations The load transient response can be defined as how fast the regulator responds to changes in the load. The regulator should be able to handle load changes in less than 10µs. For simulating load transients, the normal voltage source connected to the pvccs2 device of the regulator testbench, shown in figure 4.9, is substituted with a voltage source named vpwl which is obtained from CADENCE’s analog library. The vpwl used in the simulations has four parameters: time1, voltage1, time2 and voltage2. At the beginning (time1=0 s), the chosen voltage will be 0.5 V which refers to pulling half of the maximum load current, i.e. 25µA. Then the voltage will rise/fall until it reaches voltage2 at time2. Figure 5.15 shows the form of the vpwl generated signal. The load transient response simulations are done for 0.9 V Figure 5.15. The vpwl signal used to cause load transient. output voltage and input voltages of 1.9 and 3.3 V, where the output error does not exceed 5%. Figures 5.16 and 5.17 show the output voltage transient signal where the load has been changed from half-load to full-load DC current during 10µs. As seen in the figures, the signal is stable at 12.8µs, just 2.8µs after the DC load current has been stabilized. This means that the output voltage signal is stabilized in less than 10µs. 5.4 Transient Response Simulations 65 Figure 5.16. The output voltage load transient response for 1.9 V, load changes from half-load to full-load. Figure 5.17. The output voltage load transient response for 3.3 V, load changes from half-load to full-load. 66 Simulation Results In a similar manner, simulations are done again for 1.9 and 3.3 V input voltages, with the load current being changed from half-load to no-load current. Figure 5.18. The output voltage load transient response for 1.9 V, load changes from half-load to no-load. Figure 5.19. The output voltage load transient response for 3.3 V, load changes from half-load to no-load. As shown in the figures, the regulator’s output voltage takes longer time before 5.5 Temperature Changes Simulations 67 it gets stabilized for the case of half-load to no-load. Figure 5.18 shows that the signal gets stable around 22µs, meaning that the transient response for this case is more than 10µs. While figure 5.19 shows that the signal is stable around 17µs, meaning that the regulator transient response is around 7µs for 3.3 V input voltage. The transient response simulation results can be summarized in table 5.2. Although the required transient response is not achieved in one case, the achieved result is close to the requirements. There might be a room to improve that result by tweaking the transistor sizes until the required transient response is achieved. The simulation case Load current changes from half-load to full-load for 1.9 V input voltage Load current changes from half-load to full-load for 3.3 V input voltage Load current drops from half-load to no-load for 1.9 V input voltage Load current drops from half-load to no-load for 3.3 V input voltage Achieved result around 2.8 µS around 2 µS around 12 µS around 7 µS Table 5.2. A summary of the transient response simulation results. 5.5 Temperature Changes Simulations The wide variety of potential applications that employ the smart dust put more demands on the mote to be able to operate in different environments. Therefore, the mote designed in this project is required to handle various temperatures. The regulator circuit is required to operate in the temperature range -20 to 70 C. The following simulations show the effect of temperature changes on the regulator performance. Simulations are done for temperatures between -20 C and 70 C. The results are shown using the output error, which indicates the error in the output voltage for different input voltages, in a specific temperature. Figure 5.20 shows the output error for temperatures between -20 and 70 C with 10 C step change. The input voltages are between 1.8 and 3.6 V and the selected output voltage is 0.9 V. The applied DC load current is 50µA. It can be seen from figure 5.20 that the output error of temperature changes behaves differently with different input voltages. • When the input voltage is between 1.8 V and 2.2 V, the lower temperatures have higher output error. • The temperature effect is minimized at the input voltage 2.2 V as the output errors of all temperatures drop down to zero. 68 Simulation Results Figure 5.20. The output error for temperatures between -20-70 C and input voltages between 1.8-3.6 V. • The output error increases accordingly until the input voltage 3.25 V where the temperature effect is minimized again. • Finally, the output error of lower temperatures becomes lower than the output error of higher temperatures for input voltages 3.25 to 3.6 V, opposite to the low input voltages. Simulations that show the output error versus DC load current changes for various temperatures have been done as well. Figures 5.21 to 5.23 show the output error against the load current changes for temperatures between -20 C and 70 C. The selected input voltages are 1.8, 2.7 and 3.6 V respectively and the selected output voltage is 0.9 V. It can be seen that the output error effect by the load current is different for the different input voltages. The output error decreases proportionally with the load current for 1.8 V input voltage, while it doesn’t differ for 2.7 V and it decreases when the load current increases for 3.6 V. It can also be seen that higher temperatures have less output error in figures 5.21 and 5.22, while they have higher output error for the 3.6 V input voltage. Those temperature changes simulations which are done above show the regulator performance in different temperatures. It can be concluded from the simulations that the regulator is able to supply a regulated output voltage within all the specified temperature range, for input voltages between 2 and 3.5 V. 5.5 Temperature Changes Simulations 69 Figure 5.21. The output error for temperatures between -20-70 C and DC-load between 0-50 uA ,1.8 V input voltage. Figure 5.22. The output error for temperatures between -20-70 C and DC-load between 0-50 uA, 2.7 V input voltage. 70 Simulation Results Figure 5.23. The output error for temperatures between -20-70 C and DC-load between 0-50 uA, 3.6 V input voltage. 5.6 Ctrl-bit Settings Simulations All the previous simulations have been done with the selected output voltage 0.9 V. According to the requirements, it should be possible to select different output voltage levels. Transmission gates are employed in the regulator design for this purpose. Ideally, the regulator performance should be identical for the different outputs. However, this can change in reality. Therefore, simulations should be run to test the performance of the regulator when selecting different output voltages. The following sections show the simulation results of different selected output levels. 5.6.1 0.5 V Output The 0.5 V output voltage is obtained by turning the four transmission gates ON,ON,ON,ON. This changes the value of 'R1' accordingly to get the desired output. Figure 5.24 shows the output error for 1.8 to 3.6 V unregulated voltage and full DC load. The output error increases significantly after 3 V, where the voltage drop on the pass transistor becomes higher than 2.5 V. Figure 5.25 shows the output error for input voltages between 1.8 and 3 V, the DC load current is changing between 0 and 50µA. It can be seen that the output error exceeds 5% for input voltages higher than 2.7 V when there is no load current pulled. The output error also differs significantly for higher voltages while it is relatively constant for low voltages. 5.6 Ctrl-bit Settings Simulations 71 Figure 5.24. The output error for input voltages between 1.8-3.6 V and full DC load, 0.5 V regulated voltage. Figure 5.25. The output error for input voltages between 1.8-3 V and DC-load between 0-50 uA, 0.5 V regulated voltage. 72 5.6.2 Simulation Results 0.6 V Output The 0.6 V output voltage is acquired by configuring the transmission gates to ON,ON,ON,OFF. Similarly to section 5.6.1, figures 5.26 and 5.27 show the output error with variations of input voltages and DC load current. The results are very similar to the 0.5 V output voltage configuration, but slightly improved regarding input voltages. The output error exceeds 5% for input voltages higher than 2.9 V. Figure 5.26. The output error for input voltages between 1.8-3.6 V and full DC-load, 0.6 V regulated voltage. Figure 5.27. The output error for input voltages between 1.8-3.2 V and DC-load between 0-50 uA, 0.6 V regulated voltage. 5.6 Ctrl-bit Settings Simulations 5.6.3 73 0.7 V Output Similarly to the previous cases, the 0.7 V output voltage is acquired by setting the transmission gates ON,ON,OFF,OFF. Figure 5.28 shows the output error versus input voltage changes, where the load current pulled is full DC load current. It can be seen in figure 5.28 that the output error is slightly improved for higher input voltages, comparing to lower output voltage levels. However, the output error does not increase proportionally with the input voltage as it slightly decreases between 1.8 and 1.9 V, where the voltage drop on the pass transistor becomes less than 1.2 V. Figure 5.29 shows the output error with variation of the DC load current for Figure 5.28. The output error for input voltages between 1.8-3.6 V and full DC-load, 0.7 V regulated voltage. input voltages between 1.8 and 3.3 V. It can be seen that the 1.8 V curve behaves differently from the others as it decreases and increases again. Figure 5.29. The output error for input voltages between 1.8-3.3 V and DC-load between 0-50 uA, 0.7 V regulated voltage. 74 5.6.4 Simulation Results 0.8 V Output Figure 5.30 illustrates the output error for the 0.8 V output voltage. The curve is decreasing from 1.8 to 2 V, then starts to slightly increase until 3.2 V where it starts to increase sharply. The 0.8 V output voltage is obtained by setting the transmission gates ON,OFF,OFF,OFF. The output error versus the DC load Figure 5.30. The output error for input voltages between 1.8-3.6 V and full DC-load, 0.8 V regulated voltage. current variation shows a different behavior for different input voltages. In Figure 5.31, the output error increases when the DC load current is more than 10% of the full load for 1.8 V, while it increases after 25% for 1.9 V input voltage. The lowest output error point moves towards higher load current by increasing the input voltage. In figure 5.32, the output error for the highest voltages shown is increasing sharply when there is no DC load, similarly to the lower selected outputs. Simulations show that the maximum input voltage, for which the regulator is still able to provide a regulated output voltage, is increasing with the output increment. Table 5.3 shows the maximum input voltage and the adequate output regulated voltage. It can be concluded from all previous simulation results that the output error increases (in a proportional way) when the voltage drop on the pass transistor is higher than 1.2 V and lower than 2.4 V. The simulation results also show that the regulator achieves an output regulated voltage with an error that is within the tolerable range when the voltage drop on the pass transistor is lower than 2.5 V. The reason behind the increment of the regulator’s output error for low input voltages is the pass transistor used during simulations. The threshold voltage of the thick-oxide transistor used in this case is 0.7 V; higher than that of core transistors. This causes a low drop out case for low input voltages. Since the pass transistor is NMOS, the voltage drop on the pass transistor Vds should be higher than the gate over drive voltage Vovn = VGS −VT HN in order to set the transistor’s state to ON. This explains the regulator’s inability to deliver an acceptable output voltage for the case of 1.8 V input voltage and 0.9 V output voltage. 5.6 Ctrl-bit Settings Simulations 75 Figure 5.31. The output error for input voltages between 1.8-2.1 V and DC-load between 0-50 uA, 0.8 V regulated voltage. Figure 5.32. The output error for input voltages between 2.1-3.4 V and DC-load between 0-50 uA, 0.8 V regulated voltage. 76 Simulation Results Selected voltage output 0.5 V 0.6 V 0.7 V maximum input voltage for which the output is regulated 2.7 V 2.9 V 3.0 V 0.8 V 3.1 V 0.9 V 3.3 V Comments Output error increases proportionally Output error increases proportionally Output error for 1.8 V input voltage is higher than 1.9 V input voltage Output error for 1.8 V is higher than previous case (0.7 V output voltage) Output error for 1.8 V is more than 5 % Table 5.3. The maximum input voltage versus the output voltage for which the regulator is still able to provide a good output regulated voltage. 5.7 Sleep Mode Simulations Sleep mode is a necessary feature for the smart dust application. It saves the battery power and increases the mote’s life time. Cutting/connecting the power is done through a switch. When there is no need for the mote to operate, the switch is switched off and the mote goes into sleep mode. The current consumption during the sleep mode should be zero according to the requirements. The switch used for the sleep mode is a transmission gate that is placed on the regulator’s input voltage line. The ctrl signal of the transmission gate is used to turn the sleep mode ON or OFF. In order to get back to normal mode from sleep mode, when there is no power going through the circuits of the mote, the ctrl signal should be independent from the input voltage. One solution is to add a power on reset circuit. The purpose of this circuit is to handle the ctrl signal until the regulator is able to take over again. The simulations that have been executed serve to check the current consumption when the sleep mode is ON and OFF. Figure 5.33 shows the current consumption of the regulator when the circuit is operating. The current consumption rises with the input voltage. The results are much higher than the required current consumption. Further work needs to be done to improve the current consumption of the regulator. Simulation results have been improved by tweaking the sizes of the transistors; other possible changes need to be investigated. Figure 5.34 shows the current consumption during sleep mode. The consumed current is a leaked current which is almost impossible to avoid. However, this current is insignificant compared to the actual current consumption. During simulations it was noticed that a better sleep mode current consumption is achieved if the ctrl signal is higher than the input voltage. 5.7 Sleep Mode Simulations 77 Figure 5.33. The current consumption for the regulator when Ctrl equals VDD. Figure 5.34. The current consumption for the regulator in sleep mode. 78 5.8 Simulation Results Power Down Simulations The purpose of the following simulations is to check the behavior of the regulator when the input voltage changes dramatically in a short time. Simulations have been done using vpwl voltage source, which is explained in section 5.4, as the input voltage. The input voltage changes from 1.9 V to 3.6 V at the specified time2. Figure 5.35 shows the output voltage signal during simulation with input voltage that changes periodically every 10µs. As seen in the figure the maximum change in the output voltage is 40 mV. Figure 5.35. The output voltage versus time during periodic VDD change every 10µs. Figure 5.36 shows the simulated output voltage result when the input voltage changes every 200µs with a pulse width of 1µs. The input voltage changes from 1.9 V to 3.6 V. As seen in the figure, the maximum drop in the output voltage is only 4 mV. This result can be explained by the regulator’s response to the changes in the input voltage; it is probably not fast enough to settle during 1µs. Hence, it can be concluded that the output voltage stays almost constant if a power in the mote dropped down for a short time. This guarantees safety for the other devices in the mote in cases of power fluctuations. 5.9 Corner Analyze Simulations 79 Figure 5.36. The output voltage versus time during VDD change with period of 200µs and a pulse width of 1µs. 5.9 Corner Analyze Simulations Corner analyze simulations were run in order to verify the regulator’s performance in different process variations. The transistor’ performance can differ depending on the process variations. Hence, the whole design could be affected by the process variations. Therefore running a number of simulations with different process cases makes it possible to estimate the potential effects of the process variations on the design. The results shown below are achieved during simulations with several combinations of three different transistor process variations: typical, slow and fast. In addition to the case where all transistors process is typical, there have been eight different simulations with eight different process variation possibilities that have been executed for this regulator design. Figures 5.37 to 5.45 show the output error against input voltage variations. The current pulled from the load is a full DC current and the selected output voltage is 0.9 V. The figures represent the following process variation combinations respectively: 1. Typical 2. Fast-Fast-Fast 3. Slow-Slow-Slow 4. Fast-Slow-Typical 5. Slow-Fast-Typical 80 Simulation Results 6. Fast-Slow-Slow 7. Slow-Fast-Slow 8. Fast-Slow-Fast 9. Slow-Fast-Fast Figure 5.37. The output error for full DC load in corner analyze typical case. Figure 5.38. The output error for full DC load in corner analyze fast-fast-fast case. As seen in the figures, the graphs differ according to the process variations. Table 5.4 shows the variation effect on the input voltage range, where the regulator is able to supply a regulated voltage within the acceptable range. Different behavior of the output error can be clearly seen for the fast-fast-fast case and the slow-slowslow case, where slow transistors improve the regulator performance for higher input voltages. 5.9 Corner Analyze Simulations 81 Figure 5.39. The output error for full DC load in corner analyze slow-slow-slow case. Figure 5.40. The output error for full DC load in corner analyze fast-slow-typical case. Figure 5.41. The output error for full DC load in corner analyze slow-fast-typical case. 82 Simulation Results Figure 5.42. The output error for full DC load in corner analyze fast-slow-slow case. Figure 5.43. The output error for full DC load in corner analyze slow-fast-slow case. Figure 5.44. The output error for full DC load in corner analyze fast-slow-fast case. 5.9 Corner Analyze Simulations 83 Figure 5.45. The output error for full DC load in corner analyze slow-fast-fast case. Corner analyze case Typical case Fast-fast-fast case Slow-slow-slow case Fast-slow-typical case Slow-fast-typical case Fast-slow-slow case Slow-fast-slow case Fast-slow-fast case Slow-fast-fast case The input voltage range for which the output is regulated 1.9 to 3.3 V 1.9 to 3.3 V 2.0 to 3.6 V 1.9 to 3.6 V 2.0 to 3.3 V 1.9 to 3.6 V 2.0 to 3.4 V 1.9 to 3.6 V 2.0 to 3.4 V Table 5.4. The corner cases and the respective input voltage range for which the regulator is still able to provide a good output regulated voltage. Chapter 6 Conclusion This chapter concludes the work and the investigation that has been done during this thesis. At the beginning, the achieved results are compared with the requirements. The comparison is followed by the final results that have been achieved during the work. To simplify the comparison between the simulation results and the requirements, the input voltage range for each simulation made in chapter 5 has been used to indicate the regulator’s performance. Table 6.1 shows each simulation type and the according input voltage range for which the regulator is able to deliver acceptable results according to the requirements. Simulation Type Requirement DC-load simulations AC-load simulations Transient response simulations Temperature changes simulations Ctrl-bit simulations Corner Analyze 0 to 50 µA 0 to 100 µA less than 10ms -20 to 70 C 0.5, 0.6, 0.7, 0.8 and 0.9 V All possible process variations The input voltage range for which the output is regulated 1.9 to 3.3 V 1.8 to 3.3 V 2.0 to 3.3 V 2.0 to 3.5 V 1.9 to 2.7 V 2.0 to 3.3 V Table 6.1. The simulation type and the respective input voltage range for which the regulator is still able to provide a good output regulated voltage. The input range for each of the simulations in the table is the range in which the regulator is able to fulfill the requirements. This means that this regulator design is able to fulfill all the requirements of the simulation types shown in the previous table within the input range 2 to 2.7 V. However, as mentioned before, it was not possible to use a core transistor as a driving transistor for the regulator and the driving transistor was substituted with a thick-oxide transistor. The current consumption was also significantly higher than the targeted current consumption. Based on these results, a final conclusion could be drawn as follows: 85 86 Conclusion During this thesis work, the design and implementation of an extreme low power regulator using 65-nm core transistors has been investigated. In chapter 3.2 it has been shown that using core transistors has several advantages, especially when it comes to chip manufacturing, which made it attractive for the smart dust project. However, as seen in the design, it was not possible to use a core transistor as the driving transistor in the regulator, due to the relatively large range of the specified input voltage. The simulation results, which have been achieved with a thick-oxide driving transistor, have also shown that a regulated voltage was obtained for a smaller input voltage range than the specified input voltage range in the requirements. It is widely known in the analog design world that there is no perfect solution. In the power supply cook book it is said: "The engineer’s motto to life is 'Life is a tradeoff' and it comes into play here. It is impossible to design a power supply system that meets all the requirements that are initially set out by the other engineers and management and keep it within cost, space, and weight limits. The typical initial requirement of a power supply is to provide infinitely adaptable functions, deliver kilowatts within zero space, and cost no money. Obviously, some compromise is in order." Therefore, there should be a case study for the smart dust project to check the possibility of reducing the requirements on the regulator while having a better performance battery, or changing the regulator design. Cost, area, power consumption and the other factors must be considered on general basis to reach the most suitable solution for the project. Chapter 7 Future Work Based on the conclusion of this thesis work, the suggested design does not meet all the requirements, yet it could be used in the smart dust project if the following points are taken into consideration as a future work: • The general project requirements must be reviewed, and the possibility of changing the requirements should be considered in order to make a decision wether this regulator design is going to be implemented. After all, it is not uncommon to change the requirements when it comes to power supply design. It might be better in some cases to change some of the requirements rather than changing the whole regulator design. • Once the requirements have been negotiated and it has been decided to select this design, improving the design performance to meet the new requirements should be the next step. Improvements can be started by further trying to tune the transistors’ sizes, which can notably improve the results. More specifically the transistor sizes must be optimized to reduce the current consumption. Even though the number of parameters to be changed is relatively high, optimizing the transistors’ sizes, if the requirements are edited, can highly improve the circuit’s performance. • The power on reset circuit that is needed to supply the voltage of the ctrl signal on startup needs to be implemented in order to enable sleep mode feature for the mote. • The bandgap reference circuit is an important part of the power management design. The required reference voltage used for this design is 0.3 V. Although it was considered during the design that the bandgap reference circuit could introduce an error in the output voltage that is up to 5%, simulations should preferably be run with a transistor level bandgap reference circuit. • The ideal current source used during simulations should be implemented on transistor level since the current source circuit can significantly affect the simulation results. 87 88 Future Work • A big number of simulations have been executed during this thesis work. However, more simulations and more test cases are required in order to assure that the results are as close as possible to the real time performance. • When the whole regulator circuit has been implemented and simulated on transistor level including the sub-circuits, then the layout level of the design should be the next step towards producing the real time chip. Layout design can be very challenging and requires good analog design experience. Mainly because the circuit contains a lot of cascoded current mirrors, transmission gates and other components that produce further complications on the layout level. Finally, combining other systems of the smart dust mote and simulating on a layout level provides the most precise results before the mote is manufactured and tested on a real time level. Bibliography [1] K. S. J. Pister, “Smart dust-hardware limits to wireless sensor networks,” in Distributed Computing Systems, 2003. Proceedings. 23rd International Conference on, p. 2, 2003. ID: 1. [2] B. W. Cook, S. Lanzisera, and K. S. J. Pister, “Soc issues for rf smart dust,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1177–1196, 2006. ID: 1. [3] P. F. Gorder, “Sizing up smart dust,” Computing in Science & Engineering, vol. 5, no. 6, pp. 6–9, 2003. ID: 1. [4] S. Bazarjani, L. Mathe, D. Yuan, J. Hinrichs, and G. Miao, “High-voltage lowpower analog design in nanometer cmos technologies,” in Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM ’07. IEEE, pp. 149–154, 2007. ID: 1. [5] J. Gjanci and M. Chowdhury, “Investigating issues of on-chip voltage regulator in nanoscale integrated circuits,” in Microelectronics, 2008. ICM 2008. International Conference on, pp. 123–126, 2008. ID: 1. [6] K. Swan, “What are voltage regulators?.” [7] K. A. Kuhn, “Introduction to voltage regulators,” 2009. [8] M. Brown, Power Supply Cookbook. Elsevier Newnes, 2001. Compilation and indexing terms, Copyright 2012 Elsevier Inc. [9] G. A. Rincon-Mora, “current efficient, low voltage, low dropout regulators,” 1996. [10] M. K. Kazimierczuk, Pulse-width Modulated DC-DC Power Converters. United Kingdom: John Wiley & Sons, Ltd, september 2008 ed. [11] R. J. Baker, CMOS : circuit design, layout, and simulation. Hoboken, N.J: IEEE Press/Wiley, 3rd ed. ed., 2010. [12] A. J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-v i/o in a 2.5-v 0.25-μm cmos technology,” Solid-State Circuits, IEEE Journal of, vol. 36, no. 3, pp. 528–538, 2001. ID: 1. 89 90 Bibliography [13] B. Razavi, Design of analog CMOS integrated circuits. Singapore: McGrawHill Education, 2001. [14] D. Johns and K. W. Martin, Analog integrated circuit design. New York: Wiley, cop., 1997. [15] M. I. Products, “What is a transmission gate (analog switch)?,” 2008. [16] R. G. Raghavendra, “A low power, moderate accurate, single stage driver circuit for on-chip voltage regulator,” in Circuits and Systems, 2005. 48th Midwest Symposium on, pp. 1798–1801 Vol. 2, 2005. ID: 1. [17] R. Wies, B. Satavalekar, A. Agrawal, J. Mahdavi, A. Agah, A. Emadi, and J. S. Daniel, DC-DC Converters. The Power Electronics Handbook, CRC Press, 11/20; 2012/05 2001. 11; M1: 0; doi:10.1201/9781420037067.pt2; M3: doi:10.1201/9781420037067.pt2. Appendix A Permission of using the photo of the Mica mote The photo of the Mica mote (figure 1.1) was taken from the authors of [2]. Many thanks to Steven Lanzisera for replying my email request about a permission for using the photo, he has provided me with the original colored photo to use it in my thesis. He wrote: "The copyright is held be IEEE for those figures, so we can’t give permission for you to reuse them. However, you can use the original image that we provided to IEEE because it is in color. See attached." 91