Transcript
Institutionen för systemteknik Department of Electrical Engineering Examensarbete
A Study on QPSK Modulator Architectures for Ultra Low Power Transmitters Examensarbete utfört i Elektroniska komponenter vid Tekniska högskolan i Linköping av Per Eidenvall, Nils Gran LiTH-ISY-EX--10/4357--SE Linköping 2010
Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden
Linköpings tekniska högskola Linköpings universitet 581 83 Linköping
A Study on QPSK Modulator Architectures for Ultra Low Power Transmitters
Examensarbete utfört i Elektroniska komponenter vid Tekniska högskolan i Linköping av Per Eidenvall, Nils Gran LiTH-ISY-EX--10/4357--SE
Handledare:
Atila Alvandpour , Linköpings universitet
Examinator:
Atila Alvandpour , Linköpings universitet
Linköping, 22 November, 2010
Avdelning, Institution Division, Department
Datum Date
Division of Electronic Devices Department of Electrical Engineering Linköpings universitet SE-581 83 Linköping, Sweden
2010-11-22
Språk Language
Rapporttyp Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete C-uppsats D-uppsats
— LiTH-ISY-EX--10/4357--SE Serietitel och serienummer Title of series, numbering
Övrig rapport
ISSN —
URL för elektronisk version http://www.ek.isy.liu.se http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-62656
Titel Title
Författare Author
A Study on QPSK Modulator Architectures for Ultra Low Power Transmitters
Per Eidenvall, Nils Gran
Sammanfattning Abstract Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids and drug delivery systems are increasingly more important and frequently used in the health care system. This type of devices have historically used inductive coupling as communication medium. New demands on accessibility and increased performance in technology drives new research toward using radio communications. The FCC MICS radio standard are specifically devoted for implantable devices. Basically all published research on transmitters in this area are using frequency shift keying (FSK) modulation. The purpose of this thesis is to explore the viability of using phase shift keying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.
Nyckelord Keywords
Ultra Low Power, MICS, PSK, QPSK, Radio Transmitter, QPSK Modulator
Abstract Today, medical implants such as cardiac pacemakers, neurostimulators, hearing aids and drug delivery systems are increasingly more important and frequently used in the health care system. This type of devices have historically used inductive coupling as communication medium. New demands on accessibility and increased performance in technology drives new research toward using radio communications. The FCC MICS radio standard are specifically devoted for implantable devices. Basically all published research on transmitters in this area are using frequency shift keying (FSK) modulation. The purpose of this thesis is to explore the viability of using phase shift keying (PSK) modulation in ultra low power transmitters and suggest suitable architectures.
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Acknowledgments We would like to thank: Atila Alvandpour, Professor Håkan Bengtsson at Zarlink Semiconductor Inc. Amin Ojani, Ph.D. student Jonas Fritzin, Ph.D. student Johan Bengtsson for their help in this thesis Per Eidenvall and Nils Gran
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Contents Abbreviations and Acronyms 1
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Introduction 1.1 Purpose . . . . . . . . . . . . . . . 1.2 Background . . . . . . . . . . . . 1.3 Goal . . . . . . . . . . . . . . . . . 1.4 Method . . . . . . . . . . . . . . . 1.5 Delimitations . . . . . . . . . . . 1.5.1 High Level Architectures 1.5.2 Mixer-Less Architectures 1.5.3 MICS Standard . . . . . . 1.6 Tools . . . . . . . . . . . . . . . . 1.7 Report Outline . . . . . . . . . . .
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1 1 1 2 2 2 2 3 3 3 3
Related Theory 2.1 Quadrature detection . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Spectrum, Power and Data Rate . . . . . . . . . . . . . . . . . . . 2.2.1 Power and Bit Error Rate . . . . . . . . . . . . . . . . . . 2.2.2 Theoretical limits on data rate . . . . . . . . . . . . . . . . 2.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Minimum Tone Spacing for Orthogonal FSK . . . . . . . . . . . 2.4.1 Orthogonal FSK and Coherency . . . . . . . . . . . . . . 2.4.2 Alternative Approach to non-Coherent Orthogonal FSK 2.5 Spectral Regrowth Issues . . . . . . . . . . . . . . . . . . . . . . . 2.6 Constant Envelope . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6.1 Frequency Modulation . . . . . . . . . . . . . . . . . . . . 2.6.2 Phase Modulation . . . . . . . . . . . . . . . . . . . . . .
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A Brief Overview of Current Architectures 3.1 A Brief Overview . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Distributed Frequency Correction . . . . . . . . . . 3.1.2 Frequency Multiplying Power Amplifier . . . . . . 3.1.3 Direct VCO Modulation Using Low Supply Voltage 3.2 65 nm Designs . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Concluding Summary . . . . . . . . . . . . . . . . . . . . .
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Contents The MICS Standard and PSK Bandwidth Efficiency Issues 4.1 MICS Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 MICS Transmitter from Paragraph §95.628 . . . . . . . 4.1.2 Emission Types from Paragraph §95.631 . . . . . . . . . 4.1.3 Emission bandwidth from Paragraph §95.633 . . . . . . 4.1.4 Unwanted Radiation from Paragraph §95.635 . . . . . 4.1.5 Maximum Transmitted Power from Paragraph §95.639 4.1.6 Additional Power Constraint from Paragraph §95.649 . 4.1.7 Crystal Control Requirements from Paragraph §95.651 4.1.8 Resulting Spectral Mask . . . . . . . . . . . . . . . . . . 4.2 PSK Bandwidth Efficiency Issues . . . . . . . . . . . . . . . . .
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Testbenches 5.1 Detectors . . . . . . . 5.1.1 PSK Detector 5.1.2 FSK Detector 5.2 Measurements . . . . 5.3 Test Methodology . .
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Designed Architectures 6.1 PSK Modulators . . . . . . . . . . . . . . . . . . . . 6.1.1 Simple QPSK . . . . . . . . . . . . . . . . . 6.1.2 PLL Based QPSK Modulation . . . . . . . . 6.1.3 PLL Based QPSK Modulation with Dither . 6.1.4 Direct Multiplexing . . . . . . . . . . . . . . 6.2 FSK Modulator . . . . . . . . . . . . . . . . . . . .
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Simulation Results 7.1 Overview . . . . . . . . . . . . . . . . . . . 7.2 Unfiltered QPSK . . . . . . . . . . . . . . . 7.3 PLL Based QPSK Modulation . . . . . . . 7.4 PLL Based QPSK Modulation with Dither 7.5 Direct Multiplexing . . . . . . . . . . . . .
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Conclusion 8.1 Evaluating the Results . . . . . . . . . . . 8.1.1 PLL Based Modulator . . . . . . . 8.1.2 PLL Based Modulator with Dither 8.1.3 Direct Multiplexing . . . . . . . . . 8.2 Final Conclusion . . . . . . . . . . . . . .
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Contents
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List of Tables 3.1 3.2 3.3 3.4
Summary of power consumption. . . . . . . . . . . . . . . . . . . . Overview of ten ultra-low power radio transmitters. . . . . . . . . Ten ultra-low power radio transmitters ordered by energy per bit. PA efficiency for ultra-low power transmitters. . . . . . . . . . . .
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4.1
Attenuation of signal 250 kHz outside the MICS band. . . . . . . .
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6.1
Parameter values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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8.1
Additional hardware needed in PSK modulation. . . . . . . . . . .
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Contents
List of Figures 2.1 2.2
2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14
Quadrature detector block diagram. . . . . . . . . . . . . . . . . . . Examples of IQ-diagram. a) Constellation diagram, b) Transition diagram, c) Constellation diagram with phase shift, d) Constellation diagram of 16-QAM and e) Constellation diagram of 16-QAM with gain compression. . . . . . . . . . . . . . . . . . . . . . . . . . . Illustration of the interdependency between power, bandwidth and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quadrature PSK architecture using Raised Cosine pulse shaping. . BER for BPSK, QPSK, coherent BFSK and non-coherent BFSK as a function of Eb /n0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BER for multi-valued FSK and PSK . . . . . . . . . . . . . . . . . . . Second order PLL with charge pump. . . . . . . . . . . . . . . . . . Minimum frequency separation for non-coherent FSK signaling. . . Low-pass time domain filtering of the baseband signal. . . . . . . . Unfiltered and filtered QPSK waveforms. . . . . . . . . . . . . . . . Analog frequency modulation waveform. . . . . . . . . . . . . . . . Discontinuous and continuous FSK waveforms . . . . . . . . . . . . Continuous and discontinuous phase architectures. . . . . . . . . . Constellation diagrams of QPSK, π/4-DQPSK, OQPSK and MSK . .
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3.1 3.2 3.3 3.4
DCO based transmitter with distributed frequency correction. Transmitter based on a frequency multiplying edge combiner. Direct VCO modulated transmitter. . . . . . . . . . . . . . . . . 65 nm weak inversion MICS receiver. . . . . . . . . . . . . . . .
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4.1 4.2 4.3
In band frequency mask for MICS standard . . . . . . . . . . . . . . QPSK and MSK Spectrum . . . . . . . . . . . . . . . . . . . . . . . . Unfiltered QPSK spectra using RBW of 3 kHz. . . . . . . . . . . . .
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PSK demodulator block diagram. . . . . . . . . . . . . . . . . . . . . Block diagram of non-coherent FSK demodulator . . . . . . . . . . Signal after mixer stage. . . . . . . . . . . . . . . . . . . . . . . . . . Eye diagram used for timing of reset and sample-and-hold control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test methodology for determining the SNR given a certain data rate.
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Switch based QPSK with discontinuous output. . . . . . . . . . . . Basic PLL architecture modified with quadrature feed back. . . . . Basic PLL architecture with quadrature feed back. . . . . . . . . . . Functional block diagram over the shaping logic. . . . . . . . . . . . Direct multiplexing between multiple phases. . . . . . . . . . . . . . How symbol changes are performed when only one (a) or both (b) bits are changed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FM modulator based FSK architecture. . . . . . . . . . . . . . . . . .
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2.3 2.4 2.5
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Contents Plot of the Eb /n0 , the ratio between required energy per bit and the single ended thermal noise, using the bandwidth containing 98% of the signal power. The gray bands represent the theoretical Eb /n0 for coherent and non-coherent FSK. . . . . . . . . . . . . . . . . . . . 7.2 IQ and phase diagram for simple QPSK architecture, phase diagram for a data rate of 80 kbit/s. . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Frequency spectrum of QPSK transmitted at 80 kbit/s. . . . . . . . . 7.4 IQ and phase diagram for PLL architecture, phase diagram for a data rate of 150 kbit/s. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Frequency spectrum of the PLL-shaped QPSK signal. . . . . . . . . 7.6 IQ and phase diagram for PLL with dither based architecture, phase diagram for a data rate of 250 kbit/s. . . . . . . . . . . . . . . . . . . 7.7 Ramp-up ratio for PLL based modulation with dither. . . . . . . . . 7.8 Frequency spectrum of the PLL- and dither-shaped QPSK signal. . 7.9 IQ and phase diagram for direct multiplexing architecture, phase diagram for a data rate of 250 kbit/s. 4 intermediate steps are shown in (a) and (b) and 8 are shown in (c) and (d). . . . . . . . . . 7.10 Ramp-up ratio for the direct multiplexing architectures. . . . . . . . 7.11 Frequency spectrum for the direct multiplexing architectures. . . .
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7.1
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Graph showing what data rates could be considered for which architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Abbreviations and Acronyms
Abbreviations and Acronyms Acronyms ADS AWGN bps CB Radio Coherent detection CPFSK CPM DCO DQPSK EIRP FLL FRS FSK FSM GMSK I LO LPRS MICS MSK MURS OQPSK PA PFD PLL PSK Q QAM QPSK R/C RBW RF ROM SNR VCO WMTS
Explanation Advanced Design System (Agilent) Additive White Gaussian Noise Bit Per Second Citizens Band Radio Phase aligned- or synchronized detection Continuous Phase Frequency Shift Keying Continuous Phase Modulation Digital Controlled Oscillator Differential Quadrature Phase Shift Keying Equivalent Isotropically Radiated Power Frequency Locked Loop Family Radio Service Frequency Shift Keying Finite State Machine Gaussian Minimum Shift Keying In-phase Signal Local Oscillator Low Power Radio Service Medical Implantable Communications System Minimum Shift Keying Multi-Use Radio Service Offset Quadrature Phase Shift Keying Power Amplifier Phase Frequency Detector Phase Locked Loop Phase Shift Keying Quadrature Signal Quadrature Amplitude Modulation Quadrature Phase Shift Keying Radio Control (also Radio Control Radio Service) Resolution Bandwidth Radio Frequency Read Only Memory Signal to Noise Ratio Voltage Controlled Oscillator Wireless Medical Telemetry Service
Chapter 1
Introduction This chapter presents the introduction of the thesis. The introduction describes the purpose, background, goal, method and delimitations and gives a report outline.
1.1
Purpose
The division of Electronic Devices at the Department of Electrical Engineering at the Linköping University has a long history of researching and working with high-speed and low power CMOS devices. Recently the division has turned focus toward ultra-low power radio transmitters used in e.g. medical implants. Today basically all published research on transmitters in this area are using frequency shift keying (FSK) modulation. The purpose of this thesis is to explore the viability of using phase shift keying (PSK) modulation in ultra-low power transmitters and suggest suitable architectures.
1.2
Background
Today medical implants such as cardiac pacemakers, neurostimulators, hearing aids and drug delivery systems are increasingly more important and frequently used in the health care system. The implant must be able to communicate with the outside world to enable evaluation and configuration of its performance and to study medical events that a patient is experiencing or has experienced. Traditionally communication, i.e. transmission of information, was carried out by magnetic coupling1 [19]. With magnetic coupling a reader/transmitter head must in general be placed directly on the patients skin in the absolute proximity of the implant. The reading of data from the device takes relative long time. The data rate could range about 50 kbit/s [19] over a distance of only a few inches. The benefit of using magnetic coupling is the relatively low power consumption. 1 Also
often referred to inductive coupling.
1
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Introduction
Today new demands on accessibility and advances in technology drive the attention toward radio transmission instead of magnetic coupling. Radio has the benefit of higher data rates and longer transmission distances. Radio is not affected by electromagnetic interference which inductive coupling is. Thereby the safety of the patient is improved. The major challenge is however to achieve the same low power consumption as the magnetic coupling. Because of the difficulty of changing or recharging the power source of medical implants, the power consumption is a major issue.
1.3
Goal
The goals of this thesis are: 1. Provide a summary on current ultra-low power transmitters for the MICS standard in terms of modulation scheme, power consumption, data rate and output power. 2. Suggest high level, mixer-less, PSK architectures relevant for future work. 3. Describe the benefits and drawbacks of using PSK in ultra-low power transmitters used in compliance with the MICS standard.
1.4
Method
In order to achieve the goals presented in the previous section 1.3, a method has been designed. The method is divided into the following three phases. Phase 1: Perform a literature study on current ultra-low power designs to gather specifications and give inspiration for new ideas to be used in the next phase. The study should be based on the most relevant IEEE papers. Phase 2: Design and implement mixer-less high level phase shift keying architectures for computer simulations in ADS. Phase 3: Simulate and evaluate the implemented PSK architectures.
1.5 1.5.1
Delimitations High Level Architectures
This thesis is restricted to the investigation and design of high level phase-shiftkeying architectures for simulation in ADS viable for ultra-low power operation. Hence, this thesis does not give any suggestions or examples of on chip implementations. This is left for future work.
1.6 Tools
1.5.2
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Mixer-Less Architectures
At the beginning of the work a decision was made to focus on mixer-less architectures. Mixers typically require linear signal paths both at their inputs and outputs when used in PSK transmitters with phase shaping. This also affects the power consumption of the power amplifier since linear PA:s tends to consume more power than their non-linear counterpart. Mixers were also recognized as a main contributor to the global power consumption. For these reasons it was decided to narrow the field and focus on mixer-less architectures.
1.5.3
MICS Standard
The MICS standard has become the major radio standard for medical implants since FCC introduced it in 1999 (see chapter 4). Most current papers on ultra-low power radio transmitters for medical implants states that they conform to the MICS standard to some degree. This thesis will for this reason focus primarily on PSK transmitters complying with the MICS standard.
1.6
Tools
The following tools has been used during the work: ADS 2009 Advanced System Design from Agilent has been the main tool during the work. All architectural models have been designed and simulated in ADS. Ptolemy functional blocks, i.e. blocks from the DSP design type, have been used when possible in order to minimize simulation time. Matlab 7.7.0 (R2008b) Matlab has been used for verifying our models used in ADS and calculating appropriate input parameters. Matlab has also been used to generate many of the plots in the thesis. Appart from standard functions, functions from the System Toolbox have been used.
1.7
Report Outline
Chapter 1 presents the introduction of the thesis. The introduction describes the purpose, background, goal, method and delimitations and gives a report outline. Chapter 2 cover some of the basic theory related to this thesis. The chapter discuss: common trade-off issues in radio frequency (RF) design related to bandwidth, power and data rate; frequency synthesis using charge pump based phase locked loops; minimum tone spacing in FSK systems; spectral regrowth issues and constant envelope behavior. The chapter is foremost intended for the novice RF reader.
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Introduction
Chapter 3 presents an overview of ten low-power transmitters, a description of the three most power-efficient architectures and a short discussion on using 65 nm technology in MICS applications. Chapter 4 presents a summary of the Medical Implantable Communications Service (MICS) radio standard introduced by Federal Communications Commission (FCC). It also points out bandwidth efficiency issues for PSK modulation complying to the MICS standard, which will be a major challenge throughout the thesis. Chapter 5 describes the two testbenches used during simulations, the available measurements and the test methodology. Chapter 6 presents the architectures designed and simulated during the thesis. A short description of the idea leading up to each architecture is also given along with some brief details of the implementation. Chapter 7 summarizes the performance of the simulated architectures. The presented measurements includes: phase- and IQ-transition characteristics; Eb /n0 and ramp up ratio for different data rates. Conclusions from the results are discussed in chapter 8. Chapter 8 presents the conclusions made from the simulations and the overview of architectures presented in chapter 3.
Chapter 2
Related Theory This chapter cover some of the basic theory related to this thesis. The chapter discuss: common trade-off issues in radio frequency (RF) design related to bandwidth, power and data rate; frequency synthesis using charge pump based phase locked loops; minimum tone spacing in FSK systems; spectral regrowth issues and constant envelope behavior. The chapter is foremost intended for the novice RF reader.
2.1
Quadrature detection
One common QPSK receiver architecture is the quadrature detector, see figure 2.1. The received signal is down converted by a mixer using a phase aligned oscillator. Using the trigonometric function cos(a − b) + cos(a + b) 2 the output from the upper mixer in figure 2.1 will be cos(a) cos(b) =
cos([ωt + ϕ] − [ωt]) + cos([ωt + ϕ] + [ωt]) 2 cos(ϕ) + cos(2ωt + ϕ) = 2
(2.1)
cos(ωt + ϕ) cos(ωt) =
(2.2)
and in the same way the output from the lower mixer will be cos(ϕ + π/2) + cos(2ωt + ϕ + π/2) 2 sin(ϕ) + sin(2ωt + ϕ) = 2
cos(ωt + ϕ) cos(ωt + π/2) =
(2.3)
The output from the mixers hence contain one high frequency component and one DC component proportional to the phase of the incoming signal. Since 5
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Related Theory
in phase-modulation, the data is carried in the phase of the transmitted signal the high frequency component is filtered out with a low pass filter. The DC component is then integrated over one symbol time to filter out noise added by the channel before it is sampled and converted into a digital value.
I {0,1}
LO
Reset
Sample&hold
+90° Q {0,1}
Figure 2.1: Quadrature detector block diagram.
IQ diagram IQ diagrams can be useful when evaluating radio systems and will be used in this thesis to evaluate the simulated architectures. An IQ diagram consist of the I and Q values for the demodulated signal. The I value is typically represented by the x-axis and the Q value by the y-axis. If the signal is sampled at discrete symbol times, the diagram will contain the constellation diagram in figure 2.2 (a). If the signal is sampled and plotted continuously the IQ diagram will also contain the transitions between the constellation points as in figure 2.2 (b). The diagram can show if the transmitter and receiver are not phase aligned as in figure 2.2 (c) and can help when aligning them. IQ diagrams can also be used to view other modulation schemes beside QPSK, see figure 2.2 (d) where the diagram contain the constellation of 16-QAM. It is also possible to view the effect of gain compression in the constellation, see figure 2.2 (e).
(a)
(b)
(c)
(d)
(e)
Figure 2.2: Examples of IQ-diagram. a) Constellation diagram, b) Transition diagram, c) Constellation diagram with phase shift, d) Constellation diagram of 16-QAM and e) Constellation diagram of 16-QAM with gain compression.
2.2 Spectrum, Power and Data Rate
2.2
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Spectrum, Power and Data Rate
The performance of radio communication systems are limited by the available frequency spectrum, power supply and the data rate. These three components are interdependent, hence improving one parameter results in the deterioration of one or both of the other parameters. Maintaining this interdependency without violating any given specification is a major design challenge in radio communication systems.
Power
Bandwidth
Data rate
Figure 2.3: Illustration of the interdependency between power, bandwidth and data rate. The majority of the power consumption in radio transmitters are usually caused by the operation of the power amplifier. This is not necessarily the case in ultra-low power transmitters since the relative output power is very low1 compared to common transmitters at higher power levels. The global efficiency deteriorates at these lower signal powers due to the frequency generation and modulation overhead starts to compete with power amplifier dissipation. For this reason special care has to be taken in the design of the frequency synthesis and base band modulation in order to maintain an “ultra” low global power consumption. Hence common competitive transmitter architectures like e.g. the Quadrature Raised Cosine architecture depicted in figure 2.4 are likely to suffer from poor global efficiency when used in ultra-low power applications due to its reliance on linear mixers.
2.2.1
Power and Bit Error Rate
The probability of bit error is directly determined by the signal-to-noise ratio (SNR). A larger signal-to-noise ratio reduces the error probability and vice versa. SNR =
Signal Power S = Noise Power N
(2.4)
The error probability is however usually not expressed in terms of signal-tonoise ratio but in terms of energy per bit to the single ended thermal noise density i.e. Eb /n0 . The relation between Eb /n0 and SNR is given by equation (2.5) [7]. 1 Maximum
EIRP at 3 meter distance is according to the MICS standard 25 µW or -16 dBm.
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Related Theory I: {-1,1}
Spectrum Analyzer Sine LO Cosine
+90°
delay Q: {-1,1}
Figure 2.4: Quadrature PSK architecture using Raised Cosine pulse shaping.
Eb S B STb SB = = = n0 n0 Rb n0 B N Rb
(2.5)
Where Tb is the bit time, Rb = 1/Tb is the bit rate and B denotes the bandwidth in Hz. The bit error probability for PSK is given by equation (2.6) [7, 6]. Most PSK modulation schemes requires coherent (phase aligned) detectors2 . Equation (2.6) is true for coherent PSK detection3 . r ! 2Eb Pe_PSKcoherent ' erfc (2.6) n0 Bit error probability for coherent BFSK is given by equation (2.7) [6] and equation (2.8) [6] gives the bit error probability for non-coherent BFSK. r Eb 1 Pe_BFSKcoherent ' erfc (2.7) 2 2 Es 1 exp − (2.8) 2 2 Non-coherent detection is often used in FSK applications since it require a less complex receiver. However, the required signal power for coherent detection is lower than for non-coherent detection. Coherent BFSK requires approximately 1.5 dB less signal power than non-coherent BFSK for any given bit error rate (BER). The signal power could be reduced even further with BPSK modulation. The total reduction using BPSK is approximately 4.5 dB compared to non-coherent BFSK and approximately 3 dB compared to coherent BFSK. The bit error rates are plotted as a function of Eb /n0 in figure 2.5. Quadrature PSK is a commonly used form of PSK modulation4 . It has a slightly worse SNR but offers higher data rates. Pe_BPFSKnon−coherent '
2 Some
differential PSK schemes are demodulated by non-coherent detectors [7]. error probabilities in this chapter are calculated for AWGN type channels. 4 Bit error probability for QPSK is given in equation 2.14. 3 All
2.2 Spectrum, Power and Data Rate
9
QPSK needs an Eb /n0 ratio of 8.46 dB when BPSK has an Eb /n0 ratio of 8 dB in order to maintain the same BER. The difference in required SNR between BPSK and QPSK decreases as the SNR increases. BPSK QPSK Coherent FSK Non−coherent FSK
−2
Bit Error Rate
10
−4
10
−6
10
−8
10
2
4
6
8 Eb/no (dB)
10
12
14
Figure 2.5: BER for BPSK, QPSK, coherent BFSK and non-coherent BFSK as a function of Eb /n0
2.2.2
Theoretical limits on data rate
In most cases higher data rates also means a higher bit error rate and wider bandwidth. Hence, bandwidth and bit error rate limits the data rate. In the section below about the Shannon Capacity Theorem the theoretical limit on data rate is discussed in terms of bandwidth efficiency. A discussion on how data rate affects the bit error rate for FSK and PSK modulation is presented in the section below about maximum data rates. Shannon Capacity Theorem The bandwidth efficiency is a major criteria when selecting modulation schemes. Bandwidth efficiency is measured in bps/Hz and is defined by equation (2.9) [7] ηBW =
RB BW
bps/Hz
(2.9)
10
Related Theory
, where RB is the bit rate transmitted over an AWGN channel and BW is the channel bandwidth in Hz. The Shannon Capacity Theorem gives the theoretical maximum capacity, i.e. the maximum bandwidth efficiency, of a channel for a given bandwidth and signal-to-noise ratio. The theorem is given in equation (2.10) [7] ηBWmax
Signal Power C = log2 1 + = BW Noise Power
! bps/Hz
(2.10)
, where C is the channel capacity in bps. C is also often referred to as the Shannon Limit. Maximum data rates Determining the relationship between data rate and bandwidth could lead to a quite lengthy discussion about the definition of bandwidth and how to appropriately address base band filtering techniques. The following equations (2.11) and (2.12) are presented without any further discussion on these issues. The equations provides a good basis for discussion about the trade-offs of multi-valued modulation schemes [21]. log2 (M) RB_MFSK = BT (1 + r)M
(2.11)
log2 (M) RB_MPSK = BT 1+r
(2.12)
Equations (2.11) and (2.12) give the bandwidth efficiency for multivalued FSK and PSK [21]. M denotes the number of symbols used in the modulation scheme and each symbol represents log2 (M) number of bits. BT denotes the transmission bandwidth in Hz, RB is the bit rate in bps and r is a constant related to the filtering technique and is typically in the range between 0 and 1. Describing bandwidth efficiency as a function of the number of symbols (M) used in the modulation scheme gives opposite behavior for FSK and PSK modulation. The bandwidth efficiency for PSK modulation is improved when M is increased while the bandwidth efficiency is decreased for FSK modulation. Describing the bit error probability as a function of the number of symbols also gives opposite behavior for PSK and FSK. Combining equations (2.7) and (2.13) with figure 2.6 (a) visualizes that the FSK bit error rate is improved when the number of symbols (M) is increased. Equations (2.6), (2.14) and (2.15) gives the behavior of the bit error rate for PSK modulation schemes illustrated in figure 2.6 (b). The bit error rate for PSK modulation is increased when the number of symbols (M) is increased. s Pe_MFSK '
M−1 erfc 2
Eb log2 (M) 2n0
,M > 2
(2.13)
2.3 Phase Locked Loop
11
Bit error probability
0
10 2 FSK 4 FSK 8 FSK
−1
10
−2
−2
Bit Error Rate
Bit Error Rate
10
−3
10
−4
10
−5
−3
10
−4
10
−5
10
10
−6
−6
10
10
−7
2
BPSK QPSK 8−PSK
−1
10
10
10
Bit error probability
0
10
−7
4
6
8 10 Eb/no (dB)
12
14
10
2
(a) Multilevel FSK (MFSK)
4
6
8 10 Eb/no (dB)
12
14
(b) Multilevel PSK (MPSK)
Figure 2.6: BER for multi-valued FSK and PSK
r Pe_QPSK ' erfc
Pe_MPSK ' erfc
r " # Eb Eb 1 1 − erfc n0 4 n0
(2.14)
Eb log2 (M) n0
(2.15)
s ,M > 4
To conclude this discussion, PSK architectures can improve the bandwidth efficiency by increasing the number of symbols, at the expense of a deteriorated bit error probability. In contrast, when increasing the number of symbols used by a FSK architecture, the bandwidth efficiency is deteriorated while the bit error rate is improved.
2.3
Phase Locked Loop
Phase locked loops are a common type of architecture in frequency synthesizers. Phase locked loops are able to lock the output frequency to a reference frequency by using a negative feedback loop. The ratio between the output frequency and the reference frequency is determined by placing a frequency divider in the feedback loop, thus providing a frequency synthesizer. A phase-frequency detector compares the divided frequency with the reference frequency and regulates the voltage level at the input of the voltage controlled oscillator. A stable and accurate output frequency is often achieved by using a crystal oscillator for the reference frequency. There are several types of frequency dividers. The simplest type is the integer-N divider that divides the output frequency by an integer N. Frequency
12
Related Theory
modulation can be achieved by altering the division ratio of the frequency divider5 . A second order PLL is characterized by its use of a first order low pass filter at the input to the VCO. Second order indicates that the closed loop transfer function is of second order. Phase discontinuities during FSK and PSK modulation are unwanted since it causes spectral regrowth. This is however not a major concern when using a PLL for modulation since the phase of the signal at the VCO output is always continuous.
Ip
fref
PFD
VCO Rp Ip
Cp
C2
Div. Figure 2.7: Second order PLL with charge pump. A closed loop transfer function of a second order PLL can be expressed as in equation (2.16). HCL (s) =
K(s + α) + Ks + α
s2
(2.16)
An advantage using second order PLLs is the similarity to other common physical systems. Basic knowledge from control theory can be used to express the transfer function in terms of natural frequency ωn and dampening factor ζ as can be seen in equation (2.17). HCL (s) =
2ζωn (s +
ωn 2ζ )
s2 + 2ζωn + ω2n
(2.17)
The following two equations hold for the second order PLL depicted in figure 2.7 [17]. 5 There are of course more ways to produce frequency modulation with an PLL not discussed in this thesis.
2.4 Minimum Tone Spacing for Orthogonal FSK
s ωn =
ζ=
Rp 2
13
Ip
KVCO 2πCP M r
(2.18)
Ip Cp KVCO 2π
(2.19)
M
The 3 dB cut-off frequency can be expressed in ζ and ωn as follows in equation (2.20). The equation can be derived from (2.17), (2.18) and (2.19). s f3dB = ωn
r 2ζ2 + 1 ± 2ζ
ζ2 + 1 +
, 1 2π 2ζ2
(2.20)
The step response is proportional to the inverse exponential of ζωn and can be expressed as in equation (2.21). The equation is derived by applying a unit step to the closed loop transfer function in (2.17) " fresponse (t) = ∆ω 1 − e
−ζωn t
#! p p ζ 2 2 sin(ωn 1 − ζ t) cos(ωn 1 − ζ t) − √ 1 − ζ2
(2.21)
The cut-off frequency and frequency response gives the main properties of a PLL. The maximum symbol rate is limited by the cut off frequency in the case where the modulation occurs within the frequency loop. A higher cut-off frequency enables higher symbol rate but with the cost of a higher settling time. The settling time is hence dependent on the cut-off frequency (2.21) (2.20). A short settling time is generally preferred. Short settling time often results in higher power consumption due to increased charge pump currents (2.19).
2.4
Minimum Tone Spacing for Orthogonal FSK
The maximum data rate in orthogonal FSK communication systems is limited by the ”minimum tone spacing“, also known as ”minimum frequency separation“. Since the data rate is of great importance a discussion on minimum tone spacing is presented in this section. First a mathematical view of coherent and noncoherent FSK is given and then an alternative and a perhaps more intuitive way of describing minimum frequency separation for non-coherent FSK is presented.
2.4.1
Orthogonal FSK and Coherency
As indicated in section 2.2.1, detection and demodulation of M FSK signals may be accomplished phase-coherently or non phase-coherently. Consider the sinusoids cos(2π f1 t + φ) and cos(2π f2 t). The phase φ is an arbitrary constant angle at the interval 0 to 2π. These sinusoids are orthogonal if their convolution, equation (2.22), equates to zero.
14
Related Theory
ZT cos(2π f1 t + φ) cos(2π f2 t)dt
(2.22)
0
Integrating and applying the limits to equation (2.22) simplifies to equation (2.23) assuming f1 > f2 . T is the symbol duration in seconds. # " sin 2π( f1 + f2 )T sin 2π( f1 − f2 )T + cos φ 2π( f1 + f2 ) 2π( f1 − f2 )T " # cos 2π( f1 + f2 )T − 1 cos 2π( f1 − f2 )T − 1 + sin φ + =0 2π( f1 + f2 ) 2π( f1 − f2 )
(2.23)
The following approximation can be done assuming f1 + f2 >> 1: sin 2π( f1 + f2 )T cos 2π( f1 + f2 )T ≈ ≈0 2π( f1 + f2 ) 2π( f1 + f2 )
(2.24)
Combining (2.23) and (2.24) gives cos φ sin 2π( f1 − f2 )T + sin φ[cos 2π( f1 − f2 )T − 1] ≈ 0
(2.25)
In the non-coherent case the phase φ can assume an arbitrary value from 0 to 2π. This means that in order for the sum (of equation (2.25)) to equate to zero the terms sin 2π( f1 − f2 )T and cos 2π( f1 − f2 )T − 1 also have to equate to zero. This gives the following equivalence. 2π( f1 − f2 )T = 2kπ ⇔ f1 − f2 =
k T
(2.26)
Hence, for non-coherent minimum frequency spacing k = 1 and f1 − f2 = Tk . However in the coherent case the phase φ is known which makes it possible for the receiver to phase-align itself with the incoming signal. Since the phase is known the tone spacing for orthogonality is found in equation (2.22) by setting φ = 0, which gives n (2.27) 2T Thus the minimum frequency separation for coherent FSK signaling occurs when n = 1 as in sin2π( f1 − f2 )T = 0 ⇔ f1 − f2 =
1 (2.28) 2T Concluding the results of the above equations, the coherent detected FSK can, for a given symbol rate, occupy less bandwidth than a non-coherent detected FSK and still be orthogonal. Remember that orthogonal FSK benefits from an optimal bit error rate for any given signal to noise ratio. f1 − f2 =
2.5 Spectral Regrowth Issues
2.4.2
15
Alternative Approach to non-Coherent Orthogonal FSK
When modulating a FSK signal by switching between the available frequencies the individual tones will assume the shape of a sinc according to Fourier transform theory. This is visualized in figure 2.8 where the frequency spectra of binary, two tone, FSK signaling is depicted. For a detected non-coherent tone to manifest a maximum output the peak of the tones in the corresponding frequency spectra has to align with a zero crossing of the adjacent tones. The distance from the peak of the tones main lobe and its first zero crossing gives the minimum frequency separation. That is the smallest possible separation between adjacent tones for which orthogonality is fulfilled. Maximum bandwidth efficiency for non-coherent FSK is achieved by aligning the centers of the main lobes with the first zero crossing of the neighboring tone or tones. The minimum frequency separation for non-coherent FSK is thereby 1/T Hz where T is the symbol duration. The tones in figure 2.8 are separated with the “minimum frequency separation” distance and the highest bandwidth efficiency is therefore accomplished6 . The tones are orthogonal, which means that the detected signal manifests a maximum output. Orthogonality between tones gives an optimal bit error rate for any given signal to noise ratio. T sinc(f-f2)T
T sinc(f-f1)T
1/T Hz
f2
f
f1
Figure 2.8: Minimum frequency separation for non-coherent FSK signaling. The required bandwidth of binary FSK can be derived from figure 2.8 as the minimum frequency spacing distance between the two tones plus one half of the tone spacing on both sides of the spectra. Hence the required bandwidth for binary FSK is 2/T Hz. The required bandwidth for M-ary FSK can be derived analogous to M/T Hz.
2.5
Spectral Regrowth Issues
Spectral regrowth is caused by abrupt phase changes of the transmitted signal. Remembering Fourier Series Theory, a signal with abrupt phase transitions in6 That
is for non-coherent FSK signaling.
16
Related Theory
cludes a large number of high frequency components. These high frequency components cause a higher percentage of the transmitted power to occur outside the designated frequency band leading to poor spectral efficiency. Base band filtering is often used to mitigate this effect by smoothering the transitions in the time domain as illustrated in figure 2.9.
xBB(t)
LPF
Modulator
PA
Figure 2.9: Low-pass time domain filtering of the baseband signal. Filtering phase transitions reduces spectral regrowth and hence improves spectral efficiency. However, filtering also causes greater envelope variations, e.i. amplitude variations, of the transmitted carrier (see figure 2.10). The amplitude variations increase as the filter narrows. The operation of the power amplifier becomes a key factor in order to maintain the desired spectrum to the limited bandwidth. The PA must be able to follow the amplitude variations without distorting the signal by adding frequency components to the spectra. This implies that the PA needs to be linear to some degree. Larger amplitude variations requires higher linearity. The effect when a non-linear component distorts the shape of a filtered signal and deteriorates the limited bandwidth is called “spectral regrowth”. 180°
180°
90°
Unfiltered QPSK
Filtered QPSK
t
Figure 2.10: Unfiltered and filtered QPSK waveforms. Unfortunately, linear PAs are typically less efficient than their non-linear counterpart. The power efficiency of efficient linear PAs ranges about 40% and about 60% for non-linear PAs [16]. These figures are usually significantly lower for ultra low power PAs.
2.6 Constant Envelope
2.6
17
Constant Envelope
As stated in the previous section, the term envelop is referring to the amplitude of a signal. In this section, envelope refers to the amplitude of the carrier wave signal specifically. Constant envelope simply states that the amplitude of the carrier wave signal is constant.
2.6.1
Frequency Modulation
Analog FM and discrete FSK are both constant envelope. While analog FM is by nature phase continuous, this is not the case with FSK when considering a switch based architecture (e.g. the architecture in figure 2.13 b). FSK modulation causes phase discontinuities if no consideration is taken in respect to carrier wave frequency and data rate.
FM (Analog)
Figure 2.11: Analog frequency modulation waveform. Phase discontinuities can be avoided by choosing the difference of the carrier frequencies to be multiples of 1/2T 7 where T is the symbol duration. Hence, equation (2.29) [9] must hold f1 − f2 = N 2T
(2.29)
, where N is an integer. Choosing the carrier frequency difference for binary FSK to the “minimum frequency separation” 1/2T discussed earlier results in a modulation scheme called Minimum Shift Keying (MSK). The phase trajectory of MSK is linear and hence also continuous. In order for the phase trajectory to also be “smooth”, its derivative also needs to be continuous which is not the case for MSK. Baseband filtering is often introduced to “smooth” the MSK signal. A common way of performing base band filtering on MSK is to introduce Gaussian filtering. Gaussian MSK or GMSK are very popular and commonly used in the industry and are found in e.g. GSM, Bluetooth and IEEE 802.11 devices. Another way of dealing with the issues with the continuous phase during FSK modulation is to use a different type of architecture than the switching type discussed so far. By using a VCO based type of architecture, see figure 2.13 (a), a continuous phase can be guaranteed independently of carrier frequency and the data rate. The carrier frequency can be modulated by for example altering the impedance of the ocillator resonant tank. 7 E.i.
for coherent FSK.
18
Related Theory
0
Message
1
0
Discontinuous FSK
Continuous FSK
Figure 2.12: Discontinuous and continuous FSK waveforms
f1 Data
CMod
f2 Data
(a) VCO based FSK
(b) Switching based FSK
Figure 2.13: Continuous and discontinuous phase architectures.
2.6 Constant Envelope
2.6.2
19
Phase Modulation
PSK modulation is not regarded as being constant envelope. However, since the envelope behavior is proportional to the amount of phase discontinuity, different PSK modulation schemes exhibit different envelope characteristics. The envelope behavior of a modulation scheme is captured by its constellation diagram. The lines between symbol states represents possible symbol transition trajectories. The envelope behavior is determined by the distance from the trajectory to the origin. QPSK has the largest phase shifts of the constellation diagrams depicted in figure 2.14 with a maximum phase shift of 180 degrees. A 180 degree phase transition is represented by a symbol trajectory crossing the origin. Therefor, QPSK also displays the largest amplitude variations and hence the poorest envelope characteristics. π/4-DQPSK has a maximum phase shift of 135 degrees and its symbol trajectories never crosses the origin which means that it has less amplitude variations than QPSK. QPSK
π/4-DQPSK
OQPSK
MSK
Figure 2.14: Constellation diagrams of QPSK, π/4-DQPSK, OQPSK and MSK In OQPSK in-phase and quadrature transitions are offset by half of a symbol period which reduces the maximum phase shift to 90 degrees compared to 180 degree shift for QPSK. For constant envelope behavior the distance between the origin and the trajectory must be constant, like in the case of MSK. MSK was described in section 2.6.1 as a FSK type of modulation scheme. One other way to view MSK modulation is to view it as a PSK modulation scheme with a constant phase shift.
Chapter 3
A Brief Overview of Current Architectures This chapter presents an overview of ten low-power transmitters, a description of the three most power-efficient architectures and a short discussion on using 65 nm technology in MICS applications.
3.1
A Brief Overview
An overview of existing ultra low-power transmitters and their characteristic features is presented in table 3.2 where the transmitters are ordered by their global power consumption. The transmitters are in table 3.3 ordered by the energy dissipated per bit. Some of the architectures use conventional power amplifiers with specified power efficiencies. These architectures and their efficiencies are listed in table 3.4. The four most power efficient transmitters in table 3.3 represents three different types of architectures. A short summary of these architectures is given in the following subsections.
3.1.1
Distributed Frequency Correction
For implantable devices the MICS standard, paragraph §95.6281 , specifies the frequency stability to be maintained for ±100 ppm over a range of 25°C to 45°C. The ±100 ppm requirement is relatively relaxed compared to other standards since the temperature of an implanted transmitter is constantly moderated by the human body. The architectures in [8] and [10] have taken advantage of the relaxed frequency stability requirements and completely removed the on-chip frequency loop back used for frequency correction. The frequency loop back is instead distributed to the base station, now responsible for tracking the frequency errors 1 See
section 4.1.1
21
22
A Brief Overview of Current Architectures
and periodically sending frequency correction bits to the implantable device. Both architectures utilize a digital controlled oscillator (DCO) for frequency synthesis and modulation. No crystal oscillator is needed. The frequency is controlled by capacitor banks and both architectures employs FSK modulation.
DCO PA Data
CMod
Message
Message + Correction bits
CArray
Figure 3.1: DCO based transmitter with distributed frequency correction. The benefits of using a distributed frequency feedback could be questioned since many applications would need to utilize a reference frequency for other parts of the application than the transmitter. In that case the frequency loop back overhead would have a less significant footprint on the global power consumption.
3.1.2
Frequency Multiplying Power Amplifier
In order to improve the global power consumption [18] presents an architecture that operates entirely on the crystal frequency at 45.454 MHz. Basic building blocks are the crystal oscillator circuit, digital delay loop and the power amplifier. FSK modulation is performed at the crystal frequency by pulling the frequency with a capacitor. The crystal frequency is then forwarded to a 9-state DLL controlled by two feedback loops for frequency and duty-cycle control, respectively. The power amplifier operates as an edge combiner, which combines the 9 edges from the DLL producing a modulated output radio frequency at 9 × fXTAL . This topology offers crystal stability without the need of a PLL or DLL operating at radio frequencies. One major drawback is however the lack of channel selectivity.
3.1.3
Direct VCO Modulation Using Low Supply Voltage
Paper [4] presents a transceiver architecture for wireless sensor networks and not specifically for use in MICS applications. The transmitter is designed to operate in the 2.4 GHz ISM band. The transmitter is of a direct VCO modulation type and is designed for 400 mV supply voltage to enable it to be driven from a single solar cell. Frequency control is achieved by setting a 17 bit capacitor array in the VCO. Contributors to low power consumption are: the ability to operate at a low power supply (400 mV), stacked topology in order to reuse bias current and direct VCO modulation. Further contribution is made by lowering the frequency at the
3.2 65 nm Designs
23
FSK Data 45.545 MHz
PDF
PDF
CP + LF1
CP + LF2
Delay Chain
fXTAL
A1 A2
A9
9xfXTAL
Edge Combiner
Figure 3.2: Transmitter based on a frequency multiplying edge combiner. counter input by preceding the counter with a dynamic ring divider. Custom dynamic logic is also used in early high frequency parts of the counter. Quadrature VCO N Tx bits
32 kHz Oscillator
FLL
17 bits
Counter
/8
PA
50 Ohm Antenna
To the receiver
Figure 3.3: Direct VCO modulated transmitter.
3.2
65 nm Designs
The papers covered in table 3.2 and 3.3 use technologies from 180 to 90 nm. No papers were found on transmitters using 65 nm or newer technologies during the thesis. However there is at least one paper [22] on a MICS receiver utilizing the 65 nm technology. The receiver uses linear mixers and a VCO operating at radio frequency which typically would lead to high power consumption (the architecture is depicted in figure 3.4). However ultra-low power consumption is achieved by a wide use of sub-threshold devices. 90% of the transistors in all analog building blocks are operating in deep week inversion region. Sub-threshold design has historically been associated with low frequency devices. Sub-threshold device operation exhibit higher transconductance but with a worsened frequency ability limiting the operation to lower frequencies. Fortunately, the transit frequency is increased by 75 to 100% in all operation regions for each new generation of scaling [15]. The degree of sub-threshold operation or inversion can be approximated by the inversion constant in equation (3.1).
24
A Brief Overview of Current Architectures
IC =
ID I0 W L
(3.1)
This 65 nm device covered in [22] is driven to deep week inversion which means that the inversion constant is less than 0.1. This in turn means that the highest power efficiency (gm /ID ) is achieved for this receiver during operation at 400 MHz. An overview of the power consumption is given in table 3.1.
IF amp
Real BPF
RF in
FSK Demod LNA
IF amp
900
Complex BPF
On chip MEMS resonator
PLL
Channel Selection
Figure 3.4: 65 nm weak inversion MICS receiver.
Building Blocks LNA Quadrature Mixers Complex IF BPF Real IF BPF IF Gain Stage BFSK Demodulator VCO PLL Total (Quadrature channel + Complex IF BPF) Total (Inphase channel only + Real IF BPF)
Power Consumption (µW) 370 240 500 95 1.6 8 210 160 1490 925
Table 3.1: Summary of power consumption.
3.3
Concluding Summary
All transmitters covered in section 3.1 are utilizing FSK modulation and are using capacitor banks for modulation and frequency selection. It is hard, if at all possible2 , to perform PSK modulation by pulling capacitors in order to alter the phase 2 Opinion
of the authors of this document.
3.3 Concluding Summary
25
of the signal using proposed types of architectures. Hence, modifications of the above mentioned architectures are required for use in PSK applications. Even though smaller modifications easily could be made to generate multiple phases for PSK modulation, these architectures does not facilitate any means of filtering or smothering of the phase transitions, decremental to the overall performance. The architectures presented in table 3.2 offer a wide range of characteristics. The data rate ranges from 50 kbit/s to 1 Mbit/s, output signal power ranges between −16 and 0 dBm while the power efficiency lies between 13 and 44%.
400 µW @ -16 dBm, 250 kbit/s
DCO based with distributed feedback. No external crystal.
A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK Transmitter [18]
500 µW @ -16 dBm, 100 kbit/s
9x frequency multiplying power amplifier. (Edge combiner)
An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End [4]
700 µW @ -8.5 dBm, 300 kbit/s
Direct FSK quadrature VCO modulation, PLL based.
2.4 mW @ -10 dBm, 50 kbit/s 1.8 mW @ -12 dBm, 128 kbit/s
Sliding-IF; PLL based; FSK and GFSK modulation. Zero-IF; PLL and mixer based; FSK modulation.
Single phase or quadrature down conversion; passive mixer; PLL based; FSK demodulation. Sliding-IF; PLL based; FSK and GFSK demodulation. Zero-IF; PLL and mixer based; FSK modulation.
A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable Applications [5]
5.4 mW @ 0 dBm, 400 kbit/s
Programmable integer-N PLL with VCO, 6 IQ mixers.
Super regenerative OOK, PLL based with envelope detector.
A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for Medical Imaging [12]
12.7 mW @ -15d Bm, 524 kbit/s
A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18µm CMOS [11]
16 mW @ -12 dBm, 1 Mbit/s
≥ 15 mW
1 to 5 mW
500 µW to 1 mW
500 µW
A 490µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10]
5 to 10 mW
Receiver DCO based. Super regenerative OOK demodulation. DCO based with relaxation mixer, Qenhanced low-IF FSK receiver.
10 to 15 mW
Categorization by Total Transmitter Power Consumption Paper Power (Tx) Transmitter A 350µW CMOS MSK Transmitter and 400µW 350 µW @ DCO based with OOK Super-Regenerative Receiver for Medical -16 dBm, distributed feedback. Implant Communications [8] 120 kbit/s No external crystal.
A 1V Wireless Transceiver for an Ultra-LowPower SoC for Biotelemetry Applications [3] A 2mW 400MHz RF Transceiver SoC in 0.18µm CMOS Technology [13]
An Ultra-Low Power, High Performance Medical Implant Communication System (MICS) Transceiver for Implantable Devices [14]
16 mW @ -17 to -4 dBm, 400 kbit/s
Pseudo-open-loop PLL, high speed phase selector, G/FSK modulation. PLL based; 3-5 GHz VCO; Wide band, inductorless mixer; FSK modulation. PLL and mixer based, direct conversion, 2/4FSK modulation.
-
Super regenerative OOK, PLL based with envelope detector.
Direct conversion OOK PLL and mixer based receiver.
Table 3.2: Overview of ten ultra-low power radio transmitters.
26
A Brief Overview of Current Architectures
Power Consumption Considering Data Rate Energy per Bit 1.60 nJ/bit ∼2.33 - 3 nJ/bit 2.9 nJ/bit 4.0 nJ/bit 13.5 nJ/bit 14 nJ/bit 16 nJ/bit 24 nJ/bit 40 nJ/bit 48 nJ/bit
Paper A 490 µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10] An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End [4] A 350uW CMOS MSK Transmitter and 400uW OOK Super-Regenerative Receiver for Medical Implant Communications [8] A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK Transmitter [18] A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable Applications [5] A 2mW 400MHz RF Transceiver SoC in 0.18um CMOS Technology [13] A 400-MHz/900-MHz/2.4-GHz Multi-band FSK Transmitter in 0.18-µm CMOS [11] A Low-Power Asymmetrical MICS Wireless Interface and Transceiver Design for Medical Imaging [12] An Ultra-Low Power, High Performance Medical Implant Communication System (MICS) Transceiver for Implantable Devices [14] A 1V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications [3]
Table 3.3: Ten ultra-low power radio transmitters ordered by energy per bit.
PA Power Efficiency Efficiency 13% 16% 31% 32% 44%
Paper A 490µW Fully MICS Compatible FSK Transceiver for Implantable Devices [10] A 500µW Neural Tag with 2µVrms AFE and Frequency-Multiplying MICS/ISM FSK Transmitter [18] A 1V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications [3] A 400-MHz CMOS Radio Front-End for Ultra Low-Power Medical Implantable Applications [5] An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End [4]
Table 3.4: PA efficiency for ultra-low power transmitters.
Chapter 4
The MICS Standard and PSK Bandwidth Efficiency Issues This chapter presents a summary of the Medical Implantable Communications Service (MICS) radio standard introduced by Federal Communications Commission (FCC). It also points out bandwidth efficiency issues for PSK modulation complying to the MICS standard, which will be a major challenge throughout the thesis. The complete MICS standard can be found in [2].
4.1
MICS Standard
In 1999 the FCC introduced a new standard devoted to medical implantable services called MICS. The specified frequency band for MICS is 402-405 MHz. There were a number of reasons for choosing this specific band. One reason is that the propagation characteristics for frequencies in this band are favorable for transmission through the human body [19]. A summary of the MICS standard is given in the following subsections. The summary is divided into the corresponding paragraphs related to the MICS standard and the main features of each paragraph are listed by bullet points. The reader is referred to “FCC Rules and Regulations Part 95” [2] for more detailed information. The related FCC paragraphs is stated in the corresponding subtitles.
4.1.1
MICS Transmitter from Paragraph §95.628
• Any frequencies from 402 to 405 MHz can be used (no channeling scheme exists). • The emission bandwidth is 300 kHz and is measured at the points on either side of the carrier frequency situated 20 dB below the top value. Measurement resolution is 1% of the emission bandwidth (300 kHz). 27
28
The MICS Standard and PSK Bandwidth Efficiency Issues • A communications session involving a MICS device shall not use more than 300 kHz of bandwidth. • Each transmitter shall maintain ±100 ppm frequency stability over a range of: 1. 25°C to 45°C for implanted transmitters. 2. 0°C to 55°C for programmer/controller transmitters.
4.1.2
Emission Types from Paragraph §95.631
• A MICS transmitter may transmit any emission type appropriate for communication. However, voice communication is not allowed.
4.1.3
Emission bandwidth from Paragraph §95.633
• Bandwidth limitations according to §95.628. • Maximum EIRP is 25 µW (−16 dBm). See following paragraphs for measuring details.
4.1.4
Unwanted Radiation from Paragraph §95.635
• Emissions 250 kHz outside the MICS band shall be attenuated according to the following table. Frequency MHz Field Strength ( µV/m) Measurement Distance (m) 33-88 100 3 150 3 88-286 216-960 200 3 960 and above 500 3 Note - At band edges, the tighter limit apply Table 4.1: Attenuation of signal 250 kHz outside the MICS band.
• The emission should be measured to at least the tenth harmonic of the highest fundamental frequency to be transmitted. • Emissions within the MICS band 150 kHz from the center frequency shall be attenuated 20 dB bellow the transmitted output power. • Any other frequencies shall be attenuated 20 dB bellow the transmitted power.
4.1 MICS Standard
4.1.5
29
Maximum Transmitted Power from Paragraph §95.639
• The maximum EIRP for a MICS transmitter is 25 µW. Compliance may be determined by measuring the EIRP at 3 m. The equivalent radiated field at 3 meters for 25 µW is 18.2 µV/m at an “open test area site”, or 9.6 µV/m which is equivalent to “free space”. • Implantable transmitters shall be tested in a body/tissue-like medium. • The power radiated in any 300 kHz bandwidth shall not exceed 25 µW EIRP. • The antenna is considered as a part of the transmitter. Antenna and transmitter are tested as a unit.
4.1.6
Additional Power Constraint from Paragraph §95.649
• No CB, R/C, LPRS, FRS, MICS, MURS or WMTS unit shall incorporate provisions for increasing its transmitter power to any level in excess of the limits specified in §95.639.
4.1.7
Crystal Control Requirements from Paragraph §95.651
• No crystal control is required for MICS.
4.1.8
Resulting Spectral Mask
The following spectral channel mask can be derived from the preceding specifications for the in band frequencies (see figure 4.1).
Figure 4.1: In band frequency mask for MICS standard
30
The MICS Standard and PSK Bandwidth Efficiency Issues
4.2
PSK Bandwidth Efficiency Issues
The rational for considering the use of PSK instead of FSK modulation is that PSK modulation schemes, in common theory, require lower signal power1 than FSK based modulation schemes. PSK is also generally regarded as more bandwidth efficient facilitating the possibility of higher data rates. However, the bandwidth efficiency is affected by the spectral mask and the performed filtering. A higher amount of filtering is also affecting the signal to noise ratio leading to higher required signal powers.
Spectrum (dB)
0
QPSK MSK
-10 -20 -30 -40 -50 fC fC+fS
fC+2fS
fC+3fS
fC+4fS
fC+5fS
fC+6fS
Figure 4.2: QPSK and MSK Spectrum As described in chapter 2, MSK can be viewed as binary FSK modulation with minimal frequency separation. Comparing the MSK and QPSK frequency spectra in figure 4.2 reveals that MSK has a wider main lobe than QPSK and that the sidelobes in the QPSK spectra have a slower attenuation than the MSK spectra. The attenuation of the side-lobes in the MSK spectra is proportional to f 4 while the attenuation in QPSK spectra is proportional to f 2 [20]. The main lobe is often the deciding factor when determining the bandwidth efficiency. However, it is not the case when using the MICS mask due to its 20 dB cut-offs. This drastically limits the unfiltered QPSK data rate since the first and second side-lobe fall within the 300 kHz channel bandwidth of the MICS mask (see figure 4.2 where the amplitude of the first and second side-lobe are attenuated less than 20 dB). During simulation with a resolution bandwidth of 3 kHz, also the third side lobe has to be included in the 300 kHz channel width. Limiting the theoretical data rate of the unfiltered QPSK signal to approximately 80 kbit/s. Other FSK modulation schemes with larger frequency separation distances than the minimum distance used by MSK have even higher attenuation of the unwanted side-lobes. Hence under the MICS mask, the data rate for FSK modulation is limited by the frequency separation 1 See
section 2.2.1 for reference.
4.2 PSK Bandwidth Efficiency Issues
31
while the data rate of QPSK signaling is limited by the influence of its side-lobes. The data rate of unfiltered MSK modulation is limited to about 230 kbit/s. Almost three times higher than the data rate using QPSK modulation.
Figure 4.3: Unfiltered QPSK spectra using RBW of 3 kHz. To improve the PSK bandwidth efficiency and increase the data rate one could apply different filtering or shaping techniques in order to suppress the side-lobes. The competitiveness of using PSK modulation in MICS applications is determined by the ability to shape the frequency spectrum to better fit the MICS mask while minimizing the deterioration of the signal to noise ratio. Since additional hardware is most likely needed2 it is also crucial that the added power consumption due to the additional hardware does not exceed the power saved by reducing the signal power.
2 Compared
to the FSK architectures discussed 3.
Chapter 5
Testbenches This chapter describes the two testbenches used during simulations, the available measurements and the test methodology.
5.1
Detectors
What differs the two testbenches used during this thesis are the detectors. One testbench uses a PSK detector and is used for simulating the PSK architectures. The other testbench uses a FSK detector. The FSK testbench is used to validate the relative behavior of the PSK architectures by simulating FSK architectures.
5.1.1
PSK Detector
The detector that has been used is a coherent phase detector. The incoming radio frequency is down-converted with a phase aligned local oscillator. The product from this multiplication consists of one high frequency component and one DC component proportional to the phase of the input signal. The high frequency component is discarded by low pass filtering and only the DC component is used. The detection and demodulation are analogous for the in-phase and quadrature paths. They differ however in respect to the local oscillator which is shifted 90° between the paths. After the multiplication and filtering, the DC component is integrated over at most a symbol period and then sampled. Different modulation techniques requires different timing. The timing for the two paths are controlled individually by an integrator reset and a sample-and-hold signal for each path respectively. The PSK demodulator is depicted in figure 5.1.
5.1.2
FSK Detector
The FSK detector used is a binary non-coherent quadrature detector. Hence, it does not track the phase of the transmitted carrier frequency. A non-coherent 33
34
Testbenches
I {0,1}
LO
Reset
Sample&hold
+90° Q {0,1}
Figure 5.1: PSK demodulator block diagram. detector requires an Eb to n0 ratio which is 1.5 dB higher than its coherent equivalent1 . The binary modulated FSK signal is composed of two alternating carrier frequencies with a frequency spacing of ∆ f . The received signal is down-converted in the mixer stages which in turn are followed by integrator stages acting as low-pass filters by removing higher frequency components. The resulting DC components are then sampled and squared. If the received carrier frequency is equal to fc the decision branch will assume a positive value while it will assume a negative value in the case where the carrier frequency is equal to fc + ∆ f . The values in the decision branch are converted to a binary sequence by a comparator. The FSK detector is depicted in figure 5.2.
5.2
Measurements
To determine the performance of the architecture under test, the testbench measures the spectrum of the modulated signal. Additive white Gaussian noise is added before demodulation to simulate a noisy channel. The demodulated signal is then compared with the input data to test for bit errors under a predetermined SNR. The following measurements are available in the testbench. • MICS mask compliance • BER measurement • Eye diagram of the integrated signal to tweak the timing • SNR measurement • Eb /n0 measurement • Channel power and Adjacent channel power 1 See
section 2.2.1.
5.2 Measurements
35
cos 2 f c t t
∫ dt
2
0
sin 2 f c t t
∫ dt
2
0
+
cos 2 f c f t
-
t
∫ dt
Decision
2
0
sin 2 f c f t t
∫ dt
2
0
Integrate Sample t=T
Figure 5.2: Block diagram of non-coherent FSK demodulator MICS Mask Compliance In-band frequencies are tested for MICS compliance according to section 4.1.4. BER Measurement Supplied for performing BER measurement, but also used to verify proper behavior of different architectures. The simulation environment used during the thesis work limits the number of bits in the BER measurement to approximately 2000. Increasing the number of bits further causes sporadic crashes during simulation. Eye Diagram Eye diagram measurements are performed after the integration blocks. These measurements are useful when tweaking the timing control signals in order to minimize the bit error rate. The timing of the reset signal to the integration block and sample-and-holdsignal needs to be adjusted to match the shape of the phase transition. Figure 5.3 depicts a down-converted signal of one of the channels. The signal is integrated by the integrator and then sampled by the sample-and-hold block. Looking at figure 5.3 the control signals are set to integrate each symbol between its zero crossings. If the signal is unshaped, the integration can be performed during the
36
Testbenches
entire symbol length. The optimal integration duration are in some cases less than a symbol length, hence the possibility to set the control signals independently.
Shaped
Vmax
Un-shaped
0
Vmin
Figure 5.3: Signal after mixer stage. Figure 5.4 depicts the eye diagram used when tweaking the control signals. To minimize the bit error rate the minimum amplitude, in the eye diagram, is maximized at the time for sample-and-hold. 80
eye_Q_integrate
60
Sample & hold
40 20 0 -20 Reset
-40 -60 -80 -2
0
2
4
6
time, usec
8
10
12
14
Figure 5.4: Eye diagram used for timing of reset and sample-and-hold control signals.
SNR Measurement Basic SNR measurement in linear and decibel scale. Used when calculating the Eb /n0 measurement. The signal power measurement is performed with the built
5.3 Test Methodology
37
in function “Spec_power()” that uses data from an ADS spectrum analyzer component. This approach of calculating signal power is verified by also calculating the signal power in time domain using equation 5.1. Z 2 1 1 (5.1) P= x(t) dt Simulation Time Z Eb /n0 Measurement This measurement calculates the energy per bit over the noise floor and is more useful than the SNR measurement since it also consider the data rate. Channel Power/Adjacent Channel Power Measurement Power measurements are performed for both in-channel and adjacent channel power.
5.3
Test Methodology
There are basically two ways to decrease the power consumption for the given high level architectures: 1. Decrease the transmission time by increasing the data rate. 2. Minimize the required signal power. Thus, the idea behind the test methodology is to determine the minimum signal power (i.e. Eb /n0 ) for different data rates in order to acquire the power characteristics for the designed architectures. The minimum signal to noise ratio is determined for a specified data rate, see figure 5.5. The test start with a short data sequence to determine starting points for the amount of shaping that must be performed to comply to the MICS spectral mask. When the transmitter is complying to the spectral mask the noise in the channel is increased to find the highest noise level while still being able to send detectable data. In an ideal simulation environment increasing the power of the added noise has the same effect as decreasing the power of the transmitted signal. When the maximum noise level for this, short, data sequence is determined a longer sequence is simulated until 2000 symbols are sent and received without any bit errors. A test with 2000 error free symbols indicate a BER no higher than 10−3 with a confidence level of 86% and a BER no higher than 1.5 ∗ 10−3 with a confidence level of 95%, [1].
38
Testbenches
Start Yes
Simulate
No
MICS Mask
Zero BER
No
Does Not Meet Minimum Data Rate
More Shaping
Yes Increase Noise Simulate
Yes
Zero BER No
Latest Approved Noise Level More Symbols Simulate No Zero BER
No
Less Noise
2k Sym
Yes
Stop
Yes
Figure 5.5: Test methodology for determining the SNR given a certain data rate.
Chapter 6
Designed Architectures This chapter presents the architectures designed and simulated during the thesis. A short description of the idea leading up to each architecture is also given along with some brief details of the implementation.
6.1
PSK Modulators
The different PSK architectures designed and simulated during the thesis are presented in the following sections.
6.1.1
Simple QPSK
One seemingly obvious way to modulate a radio signal with QPSK is to generate four signals, 90 degree apart, and simply switch between them in order to drive the areal as in figure 6.1. However this type of architecture typically suffer from spectral regrowth since the phase trajectory is discontinuous. Another drawback is that the non-constant envelope behavior causes amplitude variations requiring a more linear and power consuming power amplifier. This architecture is foremost included for reference purposes. The following architectures are addressing the issues with discontinuous phase trajectory and the lack of constant envelope behavior. Implementation The architecture was implemented in ADS using a standard QAM building block set to four constellation points. The QAM component does not perform any timing or filtering. Hence the output phase is discontinuous as described above.
6.1.2
PLL Based QPSK Modulation
PLLs are used in most radio transmitters to synthesize the correct frequency for the local oscillator. Direct QPSK modulation can be achieved by using a quadrature 39
40
Designed Architectures
Quadrature VCO
Phase Select
Figure 6.1: Switch based QPSK with discontinuous output.
VCO which produce four signals separated by 90 degree (see figure 6.2). The modulation is performed by choosing which of these signals or phases to be used in the feed back loop using a multiplexer. The feedback signal will after an initial settling time be locked to the reference signal. Hence, the phase of the VCO will change as switching is performed between the four phases. One of the signals are fed through to the power amplifier, or as in the testbench to a spectrum analyzer. The feedback loop in the PLL acts as a low-pass filter. By adjusting the filter characteristics of the feedback loop, the phase transitions could be smoothened, hence reducing the spectral regrowth. Constant envelope modulation is also achieved since the VCO always outputs a continuous phase.
fref
Spectrum Analyzer
PFD
Phase Select (I and Q)
Div N Figure 6.2: Basic PLL architecture modified with quadrature feed back.
Implementation The PLL was created by using existing behavioral models for phase-frequencydetector (PFD) and VCO. This drastically reduces simulation time but also reduces the flexibility of the PLL model. The single phase output from the VCO were fed to a “custom made” block that produced four quadrature phase shifted signals from the input signal. The binary I and Q signals were then used to select which of the four phase shifted signals to be fed back to the phase detector.
6.1 PSK Modulators
6.1.3
41
PLL Based QPSK Modulation with Dither
To smoothen the phase transitions even further, compared to 6.1.2, an architecture with dither is proposed in this thesis. This architecture is based on the previous described PLL architecture but a multiplexer and shaping logic were added see figure 6.3. The added hardware allows this architecture to dither1 between the new and old IQ-value according to a time varying pattern or shape. Since the dithering frequency is greater than the cut-off frequency of the closed loop filter, the output to the spectrum analyzer will not change as fast as the dithering frequency, but instead assume an average phase. This average phase will be changed from being close to the previous IQ-value to being close to the new IQ-value over time by changing the portion of time that the new and old values are fed back into the loop. This could potentially reduce the spectral footprint compared to the previously presented simple architecture.
fref
Spectrum Analyzer
PFD
IQ new
Div N
IQ old Shaping Logic
Figure 6.3: Basic PLL architecture with quadrature feed back. The switching between symbol states are performed by 90 degree phase shift transitions. A 180 degree phase shift is therefor performed in two 90 degree steps passing an intermediate symbol state in each transition. The reason for this is to secure the performance of the PLL feedback. Dithering between two phases 180 degree apart causes the PLL to loose its lock, leading to unpredictable PLL behavior. In radio designs a PLL is often used to synthesize a frequency from a reference. In this architecture the dithering must not interfere with the synthesis. The synthesis consist of a frequency divider, see figure 6.3. If the frequency divider is a digital counter this will most likely get a false count from the dithering from the shaping logic. There are other frequency dividers such as injection-locked frequency dividers that could be less sensitive to the dithering. For this thesis only high level simulation is performed and it is assumed that this QPSK modulator can be designed without interfering with the frequency synthesis. 1 That
is to rapidly alternate from one to the other.
42
Designed Architectures
Implementation The PLL was implemented as in section 6.1.2 using behavioral models. Bit precision Ptolemy was used for implementing the shaping logic. The main building blocks used are a finite state machine (FSM), a counter and a ROM memory (see figure 6.4). The FSM starts a new phase transition by enabling the counter when a new IQ-value appears at its input. The FSM also controls the IQ-values at the input to the multiplexer. The IQ-values are then multiplexed to the output using the overflow from the delta sigma accumulator as select-signal. The overflowratio of the accumulator is dynamically set by the ROM. Hence, the shape of the phase transition can be controlled by programming of the ROM. The time duration for a phase transition can be altered. The maximum time duration is typically not longer than a symbol duration. Increasing the time duration results in a smoother phase transition and a narrower spectral foot-print but with the expense of a higher bit error rate. clk
IQ
IQ old
FSM
Mux
IQ new
IQ out
1st Order Sigma Delta
Counter
ROM
fraction
+
overflow
div_clk
Div. X clk
Figure 6.4: Functional block diagram over the shaping logic. The following parameters are used by the shaping logic: • Ramp-up Ratio • Clock Ratio • ROM Precision • Counter Width The parameter “Ramp-up Ratio” determines the ratio between the duration of the phase transition and the symbol duration. The duration of the phase transition shall not exceed the symbol duration, hence relation (6.1) must hold. Ramp − up Ratio ≤ 100%
(6.1)
6.1 PSK Modulators
43
The “Clock Ratio” parameter determines the ratio between clk and clk_div where 2Clock Ratio = clk/clk_div. The parameter “ROM Precision” determines the number of fractional bits at the input to the 1st order delta sigma accumulator. The Clock Ratio is set to be equal or greater than the ROM precision in order to not loose accuracy. Hence, relation (6.2) must hold. Clock Ratio ≥ ROM Precision
(6.2)
The frequency for which the multiplexer changes value at the output is in this thesis referred to as the “dithering frequency”. The lowest dithering frequency must be greater than the PLL closed loop cut-off frequency. Hence relation (6.3) must hold. PLL cut − o f f f requency < Lowest Dithering Frequency
(6.3)
Too low PLL cut-off frequency deteriorates the signal beyond the point for which it can be successfully detected and demodulated. This pivotal point appears when the PLL cut-off frequency is about 30% lower than the symbol rate. This is true for the 1st order PLL used in this architecture. Hence, relation (6.4) must hold. Symbol Rate (6.4) 1.3 The chosen values for the parameters used in this architecture are listed in table 6.1. Among the parameters, Counter Width has the greatest impact of the overall spectrum. Increasing the counter width suppresses the spectral power falling into adjacent and alternate channels. While the suppression scale with an increasing counter width, the effect of suppression of unwanted radiation in the 300 kHz channel of the MICS mask diminishes when the Counter Width equals 4. No further improvements could be detected during simulation, when increasing the ROM precision and clock ratio beyond 4. PLL cut − o f f f requency >
Parameter Counter Width ROM Precision Clock Ratio
Value 4 4 4
Table 6.1: Parameter values. The ramp-up ratio is chosen to be the smallest value possible for which the frequency spectrum still comply to the MICS spectral mask. A small ramp-up ratio is chosen in order to minimize the bit error rate.
6.1.4
Direct Multiplexing
The simple concept of switching between four phases to drive the power amplifier presented in section 6.1.1 could be expanded to have more than four phases, i.e. to switch between signals with less than 90 degree phase difference. One modulator based on this concept is proposed in this thesis.
44
Designed Architectures
When the symbols change the modulator switches between several intermediate phases one after another to reach the correct phase shift. Since the modulator switches between signals that are closer in phase to each other than with the architecture previously presented in 6.1.1, this modulator could potentially generate less spectral re-growth. Constant envelope behavior is also improved as the phase trajectory becomes more continuous. The extra phases could be generated with a DLL or a poly-phase filter. Spectrum Analyzer DLL Chain/ Polyphase Filter
Modulation Logic
Figure 6.5: Direct multiplexing between multiple phases.
Implementation Two different modulator models were constructed in ADS Ptolemy. They have four and eight intermediate phases within each symbol transition respectively. The models consist of signal generators, one for each phase, connected to switches that select the phase to be transmitted. The I and Q input is fed to a counter-based logic network that generates the switching sequence that carry out the symbol transition. When only one bit is changed the phase changes between the two corresponding signal points, see figure 6.6 (a). But when both I and Q changes, both bits change, the implemented logic only change the phase over certain paths, see figure 6.6 (b). This was easier to realize.
6.2
FSK Modulator
A FSK modulator was constructed for comparison reasons in order to evaluate the PSK architectures. The modulator is based on an FM modulator, or simply a variable oscillator, controlled by the data. The frequency separation and data rate can be adjusted to accommodate different FSK modulation schemes. Implementation The modulator was implemented in ADS using a FM modulator building block. The modulation index is adjusted to produce FSK with a frequency separation
6.2 FSK Modulator
45
10
11
00
01 (a)
10
11
00
01 (b)
Figure 6.6: How symbol changes are performed when only one (a) or both (b) bits are changed.
Spectrum Analyzer Data {0,1}
FM
Figure 6.7: FM modulator based FSK architecture. equal to the bit rate, non-coherent FSK, and half the bit rate, coherent FSK, respectively.
Chapter 7
Simulation Results This chapter summarizes the performance of the simulated architectures. The presented measurements includes: phase- and IQ-transition characteristics, Eb /n0 and ramp-up ratios for different data rates. Conclusions from the results are discussed in chapter 8.
7.1
Overview
Simulations for measuring the required Eb /n0 i.e. the ratio between required energy per bit and the single ended thermal noise, were performed at the data rates 80, 120, 150, 223 and 250 kbit/s. The result is depicted in figure 7.1. The data rates 80, 150 and 223 kbit/s were chosen as these are the maximum data rates where the simple QPSK architecture, the non-coherent FSK modulation and MSK modulation respectively would fit the MICS spectral mask. To get more data points, the architectures were also simulated at 120 and 250 kbit/s. All data points included in the results are from successfully demodulated signals and in compliance with the specified spectral mask according to the methodology described in chapter 5. An overview of the result from the Eb /n0 simulations is presented in figure 7.1. The signal and noise energy were calculated over a bandwidth including 98% of the total signal power. In the simulation the architectures were simulated transmitting 2000 symbols with no errors as described in 5.3. This test indicates a BER of no more than 10−3 with a confidence level of 86% or 1.5 ∗ 10−3 with a confidence level of 95%, [1]. From section 2.2.1 figure 2.5 the Eb /n0 required for a BER of 10−3 is 2.4 dB higher for coherent FSK than for QPSK. This difference increase to roughly 3 dB at lower error rates. In figure 7.1, the results from the QPSK architecture without filtering is used as a reference to the theoretical signal to noise ratio for FSK modulation. The theoretical SNR for coherent FSK is marked by a gray band 2.5 to 3 dB higher than the unfiltered QPSK for the same BER. Also a gray band between 4 and 4.5 dB higher than the unfiltered QPSK is included to show the same margin but for non-coherent FSK. When simulating FSK for reference the 47
48
Simulation Results
highest data rate with minimum tone spacing1 were 150 kbit/s and 223 kbit/s for non-coherent and coherent FSK modulation respectively. In the figure this is shown by only marking the gray band for non-coherent FSK up to a data rate of 150 kbit/s. The band for coherent FSK is drawn up to 223 kbit/s after which the band is broadened to indicate that FSK would need to be filtered somehow in order to reach higher data rates while maintaining the MICS mask. 18 Direct Multiplexing 8 Direct Multiplexing 4 PLL + Dither PLL Unfiltered QPSK
17 16
Eb/n0 98% (dB)
15 14 13 12 11 10 9 8 7
80
120
150
223
250
Data Rate (kbit/s)
Figure 7.1: Plot of the Eb /n0 , the ratio between required energy per bit and the single ended thermal noise, using the bandwidth containing 98% of the signal power. The gray bands represent the theoretical Eb /n0 for coherent and noncoherent FSK.
7.2
Unfiltered QPSK
The unfiltered QPSK architecture was tested at 80 kbit/s, which is the highest data rate where this architecture comply with the MICS spectral mask. The unfiltered phase transitions are sharp, as can be seen in the phase diagram in figure 7.2 (b). This is also reflected in the IQ diagram where the symbol phase and amplitude change from one symbol to the next in straight lines causing large amplitude variations, see figure 7.2 (a). A data rate of 80 kbit/s is low compared to the performance of other MICS transmitters discussed in chapter 3. The unfiltered QPSK signal occupies only a small portion of the in band spectrum due to the unfavorable shape of the MICS mask leading to poor bandwidth utilization, see figure 7.3.
7.3
PLL Based QPSK Modulation
In this architecture, the loop-filter bandwidth was used to shape the signal in order to keep it within the bounds of the MICS spectral mask. To minimize the bit 1 As
described in 2.4
7.3 PLL Based QPSK Modulation
(a) IQ diagram
49
(b) Phase diagram
Figure 7.2: IQ and phase diagram for simple QPSK architecture, phase diagram for a data rate of 80 kbit/s.
Figure 7.3: Frequency spectrum of QPSK transmitted at 80 kbit/s.
50
Simulation Results
error rate, the loop-filter bandwidth was set to the highest value possible, while keeping the spectrum inside the spectral mask. At 80 kbit/s the bandwidth was set to about 800 kHz to maintain a stable system while still allowing as fast phase changes as possible to attain as low Eb /n0 as possible. At 120 kbit/s and 150 kbit/s the bandwidth of the loopfilter was set to 84 kHz and 69 kHz respectively. The maximum data rate for noiseless transmission with the PLL-filtering QPSK architecture is approximately 180 kbit/s. The architecture is of constant envelope type since the VCO always produce a signal with a constant phase. Hence, the perfect circle in the IQ-diagram of figure 7.4 (a). To keep the frequency spectra within the MICS mask, higher data rates require more shaping. Figure 7.4 (b) depicts the phase transition for 150 kbit/s bit rate.
(a) IQ diagram.
(b) Phase diagram.
Figure 7.4: IQ and phase diagram for PLL architecture, phase diagram for a data rate of 150 kbit/s. The higher degree of bandwidth efficiency compared to the unfiltered QPSK could be demonstrated by observing the frequency spectrum where the in-band spectra is occupied to a larger degree. The frequency spectra of the PLL-shaped QPSK signal is depicted in figure 7.5.
Figure 7.5: Frequency spectrum of the PLL-shaped QPSK signal.
7.4 PLL Based QPSK Modulation with Dither
7.4
51
PLL Based QPSK Modulation with Dither
The shaping in this proposed architecture is performed both by dithering and by setting the bandwidth of the loop-filter. To minimize the bit error rate, the transition time between two symbols is set to the smallest value possible while the loop-filter bandwidth is maximized. The maximum data rate for noiseless transmission is approximately 285 kbit/s which is significantly higher than the unfiltered QPSK. The IQ-diagram in figure 7.6 (a) indicates constant envelope behavior like in the previous architecture described in section 7.3. Figure 7.6 (b) depicts a phase transition diagram with a data rate of 250 kbit/s and ramp-up ratio with 72%. The phase transitions in this architecture are smother compared to the phase transitions of the PLL-shaped signal in figure 7.4 (b).
(a) IQ diagram.
(b) Phase diagram.
Figure 7.6: IQ and phase diagram for PLL with dither based architecture, phase diagram for a data rate of 250 kbit/s. The ramp-up ratio is the ratio between the transition time and the symbol duration. The transition time is the time during which the architecture is dithering between the new and old symbol value, shaping the phase transition. Simulations were performed in order to find optimal ramp-up ratios at different data rates. See figure 7.7 for the final ratios. 1
Ramp−up Ratio
0.8 0.6 0.4 0.2 0
80
120
150 Data Rate (kbit/s)
223
250
Figure 7.7: Ramp-up ratio for PLL based modulation with dither. The bandwidth efficiency is increased by adding dithering. Comparing the spectrum in figure 7.8 and 7.5 it is shown that the signal in 7.8 has a higher degree
52
Simulation Results
of in-band occupancy.
Figure 7.8: Frequency spectrum of the PLL- and dither-shaped QPSK signal.
7.5
Direct Multiplexing
The proposed architecture with direct multiplexing was simulated with both 4 and 8 intermediate phase steps. In both cases the maximum data rate simulated for comparison was 250 kbit/s. The maximum data rate for noiseless transmission is 275 kbit/s. The IQ-diagrams are depicted in figure 7.9 (a) and (b) where the IQdiagram of the eight-intermediate-step-architecture almost has a perfect circular shape. Hence, displaying a high degree of constant envelope behavior. The phase transitions are depicted figure 7.9 (b) and (d). The two architectures were simulated individually to extract the optimal rampup ratios. The result from these simulations shows that the two architectures displays optimal behavior at identical ramp-up ratios. The ramp-up ratios are depicted in figure 7.10. The direct multiplexing architectures achieve approximately the same in-band occupancy. The lower Eb /n0 ratio achieved by the direct multiplexing architectures could be explained by a higher degree of in-band occupancy compared to the other simulated architectures, see figure 7.11. The main difference between the direct multiplexing architectures aside from the difference in Eb /n0 ratios is the attenuation of out-of-band frequencies.
7.5 Direct Multiplexing
53
(a) IQ diagram.
(b) Phase diagram.
(c) IQ diagram.
(d) Phase diagram.
Figure 7.9: IQ and phase diagram for direct multiplexing architecture, phase diagram for a data rate of 250 kbit/s. 4 intermediate steps are shown in (a) and (b) and 8 are shown in (c) and (d).
1
Ramp−up Ratio
0.8 0.6 0.4 0.2 0
80
120
150 Data Rate (kbit/s)
223
250
Figure 7.10: Ramp-up ratio for the direct multiplexing architectures.
54
Simulation Results
(a) Spectrum using 4 intermediate steps.
(b) Spectrum using 8 intermediate steps.
Figure 7.11: Frequency spectrum for the direct multiplexing architectures.
Chapter 8
Conclusion This chapter presents the conclusions made from the simulations and the overview of architectures presented in chapter 3.
8.1
Evaluating the Results
This section discusses the results presented in chapter 7. A brief discussion about additional hardware needed in PSK modulation for each architecture is also presented using the FSK architectures in chapter 3 as a baseline. The given differences in Eb /n0 discussed in this section refer to the theoretical difference between QPSK and FSK described in 2.2.1. The numbers assume a BER of 10−3 .
8.1.1
PLL Based Modulator
By using the PLL loop filter to shape the symbol transitions, the data rate could be increased from 90 kbit/s to 150 kbit/s. However, the increase in data rate comes with the cost of a significantly deteriorated Eb /n0 ratio. At 150 kbit/s the PLL architecture need about 3.41 dB higher Eb /n0 than the theoretical Eb /N0 for coherent FSK and 1.91 dB higher than non-coherent FSK. Some of the FSK architectures1 covered in chapter 3 states compliance to the MICS mask at 150 kbit/s and higher data rates. Hence, a higher Eb /n0 ratio is not offset by a superior data rate. This PSK architecture therefore do not seem to be competitive both in regard to Eb /n0 ratio and data rate. If power consumption was of less importance, loop filter shaping could prove to be a simple way to increase data rate from 80 kbit/s in MICS applications utilizing PSK modulation. Albeit to the limited data rate of 150 kbit/s. 1 For
example [10] and [12]
55
56
Conclusion
Additional Hardware A PLL is obviously needed in the PLL architecture. Hence, the additional cost in terms of power has to be considered. In chapter 3, transmitter architectures without PLL:s were discussed utilizing FSK modulation and distributed feedback. Compared to these FSK architectures, the PLL based PSK architecture needs additional hardware like e.g. frequency divider and PFD. Further hardware is needed in order to generate the four phases of the quadrature signal. See table 8.1.
8.1.2
PLL Based Modulator with Dither
By adding dithering circuitry to the PLL based modulator discussed in the section above, data rate and Eb /n0 ratio of this proposed architecture is improved. At a data rate of 150 kbit/s the Eb /n0 is 0.7 and 2.2 dB lower than that for coherent and non-coherent FSK respectively. This is an improvement compared to the PLLloop-filter architecture. The Eb /n0 ratio deteriorates sharply at data rates above 150 kbit/s. At the data rate of 223 kbit/s the Eb /n0 ratio has increased to 4.67 dB higher than the theoretical ratio for binary FSK. This architecture do not seem competitive compared to current FSK architectures due to the poor Eb /n0 ratios at data rates above 200 kbit/s. Additional Hardware As with the PLL architecture (discussed in section 8.1.1), the PLL with dither would need a PLL and hardware to generate the four phases. In addition, it would also need to dither between the phases during symbol transitions. This dithering will occur at high frequencies adding further to the global power consumption. See table 8.1 for an overview of additional hardware needed.
8.1.3
Direct Multiplexing
Two “Direct Multiplexing” architectures are proposed in this thesis and were simulated using different number of intermediate phases during symbol transitions, one with four and one with eight intermediate phases. At a data rate of 150 kbit/s both architectures require an Eb /n0 ratio 1 dB lower than that of coherent FSK and 2.5 dB lower than non-coherent FSK. The advantage of using a higher number of intermediate phases becomes apparent at data rates higher than 150 kbit/s. At 223 kbit/s the architecture using 4 intermediate phases has an Eb /n0 ratio 0.6 dB higher than coherent FSK while the architecture using 8 intermediate phases has an Eb /n0 ratio 0.42 dB lower than coherent FSK. The direct multiplexing architecture using 8 intermediate phases are, compared to the other simulated PSK architectures, the most competitive architecture at data rates over 200 kbit/s.
8.2 Final Conclusion
57
Additional Hardware The direct multiplexing architecture does not utilize the filtering techniques described in the preceding architectures and could therefor be designed without the use of a PLL. Taking advantage of the relaxed frequency deviation requirements of the MICS standard a distributed feed-back architecture could possibly be used as described in 3.1.1. If no channel selectivity is needed, an edge-combiner based architecture (see section 3.1.2) operating at low frequency could be used to generate the operating frequency. In order to use these architectures in PSK applications additional hardware is needed to generate and switch between the phases. Typically by the use of DLL:s and multiplexers. The additional hardware need are listed in table 8.1. Architecture PLL PLL + Dither Direct Multiplexing
PLL X X
Dither
X
Generate Phases Poly-phase X X
DLL 20-36
Multiplexer 4L X
4H
20-36 M
X X
X
L = Low Speed; M = Medium Speed, H = High Speed
Table 8.1: Additional hardware needed in PSK modulation.
8.2
Final Conclusion
The result from this thesis suggest that the simplified PSK architectures presented are not competitive compared to current FSK architectures at higher data rates. The benefits generally attributed to PSK, i.e. lower transmitted signal powers and higher bandwidth efficiency, is lost due to the amount of filtering needed to fit the PSK frequency spectra within the MICS mask. However, the presented PSK architectures could prove competitive at lower data rates below 230 kbit/s. What PSK architecture to use is dependent on the targeted data rate. The PLL based architectures are a viable alternative at data rates up to about 120 kbit/s wheres the multiplexing modulators are preferably used at data rates above 120 kbit/s to about 230 kbit/s. An overview of data rates and suitable architectures is summarized in figure 8.1. Architectures utilizing FSK modulation would need some means of shaping at data rates above 230 kbit/s but are less exposed to a deteriorated Eb /n0 ratio, due to a more favorable shaped frequency spectra defined by the MICS mask.
58
Conclusion
PLL
80k 90k
Unfiltered QPSK
Direct Multiplexing 4
120k
PLL + Dither
150k
FSK
223k
Direct Multiplexing 8
Figure 8.1: Graph showing what data rates could be considered for which architecture.
Bibliography [1] HFTA-010.0: Physical layer performance: Testing the bit error ratio (BER). Application note 3419, Maxim Integrated Products, 2004. [2] FCC rules and regulations , “MICS band plan” , part 95, Sep 2008. [3] Wong A.C.W., Kathiresan G., Chan C.K.T., Eljamaly O., and Burdett A.J. A 1 V wireless transceiver for an ultra low power SoC for biotelemetry applications. 33rd European Solid State Circuits Conference, pages 127 –130. IEEE Conferences, 2007. [4] Cook B.W., Berny A.D., Molnar A., Lanzisera S., and Pister K.S.J. An ultra-low power 2.4GHz RF transceiver for wireless sensor networks in 0.13µm CMOS with 400mV supply and an integrated passive RX front-end. In Digest of Technical Papers, International Solid-State Circuits Conference, pages 1460 – 1469. IEEE International, 2006. [5] Carrara F., Italia A., Palmisano G., and R. Guerra. A 400 − MHz CMOS radio front-end for ultra low-power medical implantable applications. In Proceedings of European Solid-State Device Research Conference, pages 232 – 235. IEEE Conferences, 2009. [6] Christer Frank. Telekommunikation, Informationsöverföring och Överföringssystem. Studentlitteratur, 2004. [7] Qizheng Gu. RF System Design of Transceivers for Wireless Communications. Springer, 2005. [8] Bohorquez J.L., Chandrakasan A.P., and Dawson J.L. A 350 µW CMOS MSK transmitter and 400 µW OOK super-regenerative receiver for medical implant communications. IEEE Journal of Solid-State Circuits, 44:1248 – 1259, 2009. Issue 4. [9] Maoud Salehi John G. Proakis. Communication Systems Engineering. Prentice Hall, 2002. [10] Bae Joonsung, Cho Namjun, and Yoo Hoi-Jun. A 490uW fully MICS compatible FSK transceiver for implantable devices. 2009 Symposium on VLSI Circuits, pages 36 – 37, 2009. IEEE Conferences. 59
60
Bibliography
[11] Kuan-Chao Liao, Po-Sheng Huang, Wei-Hao Chiu, and Tsung-Hsien Lin. A 400 − MHz/900 − MHz/2.4 − GHz multi-band FSK transmitter in 0.18 − um CMOS. Solid-State Circuits Conference, pages 353 – 356. IEEE Conferences, 2009. [12] Yao-Hong Liu, Ching-Jen Tung, and Tsung-Hsien Lin. A low-power asymmetrical MICS wireless interface and transceiver design for medical imaging. Biomedical Circuits and Systems Conference, pages 162 – 165. IEEE Conferences, 2006. [13] Nezhad-Ahmadi M.R., Weale G., El-Agha A., Griesdorf D., Tumbush G., Hollinger A., Matthey M., Meiners H., and S. Asgaran. A 2mW 400MHz RF transceiver SoC in 0.18um CMOS technology for wireless medical applications. Radio Frequency Integrated Circuits Symposium, pages 285 – 288. IEEE Conferences, 2008. [14] Bradley P.D. An ultra low power, high performance medical implant communication system (mics) transceiver for implantable devices. Biomedical Circuits and Systems Conference, pages 158 – 161. IEEE Conferences, 2006. [15] Nathan M. Pletcher. Micro power radio frequency oscillator design. Master’s thesis, University of California, Berkeley, 2004. [16] Behzad Razavi. RF Microelectronics. Prentice Hall, 1998. [17] Behzad Razavi. Design of Analog CMOS Integrated Circuits. McGraw Hill, 2001. [18] Rai S., Holleman J., Pandey J.N., F. Zhang, and B. Otis. A 500µW neural tag with 2µVrms AFE and frequency-multiplying MICS/ISM FSK transmitter. In Digest of Technical Papers, International Solid-State Circuits Conference, pages 212 – 213, 213(a). IEEE International, 2009. [19] Huseyin S. Savci, Ahmet Sula, Zheng Wang, and Numan S. Dogan. MICS transceivers: Regulatory standards and applications. In medical implant com-munications service, IEEE SoutheastCon, pages 179 – 182, April 2005. [20] Micheal Moher Simon Haykin. Modern Wireless Communications. Prentice Hall, 2005. [21] William Stallings. Data and Computer Communications. Pearson Prentice Hall, 8th edition, 2007. [22] Jiawei Yang, Nhan Tran, Shun Bai, D.C. Ng, M. Halpern, E. Skafidas, and I Mareels. A super low power MICS band receiver in 65 nm CMOS for high resolution epi-retinal prosthesis. In ASICON ’09, IEEE 8th International Conference on ASIC, pages 435 – 438. IEEE Conferences, 2009.
