Interconnect Opportunities – A Sematech Perspective

Transcript

Accelerating the next technology revolution Interconnect Opportunities – A SEMATECH Perspective Sitaram Arkalgud Sr. Director– Interconnect/3D IC 8th Annual Japan Symposium June 26, 2012 Tokyo, Japan Portions of this document are SEMATECH confidential, as marked Copyright ©2012 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners. The Interconnect Space • TSVs are just entering mainstream – Considerable issues around scaling (TSV and C2C interconnects), cost, thermal management and thin wafer/die handling • Cu will continue to be interconnect mainstay for many years – Resistance will rise exponentially with scaling – Considerable work on addressing issues at member companies, universities, consortia – Need to address weakest link in interconnect scheme Chip to chip (medium term driven by BW) or within chip (near term) • Power and signal mismatches between different chips will gate 3D stacking • ~Terabit/s data handling are contemplated for 2nd/3rd gen wide I/O DRAMs • Mixed electrical/optical approaches may be the only option • • Next generation options – Optical: nanophotonics – Electrical: graphene, nanowires and CNT Product functionality and power efficient performance at the right cost are the interconnect drivers 22 June 2012 2 3D Roadmap Interposer 3D 3D+ NGI? Pre-Development Logic NAND Development Heat Sink and memory TIM memory memory memory Si TSV interposer Logic - 22 June 2012 2013 Analog Common Industry Needs Production 2012 Heat Sink and TIM memory memory memory memory Si TSV interposer 2015 Materials and Process Evaluations Thermal Management Materials, EDA Understanding Costs Reference flows, BOM to CoO Technology Maturity & Standards Supply Chain Interfaces and handoffs Pathfinding Tools Performance, power, floor planning 2020 3 3D Interconnect Roadmap Interposer 3D 3D+ NGI? Pre-Development Courtesy: WWW.Intel.com Logic Development Heat Sink and TIM memory memory memory memory Si TSV interposer NAND First gen products underway Common Industry Needs Heat Sink and memory TIM memory Logic memory memory Si TSV interposer Production Analog - 2012 22 June 2012 2013 2015 Materials and Process Evaluations Thermal Management Materials, EDA Understanding Costs Reference flows, BOM to CoO Technology Maturity & Standards Supply Chain Interfaces and handoffs Pathfinding Tools Performance, power, floor planning 2020 4 Mission of Materials and Emerging Technologies Develop infrastructure for 3D transition in semiconductor industry • Infrastructure development: • Materials: Identify and down select • Tools/Processes: Develop with universities/suppliers and harden • Mechanisms: Fundamental understanding for manufacturability & scalability • Models: Develop approaches to aid characterization and reliability assessment • Key modules that enable acceleration of new technologies for manufacturing • Core competencies • • Narrow options: data driven consensus • Standardize methods: data driven benchmarking • Minimize cost, risk and avoid duplication Leverage resources from industry eco-system • Address problems that are difficult for any individual company to tackle • Nurture partnerships with suppliers and academia to execute mission 22 June 2012 5 Key Activities • Demonstrate manufacturability of key 3D processes needed for future generations • • • • • Low temperature Cu direct bonding process Underfill material development and assessment methodology for thermal management 20: 1 aspect ratio TSV test structures and associated challenges Materials and process development for thin wafer handling, temporary bonding and room temperature debonding Test structure development for package interactions and reliability monitoring • Enable and assess next generation 3D stacking implementation needs by driving inspection/metrology, standards and specifications through 3D EC • Gap assessment for feasible Next Generation Interconnect options 22 June 2012 6 Cu-Cu Direct Bond – Throughput Improvements • Conventional process (400ºC) has a throughput of ~0.5 WPH POR Low T Process – Vacuum requirement and high bond temperature negatively influence tool throughput New Tool Concept • Feasibility of low temperature (~200ºC, 5 min) process demonstrated on blankets – Process below Pb-free reflow temperatures introduces compatibility with all modern packaging materials • New tool concept proposed to increase throughput to 30 WPH – 88% reduction in COO High Resolution TEM 195 C / 5 minute bond E. Stinzianni Cu-Cu bond Interface 200ºC/10min 22 June 2012 R Edgeworth 7 TSV Module Roadmap Via Middle Gap Identification by TSV Node TSV Scaling Issues Module Process TSV LTH RIE WETS MTR INS MTL PLT FRN CMP • Increasing Aspect Ratio • Dielectric Liner Coverage and Continuity • Barrier-Seed Coverage and Continuity • Void-Free Cu Fill • Increasing RC Delay • Dielectric Liner Thickness • Cu Volume • Thermo-mechanical Performance • Improves with scaling, but remains a concern for device performance (KOZ) and reliability in increasingly fragile ULK dielectric layers • Bond and Thin Unit Process Development • Thin Wafer/Die Handling 22 June 2012 TSV Node 5µm × 50µm 2µm × 40µm Ready for HVM Ready for Initial Ramp-Up Not Ready Identify tool, material, and process gaps in the fabrication of high aspect ratio (20:1) TSVs; use cost-modeling to identify the HVM-capable solutions that best address these gaps. B Sapp 8 Scaling of Chip to Chip Interconnects Bonding Method C4 FC (Contolled Collapse Chip Connect) C2 FC (Chip Connect) TC/LR (Local Reflow) FC TC FC > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um Conventional Reflow Reflow with Cu pillar Thermal Compression with Cu pillar Thermal Compression Bump Metallurgy Solder (SnAg or SnAgCu) Cu + Solder (SnAg or Sn) Cu + Solder (SnAg or Sn) Cap Cu Bump Collapse Yes No No No - No flow - No flow - Wafer Level - Wafer Level Schematic Diagram Major Bump Pitch Range at Application Bonding Method Underfill Method 22 June 2012 - Capillary - No flow - Capillary - No flow - Wafer Level M-S Suh 9 Scaling of Chip to Chip Interconnects Bonding Method C4 FC (Contolled Collapse Chip Connect) C2 FC (Chip Connect) TC/LR (Local Reflow) FC TC FC > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um Conventional Reflow Reflow with Cu pillar Thermal Compression with Cu pillar Thermal Compression Solder (SnAg or SnAgCu) Cu + Solder 2012 TSV (SnAg or Sn) Cu + Solder (SnAg or Sn) Cap Cu No No - No flow - No flow - Wafer Level - Wafer Level Schematic Diagram Major Bump Pitch Range at Application Bonding Method Bump Metallurgy 2014/15 TSV Bump Collapse Underfill Method 22 June 2012 Yes - Capillary - No flow No - Capillary - No flow - Wafer Level M-S Suh 10 Next Generation Interconnect Doped Copper Silver Gold Graphene Carbon Nanotubes Nanowires Superconductors 2D Conductors Optical Interposer Optical Onchip Better evaluated at MC Futuristic Difficult to implement in fab Still in research mode Futuristic Futuristic Narrow to 1-2 “most likely” options 2012 2017 University Research Member Company Implementation SEMATECH testbed for materials, processes and tool evaluations • All options will leverage 3D IC in some form • We will use our 3D IC capability to narrow down options for manufacturability 22 June 2012 11 Attributes of CNT and Graphene Si Resistivity (u.ohm.cm) Current density (A/cm2) Carrier Mobility (cm2/Vs) Thermal Conductivity (W/mK) Cu 1.68 10E6 450 400 Graphene 1 10E8 200,000 5000 CNT 1 10E9 100,000 3000 • Both graphene and carbon nanotubes promise superior properties compared to Cu – Virtually ballistic transport – Higher reliability – Higher thermal conductivity 22 June 2012 12 GNR – Modeling and Status • Naeemi plot vs Murali plot Resistivity shows increase with scaling! Attractive alternatives to Cu A Naeemi and J Meindl, IEEE TED (56) 9, 2009 R Murali et al EDL(30) 96 2009 • Graphene shows considerable promise with large MFP (virtually ballistic), mobility, thermal conductivity and EM resistance • Still relatively immature • Minimizing edge effects and demonstrating low resistivity is key for interconnects 22 June 2012 13 CNT Status* MIRAI-Selete ==> Samsung ==> KAIST AIST, LEAP VIACARBON ==> LETI, Cambridge IMEC Requirement Technology Process Single Damascene Single Damascene Single Damascene Single Damascene Co particle/TiN/Ta/Cu Catalyst/Bottom Electrode CNT Growth Temperature CNT Density (/cm2) < 400C Top Electrode Resistivity (mWcm) Current density (A/cm2) • • Co film/Ti/TiN Fe film/AlCu Ni film/TiN Thermal CVD, Thermal CVD C2H2 Remote Plasma Thermal CVD, C2H4/H2/Ar, 400 365 - 450C CVD, CH4/H2, 600C C2H2/H2/He, 580C 470C > 10E12 10E11 - 10E12 4*10E11 2.5*10E12 7*10E10 ~ 2*10E11 < 400C CMP Ti/Cu (RT) CMP Ti/Al (500C) CMP Ti/Pt (RT) CMP Ti/Au (400C) ~10 (W), ~2 (Cu) 10 (52 W @ f 70nm, 450C) 73 (293 W@f 80nm) 390k (10 kW@f 1000nm) 28k (7.9 kW@f 300nm) > 10E7 2*10E8 ---------- ---------- ---------- CNT has properties similar to graphene Still relatively immature • Demonstrating low resistivity is key for interconnects * Adapted from “M Nihei “CNT/Graphene Technologies for Advanced Interconnects” IITC Short Course, June 3 2012 San Jose, CA” 22 June 2012 14 Electrical Interconnect Limitations  Bandwidth Limitations – Wires are not scalable Area 16 Maximum Bandwidth: B µ10 Length 2 D. Miller, J. Parallel and Dist. Comp. 41, 4252 (1997) Bandwidth is fundamentally limited by the available area (e.g. once all area is used there is no more capacity)  Source: IBM Power Limitations - Total interconnect power is too high ~50% of Total Chip Power Expected to rise to >80% D. Miller, Proc IEEE 97, 1166 (2009) Cannot increase total power. Limited to ~200W.  Signal Integrity and Latency Limitations RC Delay will increase considerably with scaling 22 June 2012 SEMATECH Confidential Sam Naffziger, AMD Fellow, 2011 VLSI Symposium Keynote 15 Why Silicon Photonics? Silicon photonics is a promising technology:  High Bandwidth (>200 THz)  Low Power (<100 fJ/bit)  Compact Devices (< 2mm3)  Compatible with Fiber Optics  Seamless CMOS Integration Silicon Photonic Circuit All components of a Silicon Photonic Interconnect have been demonstrated: Laser Intel/UCSB – III-V Bonded Laser MIT – Ge Laser 22 June 2012 Electro-Optic Modulator Photodetector Intel – Ge Detector Cornell University – Microring Modulator K-W Ang 16 SEMATECH’s Si Photonic Building Blocks Lasers Waveguides Modulators Detectors Switches Heaters Gratings Interconnects  SEMATECH has designed a complete Silicon Photonic device library  The device library uses a 300mm reference flow  The interconnects will be integrated into a 3D CMOS process 22 June 2012 K-W Ang 17 Maturity of Interconnect Options Stages Concept Mechanisms Reference Flow UPD Materials Selection Device Feasibility Module Development Module Equipment Hardening Infrastructure Reliability HVM C&F Cu 2D X X X X X X X X X X Interconnect Options Cu 3D Optical Graphene X X X X X X X X X X X X X X X X X CNT X X Best candidate for Next Generation HVM Relatively immature 22 June 2012 18 Enablement Center • Very successful program – Focus is on enabling standards (http://wiki.sematech.org) and ensuring chip interoperability • Obtained considerable industry attention – Attracted several new members since Jan 2011 start • Analog Devices, Altera, Invensas, NIST, On Semiconductor, Qualcomm • Increased program diversity – Network has expanded considerably • Strong relationship with SRC, SEMI, SI2, JEDEC • Fabless companies, OSATs and universities • 3D Enablement Center playbook is a template for NGI – – – – Reference flow(s) Gap analysis Standards and specifications Forward looking option assessments with pathfinding tools 22 June 2012 19 3D Members and Partners 22 June 2012 20 Summary • Interconnect Center is addressing material and tool gaps by leveraging existing capabilities in 3D program – TSV and advanced package interactions • Thin wafer/die handling • Cu-Cu direct bonding • Underfill • TSV scaling, infrastructure gaps – Working on gaps for next generation interconnect • Enhancing linkage to key research institutions and universities to translate concepts from lab to fab • Interconnect continues to require engagement of larger section of the supply chain – Fabless, packaging, suppliers, universities 22 June 2012 21 22 June 2012 22