Internal Memory

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OpenStax-CNX module: m29427 1 ∗ Internal Memory Nguyen Thi Hoang Lan This work is produced by OpenStax-CNX and licensed under the † Creative Commons Attribution License 3.0 1. Semiconductor Main Memory The basic element of a semiconductor memory is the memory cell. There are a lot of semiconductor memory types shown in table 11.1 Table 11.1 Semiconductor Memory Types RAM: Read-write memory The two basic forms of semiconductor Random Access Memory (RAM) are dynamic RAM (DRAM) and static RAM (SRAM). SRAM is faster, more expensive and less dense than DRAM. DRAM is usually used for main memory. • Dynamic RAM - Storage cell is essentially a transistor acting as a capacitor - Capacitor charge dissipates over time causing a 1 to ip to a zero - Cells must be refreshed periodically to avoid this - Very high packaging density • Static RAM: It is basically an array of ip-op storage cells - Uses 5-10x more transistors than similar dynamic cell so packaging density is 10x lower - Faster than a dynamic cell ∗ † Version 1.1: Jul 15, 2009 10:30 pm +0000 http://creativecommons.org/licenses/by/3.0/ http://cnx.org/content/m29427/1.1/ OpenStax-CNX module: m29427 2 ROM : Read Only Memories A Read only Memory (ROM) contain a permanent of data that canot be changed. - Permanent data storage - ROMs: Data is wired in during fabrication at a chip manufacturer's plant - Purchased in lots of 10k or more • PROMs: Programmable ROM - Data can be written once by the user employing a PROM programmer - Useful for small production runs • EPROM: Erasable PROM - Programming is similar to a PROM - Can be erased by exposing to UV light • EEPROMS: Electrically erasable PROMs - Can be written to many times while remaining in a system - Does not have to be erased rst - Program individual bytes - Writes require several hundred usec per byte - Used in systems for development, personalization, and other tasks requiring unique information to be stored • Flash Memory: Similar to EEPROM in using electrical erase - Fast erasures, block erasures - Higher density than EEPROM 1 2. Memory Organization 1.1 2.1 Memory Organization from the memory chip Each memory chip contains a number of 1-bit cells. The 1, 4, and 16 million cell chips are common. The cells can be arranged as a single bit column (e.g., 4Mx1) or in multiple bits per address location (e.g., 1Mx4) - To reduce pin count, address lines can be multiplexed with data and/or as high and low halves Trade o is in slower operation • Typical control lines: W* (write), OE* (output enable) for write and read operations CS* (chip select) derived from external address decoding logic RAS*, CAS* (row and column address selects) used when address is applied to the chip in 2 halves • Example: http://cnx.org/content/m29427/1.1/ OpenStax-CNX module: m29427 3 Figure 1 Figure 11.1 Organization 256Kx8 memory from 256Kx1 chips http://cnx.org/content/m29427/1.1/ OpenStax-CNX module: m29427 4 Figure 2 Figure 11.2 . Mbyte Memory Organization 1.2 2.2 Error correction • Problem: Semiconductor memories are subject to errors  Hard (permanent) errors  Environmental abuse  Manufacturing defects  Wear  Soft (transient) errors  Power supply problems  Alpha particles: Problematic as feature sizes shrink  Memory systems include logic to detect and/or correct errors  Width of memory word is increased  Additional bits are parity bits  Number of parity bits required depends on the level of detection and correction needed • General error detection and correction  A single error is a bit ip  multiple bit ips can occur in a word  2M valid data words  2M+K codeword combinations in the memory http://cnx.org/content/m29427/1.1/ OpenStax-CNX module: m29427 5  Distribute the 2M valid data words among the 2 M+K codeword combinations such that the distance between valid words is sucient to distinguish the error Figure 3 Figure 11.3 • Single error detection and correction  For each valid codeword, there will be 2K-1 invalid codewords  2K-1 must be large enough to identify which of the M+K bit positions is in error  Therefore 2K-1 > M+K  8-bit data, 4 check bits  32-bit data, 6 check bits  Arrange bits as shown in Figure 11.4 http://cnx.org/content/m29427/1.1/ OpenStax-CNX module: m29427 6 Figure 4 Figure 11.4  Bit position n is checked by bits Ci such that the sum of the subscripts, i, equals n (e.g., position 10, bit M6, is checked by bits C2 and C8) To detect errors, compare the check bits read from memory to those computed during the read operation (use XOR) + If the result of the XOR is 0000, no error + If non-zero, the numerical value of the result indicates the bit position in error + If the XOR result was 0110, bit position 6 (M3) is in error Double error detection can be added by adding another check bit that implements a parity check for the whole word of M+K bits. SED and SEC-DED are generally enough protection in typical systems http://cnx.org/content/m29427/1.1/