Transcript
Electronics a n d Software for Scanning Tun neling Microscope Kun da n Singh, B.P. Ajith Kumar. Inter University Accelerator Center, Ar u n a Asaf Ali Marg, New Delhi – 110067.
Intr o d uc tio n A Scan ning Tun neling Microsco pe (STM) is a device for imaging con d ucting s urfaces at very high m agnifications d ow n to t he scale of individual ato m s. The STM d oe s t his by m echa nically scan ning a s har p t u ngs te n tip over t he s u rface (sa m ple to be sca n ne d). Piezoelectric ele me nt s can p r ovide t he necessary s m all tra nslations of t he tip. A bias voltage is a p plied between t he tip a n d t he s a m ple. When t he tip is b ro ug h t within abo ut 10Å (1n m ) of t he sa m ple, electro n s fro m t he sa m ple begin to "tu n nel" t h ro ug h t he 10Å gap into t he tip or vice versa, de pe n ding u p o n t he p olarity of t he bias voltage. The res ulting t u n neling cur ren t varies with tip - to - s a m ple s p acing, bo t h t he sa m ple an d t he tip m u s t be con d uctor s or se micon d uctors. The t u n neling current is a n expo ne n tial function of dista nce. Based o n q ua n t u m m ech a nics, t he t u n neling curre nt (It ) is, It = ex p( - k d) where d is t he dista nce between tip an d s a m ple s u rface. This res ult t u r n s ou t to be t he key to STM. If a n ato mically s har p tip is u se d, t he t u n neling curre nt fro m t he first ato m of t he tip will be expone ntially larger t ha n t ha t of t he tip ato m s which are slightly be hin d it. If t he se paration between t he tip a n d t he s a m ple cha nges by 1 0% (on t he or der of 1Å), t he t u n neling cur ren t cha nges by an or der of m agnit u de. This expo ne n tial de pe n de nce gives STMs t heir re ma rkable se nsitivity. STMs can image t h e s u rface of t he sa m ple with s u b - angs tro m p r ecision vertically, an d ato mic resolution laterally. The Scanning Tun neling Microscope (STM) is t he a nces to r of all sca n ning p r obe microscopes. It was invente d in 1981 by Gred Binnig a n d Heinrich Rocher at IBM Zurich. Five years later t hey were awar de d t he Nobel Prize in Physics for its invention. The STM was t he first instr u me n t to generate real - s p ace images of s u rface with, so called, ato mic resolution (ato mic lattice resolutio n to be p recise). As t he co ncep t is relatively sim ple. Just place a s har p t u ngs te n or platin u m irra diu m tip close to a con d ucting s urface, so close t ha t t he wave functions of t he closest tip ato m an d s urface ato m s overla p. Apply a p o te n tial differe nce between tip an d s u rface a n d a t u n neling curre nt flows. But t here are real challenges to con t rol t he dis ta nce betwee n tip an d sa m ple at few a ngs tro m witho u t cras hing t he tip to t he s u rface. The feedback circuit, tip a p p r oach m echa nis m, an d ot her electro nic m o d ules s ho uld be very rob us t. The overall noise level of t he syste m s h o uld be < mV.
The overall sche me of t he sca n ning t u n neling microscope (STM) is s how n in figure 1. It o u tlines t he d a ta acq uisition ,control circuit logic a n d t he feedback loop for t he STM.
Block Diagram Repre s e ntation of STM Electronic s Module s :
Figure 1: Data acquisition a n d contr ol circuit logic for t he STM. The overall sche me a n d t h e feed back cont rol circuit is o utline d here.
An Over vie w of Electronic Module s The STM el ectronic s c o m pris e s of the f ollo win g m o d ule s, p erf orming th e f ollo wing function s : 1. Po w er Suppl y The d riving so u rce for all t he m o d ules of t he STM. Sup ply voltages nee de d here are Two + 5Vdc, + / - 15Vdc, + / - 110Vdc a n d 110Vac. 2. Tunn eling Current A m plifier Am plifies t he Tun neling Curre nt (as it is in t he ra nge of pA - nA). 3. PI Feedback Control Circuit Integrate t he error between t he t u n neling curre nt being observed against a cons ta n t value (here ter me d as Set - Point) of t u n neling cur re nt t ha t is to be m aintaine d which m ea n s t ha t t he tip a n d t he sa m ple are always ke pt at a fixed se paration (this error voltage is u s e d to contr ol t he z - direction m ove me n t of t he tip). 4. Slope Com p e n sation and High Voltage Am plifier The Z - o u t p u t (integrate d error for z - direction m ove me nt) fro m t he PI is slo pe co m p e n s ate d for slope along X an d Y axis. It is t ha n level s hifte d by a High voltage a n d fed b ack to t he STM Head to keep t he tip - align me n t s tea dy. Scan voltages X+, X-, Y+ a n d Y- are a m plified to ± 1 0 0V ra nge u sing high voltage a m plifiers. 5. Pie z otub e Walker Control Circuit It con tr ols t he coarse a p p r oach m echa nis m for t he sca n ning t u n neling microsco pe. It p r ovides t he neces sary contr ol signals to t he m echa nis m which is nee de d to b ring t he tip a n d sa m ple s urface within t he ra nge of sca n ner pie zo ( < 1 µ m), s tar ting fro m a se p ara tion of abou t a few millimeter s. 6. Data Acquisition, Control and PC interfac e Circuit It co - or dinates between all t he electronic m o d ules of t he STM. Here t he error signal is digitize d, containing all t he p recious infor m a tion abo u t t he s u rface p r ofile of t he sa m ple which is t reate d cos metically to p rese nt t he images o n t he screen. This boar d co m m u nicates with PC via LPT p or t. PC grou n d a n d t he syste m gro u n d is ke p t se p arate to mini mize t he effect of PC noise.
Tu n n eling Curre n t Am plifier The t u n neling curre nt between tip a n d t he sa m ple contains all t he es se n tial infor m atio n s. The t u n neling cur re n t p r ovides t he basic to pogra p hy of t he s a m ple s u rface for t he d eter mination of t he ato mic s tr uct u te an d it gives t he t u n neling s pectro sco py for t he electronic s t r uct ure. Since t he m agnit u de of t he t u n neling curren t occur ring in STM is very s m all, typically fro m 10 pA to 50 nA. It s ho uld be a m plified by t he gain of 10 9 (V /A) to be u se d in t he electronic circuits of STM. Hence t he high p erfor m a nce cur ren t - to - voltage conver ter (IVC) is a n esse ntial ele me n t of a n STM. In o u r electronics de sign we have u se d inverting feedback type IVC, since it is convenien t for t he de tection of a fast an d low current signal d ue to wider b an dwid t h a n d lower noise. The inverting feedback IVC can be b uilt easily u sing co m m ercial ultra - low inp u t bias cur ren t a n d very high inp u t im pe de nce o peratio nal a m plifiers an d a very high - o h m fee dback resistor as s hown in Fig.2. Ideally t he inverting feedback curren t - to - voltage conver ter with a large feedback resista nce above 1G Ω can p r ovide a p r o per dyna mic ra nge covering t he t u n neling cur re nt (pA nA) a n d mini mise t he noise.
The n o n - inverting inp u t of t he o p - a m p is gro u n de d, a n d t he voltage at t he inverting in p u t s ho uld be equal to gro u n d. This im plies VOUT =
- IIN * RFB
; RFB is 1G Ω in o ur de sign
In t he d esign we a p ply negative bias voltage o n t he sa m ple plate a n d t he directio n
of curren t is o ut of t he o p - a m p. For RFB = 1G Ω, 200 pico a m pere of t u n neling curren t res ults in an ou t p u t voltage of 200 mV.
Fee d b ack Circuit : P - I co n t r ol In sca n ning t u n neling microsco py, a fee dback sys te m is u se d to cont rol t he tip sa m ple s p acing in or der to m aintain a s table t u n neling ju nction. A fixed tip - s a m ple bias voltage is a p plied a n d t he de sire d t u n neling cur ren t is selecte d by t he o p erato r. The feedback cont rol is u se d to a dj us t t he gap between t he tip an d t he sa m ple u n til t h at t u n neling curre n t is achieved. The t u n neling curren t picked u p is co n verte d into voltage u sing cur ren t - to - voltage conver ter (IVC) a n d is co m pa re d with a reference voltage, which re prese n ts t he set p oint of t he t u n neling curre nt. The erro r signal is t he n se n t to t he feedback circuit, a rob u s t de signe d P - I (propor tional integratio n) a m plifier, which se n d s a voltage signal to t he z - pie zo. The p h a se of t he collection of all t he a m plifiers is chose n to cons tit ute a negative feedback i.e. if t he t u n neling curren t is larger t ha n t he p re set current, t he n t he voltage a p plied to t he z - pie zo ten d s to with dr aw t he tip fro m t he s a m ple s urface, a n d vice versa. There fore t he eq uilibriu m z - p o sition is establishe d t hr o ugh t he fee dback loop. As t he tip sca n s in t he x - direction, t he conto ur height z also cha nges with time. The fu nctio n of t he fee d back circuit is to m ake t he tip accurately follow t he cons ta n t t u n neling curren t con to ur at t he highes t p o s sible s pee d. A block diagra m of t he fee dback syste m of a n STM is s how n in Fig.3.
Gain (1- 128) Volt age t o Dat a Acq u is it ion boar d
VTC VZp i
PGA Program m able Gain Am p lifier
Gain (0.1- 2)
Res e t
∫
+/
X/ Y- Slop e com p en s at ion
P H
Polarit y Select or In t egrat ion circu it An alog Swit ch Tim e con s t an t 10µ s – 10m s
Z- Offs et Volt age
Prop ort ion al Gain Am p lifier
∑ High Volt age Gain
y
Fe e dbac k Ele ctro nics R FB 1 GΩ
z x Tip
Volt age t o Zp iez o
Bias volt age
VTC
IIN Sam p le Sam p le Dis c
Segm en t e d Scan n er Piez o
ε Error Sign al
Tu n n elin g Cu rr en t Am p lifier
Fig.3. A s ch em at ic of t h e feed back loop in an STM.
B Bu ffer
VS Set Poin t for d es ired cu rren t
Figu re.3. illustrates t he block diagra m for t he z - m o tion, i.e. t he m o tion of t he tip p er pe n dicular to t he plane of t he sa m ple, of t he STM. A s tr aight forwar d a nalysis of t he syste m m ay be perfor me dif t he sys te m is as s u m e d to be linear. Most of t he co m p o ne n t s be have in a fairly linear fas hion except for t he t u n neling gap. The t u n neling gap o ut p u t is a n expo ne ntially varying cur ren t for linear variations in t he gap dista nce b u t it can be treate d as linear if t he variations in t he gap dista nce are s m all. By t his as s u m p tion we can o mit t he req uire me nt of logarith mic a m plifier after curre n t to voltage conver ter in t he design. The goal of t he fee dback circuit d e sign is to mini mi ze t he error signal ‘ε’. The contr ol block is develope d s uch t h a t t he syste m m aintains t he de sired t u n neling curren t with t he neces sary accuracy. The co n s traints p u t o n t he electro nics design are : 1. The res ulting syste m m u s t be s table, i.e. t he error signal ‘ε’ m u s t n ot increase in a n u n bo u n de d fas hion (when t he feedback loop is on) as a fu nction of ti me. 2. The s tea dy s ta te error of t he syste m m u s t be s m all. 3. The tr a n sient res po n se of t he syste m m u s t be reasonably fas t an d oscillations s ho ul d decay q uickly. Keeping in min d t he above ba sic req uire me n t s of t he syste m de sign, t he error signal ‘ε’ is p r oces se d by t he feedback electro nics which typically contain s a p r o p o r tion al gain a m plifier, a n integrator circuit a n d a high voltage gain a m plifier. The p r o p o r tional gain a m plifier ha s a si m ple p r o por tional cont rol fu nction G1 (s) = k P ωc / (s + ωc) Where k P is t he dc - gain a n d ωc is t he high freque ncy cutoff at f c = ωc / 2 π. Since t he s tea dy s tate error signal ‘ε’ in o ur design is reference signal divide d by t he ter m 1 +G(s), so if t he p r o por tional gain k P is large t he n t he s tea dy s ta te error signal ‘ε’ is s m all, b u t n ot z ero. Practically we h ave see n t hat for s ufficiently high gain t he syste m beco mes u n s ta ble. Thus t here is a co m p r o mise between re d ucing t he s tea dy s tate error signal a n d m aintaining t he sys te m s tability with p r o p or tio nal s tage. A low pa s filter ha s been inclu de d in t he p r o p or tional gain s tage to im pr ove t he sys te m s tability. The cutoff freq uency ωc is m uc h lower ( ~ 1.6kh z) t ha n t he pie zoelectric ele me nt’s reso na n t freque ncy ( ~ 10k h z). This low p a s s filter p reven t s t he p r o p o r tional gain s t age fro m a m plifying t he resona nce. The dc gain of t he p r o p o tio nal gain s tage varies fro m 0.1 to 2. The finite s tea dy s t ate error h as bee n eliminate d by inclu ding a n integrator in t he con t rol block. In fact we can say t his feedback cont rol is m o re like a integratio n o nly con t rol syste m. In t he de sign integration s tage follows t he p r o por tional gain s tage an d t he res ulting tr a n sfer fu nction is G1 (s) = k P ωc / (s + ωc) * k I / s Here t he first ter m is t he p r o por tional gain with a n u p pe r cutoff freq ue ncy ωc, while t he seco n d ter m is a n integrator with gain k I. The integrator causes a s m all error signal to be integrate d in ti me, p r o d ucing m o re an d m o re cont rol action u n til t he error is eliminate d. Thus t he s tea dy s tate error of t his syste m is z e ro for a signal t h a t cha nges in a s te p like m a n ner. The p olarity selector switch selects t he p h a se of t he signal s uch t ha t t he syste m
con s tit u te n egative feedback to m aintain a cons ta n t curre nt in close d loop. The signal is followed by t he high voltage gain a m plifier. The high voltage a m plifier h a s a tr a n sfer fu nction G2 (s) = k hv ωhv / (s + ωhv) Where k hv is t he dc gain an d ωhv is t he high freque ncy cutoff of t he a m plifier. The integrator circuit p r ovides a n integration co m pe nsa tion, typically ti me con s ta n t varies fro m 10 µ s to 10 m s. A high voltage a m plifier p r ovides a n o ut p u t of ± 10 0V to d rive t he z - pie zo. The o u t p u t of t he feedback electronics is a p plied to t he z - pie zo (tip), to keep t he error between t he act ual t u n neling curre nt an d t h e reference cur re n t very s m all. As t he tip is sca n ne d acros s t he s u rface, variation s in t he sa m ple to pogra p hy an d electro nic s tr uct u re affect t he t u n neling cur ren t. The fee d back co n tr ol circuit m u s t react to bring t he curre nt back to t he de sire d value. Ideally, t h e correction s ho uld be m a de insta nt a neo usly a n d exactly. However, t here is always a finite res po n se time of t he feedback contr ol syste m. The voltage a p plied to t he tip (before high voltage a m plifier) is digitize d with 16 - bit resolutio n a nalog - to - digital conver ter (ADC) an d recor de d as t he to pogra p hic image.
P - I Co n t r ol Setting s : Proportional dc Gain: Vp = KP * (VT − (1 / 1 0)VS) Verror = VT – Vs k P = (100 Ω + 20k Ω(variable)) / 10k Ω = 0.1 to 2.1 P - Gain Dial Pot (10 - t ur n s) Settings: 6.5 k P = (100 Ω + (6.5 / 1 0)*20k Ω) / 10k Ω = 13.1k Ω / 10k Ω = 1.31 Integration circuit settings: Zpi = 1 /T * ∫t (Vp) d t I - Gain Dial Pot (10 - t ur n s) Settings: 3.0 RI = 100 Ω + (3.0 / 1 0)*100k Ω = 30.1k Ω CI = 0.1uF Integral Ti me Constant: T = 30.1 * 0.1 μ f = 3.01 * 10 - 3 s = 3.01 m s
Feedback Bandwidth: f = 1 /T = 1 / 3.01 * 10 - 3 s = 3.33 kH z
Piez oelectric Scan n er Tu be Theory : X, Y Scan voltages A piez oelectric t ube is a cera mic t u be in which t he m a ny m olecular di poles, or p o sitive - n egative charge se parations, are p olarize d at an elevate d te m pera t ure by a p plying a (typically) p o sitive voltage to an o uter electro de (inner at grou n d). The p o sitive o u ter voltage causes t he m olecules to p a r tially align t he m selves with t h e p o sitive directe d ou twar d, res ulting in + o uter a n d - inner ra dial p olarization. The cera mic is t he n cooled to retain t his p olarization per m a ne n tly. The res ulting cera mic h a s a net negative charge on t he inside s urface a n d net p o sitive charge o n t he o u t side s urface. When a s m aller voltage is t he n a p plied with t he sa me p olarity as t he p olarizing voltage, t he ele me n t experiences a te m p or ary expan sion in t he p olarizing direction (i.e., t he t ube ra dius expa n d s) a n d contraction in t he p er pe n dicular direction (i.e., t he t u be lengt h contracts). It is t his cont raction t h a t res ults in t he t u be be n ding, t h u s allowing X-Y sca n ning. The be n ding of t he a pie zo t u be in X an d Y direction (as s how n in Fig.4b.) is d u e to t he p o ten tial difference over differen t seg me n t s of t he sca n ner pie z o. Voltage variation s over X+ /X - m ake it deflect right a n d left whereas over Y+ /Y - causes deflectio n u p a n d d ow n. The four seg me n t s are s how n in Fig .4a.
Extracting d e sign param et er s:
For calculating X a n d Y m ove me n t / volt we ass u me t hat equal a n d o p po site voltages are a p plied on t he o p p osite q ua d ra n t s. X-Y Flex m o tion u sing m ulti - electro de co nfiguration is given below: ΔX = 1.8 * d 31 * V x * L² / [ ID * (OD - ID) ] where, ΔX : Deflection p r o d uce d in t he scan ner pie zo along X-axis d 3 1 : Piezoelectric Charge Coefficient (pC /N) L : Length of t he Scan ner Tube Vx : Applied Voltage ID : Inner Diameter of t he t u be OD : Outer Dia meter of t he t u be Our Pie z o Param eters are: d 3 1 : - 2 15 pC /N L : 11.0 m m Vx : 1V ID : 5.33 m m OD : 6.60 m m Therefore, for Vx = 1V ΔX = 1.8 * ( - 215 * 10 - 12 ) * 1 * (11 * 10 - 3 )² / [ 5.33 * 10 - 3 * (6.60 - 5.33) * 10 - 3 ] = 69 17.7 * 10 - 12 m = 6.9177 * 10 - 9 m = 6.9177 n m So, the d eflection produ ce d in th e pie z o tub e in X /Y direction = 6.9 1 7 7 n m / V Peculiarit y o f De sign: Since, t he voltage a p plied on t he o p p osite faces of sca n ner pie zo seg me n t are of o p p o site p olarity - t he p o te ntial difference between t hese two faces is d o u ble of t he act ual voltage a p plied. So, when t he DAC ou t p u t o n t he X/Y seg me nt s of t he sca n ner pie zo is, say V volts – t he deflection p r o d uced in t he t ube corres po n d s to 2V volts. Hence, in t his case t he deflection p r o d uce d for when X/Y Scan signal is 1V is cha nge d. ΔX = 2 * 6.9177 n m = 13.835 n m /V The v alu e of d eflection produc ed (in thi s ca s e) in X /Y direction = 1 3.8 3 5 nm /V These calculations gave fair idea of t he or der of X an d Y scan voltages req uired. These X a n d Y voltages will co me fro m Digital - to - Analog converter’s d riven by software. Since o ur DACs are 12 - bit resolution with ra nge ± 10V. So t he mi ni m u m cha nge in X, Y voltages will be 20000 mV / 4096 s te p s = 4.88 mV pe r s te p in t he large area m o de of sca n ning. The m axi m u m scan ning area of abou t 2800 a ngstr o m s by 28 00 angs tro m s (280n m x 280 n m) is achieved with ± 10 volts a n d 256 s te p s p er
line sca n, with o ur scan ner t ube. In t he s m all area m o de(highes t resolution), DACs p r o d ucing X a n d Y sca n voltages are res tricte d to ± 2.5V ra nge over 12 - bit resolu tio n, so t he mi ni m u m change in X, Y voltage is 5000 mV / 4 0 96 = 1.22 mV. The min imu m sca n ning area ( with highes t resolution) of abo ut 43 a ngs tro m s by 4 3 a ngst ro m s is achieved with t his scan m o de. Since a typical ato m si ze is aro u n d 3 a ngst ro m in dia meter, s o with t he s m all area m o de we can resolve t he ato m s e.g. HOPG (Highly Oriente d Pyrolytic Grap hite) sa m ple. There is a a not her se t of DACs p r ovided ( one each for X an d Y) called offset DACs which will p o sition t he tip on x - y plane to take highes t resolution scan s o n differ en t locatio n s of t he s urface. We can p o sition t he tip u sing t hese offset DACs in x - y plane a n d genera te two equal an d o p p osite sawtoot h waves i.e. X+ on one electr o de q u a d r a n t a n d X- o n o p po site electro de q ua dr a n t u sing scan DAC. Many sawtoo t h waves will be generate d d u ring X-sca n ning (na me d horizo n tal scan ning) with Y incre me n te d at t he en d of each x - scan / r e tr ace line. Alter natively, m a ny s awtoot h waves will be generate d d u ring Y-scan ning (na me d vertical sca n ning) with X incre me n te d at t he en d of each y - scan / r e tr ace line. To fur t her increase t he scan area we are u sing high voltage a m plifiers which is a m plifying t hese X+, X-, Y+ a n d Y- sca n voltages. In effective we are increasing t he ra nge of s u rface area scan s. These high voltage a m plifier can be u se d in two gain m o de s either 1X or 10X, which is software controlled. The 1X gain m o de is kee ping t he scan voltages in t he + - 10V ra nge. Where as 10X gain m o de jacks u p t he scan voltages to ± 100V ra nge. Effectively o ur m axi m u m sca n area in t he 10X m o d e is abo u t 2.8 µ m by 2.8 µ m.
Z - Motio n of sca n n e r pie z o : Driver voltage The Z - voltage cont rols t he lateral m o tion of t he tip. Z - p o sitioning in t he scan ning m o de, u ses a ± voltage ra nge to vary t he tip p o sition to kee p t he tip within a n a ngst ro m or two of t he sa m ple s urface, via fee dback m aintena nce of a cons ta n t t u n neling curren t. The m ajor co m po ne n t of Z - voltage co mes fro m t he fee dback circuit, which t ries to m aintain a cons ta n t cur ren t set by t he feedback. The lateral m ove men t of t he scan ning t ube is calculate d by for m ulae
ΔL = 2 * d 31 * V Z * L / [OD - ID ] where, ΔL : Change in lengt h in t he sca n ner pie zo along Z - axis d 3 1 : Piezoelectric Charge Coefficient (pC /N) L : Length of t he Scan ner Tube VZ : Applied Voltage ID : Inner Diameter of t he t u be OD : Outer Dia meter of t he t u be ΔL = 2 *215* 10 - 12 *1 *11.0 * 10 - 3 / [6.60 - 5.33] * 10 - 3 = 3724.4 * 10 - 12 m /V
= 37.244 Ao / V = 3.7 n m / V In o u r scan ner pie zo t his value co me s o ut to be 3.7n m /V. There are ot her co m p o n e n t s which are a d de d at t he high voltage s tage i.e. Z - offset voltage (12 - bit DAC), ra nges ± 1 0V, a n d X/Y slo p co m pe n s ation. Since in t he to pogra p hic image we are interes te d in s m aller variations of t he fee dback voltage. The Z - offset co m p o n e n t corrects t he dc - offset intro d uce d by t he feedback circuit in t he Z - voltage. The slo p co m p e ns ation co m p o ne n t is effective while sca n ning an d eliminates any slo p between t he tip an d sa m ple s urface. The final Z - voltage after high voltage a m plifier is, Zhi = HVA - Gain * (Zpi + Zoffset + X/Y - Slope Com po ne nt s) HVA - Gain = 10
Dat a Acq uisitio n a n d PC Interface : All t he co n tr ol voltages req uire d in t he de sign are generate d in t he d a t a - acq uisitio n a n d interface boar d. Data acq uisition is acco m plishe d u sing 16 - bit analog - to - digital co nverter (ADC). Each dis play p oint sa m pled would contain t he analog Z p o sitio n, so we h ave u s e d at a mini m u m a single 16 - bit analog - to - digital conver to r (ADC). Control is d o ne by 12 - bit digital - to - analog convertor s (DACs). Eight cha n n els of DACs are u se d in t he de sign. In a d dition to t hese fine analog cont rol signals, 8 - digital contr ol signals are p r ovide d. All t he se signals are s oftware d riven t h r o ug h LPT p o r t. To mi ni mi ze t he PC noise to t he STM electro nics, o p tical isolatio n h as bee n p rovide d between t he PC grou n d a n d t he syste m gro u n d. High s peed o p tical isolato rs (10Mbit / s) are u se d. 8 - Bit Digit al con t rol Regis t er WDIRWPULSELOCK ON/ OFFHOLDT c / ZPi MODEG2G1G0 Con t r ols t h e d irect ion of p iez ot u b e walker Con t r ols s in gle s t ep m ot ion of p iez ot u b e Byp as s t h e feed back loop
Gain s elect ion for p rogr am m ab le Con t r ols t h e d igit iz at ion of t u n n elin g cu r ren t or Zp i volt age Select s con s t an t cu rr en t (CC) or con s t an t h eigh t (CH) m od e of s can n in g
The ADC digitizes t he ZPi signal whe n t he loop is on an d digitizes t he t u n neling voltage VTC signal irres pective of t he loop on / off. This feat ure is im ple me nte d since while coar se a p p r oach we want to check t he t u n neling voltage with feedback loo p o n. It m akes t he coar se a p p r oach a uto m a tic as soo n as tip an d sa m ple are within t u n neling ra nge t he coar se a p p r oach m ec ha nis m s to p s an d feedback loop takes t he con t rol of tip m ove me nt. The p r ogra m m a ble gain a m plifier (PGA) p r ovides t he gain, 1 to 1 28 (2 0 – 2 7), selection before t he signal fe d to t he ADC. ADC ha s inp u t ra nge ± 1 0V with 16 - bit accuracy an d 1MHz conver sion clock. As soo n as ADC convert s t he d ata, it is rea d by t he PC via p a rallel p or t. Piezot u be walker contr ol signals WDIR, walker direction ( forwar d or backwar d) an d WPULSE, (interr u p t signal to t he micro - controller in walker circuit.) are software d riven. These two signals contr ol t he walker m o tion a n d set t he direction as far war d d u ring coarse a p p r oach. If we want to extract t he tip we set t he directio n b ackwar d a n d p r ovide walker p ulses, it will m ove t he walker in backwar d direction a n d tip co mes ou t of t u n neling.
Power Su p ply a n d Pie z o t u b e Walker co n t r ol circuit : Po w er s u p pl y d e sign : Since t he n oise level of t he syste m nee ds to be ke p t < 1 mV. The p ower s u p ply d e sign is a very cr ucial. The p ower cons u m p tion of t he sys te m is abo ut 20W. Since o p tical isolation ha s been p r ovide d to kee p t he noise level u n der control at t he cost of a d ditio nal + 5V dc, 500 mA p ower s u p ply req uire me nt. Digital + 5V dc, 500 mA, p ower s u p ply will p ower t he digital circuit of t he syste m. Both of t hese + 5V dc s u p plies are linear regulate d designs. The a nalog p or tion of t he syste m is p owere d with ± 1 5V dc , 200 mA linear regulate d p ower s u p ply. For high voltage section of t he sys te m ± 1 1 0V dc s u p ply is req uire d. It is a linear regulated de sign with 40 mA curren t o u t p u t. All t he p ower s u p ply grou n d s are isolate d a n d joine d at t he a p p r o p riate p oin ts o n t he electronics boar d s, e.g. analog grou n d an d digital grou n d s are co m bine d at ADC to avoid t he grou n d loop p r oble m s in t he design. Pie z otub e w alk er : c o m pact c oars e approach m e c hanis m The coar se a p p r oach m echa nis m of tip, called a pie zot ube walker, contr ols t he Z directio n m ove me nt of t he pie zot u be walker. This m echa nis m is nee de d to bring t he tip a n d t he sa m ple s u rface within t he ra nge of t he sca n ner piez o ( < 1 u m), s tar ting fro m a se para tion of abou t a few millimeter s. The walker cont rol circuit is im ple me n te d u sing a microcontr oller a n d six t riacs synchr o ni ze d with m ain contr ol b oar d. The direction of m o tion i.e. forwar d or backwar d is cont rolled fro m t he m ain b oar d. Basically microcon troller fires t he six triacs one by o ne as soo n as it gets a walker p ulse signal fro m t he m ain contr ol boar d. This seq ue nce generates six sy n chro ni ze d voltage ou t p u t s one each for six sections of t he walker t ube. This s te p voltage ( ± 150V AC), as s how n in Figure .5, is a p plied to each section one by o ne, m oving t he m along t he s a m e direction. Then t he voltage o n each section is slowly b ro ug h t d own to z ero at t he sa me ti me. This cons titu te o ne s te p of t he pie zo t u be walker.
If t he walker as se m bly takes p ositive s te p voltages to m a ke forwar d m o tion t h en t he n egative s te p voltages will give backwar d m o tion to t he walker. These s te p volt ages are extracte d fro m 50 Hz ± 1 5 0V peak - to - peak AC signal.
Software: The acq uisition an d t he a nalysis s oftware for t he STM is written with Python scrip ts a n d Tkinter for gra p hical u ser interface (GUI). A wra p per d river in C is written for t he LPT oor t a n d inser te d as a ker nel m o d ule.
Overall de sign vi e w of m echanical as s e mbl y of s can head pie zo, sa mple holder , graphical u s er interface (GUI) and the control elec tronics :
Res ult s: To p og ra p hic im age of Highly Orie n te d Pyrolytic Gra p hite (HOPG)
Angs) = 2.4 Angs
Functional De s cription of STM Electronic Cards: 1. POWER SUPPLY AND WALKER CONTROL PCB as s e m bl y:
2. FEEDBACK CONTROL PCB as s e m bl y:
3. DATA ACQUISITION and COMPUTER INTERFACE b oard as s e m bl y:
4. TUNNELING CURRENT AMPLIFIER PCB as s e m bl y:
