Transcript
PD - 97230A
IRF6665PbF IRF6665TRPbF
DIGITAL AUDIO MOSFET
Features • Latest MOSFET Silicon technology • Key parameters optimized for Class-D audio amplifier applications • Low RDS(on) for improved efficiency • Low Qg for better THD and improved efficiency • Low Qrr for better THD and lower EMI • Low package stray inductance for reduced ringing and lower EMI • Can deliver up to 100W per channel into 8Ω with no heatsink • Dual sided cooling compatible · Compatible with existing surface mount technologies · RoHS compliant containing no lead or bromide ·Lead-Free (Qualified up to 260°C Reflow)
Key Parameters 100
VDS
RDS(on) typ. @ VGS = 10V Qg typ. RG(int) typ.
SH
53 8.7
V m: nC
1.9
DirectFET ISOMETRIC
Applicable DirectFET Outline and Substrate Outline (see p. 6, 7 for details)
SQ
SX
ST
SH
MQ
MX
MT
MN
Description This Digital Audio MOSFET is specifically designed for Class-D audio amplifier applications. This MOSFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, gate charge, body-diode reverse recovery and internal gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD, and EMI. The IRF6665PbF device utilizes DirectFETTM packaging technology. DirectFETTM packaging technology offers lower parasitic inductance and resistance when compared to conventional wirebonded SOIC packaging. Lower inductance improves EMI performance by reducing the voltage ringing that accompanies fast current transients. The DirectFETTM package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing method and processes. The DirectFETTM package also allows dual sided cooling to maximize thermal transfer in power systems, improving thermal resistance and power dissipation. These features combine to make this MOSFET a highly efficient, robust and reliable device for Class-D audio amplifier applications.
Absolute Maximum Ratings Max.
Units
VDS
Drain-to-Source Voltage
Parameter
100
V
VGS
Gate-to-Source Voltage
± 20
ID @ TC = 25°C ID @ TA = 25°C
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V
19 4.2
ID @ TA = 70°C
Continuous Drain Current, VGS @ 10V
3.4
IDM
Pulsed Drain Current
34
PD @TC = 25°C
c
Maximum Power Dissipation
42
Power Dissipation
2.2
PD @TA = 70°C
e Power Dissipation e
TJ
Linear Derating Factor Operating Junction and
TSTG
Storage Temperature Range
PD @TA = 25°C
A
W
1.4 0.017 -40 to + 150
W/°C °C
Thermal Resistance Parameter
RθJA RθJA RθJA RθJC RθJ-PCB
ek Junction-to-Ambient hk Junction-to-Ambient ik Junction-to-Case jk Junction-to-Ambient
Junction-to-PCB Mounted
Notes through are on page 2
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Typ.
Max.
Units °C/W
–––
58
12.5
–––
20
–––
–––
3.0
1.4
–––
1 08/25/06
IRF6665PbF Static @ TJ = 25°C (unless otherwise specified) Parameter
Conditions
Min.
Typ.
Max.
Units
V(BR)DSS
Drain-to-Source Breakdown Voltage
100
–––
–––
V
∆V(BR)DSS/∆TJ RDS(on)
Breakdown Voltage Temp. Coefficient
–––
0.12
–––
V/°C
Reference to 25°C, ID = 1mA
Static Drain-to-Source On-Resistance
–––
53
62
VGS = 10V, ID = 5.0A
VGS(th)
Gate Threshold Voltage
3.0
–––
5.0
mΩ V
IDSS
Drain-to-Source Leakage Current
–––
–––
20
µA
VDS = 100V, VGS = 0V
–––
–––
250
Gate-to-Source Forward Leakage
–––
–––
100
nA
VGS = 20V
Gate-to-Source Reverse Leakage
–––
–––
-100
Internal Gate Resistance
–––
1.9
2.9
Ω
IGSS RG(int)
VGS = 0V, ID = 250µA
f
VDS = VGS, ID = 250µA
VDS = 80V, VGS = 0V, TJ = 125°C VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified) Parameter gfs Qg
Min.
Typ.
Max.
Units
Forward Transconductance
6.6
–––
–––
S
Conditions VDS = 10V, ID = 5.0A
Total Gate Charge
–––
8.4
13
VDS = 50V
Qgs1
Pre-Vth Gate-to-Source Charge
–––
2.2
–––
VGS = 10V
Qgs2
Post-Vth Gate-to-Source Charge
–––
0.64
–––
Qgd
Gate-to-Drain Charge
–––
2.8
–––
Qgodr
Gate Charge Overdrive Switch Charge (Qgs2 + Qgd)
–––
2.8
–––
Qsw
–––
3.4
–––
td(on)
Turn-On Delay Time
–––
7.4
–––
VDD = 50V ID = 5.0A
tr
Rise Time
–––
2.8
–––
td(off) tf
Turn-Off Delay Time Fall Time
––– –––
14 4.3
––– –––
ID = 5.0A nC
ns
See Fig. 6 and 17
RG = 6.0Ω VGS = 10V
f
Ciss
Input Capacitance
–––
530
–––
VGS = 0V
Coss
Output Capacitance
–––
110
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
–––
29
–––
Coss
Output Capacitance
–––
510
–––
ƒ = 1.0MHz VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss
Output Capacitance
–––
67
–––
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff.
Effective Output Capacitance
–––
130
–––
VGS = 0V, VDS = 0V to 80V
pF
g
Avalanche Characteristics Parameter EAS
Single Pulse Avalanche Energy
IAR
Avalanche Current
c
d
Typ.
Max.
Units
–––
11
mJ
–––
5.0
A
Diode Characteristics Parameter Continuous Source Current
IS
Min.
Typ.
Max.
–––
–––
38
–––
–––
34
(Body Diode) ISM
Pulsed Source Current
c
Units
Conditions MOSFET symbol
A
D
showing the integral reverse
G
p-n junction diode.
(Body Diode)
S
VSD
Diode Forward Voltage
–––
–––
1.3
V
TJ = 25°C, IS = 5.0A, VGS = 0V
trr
Reverse Recovery Time
–––
31
–––
ns
Qrr
Reverse Recovery Charge
–––
37
–––
nC
TJ = 25°C, IF = 5.0A, VDD = 25V di/dt = 100A/µs
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 0.89mH, RG = 25Ω, IAS = 5.0A. Surface mounted on 1 in. square Cu board. Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
2
f
f
Used double sided cooling , mounting pad. Mounted on minimum footprint full size board with metalized back and with small clip heatsink.
TC measured with thermal couple mounted to top (Drain) of part.
Rθ is measured at TJ of approximately 90°C. Based on testing done using a typical device & evaluation board at Vbus=±45V, fSW=400KHz, and TA=25°C. The delta case temperature ∆TC is 55°C.
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IRF6665PbF 100
100
BOTTOM
10
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS 15V 10V 9.0V 8.0V 7.0V 6.0V
6.0V 1
BOTTOM
10 6.0V
1
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 150°C
Tj = 25°C 0.1
0.1 0.1
1
10
100
1000
0.1
V DS, Drain-to-Source Voltage (V)
10
100
1000
Fig 2. Typical Output Characteristics
100
2.0 RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (Α)
1
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
T J = -40°C T J = 25°C
T J = 150°C
1
VDS = 25V ≤60µs PULSE WIDTH 0.1
ID = 5.0A VGS = 10V
1.5
1.0
0.5 2
4
6
8
10
12
20 40 60 80 100 120 140 160
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics 10000
-60 -40 -20 0
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
12.0
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED
ID= 5.0A VGS, Gate-to-Source Voltage (V)
C rss = C gd C oss = C ds + C gd
C, Capacitance(pF)
VGS 15V 10V 9.0V 8.0V 7.0V 6.0V
1000 Ciss Coss 100 Crss
10.0
VDS= 80V VDS= 50V VDS= 20V
8.0 6.0 4.0 2.0 0.0
10 1
10 VDS, Drain-to-Source Voltage (V)
100
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
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0
2
4
6
8
10
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
3
IRF6665PbF 1000
ID, Drain-to-Source Current (A)
100
Tc = 25°C Tj = 150°C Single Pulse
ISD, Reverse Drain Current (A)
100
10 T J = -40°C T J = 25°C
T J = 150°C
OPERATION IN THIS AREA LIMITED BY R DS(on)
100µsec
10
1msec
1 DC
10msec 0.1
VGS = 0V
0.01
1 0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
VSD, Source-to-Drain Voltage (V)
10
100
1000
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage 5 VGS(th) Gate threshold Voltage (V)
5.5
4 ID, Drain Current (A)
1
VDS, Drain-to-Source Voltage (V)
3
2
1
5.0
4.5
4.0
3.5
ID = 250µA
ID = 1.0mA
3.0
ID = 1.0A
2.5
0 25
50
75
100
125
-75
150
-50
-25
0
25
50
75
100
125
150
T J , Temperature ( °C )
T A , Ambient Temperature (°C)
Fig 10. Threshold Voltage vs. Temperature
Fig 9. Maximum Drain Current vs. Ambient Temperature 100
Thermal Response ( Z thJA )
D = 0.50 0.20
10
0.10 0.05 0.02
1
τJ
0.01
0.1
R1 R1 τJ τ1
SINGLE PULSE ( THERMAL RESPONSE )
R2 R2
R3 R3
R4 R4
Ri (°C/W)
R5 R5
1.6195 τA
τ1
τ2
τ2
τ3
τ3
τ4
τ4
τ5
τ5
Ci= τi/Ri Ci= τi/Ri
τA
τi (sec) 0.000126
2.1406
0.001354
22.2887
0.375850
20.0457
7.410000
11.9144
99
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthja + Tc
0.01 1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
4
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RDS(on), Drain-to -Source On Resistance ( mΩ)
RDS(on) , Drain-to -Source On Resistance ( mΩ)
IRF6665PbF 200 ID = 5.0A
180 160 140 120
T J = 125°C
100 80 60 40
T J = 25°C
20 0 4
6
8
10
12
14
16
120
80
Vgs = 10V 40 0
+ V - DD
VGS 20V
A
0.01Ω
tp
Fig 15a. Unclamped Inductive Test Circuit V(BR)DSS tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
6
8
10
50
DRIVER
IAS
4
Fig 13. On-Resistance vs. Drain Current
15V
RG
2
ID, Drain Current (A)
Fig 12. On-Resistance vs. Gate Voltage
L
T J = 25°C
60
18
VGS, Gate -to -Source Voltage (V)
VDS
T J = 125°C
100
ID TOP 0.86A 1.3A BOTTOM 5.0A
40
30
20
10
0 25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
I AS
Fig 15b. Unclamped Inductive Waveforms VDS VGS
RD
VDS
90%
D.U.T.
RG
+
- VDD
10% 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 16a. Switching Time Test Circuit
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VGS td(on)
tr
td(off)
tf
Fig 16b. Switching Time Waveforms
5
IRF6665PbF Current Regulator Same Type as D.U.T.
Id Vds Vgs
50KΩ 12V
.2µF .3µF
+ V - DS
D.U.T. VGS
Vgs(th) 3mA
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Fig 17a. Gate Charge Test Circuit
Qgd
Qgodr
Fig 17b. Gate Charge Waveform D.U.T
+
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
+
-
-
+
RG
• • • •
Driver Gate Drive Period
P.W.
VDD
di/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
D=
+ -
P.W. Period VGS=10V*
D.U.T. ISD Waveform Reverse Recovery Current
Re-Applied Voltage
Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
Body Diode
VDD
Forward Drop
Inductor Current Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices Fig 18. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs
6
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IRF6665PbF DirectFET™ Substrate and PCB Layout, SH Outline (Small Size Can, H-Designation). Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This includes all recommendations for stencil and substrate designs.
G = GATE D = DRAIN S = SOURCE
D
D G
D
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S D
7
IRF6665PbF DirectFET Outline Dimension, SH Outline (Small Size Can, H-Designation).
Please see DirectFET application note AN-1035 for all details regarding PCB assembly using DirectFET. This includes all recommendations for stencil and substrate designs.
DIMENSIONS IMPERIAL METRIC MAX MIN CODE MIN MAX 4.85 0.187 A 4.75 0.191 3.95 0.146 B 3.70 0.156 2.85 0.108 C 2.75 0.112 0.45 0.014 D 0.35 0.018 0.62 0.023 E 0.58 0.024 0.62 0.023 F 0.58 0.024 0.67 0.025 G 0.63 0.026 0.87 0.033 H 0.83 0.034 K 0.99 1.03 0.039 0.041 2.33 0.090 L 2.29 0.092 M 0.616 0.676 0.0235 0.0274 R 0.020 0.080 0.0008 0.0031 0.17 0.003 P 0.08 0.007
DirectFET Part Marking
8
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IRF6665PbF DirectFET Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel quantity is 4800 parts. (ordered as IRF6665TRPBF). For 1000 parts on 7" reel, order IRF6665TR1PBF REEL DIMENSIONS STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 1000) IMPERIAL METRIC IMPERIAL METRIC MIN MIN MAX CODE MAX MIN MAX MAX MIN 12.992 6.9 N.C A N.C 177.77 N.C 330.0 N.C 0.795 0.75 N.C B N.C 19.06 20.2 N.C N.C 0.504 0.53 C 0.50 13.5 12.8 0.520 12.8 13.2 0.059 0.059 D N.C 1.5 1.5 N.C N.C N.C 3.937 2.31 E 58.72 N.C 100.0 N.C N.C N.C F N.C N.C N.C 0.53 N.C 0.724 13.50 18.4 G 0.488 0.47 N.C 11.9 12.4 0.567 12.01 14.4 H 0.469 0.47 11.9 11.9 0.606 N.C 12.01 15.4
Loaded Tape Feed Direction
CODE A B C D E F G H
DIMENSIONS METRIC IMPERIAL MIN MIN MAX MAX 0.311 7.90 0.319 8.10 0.154 0.161 4.10 3.90 0.469 0.484 11.90 12.30 0.215 0.219 5.45 5.55 0.158 4.00 0.165 4.20 0.197 5.00 0.205 5.20 0.059 1.50 N.C N.C 0.059 1.50 0.063 1.60
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.08/06
9
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
