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October 2018
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PD - 97278C IRFB4410ZPbF IRFS4410ZPbF IRFSL4410ZPbF HEXFET® Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits D G S Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free VDSS RDS(on) typ. max. ID (Silicon Limited) D D D G D S G D S G D2Pak IRFS4410ZPbF TO-220AB IRFB4410ZPbF 100V 7.2m: 9.0m: 97A D S TO-262 IRFSL4410ZPbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Max. Continuous Drain Current, VGS @ 10V (Silicon Limited) Units 97 69 390 230 1.5 ± 20 16 -55 to + 175 Continuous Drain Current, VGS @ 10V (Silicon Limited) Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw A W W/°C V V/ns °C 300 10lbxin (1.1Nxm) Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current Repetitive Avalanche Energy f 242 See Fig. 14, 15, 22a, 22b, mJ A mJ Thermal Resistance Symbol RθJC RθCS RθJA RθJA www.irf.com Parameter Junction-to-Case j Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 j 2 Junction-to-Ambient (PCB Mount) , D Pak ij Typ. Max. ––– 0.50 ––– ––– 0.65 ––– 62 40 Units °C/W 1 02/14/08 IRF/B/S/SL4410ZPbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance RG Min. Typ. Max. Units 100 ––– ––– 2.0 ––– ––– ––– ––– ––– ––– 0.12 7.2 ––– ––– ––– ––– ––– 0.70 ––– ––– 9.0 4.0 20 250 100 -100 ––– Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAc mΩ VGS = 10V, ID = 58A f V VDS = VGS, ID = 150µA µA VDS = 100V, VGS = 0V VDS = 80V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 140 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related) h––– ––– Effective Output Capacitance (Time Related)g ––– 83 19 27 56 16 52 43 57 4820 340 170 420 690 ––– 120 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– S nC ns pF Conditions VDS = 10V, ID = 58A ID = 58A VDS =50V VGS = 10V f ID = 58A, VDS =0V, VGS = 10V f VDD = 65V ID = 58A RG =2.7Ω VGS = 10V f VGS = 0V VDS = 50V ƒ = 1.0MHz, See Fig.5 VGS = 0V, VDS = 0V to 80V h, See Fig.11 VGS = 0V, VDS = 0V to 80V g Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode)c Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.143mH RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use above this value. ISD ≤ 58A, di/dt ≤ 610A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 Min. Typ. Max. Units ––– ––– ––– ––– Conditions 97 A MOSFET symbol 390 A showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 58A, VGS = 0V f TJ = 25°C VR = 85V, TJ = 125°C IF = 58A di/dt = 100A/µs f TJ = 25°C S ––– ––– 1.3 V ––– 38 57 ns ––– 46 69 ––– 53 80 nC TJ = 125°C ––– 82 120 ––– 2.5 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C. www.irf.com IRF/B/S/SL4410ZPbF 1000 1000 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 4.5V 10 BOTTOM 10 ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 175°C Tj = 25°C 1 1 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 1000 2.5 VDS = 50V ≤60µs PULSE WIDTH RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) 100 T J = 25°C 10 T J = 175°C 1 0.1 ID = 58A VGS = 10V 2.0 1.5 1.0 0.5 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (°C) VGS, Gate-to-Source Voltage (V) Fig 4. Normalized On-Resistance vs. Temperature Fig 3. Typical Transfer Characteristics 100000 12.0 VGS = 0V, f = 1 MHZ Ciss = C gs + Cgd, C ds SHORTED Crss = C gd VGS, Gate-to-Source Voltage (V) ID= 58A Coss = Cds + Cgd C, Capacitance (pF) 4.5V 10000 Ciss Coss 1000 Crss VDS= 80V VDS= 40V 10.0 VDS= 20V 8.0 6.0 4.0 2.0 0.0 100 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 20 40 60 80 100 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRF/B/S/SL4410ZPbF 1000 100 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 175°C OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec 1msec 100 10 T J = 25°C 1 10msec DC 10 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.1 1 0.0 0.5 1.0 1.5 2.0 2.5 0 VSD, Source-to-Drain Voltage (V) ID, Drain Current (A) 80 60 40 20 0 75 100 125 150 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 100 50 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( °C ) Fig 9. Maximum Drain Current vs. Case Temperature 2.0 Fig 10. Drain-to-Source Breakdown Voltage EAS , Single Pulse Avalanche Energy (mJ) 1000 1.8 1.6 1.4 1.2 Energy (µJ) 100 125 T C , Case Temperature (°C) 1.0 0.8 0.6 0.4 0.2 0.0 ID TOP 6.4A 9.4A BOTTOM 58A 900 800 700 600 500 400 300 200 100 0 -10 0 10 20 30 40 50 60 70 80 90 100 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 10 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 1 VDS, Drain-to-Source Voltage (V) 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRF/B/S/SL4410ZPbF Thermal Response ( Z thJC ) °C/W 1 D = 0.50 0.20 0.1 0.10 0.05 τJ 0.02 0.01 0.01 R1 R1 τJ τ1 R2 R2 τ2 τ1 τC τ Ri (°C/W) τi (sec) 0.237 0.000178 0.413 τ2 0.003772 Ci= τi/Ri Ci i/Ri Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆ Tj = 150°C and Tstart =25°C (Single Pulse) Duty Cycle = Single Pulse Avalanche Current (A) 0.01 0.05 10 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 150 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 58A 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRF/B/S/SL4410ZPbF 20 IF = 39A VR = 85V 4.0 TJ = 25°C _____ 15 3.5 IRRM (A) VGS(th) , Gate threshold Voltage (V) 4.5 3.0 2.5 2.0 ID = 150µA 1.5 ID = 1.0mA ID = 1.0A TJ = 125°C ---------- 10 5 ID = 250µA 0 1.0 -75 -50 -25 0 100 25 50 75 100 125 150 175 200 200 300 500 600 700 dif/dt (A/µs) T J , Temperature ( °C ) Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 400 20 15 400 I = 58A F V = 85V R T = 25°C _____ J T = 125°C ---------J 350 IF = 39A VR = 85V TJ = 25°C _____ 300 TJ = 125°C ---------- Qrr (nC) IRRM (A) 250 10 200 150 100 5 50 0 0 100 200 300 400 500 600 100 700 200 300 400 500 600 700 dif/dt (A/µs) dif/dt (A/µs) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt 450 400 350 Qrr (nC) 300 I = 58A F V = 85V R T = 25°C _____ J T = 125°C J ---------- 250 200 150 100 50 0 100 200 300 400 500 600 700 dif/dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRF/B/S/SL4410ZPbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS tp 15V DRIVER L VDS D.U.T RG + V - DD IAS 20V tp A 0.01Ω I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms LD VDS VGS 90% + VDD D.U.T 10% VGS VDS Second Pulse Width < 1µs Duty Factor < 0.1% td(off) Fig 23a. Switching Time Test Circuit tf td(on) tr Fig 23b. Switching Time Waveforms Id Vds Vgs L VCC DUT 0 20K 1K Vgs(th) S Qgodr Fig 24a. Gate Charge Test Circuit www.irf.com Qgd Qgs2 Qgs1 Fig 24b. Gate Charge Waveform 7 IRF/B/S/SL4410ZPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/

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