Transcript
PD - 93986A
REPETITIVE AVALANCHE AND dv/dt RATED ®
HEXFET TRANSISTORS SURFACE MOUNT (LCC-18)
IRFE420 JANTX2N6794U JANTXV2N6794U REF:MIL-PRF-19500/555 500V, N-CHANNEL
Product Summary Part Number
BVDSS
RDS(on)
IRFE420
500V
3.0Ω
ID 1.4A
LCC-18 The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference.
Features: n n n n n n n n
Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight
Absolute Maximum Ratings Parameter ID @ VGS = 10V, TC = 25°C ID @ VGS = 10V, TC = 100°C IDM PD @ TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG
Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight
Units 1.4 0.88 5.6 14 0.11 ±20 0.242 2.2 1.4 3.5 -55 to 150 300 (for 5 S) 0.42 (typical)
A W W/°C V mJ A mJ V/ns °C g
For footnotes refer to the last page
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08/03/07
IRFE420, JANTX2N6794U, JANTXV2N6794U
Electrical Characteristics @ Tj = 25°C (Unless Otherwise Specified) BVDSS
Parameter
Min
Drain-to-Source Breakdown Voltage
500
—
—
V
VGS = 0V, ID = 1.0mA
—
0.43
—
V/°C
Reference to 25°C, ID = 1.0mA
— — 2.0 1.0 — —
— — — — — —
3.0 3.1 4.0 — 25 250
∆BV DSS /∆T J Temperature Coefficient of Breakdown Voltage RDS(on) Static Drain-to-Source On-State Resistance VGS(th) Gate Threshold Voltage g fs Forward Transconductance IDSS Zero Gate Voltage Drain Current
Typ Max Units
IGSS IGSS Qg Q gs Q gd td(on) tr td(off) tf LS + LD
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (‘Miller’) Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance
— — — — — — — — — —
— — — — — — — — — 6.1
100 -100 25 6.0 18 40 30 60 35 —
C iss C oss C rss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
— — —
350 80 35
— —
Ω V S µA nA nC
Test Conditions
VGS = 10V, ID = 0.88A VGS = 10V, ID = 1.4A VDS = VGS, ID = 250µA VDS > 15V, IDS = 0.88A V DS = 400V, VGS = 0V VDS = 400V VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VGS = 10V, ID = 1.4A VDS = 250V VDD = 225V, ID = 1.4A VGS = 10V, RG = 7.5Ω,
ns nH
Measured from the center of drain pad to center of source pad
pF
VGS = 0V, VDS = 25V f = 1.0MHz
Source-Drain Diode Ratings and Characteristics Parameter
Min Typ Max Units
IS ISM VSD t rr Q RR
Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
ton
Forward Turn-On Time
— — — — —
— — — — —
1.4 5.6 1.2 900 5.9
Test Conditions
A V ns µC
Tj = 25°C, IS =1.4A, VGS = 0V Tj = 25°C, IF = 1.4A, di/dt ≤ 100A/µs VDD ≤ 50V
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance Parameter R thJC RthJ-PCB
Junction to Case Junction to PC Board
Min Typ Max Units — —
— —
8.93 26
°C/W
Test Conditions Soldered to a copper clad PC board
Note: Corresponding Spice and Saber models are available on International Rectifier Website. For footnotes refer to the last page
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IRFE420, JANTX2N6794U, JANTXV2N6794U
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFE420, JANTX2N6794U, JANTXV2N6794U
13 a & b
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode Forward Voltage
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Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
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IRFE420, JANTX2N6794U, JANTXV2N6794U
V DS VGS RG
RD
D.U.T. +
-V DD
VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit VDS 90%
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFE420, JANTX2N6794U, JANTXV2N6794U
15V
L
VDS
D.U.T
RG 20V VGS
IAS
DRIVER
+ V - DD
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS Current Regulator Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
QG
10 V
QGS
.2µF .3µF
D.U.T.
QGD
+ V - DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
12V
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFE420, JANTX2N6794U, JANTXV2N6794U Foot Notes: Repetitive Rating; Pulse width limited by maximum junction temperature. VDD = 50V, starting TJ = 25°C, Peak IL = 2.2A, L = 100µH
ISD ≤ 1.4A, di/dt ≤ 50A/µs,
VDD≤ 500V, TJ ≤ 150°C Suggested RG =7.5 Ω Pulse width ≤ 300 µs; Duty Cycle ≤ 2%
Case Outline and Dimensions — LCC-18
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 08/2007
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