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Irfs3806pbf

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November 2018
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Industrial & lab equipment Electrical equipment & supplies Circuit protection Voltage regulators

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PD - 97310 IRFB3806PbF IRFS3806PbF IRFSL3806PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET® Power MOSFET D G Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability S VDSS RDS(on) typ. max. ID D 60V 12.6mΩ 15.8mΩ 43A D D S G S S D G G D2Pak IRFS3806PbF TO-220AB IRFB3806PbF D TO-262 IRFSL3806PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 43 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 31 IDM Pulsed Drain Current c 170 PD @TC = 25°C Maximum Power Dissipation 71 W W/°C V Linear Derating Factor 0.47 VGS Gate-to-Source Voltage ± 20 dv/dt TJ Peak Diode Recovery e 24 Operating Junction and -55 to + 175 TSTG Storage Temperature Range A V/ns °C 300 Soldering Temperature, for 10 seconds (1.6mm from case) 10lbxin (1.1Nxm) Mounting torque, 6-32 or M3 screw Avalanche Characteristics EAS (Thermally limited) Single Pulse Avalanche Energy d IAR Avalanche Current c 25 A EAR Repetitive Avalanche Energy f 7.1 mJ mJ 73 Thermal Resistance Symbol Parameter Typ. Max. RθJC Junction-to-Case j ––– 2.12 RθCS Case-to-Sink, Flat Greased Surface, TO-220 0.50 ––– RθJA RθJA Junction-to-Ambient, TO-220 ij ––– ––– 62 40 www.irf.com 2 Junction-to-Ambient (PCB Mount) , D Pak ij Units °C/W 1 02/29/08 IRFB/S/SL3806PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units 60 ––– ––– ––– 0.075 ––– ––– 12.6 15.8 2.0 ––– 4.0 ––– ––– 20 ––– ––– 250 ––– ––– 100 ––– ––– -100 Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAc mΩ VGS = 10V, ID = 25A f V VDS = VGS, ID = 50µA µA VDS = 60V, VGS = 0V VDS = 48V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Dynamic @ TJ = 25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units gfs Qg Qgs Qgd Qsync Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) 41 ––– ––– ––– ––– ––– 22 5.0 6.3 28.3 ––– 30 ––– ––– ––– S nC RG(int) td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Internal Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance ––– 0.79 6.3 40 49 47 1150 130 67 190 230 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Ω ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related)h ––– ––– Effective Output Capacitance (Time Related)g Conditions VDS = 10V, ID = 25A ID = 25A VDS = 30V VGS = 10V f ID = 25A, VDS =0V, VGS = 10V ns pF VDD = 39V ID = 25A RG = 20Ω VGS = 10V f VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 60V h VGS = 0V, VDS = 0V to 60V g Diode Characteristics Symbol Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– 43 ISM (Body Diode) Pulsed Source Current ––– ––– 170 VSD trr (Body Diode)c Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.23mH RG = 25Ω, IAS = 25A, VGS =10V. Part not recommended for use above this value. ISD ≤ 25A, di/dt ≤ 1580A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 A Conditions MOSFET symbol showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 25A, VGS = 0V f VR = 51V, TJ = 25°C IF = 25A TJ = 125°C di/dt = 100A/µs f TJ = 25°C S ––– ––– 1.3 V ––– 22 33 ns ––– 26 39 ––– 17 26 nC TJ = 125°C ––– 24 36 ––– 1.4 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C. www.irf.com IRFB/S/SL3806PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 100 10 4.5V BOTTOM VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V 4.5V 10 ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 175°C Tj = 25°C 1 1 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 100 2.5 100 T J = 175°C 10 T J = 25°C 1 VDS = 25V ≤60µs PULSE WIDTH 0.1 ID = 25A VGS = 10V 2.0 (Normalized) RDS(on) , Drain-to-Source On Resistance ID, Drain-to-Source Current (A) 10 Fig 2. Typical Output Characteristics 1000 1.5 1.0 0.5 2 3 4 5 6 7 8 9 -60 -40 -20 0 20 40 60 80 100120140160180 VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 10000 12.0 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd VGS , Gate-to-Source Voltage (V) ID= 25A Coss = Cds + Cgd C, Capacitance (pF) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) Ciss 1000 Coss Crss 100 VDS= 48V VDS= 30V 10.0 VDS= 12V 8.0 6.0 4.0 2.0 0.0 10 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 5 10 15 20 25 Q G , Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFB/S/SL3806PbF 1000 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) 100 T J = 175°C 10 T J = 25°C 1 100 100µsec 1msec 10 10msec 1 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.1 0.1 0.0 0.5 1.0 1.5 1 2.0 40 ID, Drain Current (A) 35 30 25 20 15 10 5 0 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) 45 50 80 Id = 5mA 75 70 65 60 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( °C ) T C , Case Temperature (°C) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 0.4 EAS , Single Pulse Avalanche Energy (mJ) 300 0.3 0.3 Energy (µJ) 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 10 VDS, Drain-to-Source Voltage (V) VSD, Source-to-Drain Voltage (V) 0.2 0.2 0.1 0.1 0.0 ID 2.8A 5.1A BOTTOM 25A TOP 250 200 150 100 50 0 -10 0 10 20 30 40 50 60 70 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 DC 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRFB/S/SL3806PbF Thermal Response ( Z thJC ) °C/W 10 1 D = 0.50 0.1 0.20 0.10 0.05 τJ 0.02 0.01 R1 R1 τJ τ1 R2 R2 τ2 τ1 τ2 R3 R3 τ3 τC τ τ3 Ci= τi/Ri Ci τi/Ri 0.01 1E-005 0.9926 0.001228 0.5203 0.00812 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 Ri (°C/W) τi (sec) 0.6086 0.00026 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τj = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 80 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 25A 60 40 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 4.0 14 3.5 12 IF = 17A V R = 51V TJ = 25°C TJ = 125°C 10 3.0 2.5 8 IRR (A) VGS(th) , Gate threshold Voltage (V) IRFB/S/SL3806PbF ID = 50µA ID = 250µA 6 ID = 1.0mA 2.0 4 ID = 1.0A 1.5 2 1.0 0 -75 -50 -25 0 25 50 75 100 125 150 175 200 0 200 T J , Temperature ( °C ) 600 800 1000 Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 14 260 IF = 25A V R = 51V 12 IF = 17A V R = 51V 210 TJ = 25°C TJ = 125°C Q RR (A) 10 IRR (A) 400 diF /dt (A/µs) 8 6 TJ = 25°C TJ = 125°C 160 110 4 60 2 0 10 0 200 400 600 800 1000 0 200 diF /dt (A/µs) 400 600 800 1000 diF /dt (A/µs) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt 260 IF = 25A V R = 51V Q RR (A) 210 TJ = 25°C TJ = 125°C 160 110 60 10 0 200 400 600 800 1000 diF /dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFB/S/SL3806PbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG + V - DD IAS VGS 20V tp A 0.01Ω I AS Fig 21a. Unclamped Inductive Test Circuit LD Fig 21b. Unclamped Inductive Waveforms VDS VDS 90% + VDD - 10% D.U.T VGS VGS Pulse Width < 1µs Duty Factor < 0.1% td(on) Fig 22a. Switching Time Test Circuit tr td(off) tf Fig 22b. Switching Time Waveforms Id Vds Vgs L VCC DUT 0 Vgs(th) 1K Qgs1 Qgs2 Fig 23a. Gate Charge Test Circuit www.irf.com Qgd Qgodr Fig 23b. Gate Charge Waveform 7 IRFB/S/SL3806PbF TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB Part Marking Information (;$03/( 7+,6,6$1,5) /27&2'( $66(0%/('21:: ,17+($66(0%/

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