Transcript
PD - 97343
IRFS4010-7PPbF HEXFET® Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
D
G S
VDSS RDS(on) typ. max. ID
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
100V 3.3mΩ 4.0mΩ 190A
D
S G
S
S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG
Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range
Max.
Units
190 130 740
A W
380 2.5 ± 20
W/°C V
26 -55 to + 175
V/ns °C
300
Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
10lbxin (1.1Nxm)
Avalanche Characteristics EAS (Thermally limited) IAR EAR
Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f
330 See Fig. 14, 15, 22a, 22b,
mJ A mJ
Thermal Resistance Symbol RθJC RθJA
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Parameter
Typ.
Max.
Units
Junction-to-Case jk
–––
°C/W
Junction-to-Ambient (PCB Mount) ij
–––
0.40 40
1 10/07/08
IRFS4010-7PPbF Static @ TJ = 25°C (unless otherwise specified) Symbol
Parameter
V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current
IGSS RG(int)
Min. Typ. Max. Units
Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
100 ––– ––– 2.0 ––– ––– ––– –––
––– 0.11 3.3 ––– ––– ––– ––– –––
––– ––– 4.0 4.0 20 250 100 -100
Internal Gate Resistance
–––
2.1
–––
Conditions
V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAc mΩ VGS = 10V, ID = 110A f V VDS = VGS, ID = 250µA µA VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V Ω
Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
210 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Effective Output Capacitance (Energy Related)h ––– ––– Effective Output Capacitance (Time Related)g
––– 150 36 48 102 19 56 100 48 9830 650 260 730 740
––– 230 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– –––
S nC
ns
pF
Conditions VDS = 25V, ID = 110A ID = 110A VDS = 50V VGS = 10V f ID = 110A, VDS =0V, VGS = 10V VDD = 65V ID = 110A RG = 2.7Ω VGS = 10V f VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V h VGS = 0V, VDS = 0V to 80V g
Diode Characteristics Symbol IS
Parameter Continuous Source Current
VSD trr
(Body Diode) Pulsed Source Current (Body Diode)c Diode Forward Voltage Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM ton
Reverse Recovery Current Forward Turn-On Time
ISM
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.052mH RG = 25Ω, IAS = 110A, VGS =10V. Part not recommended for use above this value . ISD ≤ 110A, di/dt ≤ 1310A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units –––
–––
186
–––
–––
740
A
Conditions MOSFET symbol showing the integral reverse
D
G
p-n junction diode. TJ = 25°C, IS = 110A, VGS = 0V f TJ = 25°C VR = 85V, TJ = 125°C IF = 110A di/dt = 100A/µs f TJ = 25°C
S
––– ––– 1.3 V ––– 60 ––– ns ––– 67 ––– ––– 150 ––– nC TJ = 125°C ––– 180 ––– ––– 4.7 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C. RθJC value shown is at time zero.
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IRFS4010-7PPbF 1000
1000 VGS 15V 10V 8.0V 7.0V 5.0V 4.5V 4.3V 4.0V
100 BOTTOM
10
BOTTOM
100
1
≤60µs PULSE WIDTH Tj = 25°C
4.0V
4.0V 0.1
Tj = 175°C
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
1
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100 T J = 175°C T J = 25°C
10
1 VDS = 50V ≤60µs PULSE WIDTH
0.1
ID = 110A VGS = 10V 2.0 (Normalized)
RDS(on) , Drain-to-Source On Resistance
2.5
1.5
1.0
0.5
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
VGS , Gate-to-Source Voltage (V)
T J , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
100000
14.0
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd
ID= 110A VGS, Gate-to-Source Voltage (V)
ID, Drain-to-Source Current (A)
≤60µs PULSE WIDTH
10 0.1
Coss = Cds + Cgd
C, Capacitance (pF)
VGS 15V 10V 8.0V 7.0V 5.0V 4.5V 4.3V 4.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
Ciss
10000
Coss
1000
Crss
12.0
VDS= 80V VDS= 50V
10.0 8.0 6.0 4.0 2.0 0.0
100 1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
25
50
75 100 125 150 175 200 225
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFS4010-7PPbF 10000
100
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
T J = 175°C
10 T J = 25°C 1
OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100µsec
100 10msec 1msec
10 DC 1
Tc = 25°C Tj = 175°C Single Pulse
VGS = 0V 0.1
0.1 0.0
0.5
1.0
1.5
1
VSD, Source-to-Drain Voltage (V)
180
ID, Drain Current (A)
160 140 120 100 80 60 40 20 0 75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
200
50
6.0
Id = 5mA 120 115 110 105 100 95 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( °C )
Fig 10. Drain-to-Source Breakdown Voltage
EAS , Single Pulse Avalanche Energy (mJ)
1400 ID 21A 38A BOTTOM 110A TOP
1200
5.0
1000
4.0 Energy (µJ)
1000
125
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs. Case Temperature
3.0 2.0 1.0 0.0
800 600 400 200 0
0
10 20 30 40 50 60 70 80 90 100 110 VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
25
10
VDS, Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRFS4010-7PPbF Thermal Response ( Z thJC ) °C/W
1 D = 0.50 0.1
0.20 0.10 0.05 0.02 0.01
0.01
τJ
R1 R1 τJ τ1
τ1
R2 R2 τ2
R3 R3
τC τ τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri Ci i/Ri
0.001 SINGLE PULSE ( THERMAL RESPONSE )
0.0001 1E-006
1E-005
Ri (°C/W)
R4 R4
τi (sec)
0.02001
0.000025
0.05145
0.000094
0.19436
0.002047
0.13433
0.012818
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse)
0.01 0.05 0.10
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth 400 350 EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 110A
300 250 200 150 100 50 0 25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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IRFS4010-7PPbF 30
4.0 3.5 3.0
IRR (A)
VGS(th) , Gate threshold Voltage (V)
4.5
ID = 250µA
2.5
ID = 1.0mA ID = 1.0A
2.0
25
IF = 74A V R = 85V
20
TJ = 25°C TJ = 125°C
15 10 5
1.5 1.0
0 -75 -50 -25
0
25 50 75 100 125 150 175
0
200
T J , Temperature ( °C )
600
800
1000
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature 30
1000
25
IF = 110A V R = 85V
20
TJ = 25°C TJ = 125°C
IF = 74A V R = 85V
900 800
TJ = 25°C TJ = 125°C
700 Q RR (A)
IRR (A)
400
diF /dt (A/µs)
15 10
600 500 400 300
5
200
0
100 0
200
400
600
800
1000
0
200
diF /dt (A/µs)
400
600
800
1000
diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
1000 IF = 110A V R = 85V
900
TJ = 25°C TJ = 125°C
800
Q RR (A)
700 600 500 400 300 200 0
200
400
600
800
1000
diF /dt (A/µs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFS4010-7PPbF Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform Reverse Recovery Current
+
RG
• • • •
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
P.W. Period VGS=10V
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
+
D=
Period
P.W.
+
+ -
Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
Re-Applied Voltage
Body Diode
VDD
Forward Drop
Inductor Current Inductor Curent ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V
DRIVER
L
VDS
tp
D.U.T
RG
+ V - DD
IAS VGS 20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit RD
VDS
Fig 22b. Unclamped Inductive Waveforms VDS 90%
VGS
D.U.T.
RG
+
- VDD
V10V GS
10% VGS
Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms Id
Current Regulator Same Type as D.U.T.
Vds Vgs
50KΩ 12V
tf
.2µF .3µF
D.U.T.
+ V - DS
Vgs(th) VGS 3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
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IRFS4010-7PPbF D2Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFS4010-7PPbF D2Pak - 7 Pin Part Marking Information
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D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 10/08
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