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Irfs4127pbf

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November 2018
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Industrial & lab equipment Electrical equipment & supplies Circuit protection Voltage regulators

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PD - 96177 IRFS4127PbF IRFSL4127PbF Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits HEXFET® Power MOSFET D G S Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free VDSS RDS(on) typ. max. ID 200V 18.6m: 22m: 72A D D S G G D2Pak IRFS4127PbF D S TO-262 IRFSL4127PbF G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS Parameter Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V c Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw e dv/dt TJ TSTG Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy c f d Units 72 51 300 375 2.5 ± 20 57 -55 to + 175 A W W/°C V V/ns °C 300 x x 10lb in (1.1N m) 250 See Fig. 14, 15, 22a, 22b, mJ A mJ Thermal Resistance Symbol RθJC RθJA www.irf.com Parameter jk ij Junction-to-Case Junction-to-Ambient Typ. Max. Units ––– ––– 0.4 40 °C/W 1 09/16/08 IRFS/SL4127PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS ∆V(BR)DSS/∆TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS RG(int) Min. Typ. Max. Units Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage 200 ––– ––– 3.0 ––– ––– ––– ––– ––– 0.23 18.6 ––– ––– ––– ––– ––– Internal Gate Resistance ––– 3.0 Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 5mA 22 mΩ VGS = 10V, ID = 44A 5.0 V VDS = VGS, ID = 250µA VDS = 200V, VGS = 0V 20 µA 250 VDS = 200V, VGS = 0V, TJ = 125°C 100 VGS = 20V nA VGS = -20V -100 c f ––– Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance h Effective Output Capacitance (Energy Related) Effective Output Capacitance (Time Related) g 79 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 100 30 31 69 17 18 56 22 5380 410 86 360 590 ––– 150 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Conditions S VDS = 50V, ID = 44A ID = 44A VDS = 100V nC VGS = 10V ID = 44A, VDS =0V, VGS = 10V VDD = 130V ID = 44A ns RG = 2.7Ω VGS = 10V VGS = 0V VDS = 50V pF ƒ = 1.0MHz (See Fig.5) VGS = 0V, VDS = 0V to 160V (See Fig.11) VGS = 0V, VDS = 0V to 160V f f h g Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM c Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.26mH RG = 25Ω, IAS = 44A, VGS =10V. Part not recommended for use above this value . ISD ≤ 44A, di/dt ≤ 760A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%. 2 Min. Typ. Max. Units ––– ––– ––– ––– Conditions 76 MOSFET symbol 300 showing the integral reverse A D G p-n junction diode. S ––– ––– 1.3 V TJ = 25°C, IS = 44A, VGS = 0V TJ = 25°C VR = 100V, ––– 136 ––– ns T = 125°C I ––– 139 ––– J F = 44A di/dt = 100A/µs TJ = 25°C ––– 458 ––– nC TJ = 125°C ––– 688 ––– ––– 8.3 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) f f Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C RθJC value shown is at time zero www.irf.com IRFS/SL4127PbF 1000 1000 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V 100 10 BOTTOM 1 0.1 100 BOTTOM 10 4.5V 1 ≤ 60µs PULSE WIDTH Tj = 175°C ≤ 60µs PULSE WIDTH Tj = 25°C 4.5V 0.01 0.1 0.1 1 10 100 0.1 VDS , Drain-to-Source Voltage (V) 10 100 Fig 2. Typical Output Characteristics 3.5 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 VDS = 50V ID, Drain-to-Source Current(Α) 1 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics ≤ 60µs PULSE WIDTH 100 TJ = 175°C 10 TJ = 25°C 1 0.1 3.0 4.0 5.0 6.0 7.0 ID = 44A VGS = 10V 3.0 2.5 2.0 1.5 1.0 0.5 8.0 -60 -40 -20 0 VGS, Gate-to-Source Voltage (V) 8000 VGS, Gate-to-Source Voltage (V) Coss = Cds + Cgd Ciss 4000 2000 Coss Crss 0 1 ID= 44A 12 VDS = 160V VDS = 100V VDS = 40V 8 4 0 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com Fig 4. Normalized On-Resistance vs. Temperature 16 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd 6000 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 0 20 40 60 80 100 120 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRFS/SL4127PbF 1000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 TJ = 175°C 100 10 TJ = 25°C 1 OPERATION IN THIS AREA LIMITED BY R DS(on) 100µsec 100 1msec 10 10msec 1 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1 1.4 60 40 20 0 75 100 125 150 175 V(BR)DSS, Drain-to-Source Breakdown Voltage (V) ID, Drain Current (A) 80 50 1000 260 Id = 5mA 240 220 200 180 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( °C ) T C , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage EAS, Single Pulse Avalanche Energy (mJ) 8.0 6.0 Energy (µJ) 100 Fig 8. Maximum Safe Operating Area Fig 7. Typical Source-Drain Diode Forward Voltage 25 10 VDS , Drain-toSource Voltage (V) VSD , Source-to-Drain Voltage (V) 4.0 2.0 0.0 1000 I D 8.2A 13A BOTTOM 44A TOP 800 600 400 200 0 0 40 80 120 160 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 DC 0.1 0.1 200 25 50 75 100 125 150 175 Starting TJ, Junction Temperature (°C) Fig 12. Maximum Avalanche Energy Vs. DrainCurrent www.irf.com IRFS/SL4127PbF Thermal Response ( ZthJC ) 1 D = 0.50 0.1 0.20 0.10 τJ 0.05 0.02 0.01 0.01 R1 R1 τJ τ1 R2 R2 τ2 τ1 R3 R3 R4 R4 τC τ τ3 τ2 τ4 τ3 Ci= τi/Ri Ci i/Ri τ4 Ri (°C/W) 0.02 0.083333 0.181667 0.113333 τι (sec) 0.000019 0.000078 0.001716 0.008764 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 100 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) Avalanche Current (A) Duty Cycle = Single Pulse 0.01 10 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth EAR , Avalanche Energy (mJ) 250 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1% Duty Cycle ID = 44A 200 150 100 50 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRFS/SL4127PbF 50 ID = 1.0A ID = 1.0mA 5.0 40 ID = 250µA 4.0 IRRM - (A) VGS(th) Gate threshold Voltage (V) 6.0 3.0 2.0 30 20 IF = 29A VR = 100V 10 TJ = 125°C 1.0 TJ = 25°C 0 -75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000 TJ , Temperature ( °C ) dif / dt - (A / µs) Fig. 17 - Typical Recovery Current vs. dif/dt 60 3000 50 2500 40 2000 QRR - (nC) IRRM - (A) Fig 16. Threshold Voltage Vs. Temperature 30 20 10 0 1500 1000 IF = 44A VR = 100V IF = 29A VR = 100V 500 TJ = 125°C TJ = 125°C TJ = 25°C TJ = 25°C 0 100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / µs) dif / dt - (A / µs) Fig. 19 - Typical Stored Charge vs. dif/dt Fig. 18 - Typical Recovery Current vs. dif/dt 3000 2500 QRR - (nC) 2000 1500 1000 500 0 IF = 44A VR = 100V TJ = 125°C TJ = 25°C 100 200 300 400 500 600 700 800 900 1000 dif / dt - (A / µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRFS/SL4127PbF Driver Gate Drive D.U.T - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG VGS 20V + V - DD IAS A 0.01Ω tp I AS Fig 22a. Unclamped Inductive Test Circuit RD VDS Fig 22b. Unclamped Inductive Waveforms VDS 90% VGS D.U.T. RG + - VDD V10V GS 10% VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % td(on) Fig 23a. Switching Time Test Circuit tr t d(off) Fig 23b. Switching Time Waveforms Id Current Regulator Same Type as D.U.T. Vds Vgs 50KΩ 12V tf .2µF .3µF D.U.T. + V - DS Vgs(th) VGS 3mA IG ID Current Sampling Resistors Fig 24a. Gate Charge Test Circuit www.irf.com Qgs1 Qgs2 Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRFS/SL4127PbF D2Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D2Pak (TO-263AB) Part Marking Information 7+,6,6$1,5)6:,7+ /27&2'( $66(0%/('21:: ,17+($66(0%/

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