Transcript
PD - 91534
IRL520NS/L Logic-Level Gate Drive l Advanced Process Technology l Surface Mount (IRL520NS) l Low-profile through-hole (IRL520NL) l 175°C Operating Temperature l Fast Switching l Fully Avalanche Rated Description
HEXFET® Power MOSFET
l
D
VDSS = 100V RDS(on) = 0.18Ω
G
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRL520NL) is available for lowprofile applications.
ID = 10A S
D 2 P ak
T O -26 2
Absolute Maximum Ratings ID @ TC = 25°C ID @ TC = 100°C IDM PD @TA = 25°C PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy
Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt
Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
10 7.1 35 3.8 48 0.32 ±16 85 6.0 4.8 5.0 -55 to + 175
Units A W W W/°C V mJ A mJ V/ns °C
300 (1.6mm from case )
Thermal Resistance Parameter RθJC RθJA
Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
Max.
Units
––– –––
3.1 40
°C/W
5/13/98
IRL520NS/L Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
Qg Qgs Qgd td(on) tr td(off) tf
Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time
Min. 100 ––– ––– ––– ––– 1.0 3.1 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– –––
LS
Internal Source Inductance
–––
Ciss Coss Crss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
––– ––– –––
V(BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th) gfs
Gate Threshold Voltage Forward Transconductance
IDSS
Drain-to-Source Leakage Current
IGSS
Typ. ––– 0.11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 4.0 35 23 22
Max. Units Conditions ––– V VGS = 0V, ID = 250µA ––– V/°C Reference to 25°C, ID = 1mA
0.18 VGS = 10V, ID = 6.0A 0.22 Ω VGS = 5.0V, ID = 6.0A 0.26 VGS = 4.0V, ID = 5.0A 2.0 V V DS = VGS, ID = 250µA ––– S VDS = 25V, ID = 6.0A
25 VDS = 100V, VGS = 0V A 250 VDS = 80V, VGS = 0V, TJ = 150°C 100 VGS = 16V nA -100 VGS = -16V 20 ID = 6.0A 4.6 nC VDS = 80V 10 VGS = 5.0V, See Fig. 6 and 13
––– VDD = 50V ––– ID = 6.0A ns ––– R G = 11Ω, VGS = 5.0V ––– RD = 8.2Ω, See Fig. 10
Between lead, 7.5 ––– nH and center of die contact 440 ––– VGS = 0V 97 ––– pF VDS = 25V 50 ––– ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics IS I SM
V SD t rr Q rr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol ––– ––– 10 showing the A G integral reverse ––– ––– 35 S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 6.0A, VGS = 0V ––– 110 160 ns TJ = 25°C, IF = 6.0A ––– 410 620 nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 4.7mH RG = 25Ω, IAS = 6.0A. (See Figure 12) ISD ≤ 6.0A, di/dt ≤ 340A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Uses IRL520N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
IRL520NS/L 100
100
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V
ID , Drain-to-Source Current (A )
ID , D rain-to-S ource C urrent (A )
10
1
2.5V
2 0µ s P U LS E W ID T H T J = 2 5°C
0.1 0.1
VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP
TOP
1
10
10
2.5 V 1
2 0µ s P U LS E W ID TH T J = 1 75 °C
0.1
A
0.1
100
1
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.0
R D S (on ) , D rain-to-S ource O n R esistance (N orm alized)
I D , D ra in -to-S ourc e C urrent (A)
100
T J = 2 5°C T J = 1 7 5°C
1
V D S = 5 0V 2 0µ s P U L S E W ID TH
0.1 2
4
6
8
V G S , G ate-to -Sou rce Voltage (V)
Fig 3. Typical Transfer Characteristics
A
100
V D S , D rain-to-S ource V oltage (V )
V D S , D rain-to-S ource V oltage (V )
10
10
10
A
I D = 1 0A
2.5
2.0
1.5
1.0
0.5
V G S = 10 V
0.0 -60
-40
-20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction T em perature (°C )
Fig 4. Normalized On-Resistance Vs. Temperature
IRL520NS/L 15
V GS C iss C rs s C o ss
= = = =
0V , f = 1MHz C g s + C g d , C d s S H O R TE D C gd C ds + C g d
V G S , G ate-to-Source V oltage (V )
C , Capacitance (pF)
800
C iss
600
400
C oss 200
C rss
0 10
V D S = 80 V V D S = 50 V V D S = 20 V
12
9
6
3
F O R TE S T C IR C U IT S E E F IG U R E 1 3
0
A 1
I D = 6.0 A
0
100
10
15
20
A 25
Q G , T otal G ate C harge (nC )
V D S , D rain-to-S ourc e V oltage (V )
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
100
O P E R A T IO N IN T H IS A R E A L IM ITE D B Y R D S (o n) 10µ s
I D , D rain Current (A )
I S D , Reverse D rain C urrent (A)
5
TJ = 1 75 °C
10
T J = 25 °C
1
10 100µ s
1m s 1 10 m s
VG S = 0 V
0.1 0.4
0.6
0.8
1.0
1.2
V S D , S ourc e-to-D rain V oltage (V )
Fig 7. Typical Source-Drain Diode Forward Voltage
A
1.4
T C = 25 °C T J = 17 5°C S ing le P u lse
0.1 1
A 10
100
1000
V D S , D rain-to-S ource V oltage (V )
Fig 8. Maximum Safe Operating Area
IRL520NS/L RD
10
V DS VGS
D.U.T.
I D , D ra in C u rren t (A m ps )
8
RG
+
V - DD 6
5.0V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 %
4
Fig 10a. Switching Time Test Circuit 2
VDS 90%
A
0 25
50
75
100
125
150
175
TC , C ase T em perature (°C )
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50 1 0.20 0.10 0.05
0.1
0.01 0.00001
0.02 0.01
P DM
SINGLE PULSE (THERMAL RESPONSE)
t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.1
IRL520NS/L
VDS D.U.T. RG
+ V - DD IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp VDD
E A S , S ingle Pulse Avalanc he E nergy (m J)
200
L
TOP B O T TO M
160
ID 2.4 A 4.2A 6 .0 A
120
80
40
0
A 25
50
75
100
125
150
175
S tarting T J , J unc tion T em perature (°C )
VDS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T.
50KΩ
QG
12V
.2µF .3µF
10 V QGS
QGD
D.U.T. VGS
VG
3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
+ V - DS
IRL520NS/L Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
+
-
-
+
• • • •
RG
Driver Gate Drive P.W.
+
dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
D=
Period
-
V DD
P.W. Period VGS=10V
D.U.T. ISD Waveform Reverse Recovery Current
Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
Re-Applied Voltage
Body Diode
VDD
Forward Drop
Inductor Curent Ripple ≤ 5%
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
ISD
*
IRL520NS/L D2Pak Package Outline
1 0.54 (.4 15) 1 0.29 (.4 05) 1.4 0 (.055 ) M AX.
-A-
1.3 2 (.05 2) 1.2 2 (.04 8)
2
1.7 8 (.07 0) 1.2 7 (.05 0)
1
1 0.16 (.4 00 ) RE F.
-B -
4.69 (.1 85) 4.20 (.1 65)
6.47 (.2 55 ) 6.18 (.2 43 )
3
15 .4 9 (.6 10) 14 .7 3 (.5 80)
2.7 9 (.110 ) 2.2 9 (.090 ) 2.61 (.1 03 ) 2.32 (.0 91 )
5 .28 (.20 8) 4 .78 (.18 8)
3X
1.40 (.0 55) 1.14 (.0 45) 5 .08 (.20 0)
0.5 5 (.022 ) 0.4 6 (.018 )
0 .93 (.03 7 ) 3X 0 .69 (.02 7 ) 0 .25 (.01 0 )
M
8.8 9 (.3 50 ) R E F.
1.3 9 (.0 5 5) 1.1 4 (.0 4 5)
B A M
M IN IM U M R E CO M M E ND E D F O O TP R IN T 1 1.43 (.4 50 )
NO TE S: 1 D IM EN S IO N S A FTER SO L D ER D IP. 2 D IM EN S IO N IN G & TO LE RA N C IN G PE R A N S I Y1 4.5M , 198 2. 3 C O N TRO L LIN G D IM EN SIO N : IN C H . 4 H E ATSINK & L EA D D IM EN S IO N S D O N O T IN C LU D E B UR R S.
LE A D A SS IG N M E N TS 1 - G A TE 2 - D R AIN 3 - S O U RC E
8.89 (.3 50 ) 17 .78 (.70 0)
3 .8 1 (.15 0) 2 .08 (.08 2) 2X
Part Marking Information D2Pak
IN TE R N A TIO N A L R E C T IF IE R LO G O A S S E M B LY LO T C O D E
A
PART NUM BER F530S 9 24 6 9B 1M
DATE CODE (Y YW W ) YY = Y E A R W W = W EEK
2.5 4 (.100 ) 2X
IRL520NS/L Package Outline TO-262 Outline
Part Marking Information TO-262
IRL520NS/L Tape & Reel Information D2Pak
TR R 1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 4 .1 0 (.1 6 1 ) 3 .9 0 (.1 5 3 )
F E E D D IRE CTIO N 1 .8 5 (.0 7 3 ) 1 .6 5 (.0 6 5 )
1 .60 (.06 3) 1 .50 (.05 9)
1 1 .6 0 (.4 5 7 ) 1 1 .4 0 (.4 4 9 )
0 .3 68 (.0 1 4 5 ) 0 .3 42 (.0 1 3 5 )
1 5 .4 2 (.6 0 9 ) 1 5 .2 2 (.6 0 1 )
2 4 .3 0 (.9 5 7 ) 2 3 .9 0 (.9 4 1 )
TR L 10 .9 0 (.42 9) 10 .7 0 (.42 1)
1 .75 (.06 9 ) 1 .25 (.04 9 )
4 .7 2 (.1 3 6) 4 .5 2 (.1 7 8)
16 .10 (.63 4 ) 15 .90 (.62 6 )
F E E D D IRE C TIO N
13.50 (.532 ) 12.80 (.504 )
2 7.4 0 (1.079) 2 3.9 0 (.9 41) 4
33 0.00 (1 4.1 73) MA X.
NO TES : 1. C O M F O R M S TO E IA -4 18. 2. C O N TR O LLIN G D IM E N S IO N : M ILL IM ET ER . 3. D IM E N S IO N ME A S U R E D @ H U B . 4. IN C LU D E S F LA N G E D IS TO R T IO N @ O U T E R E D G E .
60.00 (2.3 62) MIN .
26 .40 (1.03 9) 24 .40 (.961 ) 3
3 0.40 (1.1 97) MAX. 4
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 5/98
Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/
