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Irls4030pbf Irlsl4030pbf V 100v

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August 2018
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PD - 97370 Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits IRLS4030PbF IRLSL4030PbF HEXFET® Power MOSFET D G Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free S VDSS RDS(on) typ. max. ID 100V 3.4mΩ 4.3mΩ 180A S S D G D2Pak IRLS4030PbF TO-262 IRLSL4030bF G D G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS dv/dt TJ TSTG Parameter Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Max. Units 180 130 730 A W 370 2.5 ± 16 W/°C V 21 -55 to + 175 V/ns °C 300 Soldering Temperature, for 10 seconds (1.6mm from case) Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f 305 See Fig. 14, 15, 22a, 22b mJ A mJ Thermal Resistance Typ. Max. Units RθJC Symbol Junction-to-Case jk ––– °C/W RθJA Junction-to-Ambient (PCB Mount) ij ––– 0.40 40 www.irf.com Parameter 1 02/12/09 IRLS/SL4030PbF Static @ TJ = 25°C (unless otherwise specified) Symbol Parameter V(BR)DSS Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance Min. Typ. Max. Units VGS(th) IDSS Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage 100 ––– ––– ––– 1.0 ––– ––– ––– ––– RG(int) Internal Gate Resistance ––– ––– 0.10 3.4 3.6 ––– ––– ––– ––– ––– ––– ––– 4.3 4.5 2.5 20 250 100 -100 2.1 ––– Conditions V VGS = 0V, ID = 250µA V/°C Reference to 25°C, ID = 5mAc mΩ VGS = 10V, ID = 110A f VGS = 4.5V, ID = 92A f V VDS = VGS, ID = 250µA VDS = 100V, VGS = 0V µA VDS = 100V, VGS = 0V, TJ = 125°C VGS = 16V nA VGS = -16V Ω Dynamic @ TJ = 25°C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 320 ––– ––– ––– 87 130 ––– 27 ––– ––– 45 ––– ––– 42 ––– ––– 74 ––– ––– 330 ––– ––– 110 ––– ––– 170 ––– ––– 11360 ––– ––– 670 ––– ––– 290 ––– Effective Output Capacitance (Energy Related)h ––– 760 ––– ––– 1140 ––– Effective Output Capacitance (Time Related)g S nC ns pF Conditions VDS = 25V, ID = 110A ID = 110A VDS = 50V VGS = 4.5V f ID = 110A, VDS =0V, VGS = 4.5V VDD = 65V ID = 110A RG = 2.7Ω VGS = 4.5V f VGS = 0V VDS = 50V ƒ = 1.0MHz VGS = 0V, VDS = 0V to 80V h VGS = 0V, VDS = 0V to 80V g Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode)c Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25°C, L = 0.05mH RG = 25Ω, IAS = 110A, VGS =10V. Part not recommended for use above this value . ISD ≤ 110A, di/dt ≤ 1330A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%. Min. Typ. Max. Units ––– ––– 180 A ––– ––– 730 Conditions MOSFET symbol showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = 110A, VGS = 0V f TJ = 25°C VR = 85V, TJ = 125°C IF = 110A di/dt = 100A/µs f TJ = 25°C S ––– ––– 1.3 V ––– 50 ––– ns ––– 60 ––– ––– 88 ––– nC TJ = 125°C ––– 130 ––– ––– 3.3 ––– A TJ = 25°C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniquea refer to applocation note # AN- 994 echniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C. RθJC value shown is at time zero. 2 www.irf.com IRLS/SL4030PbF 1000 1000 100 BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP VGS 15V 10V 8.0V 4.5V 3.5V 3.0V 2.7V 2.5V BOTTOM 100 10 2.5V 2.5V ≤60µs PULSE WIDTH ≤60µs PULSE WIDTH Tj = 175°C Tj = 25°C 10 1 0.1 1 10 100 0.1 1000 Fig 1. Typical Output Characteristics 10 100 1000 Fig 2. Typical Output Characteristics 1000 RDS(on) , Drain-to-Source On Resistance (Normalized) 2.5 TJ = 175°C 100 TJ = 25°C 10 V DS = 50V ≤60µs PULSE WIDTH 1.0 1 2 3 4 ID = 110A V GS = 10V 2.0 1.5 1.0 0.5 0.0 5 -60 -40 -20 0 20 40 60 80 100120140160180 V GS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 100000 5.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd ID= 110A V GS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V) C oss = C ds + C gd C, Capacitance (pF) VGS 15V 10V 8.0V 4.5V 3.5V 3.0V 2.7V 2.5V Ciss 10000 Coss 1000 Crss 100 V DS= 80V V DS= 50V 4.0 3.0 2.0 1.0 0.0 1 10 100 V DS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 20 40 60 80 100 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRLS/SL4030PbF 10000 TJ = 175°C ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 100 TJ = 25°C 10 1 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100µsec 100 10msec 1msec DC 10 Tc = 25°C Tj = 175°C Single Pulse V GS = 0V 0.1 1 0.0 0.5 1.0 1.5 2.0 2.5 0 V SD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) 160 140 120 100 80 60 40 20 0 75 100 125 150 175 V (BR)DSS, Drain-to-Source Breakdown Voltage (V) 180 50 1000 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( °C ) Fig 10. Drain-to-Source Breakdown Voltage 4.5 EAS , Single Pulse Avalanche Energy (mJ) 1400 4.0 ID 17A 40A BOTTOM 110A TOP 1200 3.5 1000 3.0 Energy (µJ) 100 125 TC , Case Temperature (°C) Fig 9. Maximum Drain Current vs. Case Temperature 2.5 2.0 1.5 1.0 0.5 0.0 800 600 400 200 0 -20 0 20 40 60 80 100 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 10 Fig 8. Maximum Safe Operating Area 200 25 1 VDS, Drain-to-Source Voltage (V) 120 25 50 75 100 125 150 175 Starting TJ , Junction Temperature (°C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRLS/SL4030PbF Thermal Response ( Z thJC ) °C/W 1 D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01 τJ R1 R1 τJ τ1 R2 R2 τ2 τ1 τ2 R3 R3 τ3 τC τ τ3 Ci= τi/Ri Ci τi/Ri 0.001 SINGLE PULSE ( THERMAL RESPONSE ) 0.0001 1E-006 1E-005 Ri (°C/W) τi (sec) 0.0477 0.000071 0.1631 0.000881 0.1893 0.007457 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse 100 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Tj = 150°C and Tstart =25°C (Single Pulse) 0.01 0.05 0.10 1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming ∆Τ j = 25°C and Tstart = 150°C. 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth 350 300 EAR , Avalanche Energy (mJ) Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 110A 250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav Fig 15. Maximum Avalanche Energy vs. Temperature www.irf.com 5 IRLS/SL4030PbF 40 IF = 73A V R = 85V 35 2.0 TJ = 25°C TJ = 125°C 30 1.5 IRRM (A) VGS(th) , Gate threshold Voltage (V) 2.5 ID = 250µA ID = 1.0mA 1.0 ID = 1.0A 25 20 15 10 0.5 5 0 0.0 -75 -50 -25 0 0 25 50 75 100 125 150 175 200 600 800 1000 diF /dt (A/µs) T J , Temperature ( °C ) Fig. 17 - Typical Recovery Current vs. dif/dt Fig 16. Threshold Voltage vs. Temperature 35 800 IF = 110A V R = 85V 30 IF = 73A V R = 85V 720 TJ = 25°C TJ = 125°C 25 640 TJ = 25°C TJ = 125°C 560 20 QRR (A) IRRM (A) 400 15 480 400 320 10 240 5 160 0 80 0 200 400 600 800 1000 0 200 diF /dt (A/µs) 400 600 800 1000 diF /dt (A/µs) Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt 880 IF = 110A V R = 85V 800 720 TJ = 25°C TJ = 125°C QRR (A) 640 560 480 400 320 240 160 80 0 200 400 600 800 1000 diF /dt (A/µs) 6 Fig. 20 - Typical Stored Charge vs. dif/dt www.irf.com IRLS/SL4030PbF Driver Gate Drive D.U.T - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs V(BR)DSS 15V DRIVER L VDS tp D.U.T RG + V - DD IAS VGS 20V A 0.01Ω tp I AS Fig 22a. Unclamped Inductive Test Circuit RD VDS Fig 22b. Unclamped Inductive Waveforms VDS 90% VGS D.U.T. RG + - VDD V10V GS 10% VGS Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % td(on) Fig 23a. Switching Time Test Circuit tr t d(off) Fig 23b. Switching Time Waveforms Id Current Regulator Same Type as D.U.T. Vds Vgs 50KΩ 12V tf .2µF .3µF D.U.T. + V - DS Vgs(th) VGS 3mA IG ID Current Sampling Resistors Fig 24a. Gate Charge Test Circuit www.irf.com Qgs1 Qgs2 Qgd Qgodr Fig 24b. Gate Charge Waveform 7 IRLS/SL4030PbF D2Pak (TO-263AB) Package Outline Dimensions are shown in millimeters (inches) D2Pak (TO-263AB) Part Marking Information 7+,6,6$1,5)6:,7+ /27&2'( $66(0%/('21:: ,17+($66(0%/

Irls4030pbf Irlsl4030pbf V 100v

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