Iso7520c

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Product Folder Sample & Buy Support & Community Tools & Software Technical Documents ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 ISO752xC Low-Power 5 kVRMS Dual-Channel Digital Isolators 1 Features 3 Description • • • • • • The ISO7520C and ISO7521C provide galvanic isolation of up to 4243 VRMS for 1 minute per UL and 6000 VPK per VDE. These devices are also certified to 5000 VRMS reinforced insulation per end equipment standards IEC 60950-1, IEC 61010-1, and IEC 60601-1. These digital isolators have two isolated channels with unidirectional (ISO7520C) and bidirectional (ISO7521C) channel configurations. Each isolation channel has a logic input and output buffer separated by a silicon oxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and can operate from 3.3- and 5-V supplies. All inputs are 5-V tolerant when supplied from 3.3-V supplies. 1 • • Highest Signaling Rate: 1 Mbps Propagation Delay Less Than 20 ns Low-Power Consumption Wide Ambient Temperature: –40°C to 105°C 50 kV/µs Transient Immunity Typical Operates From 3.3-V or 5-V Supply and Logic Levels 3.3-V and 5.0-V Level Translation Safety and Regulatory Approvals – 6000 VPK Isolation per DIN V VDE V 0884-10 and DIN EN 61010-1 – 4243 VRMS Isolation for 1 Minute per UL 1577 – CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 61010-1, and IEC 60601-1 End Equipment Standards – TUV 5000 VRMS Isolation per EN 60950-1 and EN 61010-1 – CQC Certification per GB4943.1-2011 2 Applications • NOTE: The ISO7520C and ISO7521C are specified for signaling rates up to 1 Mbps. Due to their fast response time, these devices will also transmit faster data with much shorter pulse widths. Designers must add external filtering to remove spurious signals with input pulse duration < 20 ns, if desired. Device Information(1) Opto-Coupler Replacement in: – Industrial Field-Buses – ProfiBuses – ModBuses – DeviceNet™ Data Buses – Servo Control Interfaces – Motor Control – Power Supplies – Battery Packs PART NUMBER ISO7520C ISO7521C PACKAGE SOIC (16) BODY SIZE (NOM) 10.30 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VCCI VCCO Isolation Capacitor INx OUTx GNDI GNDO (1) VCCI and GNDI are supply and ground connections respectively for the input channels. (2) VCCO and GNDO are supply and ground connections respectively for the output channels. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 4 4 6.1 6.2 6.3 6.4 6.5 Absolute Maximum Ratings ..................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 5 Electrical Characteristics: VCC1 and VCC2 at 5 V ± 5% .............................................................................. 6 6.6 Electrical Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5% ................................................................. 6 6.7 Electrical Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5% ................................................................ 7 6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 5% .............................................................................. 7 6.9 Power Dissipation Characteristics ............................ 7 6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ± 5% .............................................................................. 8 6.11 Switching Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5% ............................................................. 8 6.12 Switching Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5% ................................................................ 8 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 5% .............................................................................. 9 6.14 Typical Characteristics ............................................ 9 7 8 Parameter Measurement Information ................ 10 Detailed Description ............................................ 11 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 11 11 12 14 Application and Implementation ........................ 15 9.1 Application Information............................................ 15 9.2 Typical Application ................................................. 15 10 Power Supply Recommendations ..................... 17 11 Layout................................................................... 17 11.1 Layout Guidelines ................................................. 17 11.2 Layout Example .................................................... 17 12 Device and Documentation Support ................. 18 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 18 13 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (October 2013) to Revision E • Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision C (November 2011) to Revision D Page • Deleted Note 1 from the INSULATION CHARACTERISTICS table..................................................................................... 12 • Changed the REGULATORY INFORMATION table, TUV column From: Certificate Number: U8V 11 08 77311 006 To: Certificate Number: U8V 1309 77311 010 ..................................................................................................................... 14 Changes from Revision B (June 2011) to Revision C Page • Changed all the devices numbers by adding a 'C' to the end ................................................................................................ 1 • Changed the Safety and Regulatory Approvals Feature........................................................................................................ 1 • Changed the Description section............................................................................................................................................ 1 • Changed the IEC 60664-1 Ratings Table ............................................................................................................................ 12 • Changed the INSULATION CHARACTERISTICS table....................................................................................................... 12 2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 Changes from Revision A (September 2010) to Revision B Page • Changed 5th Features subbullets........................................................................................................................................... 1 • Changed the first SWITCHING CHAR table, MAX value, 2nd row from 3.5 to 3.7 and third row from 4 to 4.9 .................... 8 • Changed the second SWITCHING CHAR table, MAX value, 2nd row from 4 to 5.6 and third row from 5 to 6.3 ................. 8 • Changed the third SWITCHING CHAR table, MAX value, 3rd row from 5 to 8.5 .................................................................. 8 • Changed the fourth SWITCHING CHAR table, MAX value, 3rd row from 6 to 6.8................................................................ 9 • Changed REGULATORY INFORMATION table , from: File Number: pending, to: File Number: E181974 ........................ 14 Changes from Original (June 2010) to Revision A Page • Added PIN DESCRIPTION table............................................................................................................................................ 4 • Changed tfs units in Switching Characteristics Table ............................................................................................................. 8 • Changed tfs units in Switching Characteristics Table ............................................................................................................. 8 • Changed tfs units in Switching Characteristics Table ............................................................................................................. 8 • Changed tfs units in Switching Characteristics Table ............................................................................................................. 9 • Deleted VIORM test conditions from INSULATION CHARACTERSISTCS table .................................................................. 12 • Added VPR parameter and Specifications in INSULATION CHARACTERSISTCS table ..................................................... 12 • Changed VIOTM row of the INSULATION CHARACTERISTICS tables ................................................................................ 12 • Changed VISO Specifications in INSULATION CHARACTERISTICS table .......................................................................... 12 • Changed Minimum internal gap limit from 0.016 to 0.014 mm............................................................................................. 12 Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 3 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 5 Pin Configuration and Functions DW Package 16-Pin SOIC Top View ISO7520C GND1 NC VCC1 INA INB NC GND1 NC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND2 NC VCC2 OUTA OUTB NC NC GND2 GND1 NC VCC1 OUTA INB NC GND1 NC 1 2 3 4 5 6 7 8 ISO7521C 16 15 14 13 12 11 10 9 GND2 NC VCC2 INA OUTB NC NC GND2 Pin Functions PIN NAME I/O DESCRIPTION ISO7520C ISO7521C GND1 1, 7 1, 7 — Ground connection for VCC1 GND2 Ground connection for VCC2 9, 16 9, 16 — INA 4 13 I Input, channel A INB 5 5 I Input, channel B NC 2, 6, 8, 10, 11, 15 2, 6, 8, 10, 11, 15 — No internal connection OUTA 13 4 O Output, channel A OUTB 12 12 O Output, channel B VCC1 3 3 — Power supply, VCC1 VCC2 14 14 — Power supply, VCC2 6 Specifications 6.1 Absolute Maximum Ratings (1) MIN MAX UNIT VCC1, VCC2 Supply voltage (2) –0.5 6 V VI Voltage at INx, OUTx –0.5 VCC + 0.5 (3) V IO Output Current –15 TJ Maximum junction temperature Tstg Storage temperature (1) (2) (3) –65 15 mA 150 °C 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Maximum voltage must not exceed 6 V. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) 4 Electrostatic discharge (1) UNIT ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 Machine model (MM) ±200 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC1, VCC2 MIN NOM MAX UNIT Supply voltage - 3.3-V Operation 3.15 3.3 3.45 V Supply voltage - 5-V Operation 4.75 5 5.25 IOH High-level output current IOL Low-level output current VIH High-level output voltage 2 5.25 VIL Low-level output voltage 0 0.8 V TA Ambient temperature -40 105 °C Junction temperature TJ (1) –4 mA 4 –40 136 1/tui Signaling rate 0 1 tui Input pulse duration 1 (1) mA V °C Mbps µs To maintain the recommended operating conditions for TJ, see Thermal Information. 6.4 Thermal Information ISO7520C, ISO7521C THERMAL METRIC (1) DW [SOIC] UNIT 16 PINS RθJA Junction-to-ambient thermal resistance 79.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 44.6 °C/W RθJB Junction-to-board thermal resistance 51.2 °C/W ψJT Junction-to-top characterization parameter 18.0 °C/W ψJB Junction-to-board characterization parameter 42.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 5 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ± 5% VCC1 and VCC2 at 5 V ±5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS IOH = –4 mA; See Figure 4 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current INx at VCCI (2) IIL Low-level input current INx at 0 V CMTI Common-mode transient immunity VI = VCCI or 0 V; See Figure 6 MIN TYP (1) 4.6 VCCO –0.1 5 VCCO –0.8 IOH = –20 µA; See Figure 4 MAX V IOL = 4 mA; See Figure 4 0.2 0.4 IOL = 20 µA; See Figure 4 0 0.1 400 V mV 10 –10 25 UNIT µA µA 50 kV/µs SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE-WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 0.4 1 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 3 6 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4 mA (1) (2) VCCO is the supply voltage, VCC1 or VCC2, for the output channel that is being measured. VCCI is the supply voltage, VCC1 or VCC2, for the input channel that is being measured. 6.6 Electrical Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5% VCC1 at 5 V ±5%, VCC2 at 3.3 V ±5%, TA = –40°C to 105°C PARAMETER VOH High-level output voltage TEST CONDITIONS IOH = –4 mA; See Figure 4 MIN TYP ISO7521C (5-V side) VCCO –0.8 4.6 ISO7520C/7521C(3.3-V side) VCCO –0.4 3 VCCO –0.1 VCCO IOH = –20 µA; See Figure 4 MAX V IOL = 4 mA; See Figure 4 0.2 0.4 IOL = 20 µA; See Figure 4 0 0.1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current INx at VCCI IIL Low-level input current INx at 0 V CMTI Common-mode transient immunity VI = VCCI or 0 V; See Figure 6 400 V mV 10 –10 25 UNIT µA µA 40 kV/µs SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE-WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 0.4 1 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4.5 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 1.5 3.5 mA 6 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 6.7 Electrical Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5% VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%, TA = –40°C to 105°C PARAMETER VOH TEST CONDITIONS IOH = –4 mA; See Figure 4 High-level output voltage MIN TYP ISO7520C/7521C (5-V side) VCCO –0.8 4.6 ISO7521C (3.3-V side) VCCO –0.4 3 VCCO –0.1 VCCO IOH = –20 µA; See Figure 4 MAX V IOL = 4 mA; See Figure 4 0.2 0.4 IOL = 20 µA; See Figure 4 0 0.1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current INx at VCCI IIL Low-level input current INx at 0 V CMTI Common-mode transient immunity VI = VCCI or 0 V; See Figure 6 UNIT V 400 mV 10 µA –10 µA 25 40 kV/µs SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE-WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 0.2 0.7 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 3 6 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 1.5 3.5 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4 mA MAX 6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ± 5% VCC1 and VCC2 at 3.3 V ±5%, TA = –40°C to 105°C PARAMETER MIN TYP IOH = –4 mA; See Figure 4 TEST CONDITIONS VCCO –0.4 3 IOH = –20 µA; See Figure 4 VCCO –0.1 3.3 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current INx at VCCI IIL Low-level input current INx at 0 V CMTI Common-mode transient immunity VI = VCCI or 0 V; See Figure 6 UNIT V IOL = 4 mA; See Figure 4 0.2 0.4 IOL = 20 µA; See Figure 4 0 0.1 V 400 mV µA –10 25 µA 40 kV/µs SUPPLY CURRENT (ALL INPUTS SWITCHING WITH SQUARE-WAVE CLOCK SIGNAL FOR DYNAMIC ICC MEASUREMENT) ISO7520C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 0.2 0.7 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 2 4.5 mA ISO7521C ICC1 Supply current for VCC1 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 1.5 3.5 mA ICC2 Supply current for VCC2 DC to 1 Mbps VI = VCCI or 0 V, 15-pF load 1.5 3.5 mA 6.9 Power Dissipation Characteristics over operating free-air temperature range (unless otherwise noted) ISO7520C, ISO7521C PARAMETER DW [SOIC] UNIT 16 PINS PD Device power dissipation, VCC1 = VCC2 = 5.25 V, TJ = 150°C, CL = 15 pF, Input a 0.5 MHz 50% duty cycle square wave Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C 42 mW Submit Documentation Feedback 7 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 6.10 Switching Characteristics: VCC1 and VCC2 at 5 V ± 5% VCC1 and VCC2 at 5 V ±5%, TA = –40°C to 105°C PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) TEST CONDITIONS MIN MAX UNIT 9 14 ns 0.3 3.7 ns Part-to-part skew time 4.9 ns tsk(o) Channel-to-channel output skew time 3.6 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 4 TYP 1 See Figure 4 See Figure 5 ns 1 ns 6 µs Also known as pulse skew. 6.11 Switching Characteristics: VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5% VCC1 at 5 V ± 5%, VCC2 at 3.3 V ± 5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) MIN See Figure 4 See Figure 4 See Figure 5 TYP MAX 10 17 UNIT ns 0.5 5.6 ns 6.3 ns 4 ns 2 ns 2 ns 6 µs Also known as pulse skew. 6.12 Switching Characteristics: VCC1 at 3.3 V ± 5%, VCC2 at 5 V ± 5% VCC1 at 3.3 V ±5%, VCC2 at 5 V ±5%, TA = –40°C to 105°C PARAMETER tPLH, tPHL PWD (1) TEST CONDITIONS Propagation delay time See Figure 4 Pulse width distortion |tPHL – tPLH| Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss 8 TYP MAX 10 17 ns 0.5 tsk(pp) (1) MIN 2 See Figure 4 See Figure 5 UNIT 4 ns 8.5 ns 4 ns ns 2 ns 6 µs Also known as pulse skew. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 6.13 Switching Characteristics: VCC1 and VCC2 at 3.3 V ± 5% VCC1 and VCC2 at 3.3 V ±5%, TA = –40°C to 105°C PARAMETER TEST CONDITIONS MIN MAX UNIT 12 20 ns 1 5 ns tPLH, tPHL Propagation delay time PWD (1) Pulse width distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time 6.8 ns tsk(o) Channel-to-channel output skew time 5.5 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss (1) See Figure 4 TYP 2 See Figure 4 See Figure 5 ns 2 ns 6 µs Also known as pulse skew. 6.14 Typical Characteristics IOH − High-Level Output Current − mA Fail-Safe Voltage Threshold − V 2.62 2.61 FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS− 2.54 2.53 2.52 −55 0 TA = 25°C −10 −20 −30 −40 VCC1, VCC2 at 3.3 V −50 −60 −70 VCC1, VCC2 at 5 V −80 −90 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C 0 125 1 2 3 4 5 VOH − High-Level Output Voltage − V G006 Figure 1. Fail-Safe Voltage Threshold vs Free-Air Temperature 6 G007 Figure 2. High-Level Output Current vs High-Level Output Voltage IOL − Low-Level Output Current − mA 80 TA = 25°C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 5 VOL − Low-Level Output Voltage − V 6 G008 Figure 3. Low-Level Output Current vs Low-Level Output Voltage Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 9 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 7 Parameter Measurement Information ISOLATION BARRIER IN Input Generator VI VCCI 50 W VI 1.4 V 1.4 V OUT 0V t PHL tPLH VO CL NOTE B NOTE A VOH 90% VCCO /2 VO 10% tf tr VCCO /2 VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 4. Switching Characteristic Test Circuit and Voltage Waveforms VI VCCI ISOLATION BARRIER VCCI IN = 0 2.7 V VI OUT VO 0V tfs CL VOH 50% VO FAILSAFE HIGH VOL NOTE A A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 5. Fail-safe Delay Time Test Circuit and Voltage Waveforms S1 C = 0.1 μ F ±1% Isolation Barrier VCCI IN GNDI VCCO C = 0.1 μ F ±1% Pass-fail criteria – output must remain stable. OUT + CL Note A VOH or VOL – GNDO + VCM – A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 6. Common-Mode Transient Immunity Test Circuit 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 8 Detailed Description 8.1 Overview The isolator in Figure 7 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a singleended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low frequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer. 8.2 Functional Block Diagram Isolation barrier OSC LPF Low-frequency channel (DC...100 kbps) PWM VREF 0 IN Out 1 S DCL High-frequency channel (100 kbps... 1 Mbps) VREF Figure 7. Conceptual Block Diagram of a Digital Capacitive Isolator Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 11 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 8.3 Feature Description 8.3.1 Insulation Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIORM VPR TEST CONDITIONS SPECIFICATION UNIT 1414 VPEAK Maximum repetitive peak isolation voltage Input to output test voltage Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial discharge < 5 pC 2262 Method b1, VPR = VIORM x 1.875, t = 1 s (100% Production test) Partial discharge < 5 pC 2651 After Input/Output Safety Test Subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC 1697 t = 60 sec (qualification) VPEAK VIOTM Maximum Transient Isolation voltage 6000 VPEAK VISO VTEST = VISO = 4243 VRMS, t = 60 sec (qualification); Withstanding Isolation voltage per UL VTEST = 1.2 × VISO = 5092 VRMS, t = 1 sec (100% 1577 production) 4243 VRMS RS Isolation resistance >109 Ω VIO = 500 V at TS = 150°C Pollution degree 2 8.3.2 IEC 60664-1 Ratings Table PARAMETER TEST CONDITIONS Basic Isolation Group SPECIFICATION Material Group Installation Classification II Rated mains voltages <= 150 Vrms I - IV Rated mains voltages <= 600 Vrms I - III Rated mains voltages <= 1000 Vrms I - II 8.3.3 Package Insulation and Safety-Related Specifications over recommended operating conditions (unless otherwise noted) TEST CONDITIONS MIN Minimum air gap (Clearance) PARAMETER Shortest terminal-to-terminal distance through air 8.34 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm CTI Tracking resistance (Comparative Tracking DIN EN 60112 (VDE 0303-11); IEC 60112 Index) >400 Minimum internal gap (Internal Clearance) 0.014 L(I01) RIO Isolation resistance, input to output (1) CIO Barrier capacitance input to output (1) CI (1) (2) 12 Input capacitance to ground (2) Distance through the insulation TYP MAX UNIT V mm 12 VIO = 500 V, TA = 25ºC >10 VIO = 500 V, 100ºC ≤ TA ≤ TA max >1011 Ω VIO = 0.4 sin(2πft), f = 1 MHz 2 pF VI = VCC/2 + 0.4 sin(2πft), f = 1 MHz, VCC = 5 V 2 pF All pins on each side of the barrier tied together creating a 2-terminal device. Measured from input pin to ground. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 empty para for space above the NOTE NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit-board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 8.3.4 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current-limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS Is Safety input, output, or supply current Ts Maximum Case Temperature MIN TYP MAX θJA =79.9°C/W, VI = 5.25 V, TJ = 150°C, TA = 25°C 298 θJA =79.9°C/W, VI = 3.45 V, TJ = 150°C, TA = 25°C 453 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Safety Limiting Current - mA 500 VCC1 and VCC2 at 3.45 V 400 300 VCC1 and VCC2 at 5.25 V 200 100 0 0 50 100 150 200 250 Case Temperature - °C Figure 8. DW-16 RΘJC Thermal Derating Curve for VDE Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 13 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 8.3.5 Regulatory Information VDE TUV CSA UL Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):200612 and DIN EN 61010-1 (VDE 0411-1):2011-07 Certified according to EN 60950-1 and EN 61010-1 Basic Insulation Maximum Transient Isolation voltage, 6000 VPK Maximum Repetitive Peak Isolation Voltage, 1414 VPK 5000 VRMS Isolation Rating; Reinforced insulation per CSA 60950-1-07+A1 and 5000 VRMS Isolation IEC 60950-1 2nd Ed.+A1, Rating; 380 VRMS max working Reinforced Insulation, 400 voltage; Single Protection, 4243 VRMS maximum working Reinforced insulation per VRMS Withstanding voltage; CSA 61010-1-04 and IEC Isolation Voltage Basic Insulation, 600 61010-1 2nd Ed, 300 VRMS maximum working VRMS max working voltage voltage; 2 Means of Patient Protection at 125 VRMS per IEC 60601-1 (3rd Ed.) Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage Certificate Number: 40016131 Certificate Number: U8V 1309 77311 010 Certificate Number: CQC14001109542 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1, IEC 61010-1, and IEC 60601-1 Master Contract Number: 220991 CQC Recognized under 1577 Component Recognition Program Certified according to GB 4943.1-2011 File Number: E181974 8.4 Device Functional Modes Table 1. Device Function Table VCCI (1) VCCO (1) PU (1) INPUT (INA, INB) (1) OUTPUT (OUTA, OUTB) (1) H H PU L L Open H PD PU X H X PD X Undetermined VCCI = Input-side VCC; VCCO = Output-side VCC; PU = Powered Up (Vcc ≥ 3.15 V); PD = Powered Down (Vcc ≤ 2.1 V); X = Irrelevant; H = High Level; L = Low Level Input VCCI VCCI VCCI Output VCCO 1 M 500 8 IN OUT 13  Figure 9. Equivalent Input and Output Schematic Diagrams 14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The ISO7520C and ISO7521C are high-performance, dual-channel digital isolators with a 5-kVRMS isolation voltage. The isolator uses single-ended TTL-logic switching technology. The supply voltage range is from 3.15 V to 5.25 V for both supplies, VCC1 and VCC2. When designing with digital isolators, it is important to keep in mind that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 Typical Application The ISO7521C can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter, transformer driver, and voltage regulator to create an isolated 4- to 20-mA current loop. 3 4 14 VCC1 VCC2 ISO7521 5 1, 7 13 12 9, 16 Figure 10. Isolated 4-20 mA Current Loop 9.2.1 Design Requirements For the ISO7521C, use the parameters shown in Table 2. Table 2. ISO752xC Design Parameters PARAMETER Supply voltage VALUE 3.15 V to 5.25 V Decoupling capacitor between VCC1 and GND1 0.1 µF Decoupling capacitor from VCC2 and GND2 0.1 µF Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 15 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 9.2.2 Detailed Design Procedure Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, the ISO7521C only needs two external bypass capacitors to operate. ISO7521C VCC1 VCC2 GND1 1 16 GND2 NC 2 15 NC VCC1 3 14 VCC2 OUTA OUTA 4 13 INA INB INB 5 12 OUTB NC 6 11 NC GND1 7 10 NC NC 8 9 GND1 GND2 GND1 GND1 I S O L A TI O N 0.1µF 0.1µF GND2 GND2 INA OUTB GND2 Figure 11. Typical ISO7521C Circuit Hook-up 9.2.3 Application Curve Input Voltage Switching Threshold − V 1.6 VIT+, 5 V 1.5 1.4 VIT+, 3.3 V 1.3 1.2 1.1 VIT−, 5 V 1.0 VIT−, 3.3 V 0.9 0.8 −55 −35 −15 5 25 45 65 85 105 TA − Free-Air Temperature − °C 125 G005 Figure 12. Input Voltage Switching Threshold vs Free-Air Temperature 16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C ISO7520C, ISO7521C www.ti.com SLLSE39E – JUNE 2010 – REVISED MAY 2015 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, TI recommends placing a 0.1-μF bypass capacitor at the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in the SN6501 data sheet (SLLSEA0). 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 13). Layer stacking must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note Digital Isolator Design Guide (SLLA284). 11.1.1 PCB Material For digital circuit boards operating at less than 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over less expensive alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and selfextinguishing flammability characteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane 40 mils Keep this space free from planes, traces, pads, and vias FR-4 0r §4.5 Power plane 10 mils Low-speed traces Figure 13. Layout Recommendation Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C Submit Documentation Feedback 17 ISO7520C, ISO7521C SLLSE39E – JUNE 2010 – REVISED MAY 2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Application Note Digital Isolator Design Guide (SLLA284) Isolation Glossary (SLLA353) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY ISO7520C Click here Click here Click here Click here Click here ISO7521C Click here Click here Click here Click here Click here 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. DeviceNet is a trademark of Open DeviceNet Vendor Association. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7520C ISO7521C PACKAGE OPTION ADDENDUM www.ti.com 11-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ISO7520CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 ISO7520CDW ISO7520CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 ISO7520CDW ISO7521CDW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 ISO7521CDW ISO7521CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 ISO7521CDW (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Mar-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7520CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7521CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7520CDWR SOIC DW 16 2000 367.0 367.0 38.0 ISO7521CDWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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