Jianingwang.

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Modeling of parasitic elements in high voltage multiplier modules Jianing Wang 王佳宁 Electrical Power Processing (EPP) Group Electrical Sustainable Energy Department Delft University of Technology Modeling of parasitic elements in high voltage multiplier modules Proefschrift ter verkrijging van de graad van doctor aan de Technische Universiteit Delft, op gezag van de Rector Magnificus prof. ir. K.C.A.M. Luyben, voorzitter van het College voor Promoties, in het openbaar te verdedigen op maandag 30 juni 2014 om 15.00 uur door Jianing Wang Master of Engineering, Power Electronics and Renewable Energy Center Xi’an Jiaotong University, China geboren te Anhui, China Dit proefschrift is goedgekeurd door de promotor: Prof. Dr. J.A. Ferreira Copromotor Ir. S.W.H. de Haan Copromotor Dr. Ir. M.D. Verweij Samenstelling promotiecommissie: Rector Magnificus Prof. Dr. J.A. Ferreira Ir. S.W.H. de Haan Dr. Ir. M.D. Verweij Prof. Dr. J.A. La Poutre Prof. Dr. Ir. F.B.J. Leferink Prof. Dr. J.J. Smit Prof. Dr. A. Yaravoy Prof. Ir. L. Van der Sluis voorzitter, Technische Universiteit Delft Technische Universiteit Delft, promotor Technische Universiteit Delft, copromotor Technische Universiteit Delft, copromotor Technische Universiteit Delft Universiteit Twente Technische Universiteit Delft Technische Universiteit Delft Technische Universiteit Delft, reservelid Copyright © 2014 by Jianing Wang All rights reserved. No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without the prior permission of the author. ISBN: 978-94-6186-322-5 Acknowledgement Life is short. Life is to experience the necessary experiences. I sincerely appreciate anyone who makes a mark in the travel of my life. The research presented in this thesis was carried out at Delft University of Technology in the Netherlands, in the research group of Electrical Power Processing (EPP), cooperated with Philips Solid State Lighting. Here, I would like to express my deep appreciation for the people who directly contributes to the thesis. First of all, I would like to thank you, my promoter Professor Jan A. Ferreira. You always have positive attitude to my research and give me confidence when I am dispirited. Thank you very much. I would like to thank you, my daily supervisors, Associated Professor Sjoerd W.H. de Haan and Martin D. Verweij. Prof. de Haan, you taught me the importance of the writing and presentation of the research work, which I ignored before. Martin, you helped me greatly with your abundant knowledge on the EM fields and your friendship on my personal problems. Thank you both very much. I would like to thank you also, Dr. Peter Luerkens from Philips. You always gave me detailed and valuable comments on my research all the way along, without which I can hardly finish my work on time. Thank you very much. Furthermore, I would like to thank you, Frans Pansier from NXP. Your door is always open to me and your rich knowledge is always helpful to solve my strange questions. Thank you very much. I would like to thank you, Aniel Shri for the dutch translation of the summary and propositions of this thesis. In the end, I would like to thank you, my colleagues, Rob Schoevaars, Kasper Zwetsloot, Harrie Olsthoorn and Bart Roodenburg for the helps on the experiments and computers. I would like to thank you, Marcelo, Ilija, Yeh and Prasanth for the frequent discussions, which push my work forward step-by-step. Thank you very much. Last but not least, maybe more importantly, I would like to express all my appreciation to all the colleagues, secretaries, friends, families and people I met. You touched my heart, let me fell what life is and gave me joy and courage to go further and further. Thank you all very much. Especially, I would like to thank you, Prof. Xu Yang, my supervisor in master study, who took me into the world of power electronics and introduced EPP group. Without you, I can not join EPP group for the Ph.D study. Thank you very much. I would like to express my acknowledgement to the European Commission and the Dutch Ministry of Economic Affairs for supporting this project under envelope of the ENIAC project SmartPM with the Grant Agreement no. 120008 Abbreviations and Symbols 3D Three dimensional A, B ··· Node number A, B ··· AC Alternating current AC+ Upper AC side of multiplier AC- Lower AC side of multiplier a, b, m, p Parameters aCstru Ratio of the new added structural capacitance Cdt to the original structural capacitance Cdg C Capacitance CT Computed tomography C-V Capacitance voltage curve C.W. Cockcroft Walton C0 Per-unit-length capacitance of transmission line C1, C2 ··· Capacitor number 1, number 2 ··· CDcht Total equivalent parasitic capacitance of diode chains CTS Stray capacitance of transformer windings Cdd Structural capacitance between diodes in multiplier module Cdg Structural capacitance between diode and ground in multiplier module Cdpp Structural capacitance between diode and push-pull capacitors in multiplier module Ceac Equivalent capacitance of the rectifier in LCC by fundamental frequency analysis Cem Equivalent parasitic capacitance of multiplier Cj Junction capacitance of diode Cj0 Initial junction capacitance of diode with zero-bias Co Output capacitor in rectifier or multiplier Co1, Co2 ··· Output capacitor number 1, number 2 ··· Cp Parallel resonant capacitance Cpa Parasitic capacitance, in general Cpp Push-pull capacitors in multiplier Cppg Structural capacitance between push-pull capacitor and ground in multiplier module Cppgt Total structural capacitance between push-pull capacitor and ground in multiplier module Cs Series resonant capacitance Cstru Structural capacitances between the diode and other components in multiplier module, including the capacitances Cdg, Cdpp, Cppg, Cppgt D Diode DC Direct current Dch Diode chain d Distance D1, D2 ··· Diode number 1, number 2 ··· Dch1, Dch2 ··· Diode chain number 1, number 2 ··· E Vector indicating magnitude and direction of electric field E Magnitude of electric field EM Electromagnetic EMI Electromagnetic interference E0, E1 ··· Zero-order electric field, first-order electric field ··· Ek kth-order electric field Ent Electric field on the surface of the diode in the multiplier module without shielding trace Et Electric field on the surface of the diode in the multiplier module with shielding trace F Function FE Finite element f Frequency F Fourier transform GaN Gallium nitride GND Ground H Vector indicating magnitude and direction of magnetic field H Magnitude of magnetic field HV High voltage H0, H1 ··· Zero-order magnetic field, first-order magnetic field ··· Hk kth-order magnetic field I Time invariant current IGBT Insulated gate bipolar transistor i Unit vector ix, iy, iz Unit vector at x direction, y direction and z direction respectively i Time-varying current iCp Current through parallel resonant capacitance iCo1, iCo2 ··· Current through capacitor Co1, Co2 ··· iD1, iD2 ··· Current through diode D1, D2 ··· iLs Current through series resonant inductance iTLin Input current of transmission line io Output current irect Input current of multiplier irect(1) Fundamental element of input current of multiplier irect+ Input current of multiplier at AC+ side irect- Input current of multiplier at AC- side is Source current is 0,1 Source current correct up to and including the first-order quantity is 0..k Source current correct up to and including the kth-order quantity j Imaginary unit K Surface current density k Number Kr Surface current density as reference L Inductor LCC/SPRC Series parallel resonant converter LME Lumped multi element LV Low voltage l Length or physical dimensions, in general L0 Per-unit-length inductance of transmission line Lpa Parasitic inductance, in general Lpae Effective parasitic inductance Ls Series resonant inductance MOSFET Metal-oxide-semiconductor field effect transistor N Turn ratio of transformer nd Diode number per chain nst Number of stages in multiplier PCB Printed circuit board PRC Parallel resonant converter PWM Pulse width modulation Q Charge RL Load Rdp Damping resistor Reac Equivalent resistance of the rectifier in LCC by fundamental frequency analysis rCstru Reduction factor of the structural capacitance Cdg by adding the trace rE Reduction factor of the electric field rv Ratio of the voltage vdt to vdg S Spatial surface vector S Spatial surface scalar Si Silicon SiC Silicon carbide T Thickness t Time t1 Time instant 1 tVch1, tVch2 Time when voltages across diode chain are Vch1, Vch2 tpulse Width of a pulse tr Rise time of a pulse U0 Initial voltage V Time invariant voltage VBR Breakdown voltage of diode Vch1, Vch2 Voltages across diode chain Vk Voltage at node k Vo Output voltage Vpk Peak input voltage of multiplier v Time varying voltage vC1, vC2 ··· Voltage across capacitor C1, C2 ··· vCo1 Voltage across Co1 vDch1, vDch2 ··· Voltage across the diode chain Dch1, Dch2 ··· in the multiplier vTLin Input voltage of transmission line vac+ Unipolar input voltage of multiplier at AC+ side vac- Unipolar input voltage of multiplier at AC- side vcc1+, vcc2+ ··· Voltage on node cc1+, cc2+ ··· vcp Voltage across the parallel resonant capacitor vdd Voltage across the capacitance Cdd vdg Voltage across the capacitance Cdg vdt Voltage across the capacitance Cdt vin Input voltage vrect Input voltage of multiplier vrect(1) Fundamental element of input voltage of multiplier vs Source voltage vs 0,1 Source voltage correct up to and including the first-order quantity vs 0..k Source voltage correct up to and including the kth -order quantity vtg Voltage across the shielding trace and the ground ∆vco1 Voltage ripple across Co1 in multiplier δvco1 Voltage drop on Co1 compared in multiplier to the principle voltage in multiplier w Width ZCS Zero current switching ZVS Zero voltage switching Zin Input impedance Zin 1 First-order input impedance x,y,z Spatial variables ∆ Difference ε Permittivity εr Relative permittivity εo Permittivity in vacuum λ Wavelength µ Permeability µr Relative permeability µo Permeability in vacuum φ Magnetic flux φbi Built-in potential of diode ω Angular frequency Contents Acknowledgement ..................................................................................................................... v Abbreviations and Symbols ....................................................................................................... i Contents ................................................................................................................................... vii Chapter 1.................................................................................................................................... 1 Introduction ............................................................................................................................. 1 1.1 Background .............................................................................................................. 1 1.2 Volume reduction of the generator ........................................................................... 3 1.3 Problem definition .................................................................................................... 6 1.4 Objectives and approaches ....................................................................................... 7 1.5 Thesis layout ............................................................................................................ 8 Chapter 2.................................................................................................................................. 11 Overview of circuit topologies of the HV generator ............................................................. 11 2.1 Introduction ............................................................................................................ 11 2.2 Evolution of the HV generator ............................................................................... 11 2.2.1 Early Stage ........................................................................................................ 12 2.2.1.1 Conventional generators ............................................................................... 12 2.2.1.2 Constant voltage generators .......................................................................... 14 2.2.2 The contemporary high frequency generator ..................................................... 15 2.3 Series parallel LCC resonant converter with capacitive output.............................. 16 2.3.1 Resonant topologies for the generator ............................................................... 17 2.3.1.1 SRC............................................................................................................... 17 2.3.1.2 PRC............................................................................................................... 18 2.3.1.3 LCC .............................................................................................................. 20 2.3.2 Comparison of the topologies ............................................................................ 21 2.3.3 Basic circuit operation of the LCC .................................................................... 21 2.4 Symmetrical Cockcroft-Walton (C.W.) voltage multiplier .................................... 25 2.4.1 The rectified voltage multiplier ......................................................................... 25 2.4.2 Comparison of the voltage multipliers .............................................................. 29 2.4.3 Circuit operation ................................................................................................ 32 2.5 LCC with symmetrical C.W. voltage multiplier..................................................... 35 2.5.1 Steady-state operation ....................................................................................... 35 2.5.2 Transient behaviors as the output shorted ......................................................... 38 2.6 Conclusion ............................................................................................................. 44 Chapter 3.................................................................................................................................. 45 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier .................... 45 3.1 Introduction ............................................................................................................ 45 Role of the parasitic capacitances .......................................................................... 48 3.2 3.3 Full network of the parasitic capacitances.............................................................. 50 3.3.1 Overview of the parasitic capacitances.............................................................. 51 3.3.2 The complete model .......................................................................................... 53 3.4 Equivalent parasitic capacitance of the multiplier .................................................. 53 3.5 Analytical expression of the total chain capacitance .............................................. 55 3.5.1 Chain capacitance .............................................................................................. 56 3.5.2 Chain capacitance without avalanche breakdown of diode ............................... 59 3.5.3 Unbalanced voltage distribution along chain .................................................... 61 3.5.4 Chain capacitance with avalanche breakdown of diode .................................... 64 3.6 Dependence of the total chain capacitance ............................................................. 66 3.6.1 Dependence on the junction capacitance ........................................................... 68 3.6.2 Dependence on the structural capacitance ......................................................... 70 3.6.3 Dependence on the number of diodes per chain nd ............................................ 71 3.6.4 Effect of the breakdown of diodes ..................................................................... 73 3.7 Validation ............................................................................................................... 75 3.8 Minimization of the equivalent parasitic capacitance ............................................ 80 3.8.1 Guidelines for minimization .............................................................................. 80 3.8.2 Design procedure ............................................................................................... 81 3.8.3 Case study.......................................................................................................... 83 3.9 Comparison of multipliers with Si and SiC diodes ................................................ 85 3.10 Conclusion ............................................................................................................. 88 Chapter 4.................................................................................................................................. 89 Electric field reduction in the multiplier module ................................................................... 89 4.1 Introduction ............................................................................................................ 89 4.2 Electric field distribution ........................................................................................ 91 4.3 Electric field reduction ........................................................................................... 96 4.3.1 Principle ............................................................................................................ 96 4.3.2 Case study.......................................................................................................... 99 4.4 Demonstrator ........................................................................................................ 103 4.5 Conclusion ........................................................................................................... 110 Chapter 5................................................................................................................................ 113 Parasitic modeling in case of the fast transient EM field .................................................... 113 5.1 Introduction .......................................................................................................... 113 5.2 Circuit modeling in the intermediate frequency range ......................................... 116 5.2.1 Lumped element, lumped multi element and continuous models .................... 116 5.2.2 Procedures of circuit modeling ........................................................................ 119 5.2.3 System with continuous spectrum excitations ................................................. 124 5.3 A single-turn inductor with pulsed source............................................................ 129 5.3.1 Transient EM fields in the inductor ................................................................. 131 5.3.1.1 Zero-order fields .............................................................................................. 132 5.3.1.2 First-order fields .............................................................................................. 132 5.3.1.3 Higher-order fields .......................................................................................... 133 5.3.1.4 Total EM fields ................................................................................................ 134 5.3.2 LME circuit model .......................................................................................... 135 5.3.3 Numerical results ............................................................................................. 136 5.4 The modeling of parasitics in the multiplier module ............................................ 140 5.4.1 Modeling of a structure without sources at terminals ...................................... 140 5.4.2 Procedure for modeling the parasitics ............................................................. 144 5.4.2.1 Simplification of the structure ......................................................................... 144 5.4.2.2 Field calculation .............................................................................................. 145 5.4.2.3 Extraction of the LME model .......................................................................... 146 5.5 Conclusion ........................................................................................................... 148 Chapter 6................................................................................................................................ 149 Conclusions and recommendations ..................................................................................... 149 6.1 Conclusions .......................................................................................................... 149 6.2 Recommendations for future research .................................................................. 153 Appendix A ............................................................................................................................ 155 Parasitic capacitances in the HV multiplier module ............................................................ 155 A.1 Steady-state operation of the multiplier with parasitic capacitances .................... 155 A.2 Simplification of the capacitance network of the multiplier ................................ 159 A.2.1 Step 1 of the simplification .............................................................................. 160 A.2.2 Step 2 of the simplification .............................................................................. 163 A.3 Definition of capacitance ..................................................................................... 165 A.4 3D FE filed simulation ......................................................................................... 166 A.4.1 3D FE models of the module ........................................................................... 166 A.4.1.1 Simplification of the diode model .............................................................. 167 A.4.1.2 Simplification of the capacitor model ......................................................... 170 A.4.1.3 3D FE model of the multiplier module ....................................................... 171 A.4.2 Simulation results ............................................................................................ 172 A.4.2.1 Accuracy of the 3D FE simulation ............................................................. 172 A.4.2.2 Distribution of structural capacitances........................................................ 173 A.5 Derivation of chain capacitance ........................................................................... 175 Appendix B ............................................................................................................................ 179 Power series approach for fast transient analysis ................................................................ 179 B.1 The power series approach to time-varying fields................................................ 179 B.2 Circuit modeling of a single-turn inductor ........................................................... 181 References .............................................................................................................................. 191 Summary ................................................................................................................................ 199 List of Publications ................................................................................................................ 203 Curriculum vitae ................................................................................................................... 205 Chapter 1 Introduction In this thesis, the parasitic related issues in the voltage multiplier module of the high voltage (HV) generator in medical X-ray machines are described. The focus is on the modeling of the parasitics at modular level and the subsequent study on improving the effect of the parasitics on the module and the generator. In this chapter, medical X-ray machines are introduced and this triggers the exploration of the high voltage generator and multiplier. After that, the motivation and objectives of the work are presented, followed by the structure of the thesis. 1.1 Background (a) (b) Fig.1–1: Examples of medical X-ray machines, (a) computed tomography (CT) machine; (b) mobile C-arm (Image source: Philips Healthcare) Medical X-ray machines intended for medical diagnosis are used during the treatment of patients. The X-rays produce medical images. The different modes of making images are referred to as modalities, such as computed tomography (CT), mammography and fluoroscopy 2 Introduction [Bus02]. Consequently, different machines were invented, such as the CT machine, the mammography machine and the fluoroscopy machine. Fig.1–1 shows examples of the medical machines. Medical X-ray machines are utilized for the imaging of different body parts, like bone, breast, teeth, as well as different forms of imaging, such as two dimensional (2D), three dimensional (3D) and movement monitoring. High voltage (HV) power supply (HV generator) for accelerating the electrons Anode X-rays eLow voltage (LV) power supply for cathode heating Power supplies Cathode High voltage cable X-ray tube Fig.1–2: Schematic representation of main power supplies for X-ray tubes in medical X-ray machines To generate X-rays, two basic power supplies are required, the low voltage (LV) and the high voltage (HV) direct current (DC) power supplies. Fig.1–2 shows how they are connected to the X-ray tube. The LV power generates a current of several amperes in the cathode filament of the X-ray tube, heating it up to emit the electrons, which spread as a cloud around the cathode. The HV power supplies high voltage, ranging from 20 kilovolt (kV) to 160 kV across the anode and the cathode to establish a strong electric field to accelerate the electrons [Sob02]. The electrons gain sufficient energy through the acceleration and collide with the anode material, generating X-rays. The flow of electrons forms the output current of the HV power supply, which is in the range from 10 to 5000 milliampere (mA) [Sob02]. This HV power supply is also named the HV generation in many publications [Tay32][Bel05]. The shorter phrase HV generator is used in this thesis. To make the machine compact, the HV generator is required to have a small volume. Its circuit topology has been developing for almost a century with the continuous improvement of power switches. They developed from mechanical switches in the early stage of 20 century [Tay32], to low frequency semiconductor power devices in the middle of 20 century [Ras01], such as Chapter 1 3 the thyristor, then to high frequency semiconductor power devices since the 1980s , such as IGBTs and MOSFETs. Thanks to the rapid development of the HF HV semiconductor power devices, the state-of-the-art topology can cause the HV generator to operate at a switching frequency of around hundreds of kilohertz (kHz) [Cav03]. The high switching frequency and usage of HV devices significantly reduce the volume of the HV generator compared to that in the early equipment. In the next section, the state-of-the-art circuit configuration of the HV generator is introduced and two methods to reduce volume are described. 1.2 Volume reduction of the generator In this section, the state-of-the-art circuit configuration of the HV generator is presented, which gives insight into how the switching frequency and power devices influence the volume. The HV multiplier is a key component and consumes much volume. Thus, after the introduction of the HV generator as a system, description focuses on the HV multiplier. The parasitics of the multiplier is the main topic of the research. Fig.1–3: Typical circuit configuration of today’s HV generator The HV generator in medical X-ray machines is a device that supplies regulated, HV, DC power to the X-ray tube. Today’s HV generator is typically a high frequency switched mode power supply, which operates in the tens of kHz range. The output voltage of the generator can be as high as 160kV. The main power circuit of the HV generator consists of a DC-AC inverter, a step-up transformer and a rectifier, as shown in Fig.1–3. The DC input is obtained by rectifying the 3 phase AC from the electrical grid. The inverter inverts the DC input to a high frequency AC output at the primary side of the transformer. The transformer steps up the low 4 Introduction AC voltage to a high value. Then, the AC voltage is rectified to a DC output to power the Xray tube. The function of the feedback control circuit is to make the output precise, stable and adjustable. The passive components and the rectifier are the main contributors to the volume of the HV generator. The main passive components are the inductor, capacitor and the transformer. Of these the HV transformer is the largest because of the space that is required for the isolation. By increasing the switching frequency of the converter, the value and size of the passive components can be reduced [Per09]. Most HV generators have a moderate volume because the switching frequency is high. Some researchers have reported the feasibility of the generator with a switching frequency over a hundred kHz, which means that it is possible to reduce the system size further [Lue11] [Cav03]. Fig.1–4: A typical HV tank in the HV generator Besides the passive components, the rectifier is the other major contributor to the volume of the HV generator. The rectifier is typically a voltage multiplier circuit in the HV generator, such as the Cockcroft Walton circuit [Coc32], multiplying a moderately high AC voltage from the transformer to the final high DC voltage in the range 20kV to 160kV. The turn ratio of the transformer can be reduced by utilizing the multiplier compared to the normal bridge rectifier. The parasitics and cost of the transformer can be reduced in turn. The multiplier circuit comprises capacitors and diodes. It is usually assembled in a tank together with the transformer because of the high voltage they have. The tank is grounded for safety in the X-ray machine and filled with insulation oil for higher electrical breakdown voltage. Fig.1–4 shows an example of the HV tank from Philips. It can be seen that the HV multiplier module fills the biggest part of the tank. .Besides the capacitors, diodes also contribute to the volume because a Chapter 1 5 large number of diodes are required to block high voltage. For example, a HV generator with output voltage rating of 150kV can have 960 1kV Si diodes [Lue11]. Sufficient space should be available around the diodes to avoid electrical breakdown of the insulation oil and to dissipate heat. One efficient way to o reduce the volume caused by the diodes, is to use diodes with high breakdown voltage while leading to low individual losses. This can lead to a reduced number of didoes, which decreases the volume of the HV tank. The silicon carbide (SiC) diode, a wide bandgap device, is well suited to the multiplier. Benefiting from their larger critical electric field, sufficiently high carrier mobility and high thermal conductivity, SiC based devices offer ultra high voltage blocking capability and low conduction and switching losses [Mat05]. Due to these properties, SiC diodes should be a better candidate in HV applications. Using 4.5kV SiC diodes, the number of diodes in the HV multiplier can be reduced by four compared to popular commercial 1kV Si diodes. Correspondingly, the volume of the multiplier module with SiC diodes can be reduced to a quarter of the volume of a Si diode unit. In addition, the SiC diode has a faster switching transient than a Si diode, which can reduce the switching losses. Consequently, the generator can operate at a higher frequency for given losses. Thus, it is possible to increase the switching frequency of the generator with the application of a SiC diode, which can lead to a further reduction of the volume of the multiplier module. Volume Parasitics frequency SiC Fig.1–5: The two approaches and the problem of volume reduction in the multiplier module In conclusion, the HV tank in the generator is responsible for the biggest part of the volume. It is feasible to reduce the volume of the tank by increasing the switching frequency and by applying high voltage power devices like SiC diodes. Fig.1–5 shows the relations of the two 6 Introduction approaches and the volume reduction. However, parasitic related problems arise, which are introduced in the next section. 1.3 Problem definition When the volume of the HV generator becomes small and the switching frequency becomes high, parasitic elements may become important to the system operation [Dai96]. The reduced volume usually leads to the reduction of the distance between the metals as well as to reducing the loop of the circuit layout. Consequently, the parasitic capacitances become larger, although the inductances may become smaller. The increased time derivative of voltage or current (dv/dt or di/dt) leads to a higher current in parasitic capacitances or a larger voltage across parasitic inductances. This makes the parasitics more significant in circuit design. In the generator, the parasitics in the primary side of the transformer are still small compared to the circuit components, such as the resonant capacitor or inductor. Thus, they don’t have a significant effect on the circuit operation. The transformer in Fig.1–3 usually has large turn ratio in order to achieve a large voltage gain. The parasitic capacitance in the secondary side windings, which is also named as self-capacitance [Dal07], is comparable to the circuit components when they are referred to the primary side, and heavily influence the circuit operation. However, their significant effects have been extensively noticed, well analyzed and utilized in previous work [Dal07] [Bie08]. In the last bulky part, namely the HV multiplier module, the parasitic capacitances are not as large as those in the transformer mentioned earlier. However, as the volume shrinks and the switching frequency rises, the parasitic capacitances can become larger and play a role in the circuit steady operation. Besides, the parasitic inductance can also influence the circuit transient operation as the tube arcs [Bel05]. The parasitic issues in the multiplier module are not well documented and investigated, leading to the following questions: How much does the parasitic capacitance influence the circuit steady operation? Usually, the inverter in the HV generator employs a resonant topology [Mar08]. The resonant components, such as the capacitor and inductor, determine the resonant frequency of the generator, which further determines characteristics of the circuit. If the switching frequency of the generator is increased, the value of resonant components can become low enough to be comparable to parasitic capacitances in the multiplier module. In this case, the parasitic capacitances become relevant to the circuit operation and can influence the circuit Chapter 1 7 characteristics. It is crucial to have a model of parasitic capacitances in the multiplier module and to take this into account in circuit design. However, until now, the role or the modeling of the parasitic capacitances in the operation of the generator is not mentioned in literature. How can the electric field strength be contained? Another issue is the strong spatial electric fields inside the module. Due to the high voltage, the strength of the electric field can be so high as to cause breakdown of the insulation oil. As the module becomes smaller than before, the field potentially becomes stronger. It is crucial to know the distribution of the strength of the field in the module and to reduce it as much as possible to avoid the breakdown. The spatial electric field can be expressed as a function of parasitic capacitances, thus the distribution and reduction is parasitic related as well. How can the transient behavior be modeled? During the operational life of an X-ray tube, the possibility of arcing inside the tube increases due to the deposition of tungsten [Bel05]. The arcing leads to short circuit to the output of the HV multiplier and can induce abrupt current pulses in the multiplier circuit, which induces a fast transient EM field in the module. The fast current pulses may result in voltage overshoot in the multiplier and the resultant breakdown of components. To perform the circuit analysis the values of the parasitics should be determined. On the one hand, because the maximum frequency in the bandwidth of the EM field is above quasi-static range, a high-order circuit model is required for accurate circuit analysis. On the other hand, if the frequency is still lower than full-wave range, a continuous model is not necessary. Most approaches of circuit modeling of the parasitics are either for quasi-static field or full-wave field. Thus, a novel approach for the modeling the parasitics in the intermediate frequency range is needed for development. 1.4 Objectives and approaches Because of the problems listed above, the researcher had three objectives when doing this research, namely to determine the influences of the parasitic capacitances on the steady-state circuit operations, to contain the electric field strength in the module, and to model the parasitics in the case of a fast transient EM field. The objectives can be divided into two aspects, which are listed as follows: In steady operation: 8 Introduction • The role of the parasitic capacitances in the circuit operation of the HV generator should be determined. • The complete model of parasitic capacitances in the multiplier module should be determined. • A solution to reduce the electric field in the multiplier module to avoid breakdown of the insulation oil should be determined. In transient operation: • A simple approach for the circuit modeling of the parasitics in the intermediate frequency range should be determined. • High-order circuit model of the parasitics in the multiplier module should be developed in case of the fast transient EM field. The following approaches are adopted in order to achieve the aforementioned objectives: In steady operation: • The role of the parasitic capacitances is determined by the steady-state circuit analysis of the HV generator. • The parasitic capacitances in the multiplier module are obtained through 3D finite element (FE) field simulation. • The complete model is constructed by circuit reduction of the obtained parasitic capacitances. • The electric field distribution in the multiplier module is obtained through 3D FE field simulation. • A field shielding technique is proposed based on the expression of the electric field as a function of parasitic capacitances. In transient operation: • A power series approach is employed for the circuit modeling of the parasitics in the intermediate frequency range. 1.5 Thesis layout • In Chapter 2, the circuit topologies of the HV generators are reviewed. Firstly, the topologies for the overall resonant converter are reviewed. Then, the focus is on the Chapter 1 9 rectifier part of the resonant converter, namely the HV multiplier. After the review, a typical and popular topology for today’s HV generator is chosen as the example for the parasitic analysis in this thesis, which is the series parallel resonant converter (LCC) with symmetrical Cockcroft Walton (C.W.) multiplier. • In Chapters 3 and 4, the parasitic capacitances and electric field distribution in the multiplier module in circuit steady operation are investigated. • In Chapter 3, the parasitic capacitances in the multiplier are introduced. The role of the parasitic capacitances in steady circuit operation is introduced, followed by a presentation of the complete model of the parasitic capacitances. Next, an analytical analysis to the complete model is introduced, leading to guidelines for optimization of the parasitic capacitances. • In Chapter 4, the reduction of the electric field in the multiplier is discussed. Firstly, the distribution of the field strength is analyzed. The electric field can be expressed as a function containing parasitic capacitances. A simple shielding technique based on the expression is proposed to reduce the field. • In Chapter 5, a simple procedure to model the parasitics in the multiplier module in fast transient EM fields is introduced. There are two steps in this chapter. The first step is the theoretical development of a procedure for applying the power series approach in a continuous spectrum system. The second step is to apply the procedure to the multiplier module. • In Chapter 6, conclusions of the thesis and recommendations for future researches are given. 10 Introduction Chapter 2 Overview of circuit topologies of the HV generator As addressed in Chapter 1, the parasitics in the HV multiplier module can play a significant role in the circuit operation of the current HV generator. Before the investigation of the parasitics starts, the circuit operation of the current HV generator is introduced to clarify the possible influence of the parasitics. 2.1 Introduction In this chapter, the circuit topologies for the HV generator are reviewed. The state-of-the-art topology with a detailed introduction of its circuit operation is presented. The introduction of the circuit operation is divided into three parts due to the relatively complex operating principle of the generator. Firstly, the operation of the whole circuit, which is a resonant converter with a normal full-bridge rectifier, is introduced. After that, the introduction moves to the operation of the rectified voltage multiplier. In the end, the combination of the converter and the multiplier for steady and transient operation is introduced. 2.2 Evolution of the HV generator In this part, there is a brief introduction of three kinds of power circuits for the HV generator widely used in the last century. The HV generator supplies DC voltage pulses to the X-ray tube. The exposure time, which is the time of one pulse at the output, depends on the modalities. X-ray machines should produce high quality images of different parts of the body. The following are required if the HV generator is to supply high quality images [Bus02] [Kre90]: 1. The output DC voltage should be stable with a small as possible ripple. 12 Overview of circuit topologies of the HV generator 2. The output voltage and load should have wide adjustable ranges. 3. The output voltage should have a fast dynamic response with a small overshoot. The tolerance for the exposure time should be as small as possible. 4. The generator should have a small volume and weight with low cost. 5. The generator should have a long lifetime. High power Low frequency Electro-mechanical switches High power High frequency Power semiconductor switches Constant voltage generators High frequency generators Conventional generators 1910s Vacuum tube diodes 1960s 2010s Power semiconductor diodes Fig.2–1: Evolution of the HV generators driven by development of power switches In last century, there were mainly three kinds of power circuits for the HV generator, which are the conventional rectified circuit from single-pulse to 12-pulse, the constant voltage generator (also named the direct current generator [Kre90]) and the high frequency generator (frequency much higher than 60Hz). The first two were widely used in the early stage of last century but have seldom been manufactured in the last 30 years. The third type is the contemporary stateof-the-art configuration for the HV generator because of its superior performance. The main driving force of the change to the new type is the development of the fast power semiconductor switches, which emerged since 1960s and quickly developed to high power high frequency field in 1980s [Ras01]. The features of the three kinds of power circuit are briefly introduced in the following sections. 2.2.1 2.2.1.1 Early Stage Conventional generators Chapter 2 13 Auto transformer Exposure timer HV transformer Rectifier 220V line voltage X-ray tube Fig.2–2: Diagram of a single-phase full-wave rectified circuit for the HV generator Fig.2–2 shows the diagram of the power circuit for a conventional generator in a fairly early stage. It consists of an autotransformer, a switch device, a HV transformer and a bridge rectifier. No output capacitor is added as a filter. The possible reasons are high cost and volume of the capacitor that filters low frequency high voltage waves. Single-phase 220V line voltage from the grid is fed as the input. The adjustable high output voltage is achieved through the autotransformer and the HV transformer. This can be controlled through an autotransformer with motorized adjustment. However, such control mechanisms operate in the 100ms range, which can eliminate the rapid disturbance on the line voltage. The exposure time is controlled by the timer, which generates electronic signals to command the electro-mechanical switches. The response time of the control is in the range of tens of milliseconds, which prevents the generation of fast accurate output pulses [Kre90]. The full-wave rectifier can convert the sinusoidal waveform into a waveform with two pulses in a cycle [Ras01]. The single-phase two-pulse rectified circuit can be easily adjusted to different similar patterns, such as singlephase one-pulse, three-phase six-pulse and three-phase twelve-pulse [Bus02]. More pulses in a cycle at the output lead to higher delivery power and smaller voltage ripple, at the price of higher cost and larger volume of the circuit. Among the conventional generators, the threephase twelve-pulse rectified circuit gives the best performance, with maximum achievable power to 150kW and minimum output voltage ripple around 3%. The conventional generator was invented and widely used before the emergence of power semiconductor devices. At that time, besides the electro-mechanical switches, the vacuum tubes were the popular devices as the switches, such as tetrodes. Vacuum tubes like vacuum tube diodes were also used as rectifiers. Although vacuum tubes have fast switching process, they have several major limitations for high power applications, such as a relatively short life 14 Overview of circuit topologies of the HV generator time, maximum current in the order of several hundreds of mA, high cost and large volume. The limitations of the tube switches prevent the invention of generators with operating frequencies much higher than 60Hz, which were made possible by the emergence of the technology of power semiconductor switches and pulse width modulation (PWM). Moreover, the low operating frequency leads to a large volume of the passive components and large output voltage ripple. With the development of the power semiconductor switches, the conventional generators have been gradually replaced by new topologies that utilize the new switches. This generator has been almost abandoned since 1980s. 2.2.1.2 Constant voltage generators HV transformer electron tube Regulator Three phase power supply Uref X-ray tube Regulator electron tube HV control circuit Fig.2–3: Power circuit of a constant voltage generator [Kre90] A constant voltage generator provides nearly constant voltage over the X-ray tube with negligible ripple, as shown in Fig.2–3. It is an improved configuration for the three-phase conventional generator. The main difference is that the output voltage and exposure time are controlled at the secondary side through HV electron tubes. The autotransformer is neglected. The line voltage is fed as the input, boosted by the three-phase transformer and rectified into six or twelve pulses. Two HV electron tubes, which can be triode, tetrode or pentrode, are connected in series in the output loop. A comparator circuit is added to measure the difference between the output voltage and the set reference voltage and to adjust the grid electrodes (as the gate of the transistor) of the electron tubes. The close loop control ensures fast adjustment of the voltage magnitude and exposure time. This configuration allows extremely constant voltage at the output. The response time for this control method can be as fast as 20µs, which is superior compared to that of the conventional generator [Kre90]. Chapter 2 15 However, the advantage of this type is at the expense of expensive, bulky devices and operational cost. Besides, the operating frequency of the generator is still low. Currently, this method of control is only used in applications with a stringent requirement of constant voltage over the X-ray tube. 2.2.2 The contemporary high frequency generator Thanks to the invention of power semiconductor switches, especially the power transistors such as insulated gate bipolar transistors (IGBT) and metal-oxide-semiconductor field effect transistors (MOSFET), the HV generator changed from conventional low frequency circuits to high frequency topologies. The operating frequency of the generator is usually at tens of kHz, and can even rise to hundreds of kHz with state-of-the-art technologies [Cav06]. Inverter Three/single phase AC from the electrical grid AC HV transformer Rectifier DC AC DC DC AC AC DC X-ray tube HV generator Fig.2–4: Power circuit of a high frequency generator (modern type) Fig.2–4 shows the block diagram of the power circuit of a high frequency generator. As already introduced in Chapter 1, the high frequency generator is a switched mode DC-DC converter. The three or single-phase line voltage is rectified into a DC output, which feeds as the input of the HV generator. The generator consists of a HV transformer and a rectifier and an inverter that chops the DC into AC through fast power transistors. The high frequency of the AC voltage, which is rectified into DC output, leads to much reduced volume of the passive components and minimized voltage ripple at the output. Besides, it can lead to fast response time through control circuit, which is approximately hundreds of microseconds. The fast close loop control, which is not shown in the figure, ensures a stable output voltage that is immune to the disturbance on the line voltage or change of the tube current. Further, the output voltage and load can be regulated over a wide range without much effort. Compared to the constant voltage generators, the high frequency generators have relatively larger voltage ripple and slower response time. However, the cost, weight and volume of the 16 Overview of circuit topologies of the HV generator high frequency generators are significantly reduced. With state-of-the-art technologies, the volume is more than 80% less, and the weight is more than 75% less than those of the constant voltage generators [Kre90] [Lue11]. Since the 1980s, resonant topologies have been invented and widely used in switched mode DC-DC converters [Ran82][Ste85]. Compared to hard-switching topologies, resonant converters can realize soft switching, which means almost no losses are generated during the switching on or/and off transitions of the switches. The soft switching is usually in forms of zero voltage switching on (ZVS) or zero current switching off (ZCS). Due to the great reduction of the switching losses, resonant converters allow much higher switching frequency than hard-switching converters. The high switching frequency in turn reduces the volume of passive components in converters, which further leads to the much shrunk volume of converters. In addition, the parasitics often induce unexpected behaviors in hard-switching converters, which can cause problems such as low efficiency, electromagnetic interference (EMI). However, resonant converters can incorporate the parasitics as part of the circuit and utilize them to generate expected waveforms. This feature makes resonant topologies quite suitable in the applications where large parasitic elements appear, such as the HV generator. Due to the superior performance, resonant DC-DC converters have been widely used in the application of HV generators. In the next section, several popular resonant topologies will be reviewed in order to find the most suitable one for the HV generator. 2.3 Series parallel LCC resonant converter with capacitive output During the last 30 years, the only topologies for HV generators found in the literature are resonant DC-DC converters. A considerable number of topologies have been proposed, covering circuits from two-element resonance [Joh88] to four-element resonance [Zha00], and from single-level [Mar08] to multi-level converters [Wu99]. Among them, three topologies are widely used in practice and fundamental to all the others, these are series resonant converters (SRC), parallel resonant converters (PRC) and series-parallel LCC resonant converters (SPRCLCC, abbreviated as LCC). In this section, the pros and cons of these converters are briefly reviewed for the application of the HV generator and the best is selected for the following parasitic research. Chapter 2 2.3.1 17 Resonant topologies for the generator Resonant DC-DC converters have been extensively and thoroughly investigated in the last 30 years. Due to the main advantage, namely the reduced switching losses, there have been attempts to adapt them to any applications of power converting. The resonant converters are also utilized in the application of the HV generator. All the resonant converters contain a resonant tank, which can filter the high harmonics of the squared wave and consequently generate a sinusoidal voltage and current that achieve the soft switching of the transistors. Different tanks lead to different resonant converters. The most fundamental and widely used resonant converters for the HV generator are still SRC, PRC and LCC. These are briefly reviewed next to check the pros and cons for the HV generator application. The three resonant converters reviewed are equipped with a classic full-bridge inverters and rectifiers. 2.3.1.1 SRC + Ls Cs . . - Fig.2–5: Schematic diagram of SRC The steady state performance of SRC is well analyzed in [Ste88]. The main pros and cons of SRC regarding its use in applications of the HV generator are listed as follows. Advantages: • The current in the switches and resonant tank decreases as the load decreases. This feature leads to reduced conduction losses and other losses, which consequently results in good light load efficiency in applications with a wide load range, such as the HV generator. • A capacitive output filter is employed in the topology rather than an inductive filter. This feature is quite attractive in HV applications, because the output inductor can be very large, heavy and expensive due to high isolation requirements. Although in the circuit with capacitive output filter, large current ripple presents in the capacitor, 18 Overview of circuit topologies of the HV generator which leads high losses. However, in the HV generator, the output current is quite low, which eliminates the losses. Disadvantages: • The maximum voltage gain of SRC can only be 1. In the case of the HV generator, the high output voltage needs a large step-up voltage gain. The limited voltage gain of SRC places the burden of voltage-boosting on the transformer and the rectifier. The large turn-ratio of the HV transformer, which realizes a high voltage gain for boosting, is likely to lead to large parasitic inductance and capacitance as well as large volume and cost. • SRC has good voltage regulation at heavy load but a poor regulation at light load, particularly at no load. This feature prevents SRC from managing the wide load range of the HV generator. • SRC can incorporate the parasitic inductance of the transformer into the series resonant inductance Ls. However, the parasitic capacitance of the transformer cannot be utilized by SRC and can deteriorate the circuit behavior. 2.3.1.2 PRC Ls + Cp . . - (a) Ls + Cp . . - (b) Fig.2–6: Schematic diagram of PRC, (a) inductive output filter; (b) capacitive output filter Chapter 2 19 Normally, there are two types of PRC, the circuit with inductive output filters as shown in Fig.2–6 (a), and the circuit with capacitive output filters, as shown in Fig.2–6 (b). The steady state operations of the two types are well analyzed and compared in [Joh88]. With regard to the HV generator, the capacitive output filter is preferred. The reason has been mentioned in subsection 2.3.1.1. The capacitive PRC is capable of almost the same performance as the inductive PRC. The removal of the output inductor results in a reduced value of the resonant components with the same transistor and tank current, which in turn leads to smaller tank volume. Thus, the capacitive PRC is selected for application in the HV generator, rather than the other one. The pros and cons of the capacitive PRC are listed as follows. Advantages: • The voltage gain of PRC can be larger than 1, which is quite useful for the HV generator. • The parasitic inductance and capacitance of the HV transformer can both be incorporated into the resonant tank. • The output inductor is removed, which saves much volume and cost. . • PRC has a natural proof for output short circuit. The short circuit current is limited by the impedance of the resonant inductance Ls. This feature adds another advantage of PRC to the application of the HV generator, of which the output is sometimes shorted because of the arcing in the X-ray tube. Disadvantages: • PRC has good voltage regulation at light load but a poor regulation at heavy load. This feature prevents the SRC from managing the wide load range of the HV generator. • The current in switches and the resonant tank does not decrease with a decreased load. The feature leads to poor light efficiency of the PRC in the generator application with a wide load range. 20 Overview of circuit topologies of the HV generator 2.3.1.3 LCC Ls Cs + Cp - . . (a) Ls Cs + - Cp . . (b) Fig.2–7: Schematic diagram of LCC, (a) inductive output filter; (b) capacitive output filter The LCC is intended to combine the advantages of the SRC and the PRC and eliminate their disadvantages [Ste88, Bha91]. By good design, usually done with proper selection of the ratio of the capacitance Cs to Cp, the goal can be met. Similarly, the LCC also has two types of output filters, the inductive filter and capacitive filter. The capacitive LCC is likewise preferred in the HV generator, the characteristics of which are nearly the same as those of the inductive LCC, although the operating modes are different. The good combination of the best characteristics the SRC and the PRC makes the LCC the most suitable for the application of the HV generator, and indeed the LCC is widely used in practice for this purpose. The pros and cons of the LCC are listed below. Advantages: • The voltage gain of the LCC can be larger than 1, which is quite useful for the HV generator. • The parasitic inductance and capacitance of the HV transformer can both be incorporated into the resonant tank. • The output inductor is removed, which saves much volume and cost. Chapter 2 • 21 The current in the switches and resonant tank decreases as the load decreases, which ensures a good light load efficiency. • The LCC can eliminate the short circuit current easily by increasing the switching frequency above the series resonant frequency, which is 1/(LsCs)0.5. Actually, when the parallel resonant capacitance Cp is shorted the LCC works as a SRC. The price paid for the advantages of the LCC is a somewhat wider frequency range of operation. 2.3.2 Comparison of the topologies The characteristics of the SRC, PRC and LCC for the HV generator application are briefly reviewed. The pros and cons are summarized here for a clear comparison. Table 2–1: Comparison of the SRC, PRC and LCC for application of the HV generator SRC Capacitive PRC Capacitive LCC voltage gain maximum is 1 can be larger than 1 can be larger than 1 voltage regulation good at heavy load but poor at light load good at light load but poor at heavy load good in a wide load range parasitic utilization parasitic capacitance of the HV transformer parasitic capacitance and inductance of the HV transformer parasitic capacitance and inductance of the HV transformer Light load efficiency good poor good 2.3.3 Basic circuit operation of the LCC The circuit diagram of the LCC with capacitive full-bridge rectifier is shown in Fig.2–7 (b). The DC input and the full bridge switches can generate a square wave as the input of the resonant tank. By taking 50% duty cycle for the switches as an example, the circuit can be redrawn as in Fig.2–8. 22 Overview of circuit topologies of the HV generator iLs Ls Cs D1 irect A vCp 0 D2 . .+ + Cp - B Vo vrect N + Co D3 R D4 Fig.2–8: LCC with square wave as input The purpose of the resonant tank, which consists of Ls, Cs and Cp, is to suppress the harmonic elements of the input square wave, leaving the fundamental sinusoidal wave [Kaz95]. Usually, for the LCC, the current iLs in the resonant tank is approximately sinusoidal. The current will charge the capacitor Cp and the load respectively in a cycle. Usually the output capacitor Co can be assumed to be large enough, which results in a constant output voltage Vo in steady state. Ls Cs A + 0 Vo/N Cp - B (a) Ls Cs A Cp B (b) Chapter 2 23 Ls Cs A - 0 Cp B Vo/N + (c) Fig.2–9: Equivalent circuits of the LCC in different intervals, (a) when D1 and D4 conduct; (b) all diodes in the rectifier are blocked; (c) when D2 and D3 conduct Fig.2–9 shows the equivalent circuits of the LCC in different intervals in one cycle. They are the simplification of the rectifier, and depend on whether the diodes conduct or not. When the current iLs flows into the rectifier and charges the load, the capacitor Cp is clamped to the voltage Vo divided by the turn ratio of the transformer N. The polarity of the clamped voltage vcp is inversed in the two half cycles, as shown in Fig.2–9 (a) and (c). In the rest of the cycle when the rectifier is blocked, the capacitor Cp is charged or discharged between the positive and negative clamped voltage, as shown in Fig.2–9 (b). The LCC can run in three modes, based on which the circuit behaviors can be well analyzed by state-space method [Bha91]. vrect vrect(1) 0 irect 0 irect(1) Fig.2–10: Input voltage and current waveform of the rectifier and their fundamental elements Another simple way to analyze the LCC is fundamental frequency analysis. Fig.2–10 shows the input voltage and current of the rectifier. The rectifier is nonlinear due to the fact that it can be turned on and off. However, the rectifier can be replaced by a RC network if the 24 Overview of circuit topologies of the HV generator fundamental elements of the input voltage and current are taken into consideration. [Ive99]. There is a phase shift between the fundamental wave of the voltage vrect(1) and the current irect(1). That is the reason why a RC circuit is used to replace the rectifier rather than a pure AC resistor [Ste88]. By using the RC circuit, the LCC can be simplified as follows: Ls Cs vab(1) Cp Ceac Reac Equivalent RC circuit Fig.2–11: Equivalent circuit of the LCC with capacitive output by fundamental frequency analysis Based on the equivalent circuit, the voltage transfer function can be easily derived as well as other steady voltages and currents in the circuit[Ive99]. The voltage gain is shown in Fig.2–12. Fig.2–12: Voltage gain of LCC In the figure, fs is the switching frequency and fsr is the series resonant frequency, which is defined as 1/2π(LsCs)0.5. The LCC can work in two regions, which are below resonance and above resonance. When the switching frequency of the converter is below resonance, zerocurrent switching condition can be created for the power switches. In contrast, if the converter Chapter 2 25 works above resonance, zero-voltage switching (ZVS) condition can be created for the power switches. For power MOSFET, ZVS condition is preferred [Kaz95]. 2.4 Symmetrical Cockcroft-Walton (C.W.) voltage multiplier The rectified voltage multiplier is a type of rectifier, which converts the AC input to DC output with a boosted voltage level. In HV applications, there are a series of rectified voltage multipliers which were developed from the one invented by John Douglas Cockcroft and Ernest Thomas Sinton Walton in 1932 [Coc32]. With a stepping-up of the input voltage, the multiplier lightens the voltage-boosting burden of the HV transformer in the HV generator. Consequently, the turn ratio and voltage stresses of the transformer are reduced, which further reduces the volume and cost as well as parasitic elements of the transformer. As a result, the overall volume of the generator is expected to be reduced and the effect of the parasitics on the circuit operation is weakened. In this section, the principle of the rectified voltage multiplier is introduced, followed by a brief review of the different types of the C.W. multipliers. In the end, a circuit operation is introduced for the symmetrical C.W. multiplier, which is selected as an optimum topology among the multipliers. 2.4.1 The rectified voltage multiplier The principle of the rectified voltage multiplier is introduced by analyzing a one-stage C.W. voltage multiplier, which is also known as a voltage doubler. vac + vc1 AC vcc C1 2Vpk vin - D1 D2 + GND vco1 - vo Co1 Fig.2–13: Schematic diagram of a one-stage C.W. voltage multiplier Fig.2–13 shows the circuit of a one-stage C.W. voltage multiplier. It consists of one push-pull capacitor C1, also named a coupling/transfer/transition capacitor [Wei69][Lue07] [Kob10], one 26 Overview of circuit topologies of the HV generator output capacitor Co1, also named a smoothing capacitor and a pair of diodes. A sinusoidal voltage with peak value of Vpk is fed as the input. The output voltage vo is generated through the multiplier as a DC voltage of 2Vpk in steady state. 1st cycle 2nd cycle vco1 1.5kV vc1 vin 0 -1.5kV t0 t1 t2 t3 t4 t5 t6 t7 ~ Fig.2–14: Building up of the voltage in the one-stage C.W. voltage multiplier Fig.2–14 exhibits how the voltage is built up in the one-stage C.W. multiplier. The peak value of the input Vpk is set to 1kV and the two capacitors are set the same. The diodes are assumed ideal. The process is explained as follows, which can clarify the essential principle of the steady-state operation of the multiplier. In the 1st cycle: • t0-t1: In the beginning of the first positive half-cycle, the diode D1 has a forward voltage bias. The push-pull capacitor C1 is charged till its voltage vc1 reaches Vpk, as shown in Fig.2–15 (a). Then the diode D1 starts to be blocked and the charging of C1 stops. • t1-t2: In the first cycle, the initial voltage of Co1 is zero. Thus, as the input voltage vin decreases from the peak, the diode D2 has a forward bias. Charge flows through Co1, D2 and C1, as shown in Fig.2–15 (c). The capacitor Co1 is charged until its voltage vco1 reaches Vpk. At this moment, the capacitor C1 is discharged to zero. It seems that in this period, the charges are moved from the capacitor C1 to Co1. A similar charge movement can be observed in subsequent cycles, thus C1 is also named the push-pull, or transfer capacitor. At t2, the diode D2 starts to be blocked when the voltage vin decreases to the negative peak. Chapter 2 • 27 t2-t3: As the input voltage vin starts to increase, both diodes are blocked. In this period, the two capacitors are both not charged, as shown in Fig.2–15 (b). The voltage across them remains constant. + vc1 - + + C1 + vc1 C1 vcc vin vin - - + vco1 + vc1 C1 vin - Co1 (a) + Vo - + (b) vco1 - Co1 Vo (c) Fig.2–15: Equivalent circuits of the one-stage C.W. voltage multiplier in different intervals, (a) when the push-pull capacitor is charged; (b) when no capacitors are charged; (c) when the output capacitor is charged In the 2nd cycle: • t3-t4: In the beginning of the second positive half-cycle, the diode D1 again has an immediate forward bias because the voltage vc1 was zero before . The same as the period t0-t1, the capacitor C1 is charged to Vpk again when the voltage vin reaches Vpk as happened in the period to t1. • t4-t5: Because the capacitor Co1 has been charged to a certain level in the previous cycle, the diode D2 needs to wait for some time before it has a forward bias. In the 2nd cycle, the diode D2 starts to conduct when the input voltage vin decreases to zero. Thus, in this period, both diodes are blocked and the voltage on the capacitors remains unchanged. • t5-t6: The input voltage decreases to zero, and D2 starts to conduct. The capacitor Co1 begins to be charged again. As in the period t1-t2, the capacitor C1 is discharged and it seems that some charges are moved from C1 to Co1. However, the amount of moved charges decreases in each cycle in the building-up transition until the circuit runs steady. In this period, the amount is half that moved in period t1-t2. • t6-t7: As the input voltage vin reaches the negative peak again, both diodes are blocked and the voltage on the capacitors remains unchanged until the next positive half-cycle, which is not shown in Fig.2–14. 28 Overview of circuit topologies of the HV generator In the subsequent cycles, the capacitor C1 is charged to Vpk in the positive half-cycles, and the charges are moved to Co1 in the negative half-cycles. The voltage vco1 builds up and goes into steady state after several cycles. Then, the diodes are always blocked and the voltage on both capacitors remains constant. The steady voltage on C1 is Vpk and on C2 is 2Vpk. If load is added in parallel to the output capacitor Co1, voltage fluctuation presents on the output voltage vco1 in steady state, as shown in Fig.2–16. The voltage ripple δvco1 is caused by charge assumption in the load. In the positive half-cycles of the input voltage vin, the charges are moved to the push-pull capacitor C1. Meanwhile, the load absorbs energy from the output capacitor Co1, thus the charge and voltage on the capacitor decreases. In the negative halfcycles, once the diode D2 conducts, the charges are moved from the capacitor C1 to Co1, consequently the voltage vco1 increases. In total, the capacitor Co1 is charged and discharged in the whole cycle, resulting in voltage ripple. ∆ vco1 δ vco1 2Vpk vco1 Vpk vin -Vpk Fig.2–16: Output voltage waveform of the one-stage C.W. voltage multiplier in steady state Additionally voltage drop ∆vco1 appears as soon as load current is drawn from the multiplier. The output voltage will be lower than that in no-load condition. The voltage drop reflects the efficiency of energy conversion of the multiplier. Thus, the ratio between the real output voltage to the no-load voltage is defined as the efficiency of a multiplier. As mentioned before the output voltage of the HV generator is required to be stable with as low a ripple as possible. Consequently, the voltage drop and ripple are two important criteria for the performance of the multiplier. They are influenced by the capacitors, the operating frequency, the load and the stage amount as well as different topologies. In the next section, different multipliers will be compared on these two criteria to evaluate their performance. Chapter 2 2.4.2 29 Comparison of the voltage multipliers The rectified voltage multiplier was first invented and the specifications published by a Swiss physicist, Heinrich Greinacher, in 1920 and 1921 [Gre20][Gre21]. However, the discovery remained unnoticed until the publication by Cockcroft and Walton in 1932, which was widely quoted [Coc32]. After that, the circuit was widely called the C.W. multiplier. C1 C2 Cn AC vo GND Con Co2 Co1 (a) C1 C2 Cn AC vo Con GND Co1 Co2 GND Co(n-1) (b) C1 C2 Cn AC+ GND Co1 ACC1_1 Co2 C2_1 (c) Con Cn_1 vo 30 Overview of circuit topologies of the HV generator full-bridge rectifier C1 symmetrical C.W. multiplier C2 AC+ Cn GND Co1 Co0 AC- C1_1 Co2 C2_1 Con vo Cn_1 (d) Fig.2–17: C.W. voltage multiplier and its derivatives, (a) original C.W. voltage multiplier; (b) C.W. voltage multiplier with one output capacitor; (c) symmetrical C.W. voltage multiplier; (d) hybrid symmetrical C.W. voltage multiplier. Fig.2–17 (a) shows the original C.W. multiplier. It was also known as the half-wave C.W. multiplier, because the output capacitors are charged once per cycle. It is a cascade of the unit multiplier that was shown in the last subsection. The operating principle the multistage multiplier is similar to that of the single stage multiplier. The output voltage of the C.W. multiplier is 2nstVpk in no-load condition, in which nst is the stage amount of the multiplier. As load is added the voltage drops and ripple appears on the output voltage Vo. Many researchers have investigated the mathematical formulas for the voltage drop and ripple caused by the resistive load current [Coc32], [Wei69]. Different researchers made different assumptions, which led to different formulas [Wei69]. Regarding the application of HV generators in medical X-ray machine, in which the stage amount is usually lower than 5, the following assumptions are valid [Wei69], [Kob10]. • The total charge flowing in i stage is i times smaller than that flowing in the first stage. • The charging time of the push-pull and output capacitors is much shorter than the period of the cycle. • The load resistor across the output and GND can be regarded as nst resistors respectively connected in parallel to each output capacitor. Based on the three assumptions, [Coc32] and [Bou40] present the formulas for voltage drop and ripple, which are shown in Table B–1. In the early stage, some authors [Eve53] [Wei69] Chapter 2 31 also mentioned the voltage drop and ripple caused by the junction capacitance of the diodes. However, currently, the effective junction capacitance of diodes per chain is usually hundreds of times smaller than the push-pull and output capacitors, which hardly influences the voltage drop and ripple [Eve53]. Besides, some researchers investigated the optimum value for the push-pull and output capacitors to minimize the voltage drop and ripple in specific applications [Bel04] [Kob10]. It can be seen that when nmst is smaller than 5, the different allocations of the capacitors don’t lead to big difference in the voltage drop and ripple [Kob10]. After the invention of the original C.W. multiplier, many modifications were made to the circuit to improve its performance, mainly decreasing the voltage drop and ripple. Fig.2–17 also shows three other typical derivatives of the original multiplier. Fig.2–17 (b) was found and analyzed efficiently in [Bru71]. The voltage drop is much decreased compared to that in the original multiplier, however, the output capacitor Con should stand 2nst higher voltage than the other output capacitors. Fig.2–17 (c) shows the symmetrical C.W. multiplier, which was proposed by [Hei55]. Another researcher [Rei65] addressed the symmetrical C.W. multiplier and compared it to the original one. A center-tapped transformer is required to feed two sinusoidal voltages that are out of phase by 180° to the multiplier. The symmetrical C.W. multiplier is also known as the full-wave multiplier, because the input can charge the output capacitors twice per cycle. The voltage drop and ripple can be much decreased compared to the original multiplier at a price of almost twice the component amount. However, the current capability of the components in the symmetrical C.W. multiplier is just half of that in the original one. Thus, in total, the symmetrical multiplier shows better performance than the original one, and consequently it is widely applied in the HV generators. Recently, some researchers proposed a modified symmetrical C.W. multiplier, as shown in Fig.2–17 (d). It is named the hybrid symmetrical C.W. voltage multiplier because it consists of a full-bridge rectifier cascaded with the symmetrical multiplier [Iqb14]. By this topology, the voltage drop can be slightly improved and the center-tapped transformer can be replaced by a normal transformer, which may decrease the complexity of manufacture. Table B–1 compares the original C.W. multiplier and the two symmetrical multipliers. The push-pull and output capacitors have the same value C. The operating frequency of the input voltage is f and the load current is Io. 32 Overview of circuit topologies of the HV generator Table 2–2: Comparison of the voltage multipliers no-load voltage gain voltage drop ∆vo voltage ripple δvo C.W multiplier 2nstVpk Io F1 (nst ) fC I o nst (nst + 1) fC 2 Symmetrical C.W. multiplier 2nstVpk Io F2 (nst ) fC I o nst fC 2 Hybrid symmetrical C.W. multiplier 2nstVpk Io F3 (nst ) fC I o nst fC 2 2 3 1 2 1 nst + nst − nst 3 2 6 1 3 1 2 1 F2 (nst ) = nst + nst + nst 6 4 3 1 3 1 2 1 F3 (nst ) = nst − nst + nst 6 4 3 F1 (nst ) = Due to the good performance of the symmetrical C.W. multiplier, it is state-of-the-art topology used as rectifier in the HV generator. The steady-state circuit operation of the symmetrical multiplier will be introduced in next section. 2.4.3 Circuit operation The steady circuit operation of the symmetrical multiplier is presented. - vo Co1 D1_1 D2_1 Co2 D3_1 D4_1 ~ + D4 ~ vac- D3 ~ . D2 D1 -vo 4Vpk∆voδvo ~ . . C2 - vac+ + C1 vac- Vpk 0 vac+ -Vpk C2_1 C1_1 t1 (a) t2 t3 t4 (b) Fig.2–18: A symmetrical two-stage C.W. voltage multiplier and its main waveforms, (a) the circuit diagram; (b) input voltage vac+, vac- and output voltage Vo Chapter 2 33 Fig.2–18 (a) shows the circuit diagram of a symmetrical two-stage C.W. voltage multiplier, which can be regarded as two C.W. multipliers connected in parallel. It consists of two-column push-pull capacitors C1, C2, C1_1 and C2_1, and one-column output capacitors Co1 and Co2. Four pairs of diodes connect the push-pull and output capacitors as charge ladders. The anti-phase sinusoidal input voltage vac+, vac- are shown in Fig.2–18 (b) as well as the output voltage vo. The peak voltage of the inputs is set as 1kV. All components are assumed as ideal in the following analysis. C1 . . C2 D3 D1 . Co1 Co2 D2_1 C2_1 C1_1 (a) C1 C2 . . . Co1 Co2 C2_1 C1_1 (b) D4_1 34 Overview of circuit topologies of the HV generator C1 . C2 . D2 . Co1 D1_1 D4 Co2 D3_1 C2_1 C1_1 (c) Fig.2–19: Equivalent circuits of the symmetrical C.W. voltage multiplier in different intervals, (a) interval t1-t2; (b) interval t2-t3; (c) interval t3-t4; The principle of the operation is similar to that of C.W. voltage multiplier. If no load is added, the voltage on C1 and C1_1 are Vpk and the voltages on the other capacitors are 2Vpk. However, there are voltage drop and ripple on each capacitor as load is added. Their equations are shown in Table B–1. Thus, as the inputs vac+, vac- swing to certain levels between zero and Vpk, such as time t1 in Fig.2–18 (b), the diodes D1, D3, D2_1, D4_1 are forward biased and start to conduct. In practice, they don’t conduct simultaneously due to the voltage drop and ripples. The diodes at higher stages conduct earlier than those at lower stages In this case, the sequence of conduction of diodes is D4_1, D3, D2_1 and D1. The time difference of conduction decreases if the voltage ripple and drop decrease. Here, it is neglected. After t1, the voltage sources charge the pushpull capacitors C1 and C2, which are prepared for the charging of the output capacitors Co1 and Co2 in the next half cycle. Meanwhile, the charges move from the other two push-pull capacitors C1_1 and C2_1, which accumulated charges in the previous half cycle, to the output capacitors Co1 and Co2. This process ends as the diodes D1, D3, D2_1, D4_1 are blocked when the input voltages reach their peaks. The instant is t2. The equivalent circuit during t1 and t2 is shown in Fig.2–19 (a). After t2, all diodes are blocked and the output capacitors charge the load, thus the voltages across them decrease. This process ends when the input voltages swing to the opposite of the values enabling the conduction of diodes D1, D3, D2_1, D4_1 in the previous half cycle. The time instant is t3. After that, the other four diodes D2, D4, D1_1, D3_1 conduct. The behaviors of the Chapter 2 35 push-pull capacitors are inversed as those in t1-t2 and the output capacitors are charged again. The equivalent circuit in t3-t4 is shown in Fig.2–19 (c). 2.5 LCC with symmetrical C.W. voltage multiplier In this section, the steady-state and transient circuit behaviors of the LCC with a two-stage symmetrical multiplier are discussed. This discussion is based on knowledge of the basic principles of the LCC with a capacitive full-bridge rectifier and voltage multipliers. 2.5.1 Steady-state operation C1 + irect + icp B Cp - vCp . . . vcc2+ D2 D1 D3 D4 vo vCo1 Co1 D1_1 vac- - A Cs + Ls VC1 vac+ N C2 vcc1+ C1_1 vcc1- D2_1 C2_1 Co2 D3_1 D4_1 vcc2- Fig.2–20: LCC with a two-stage symmetrical multiplier Fig.2–20 shows the circuit diagram of the LCC with a two-stage symmetrical multiplier. It is taken as an example for analysis of the steady state operations. The LCC with symmetrical multiplier with more stages operates on the same principle. It is crucial to emphasize that the components in the multiplier, such as the capacitor or diode, usually consist of many discrete components connected in series in practice due to the high voltage. The role of components has been introduced in previous sections. The parallel resonant capacitance Cp, which is at the primary side of the transformer in Fig.2–20, can also be put on the secondary side. The capacitances of C1 and C1_1 are twice those of the other capacitors for equal voltage distribution across each discrete capacitor and lower voltage ripple [Bel04]. The voltage drop and ripple on the push-pull and output capacitors are neglected in the following analysis. 36 Overview of circuit topologies of the HV generator 1 Vpk 2 1 2 vac+ vcc1+ 0 -Vpk -2Vpk vCo1 vcc2+ vo -4Vpk Vpk vacvcc1- 0 -Vpk -2Vpk vCo1 vcc2vo -4Vpk iCp irect t1 t2 t3 t4 t5 Fig.2–21: Steady-state waveforms of the LCC. Number 1 represents the conductive intervals and number 2 represents non-conductive intervals Fig.2–21 shows the steady-state waveforms. One cycle of operation of the multiplier can be divided into two intervals. One is when the diode conducts, which is called the conductive interval. The other cycle takes place when all the diodes are blocked, and is called a nonconductive interval. • Conductive intervals Basically, the input voltages of the multiplier vac+, vac- are a kind of squared waves. They are 180° phase shifted. Their amplitude is Vpk. As they swing to the peaks, such as when time is t1, the diodes D2, D4, D1_1, D3_1 conduct, which can be observed from the voltage waveforms. Consequently, the input voltages are clamped to Vpk due to the constant voltage across the capacitors. Current flows into the multiplier, as indicated by irect in Fig.2–21. The current accumulates charges on C1 and C2 and transfer charges from C1_1 and C2_1 to the output capacitors Co1 and Co2. Analogously, at time t3 in the other half cycle, the voltage vac+, vacswings to the opposite peaks respectively, and the other four diodes D1, D3, D2_1, D4_1 conduct. Chapter 2 37 Again, the input voltages are clamped to Vpk. From t1 to t2, or t3 to t4, the diodes in the multiplier conduct, thus, the intervals are called conductive intervals. • Non-conductive intervals When the currents in the multiplier swing to zero in the conductive intervals, the diodes are naturally switched off, such as at time t2 in the figure. At that moment, the input voltages are not ready to turn on the other four diodes. The power on the load is maintained by the output capacitors. The whole multiplier is isolated with the resonant tank. The parallel resonant capacitance Cp is charged and the voltage vCp increases until the input voltages of the multiplier reach the opposite peaks at time t3. During this interval, no diodes in the multiplier conduct, thus it is called a non-conductive interval. The same interval can be found from t4 to t5. Cs Ls A + 0 Cp - B Vpk/N or -Vpk/N (a) Cs Ls A Cp B (b) Fig.2–22: Equivalent circuits in different intervals in one cycle, (a) in conductive intervals; (b) in non-conductive intervals From the above analysis, the LCC can be simplified as the equivalent circuits shown in Fig.2– 22 in conductive and non-conductive intervals respectively. The full-bridge input can be simplified as squared voltage source, as the operation of the switches is not the concern in this 38 Overview of circuit topologies of the HV generator thesis. The characteristics of the LCC with multiplier can also be analyzed by the state-space method or fundamental frequency analysis [Li 07][Ren07][Ren08]. The important relations in the multiplier, which will be used in this thesis, are listed as: = VC1 V= Vpk C1_1 (2.1) V= VC2= V= V= 2Vpk C2 _1 Co1 Co2 (2.2) vo = −4Vpk (2.3) where Vc1 signifies the voltage across the capacitor C1, as shown in Fig.2–20. The voltages across other capacitors have the same polarity as Vc1 and similar notations. However, in reality, there are parasitic capacitances and inductances in the multiplier. For the HV multiplier, the current is usually below 1A, and the output voltage can vary from tens of kilovolt to hundreds of kilo voltage. Consequently, the parasitic inductance will not play a significant role in the steady-state operation in hundred kHz. However, the parasitic capacitance can. The parasitic capacitances in the multiplier do not only include the junction capacitances of the diodes [Du 10] but also include the parasitic capacitances between the structures of the multiplier, such as component package, layout and the module construction. Due to the high voltage property, many diodes and capacitors can be connected in series in the multiplier. This can lead to a large area of packages as well as connecting conductors. Thus, the parasitic capacitance caused by the structure can be quite relevant to the circuit operation, especially when the switching frequency of the system becomes high due to the employment of SiC diodes. It is crucial to investigate the influence of the parasitic capacitances in the steadystate circuit operation, which will be discussed in Chapter 3. 2.5.2 Transient behaviors as the output shorted Over time, X-ray tubes have a tendency to arc-over [Bel05]. The arc-over is due to the dielectric breakdown of residual gases in the tube, which can be caused by the high voltage on the deposit of tungsten on the interior surface of the tube. Normally the X-ray tube can be modeled as a large resistor. However, the arc-over changes the large resistor that models the Xray as the load of the HV generator into a very small resistor. Consequently, it leads to shortcircuit in the X-ray tube [Bey06]. Chapter 2 39 HV cable HV generator X-ray tube Fig.2–23: Block diagram of the output connection of the HV generator As the load of the HV generator, namely the X-ray tube, is shorted, large abrupt discharging current can be induced in the circuit without transient protections [Res99] [Bey06] [Bel05]. The large short-circuit current may generate huge losses as well as heat and damage components immediately. Besides, the current is usually in the form of steep pulses with a minimum rise time around nanoseconds. The spectrum of such pulses can have bandwidths in the upper megahertz (MHz) range [Pau05]. The resultant EMI induced by such pulses is in this frequency range, which can cause radiated EMI problems in the electronic devices nearby [Gon13]. Usually a HV cable connects the output of the generator and the X-ray tube, as shown in Fig.2– 23. The cable acts as a transmission line. Thus, short output of the cable can reflect energy back and provoke voltage spikes at the generator end of the HV cable [Bel05]. The high voltage output from the generator and the voltage spikes may oscillate, which can invert the polarity of the generator output. It is possible that the voltage spikes and oscillations can damage electric components in the equipment. Thus, for most practical HV generators, specific circuits are designed for the transient protections. A number of methods have been used for limiting arcing. In short, the principle of these methods is either to insert an inductance [Res99] [Bela92] [Fur94] or a resistance [Bey06] or both [Bel05] in the main discharging loop, which consists of the output capacitors of the generator, the HV cable and the X-ray tube. The inductance can prolong the rise time of the current pulses, which leaves a time margin for the control circuits. The resistance can limit the current peak and damp the oscillation. Each method has its own pros and cons. There are many issues associated with the arcing. In this thesis, the focus is on establishing an appropriate lumped circuit model for the parasitics in the fast transient EM environment. This will be addressed in Chapter 6. In the next section, the basic circuit behaviors in the transient to be introduced as background. 40 Overview of circuit topologies of the HV generator iLs Cs Ls C1 vac+ irect+ . . A 0 CTS vcc1+ D2 D1 Rdp Co1 . B iD2 iD1 vo1 iCo1 CTS RL iD2_1 iD1_1 irectvac- io D2_1 D1_1 t=t1 vo vcc1- C1_1 Fig.2–24: One-stage symmetrical C.W. voltage multiplier for transient analysis Fig.2–24 shows the circuit diagram for the transient analysis. Only the simplified one-stage multiplier is analyzed in order to show the principle. A damping resistor of 150Ω is added as protection for the arcing. Only one diode is added in a leg. The junction capacitance is not shown. The other components are the same as those introduced in sub-section 2.5.1. The parasitics in the multiplier module and the HV cable are not considered. Their effects will be briefly addressed later. The circuit operates in the steady state before short circuit takes place at time t1. t1 t2 t3 t1 t2 t3 6kV 1kV vac+ 80A vac- 60A -4kV vcc1+ -9kV vcc1- -14kV -1 20A vo vo1 -0.5 io 40A 0 t (µs) (a) 0.5 1 0 -1 iCo1 -0.5 0 t (µs) (b) 0.5 1 Chapter 2 41 t1 t2 t3 t1 t2 t3 80A -8A 60A iLs -12A 40A 20A 0 -1 iD1 iD1_1 -0.5 iD2 -16A iD2_1 0 0.5 t (µs) -20A -1 1 -0.5 (c) 0 t (µs) 0.5 1 (d) Fig.2–25: Transient waveforms in the multiplier after arc-over occurs, (a) voltages; (b) currents in main discharging branch; (c) currents in diode chains; (d) current at the primary side Fig.2–25 shows the transient waveforms in the multiplier. The time t1 is set at 0 in the figures. It can be seen that the output voltage vo jumps from -12kV to 0 at time 0 µs. This shorting of the output causes subsequent transient behaviors. The transient period can be divided into 3 intervals according the waveforms. The equivalent circuits in the transient intervals are shown as below. Co1 - Rdp vo1 + io (a) iLs . CTS . + - iD2 Co1 iCo1 - . C1 vac+ CTS vac- (b) + vo1 io Rdp 42 Overview of circuit topologies of the HV generator iLs . CTS . + - iD2 Co1 iCo1 + - . C1 vac+ CTS io Rdp iD2_1 C1_1 - vac- vo1 + (c) Fig.2–26: Equivalent circuits in the transient discharging period, (a) transient interval 1; (b) transient interval 2; (c) transient interval 3 • Transient interval 1, t1~t2: In this interval, the four diodes are blocked. There are steady-state currents flowing in the diodes through the junction capacitances. They are too small to observe in the waveforms. As the output is shorted, a discharging loop is formed consisting of the output capacitors Co1 and the damping resistor Rdp, as shown in Fig.2–26 (a). In this ideal RC discharging circuit, there is an abrupt current peak at time t1. Then the current decreases as a single-side exponential function with time constant Co1Rdp [Kul10]. Meanwhile the voltage vo1 decreases in the same way. The other currents and voltages in the multiplier remain the same as their counterparts in the steady state. • Transient interval 2, t2~t3: When the voltage vo1 decreases so as to be equal to the voltage vcc1+, the diode D2 conducts. Then another RC discharging loop is present, which consists of the damping resistor Rdp, the push-pull capacitor C1, the stray capacitance of the transformer CTS and the secondary winding of the transformer. Consequently, there is another discharging current iD2 flowing in the loop. The equivalent circuit is shown in Fig.2–26 (b). The capacitors C1 and CTS are discharged and the associated voltages, such as vcc1+, decrease rapidly. • Transient interval 3, after t3: Chapter 2 43 As the voltage vo1 decreases so as to be equal to the voltage vcc1-, the diode D2_1 conducts. Then, another RC discharging loop is present, which consists of the lower side components compared to those in the transient interval 2. The discharging current iD2_1 flows through the diode D2_1. In this interval, there are three discharging loops in the multiplier. The discharge period stops after some time, which is dependent on the effective capacitance in the discharging loops and the damping resistor. In the transient period, the diodes D1 and D1_1 are blocked, thus there are no transient currents flowing through the two diodes. Besides, the transient currents flow only in the secondary side because of the well grounding [Zha95]. There is no obvious current peaks in primary current iLs, as shown in Fig.2–25 (d). It can be seen that there are many current pulses in the multiplier in the transient period because of RC discharging. In fact, there is inductance in the discharging loop. The parasitic inductance can be the result of the discrete capacitors or the cable. As a result, the multiplier can be simplified as the RLC discharging circuit in the transient [Zha95], which is shown below. Lpa + Co1 vCo1 - Rdp io Fig.2–27: Equivalent circuit in the transient interval 1 if parasitic inductance is considered In such a RLC discharging circuit, the current will reach the peak with a rise time tr, which is determined by the values of all the components in the circuit [Kul10]. In fact, the rise time can be nanoseconds, which can add high frequency harmonics compared to the pure single-side exponential current. The bandwidth of such a pulse can enter upper MHz range, in which the minimum wavelength of resultant EM fields is approaching the physical dimensions of the multiplier module. In a high frequency environment, the parasitics in the multiplier module, including that in the discrete components and the structural parasitics, will have a stronger influence in the circuit behaviors compared to that in the steady state. However, before investigating the influence, the circuit model of the parasitics should be known. In such a high frequency range, the low-order circuit model can be too inaccurate for circuit analysis. A high - 44 Overview of circuit topologies of the HV generator order circuit model is necessary to develop the transient analysis. This circuit modelling in the fast transient will be discussed in Chapter 5. 2.6 Conclusion In this chapter, there is a review of the popular circuit topologies of the HV generator in medical X-ray machines. The LCC with symmetrical C.W. voltage multiplier is chosen as the most advantageous one in the state-of-the-art technologies for the HV generators. The steadystate operations and transient behaviors of the LCC are introduced. It is shown that the parasitic capacitances in the multiplier module can play a significant role in the steady-state operations if the switching frequency becomes high. Fast current pulses are present in the transient in the multiplier, which requires high-order circuit model of the parasitics for accurate circuit analysis. In the following chapters, the parasitcs in the multiplier will be investigated at modular level in the circuit that operates both in the steady state and short-circuit transient period. Chapter 3 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier As mentioned in Chapter 2, the parasitic capacitances in the HV multiplier can have significant influence on the steady-state operations of the generator. This chapter will elaborate the parasitic capacitances completely in the multiplier at a modular level for the first time. 3.1 Introduction The previous chapter addresses the state-of-the-art circuit of the HV generator, which is LCC with symmetrical Cockcroft Walton multiplier, and its basic behavior in medical X-ray machines. The circuit is popular, on one side, because the parasitics of the HV transformer, such as stray capacitance, can be incorporated into the basic circuit in the resonant converter [Joh88]. On the other hand, the HV transformer with high turn ratio usually has significant stray capacitance, which can limit the switching frequency of the converter and further the miniaturization of the power converter. Nevertheless, the multiplier with a transformer with lower turn ratio is an attractive alternative to the HV transformer with high turn ratio and a bridge rectifier, which can reduce the stray capacitance of the transformer as well as its voltage stresses [Sun00]. Fig.3–1 (a) shows a two-stage symmetrical Cockcroft Walton multiplier, which is taken as a typical example for the analysis in this chapter. 46 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier (a) (b) Fig.3–1: (a) LCC with two-stage symmetrical Cockcroft Walton multiplier; (b) Possible composition of the parallel resonant capacitance Cp Usually people only consider utilizing the stray capacitance of the transformer and using an added capacitor to create the required parallel resonant capacitance Cp [Joh88][Sun00]. The parallel resonant capacitance Cp should be carefully designed to be larger than the stray capacitance. The missing part can be complemented by the added capacitor. Otherwise, the system frequency and relevant components have to be re-designed to achieve optimized circuit performance. However, the parasitic capacitances in the multiplier are part of the capacitance Cp as well, as shown in Fig.3–1 (b). In the HV generator of X-ray machines, the multiplier is usually assembled as a multiplier module that consists of several circuit boards for the main Chapter 3 47 electrical function, insulation oil and a grounded container. In this thesis, the parasitic capacitances in the multiplier are the equivalent of those in the multiplier module, and consist of not only the junction capacitances of diodes, but also the parasitic capacitances associated with the spatial structure of the module. As the switching frequency of the HV generator keeps increasing, the resonant elements tend to be much smaller than before when they are much larger than the parasitics. The value of the resonant elements is currently approaching that of the parasitics. Experience has shown that the equivalent parasitic capacitance can be around 50pF for a 4-stage multiplier at high output voltage above 100kV [Wan12]. Such a capacitance takes 50% to 100% of the parallel resonant capacitance Cp shown in Table 3–1. Thereby the equivalent parasitic capacitance can lead to the converter having a larger parallel resonant capacitance than the designed one, which can dramatically change the system’s behavior. Table 3–1: Designed parallel resonant capacitance Cp at secondary side in various HV LCC applications References Input (kV) Output (kV) Turn ratio of transformer N Parallel resonant frequency (kHz) Parallel resonant capacitance Cp (pF) [Joh88] 0.012 6 ~ 10 113 *1 85 100 [Kim95] 0.44 20~140 490 28 33 [Cav03] 0.325 23 ~ 62.5 15 *2 350 53 [Mar08] 0.56 50~150 67 32 132 *1. LCC contains a multiplier with voltage gain of 4; *2. LCC contains a multiplier with voltage gain of 2; The others contain the full bridge rectifier. On the one hand, the designer should be aware of the equivalent parasitic capacitance of the multiplier and know its magnitude. He should ensure that the designed capacitance Cp has sufficient margin for all the parasitics. On the other hand, the equivalent parasitic capacitance should be minimized, without further limiting the miniaturization of the power converter. In this chapter, the concept of equivalent parasitic capacitance of the multiplier and its minimization are proposed. In the beginning, the role of the parasitic capacitances in the circuit behavior is addressed. After the clarification of the role, the full network of the parasitic capacitances is presented and simplified, resulting in the complete capacitance model. Then, the equivalent parasitic capacitance of the multiplier is presented, based on the complete model. 48 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier After that, the analytical expression of the equivalent parasitic capacitance is conducted. The dependence of the equivalent capacitance on different parameters, such as different groups of parasitic capacitances and the number of diodes per chain, is addressed. In addition, it will be shown that the parasitic capacitances lead to uneven voltage sharing of series connected diodes. This uneven sharing may lead to the breakdown of diodes. The effect of the breakdown of the diodes on the equivalent capacitance is also investigated. The complete capacitance model and the analysis of the equivalent parasitic capacitance are validated by measurements. In the end, guidelines are concluded and a design procedure is proposed for the minimization of the equivalent parasitic capacitance. 3.2 Role of the parasitic capacitances In this section, the reason why the parasitic capacitances in the multiplier are part of the parallel resonant capacitance Cp of the LCC is explained .Then, a lumped capacitance, which is called the equivalent parasitic capacitance of the multiplier is proposed to replace the parasitic capacitances. AC side + . . Cpa Cpa vac+ DC side _ . Cpa Cpa AC side Multiplier Fig.3–2: Schematic representation of representative parasitic capacitances Cpa in the multiplier Fig.3–2 illustrates some parasitic capacitances in the multiplier as an example. In the analysis of the role of parasitic capacitances, the capacitance Cp is not drawn in the circuit diagram, which is considered to consist of only the parasitic capacitances in the multiplier. In the circuit, the parasitic capacitances exist between any two electric nodes in the multiplier module. The parasitic capacitances can be the junction capacitances of diodes. In addition, what is often ignored is that there are large number of parasitic capacitances relevant to the spatial structure of the module that include the component package, layout and the module construction. Chapter 3 49 Two assumptions are made in the following analysis: 1. Except for the junction capacitance and the breakdown voltage, all the other properties of the diodes are assumed ideal. 2. The push-pull capacitors and output capacitors are assumed large enough to have constant voltage. non-conductive intervals vac+ conductive intervals Fig.3–3: Waveform of the input voltage vac+ of the multiplier in the steady state In the steady state, the multiplier with parasitic capacitances also enters two types of intervals, namely the conductive intervals and non-conductive intervals, as shown in Fig.3–3, which is the same as the ideal circuit without parasitic capacitances. The criteria for entering the two intervals are the same. The steady operation of the multiplier and the derivation of the equivalent circuit are described shortly here and elaborated in the Appendix A.1. + + .v . ac+ _ . + _ . . . + Cem _ Cem _ Multiplier Multiplier (a) vac+ (b) Fig.3–4: Role of parasitic capacitances in different intervals, (a) equivalent circuit of the multiplier in conductive intervals; (b) equivalent circuit of the multiplier in non-conductive intervals 50 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier In the conductive intervals, half of the diode chains in the multiplier conduct and half of them are blocked. As a result, the input of the multiplier, such as vac+ in Fig.3–4(a), is clamped to the voltage of the relatively large push-pull and output capacitors, which can be considered to have constant voltage. Thus, the multiplier can be replaced by equivalent constant voltage sources. The parasitic capacitances in the multiplier are between nodes with a clamped constant voltage, so they are in parallel with the voltage sources. As a result, they have no effect on the operation of the converter in these intervals. In the non-conductive intervals, all the diodes in the multiplier are blocked. The multiplier consists of the push-pull and output capacitors, the parasitic capacitances and the resistive load. The input voltage of the multiplier swings between its peak values, as shown in Fig.3–3, and induces time-varying voltage and current in the multiplier. The push-pull and output capacitors have constant voltage, thus they can still be replaced by constant voltage sources. The load is in parallel with the large output capacitors and accordingly clamped to the constant voltage, consequently it can be removed in circuit reduction of the multiplier with time-varying excitation. Thus, the multiplier, which becomes a capacitance network containing constant voltage sources in this interval, can be replaced with a lumped equivalent capacitance. Fig.3–4 (b) shows the lumped capacitance Cem, which is called an equivalent parasitic capacitance of the multiplier in this thesis. From the analysis, it is clear that the capacitance Cem has the same role as the parallel resonant capacitance, which determines the parallel resonant frequency of the system. In practice, the capacitance Cem is part of the parallel resonant capacitance Cp, which also contains the stray capacitance of the transformer and an added capacitor. On the one hand, the capacitance Cp should be designed to be larger than the sum of the capacitance Cem and the stray capacitance of the transformer. The missing capacitance can easily be added by a discrete capacitor. On the other hand, the equivalent parasitic capacitance should be minimized, without putting limiting the miniaturization of the power converter. 3.3 Full network of the parasitic capacitances In this section, the full network of parasitic capacitances in the multiplier module in the nonconductive interval is presented. The full network is obtained through 3D finite element (FE) field simulation. A complete model of parasitic capacitances is created after the simplification of the full network, which offers the possibility of obtaining the analytical expression of the equivalent capacitance Cem. Chapter 3 3.3.1 51 Overview of the parasitic capacitances There are parasitic capacitances between any two conductive objects in the multiplier module. Conductive objects appear in any locations in the module. These are listed in Table 3–2. Table 3–2: Conductive objects in the multiplier module Components Conductive objects Push-pull, output capacitors Electrodes, leads, soldering pads Diodes Electrodes, soldering pads Grounded container; electric connections push-pull capacitors AC+ AC+ Cpa Diode chain Cpa pa DC in DC out C DC in Cdpp Cj(v) DC out AC - AC- Cpa Cppg Cdg Cpa Ground (a) (b) Fig.3–5: Parasitic capacitances in the multiplier module, (a) 3D schematic representatives of the parasitic capacitances; (b) groups of parasitic capacitances. Fig.3–5 (a) shows several parasitic capacitances in a module of the multiplier as an example. In reality, there are quite a large number of parasitic capacitances in the module. The parasitic capacitances can be obtained through 3D FE field simulation. The 3D model of the module as well as the results is shown in Appendix A.4. To obtain the complete model of the parasitic capacitances, the capacitance network that contains the parasitic capacitances, push-pull and output capacitors needs simplification. The reasoning of the simplification is shown in Appendix A.2. The simplification removes many insignificant capacitances and combines parallel capacitances, so the network can be greatly simplified. Fig.3–5 (b) shows the four groups of 52 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier parasitic capacitances after the simplification. Table 3–3 defines the four groups of the parasitic capacitances. The ground denotes the grounded container and the output capacitors. Table 3–3: The four groups of the parasitic capacitances Group of parasitic capacitances Cj(v) Cstru junction capacitance of the diode Cdg the structural capacitance between the diodes and the ground Cdpp the structural capacitance between the diodes and the push-pull capacitors Cppg the structural capacitance between the push-pull capacitors and the ground The four groups of parasitic capacitances are quite general with regard to different spatial configurations of the multiplier module, and different modules lead to different values. In general, the four groups of parasitic capacitances can be divided into two types. One is voltagedependent capacitance and the other one is linear capacitance. 1. The junction capacitance of the diode is voltage dependent. 2. With the exception of the junction capacitance of diodes, the other parasitic capacitances are linear. They are relevant to the electric field outside electric components and are determined by the size of the conductive objects and the structure of the module. Thus, they are called structural capacitances, which are denoted as Cstru in Table 3–3. In this thesis, the definition of dynamic capacitance is utilized to describe the voltagedependent capacitance. The definition is introduced in Appendix A.3. Chapter 3 3.3.2 53 The complete model AC side Cppg Cdg Cj(v) Cdpp DC side Fig.3–6: The complete model of the parasitic capacitances of half a stage in the multiplier Fig.3–6 illustrates the complete model of the parasitic capacitances of half a stage in the symmetrical Cockcroft Walton multiplier. The push-pull and output capacitors are replaced by constant voltage sources. The model is quite general for any spatial configuration of the multiplier module. In the case of the symmetrical multiplier, the other half stage usually has the symmetrical capacitance network. The different stages in the multiplier have the identical network structures and values as structural capacitances due to the same spatial configuration for different stages. Consequently, this model can easily be extended to the multiplier with more stages. Based on the 3D finite element (FE) electromagnetic (EM) field simulation, each group of parasitic capacitances can be assumed to have the same value, which is acceptable for many spatial configurations of the multiplier module. 3.4 Equivalent parasitic capacitance of the multiplier In this section, the equivalent parasitic capacitance of the multiplier based on the complete model is expressed. It is in general the sum of two capacitances. The two capacitances include a linear capacitance and a voltage-dependent capacitance. 54 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier Cppgt CDcht AC side DC side Fig.3–7: The capacitance Cppgt and the total chain capacitance CDcht Table 3–4: Equivalent parasitic capacitances Cppgt total capacitance of the parasitic capacitances Cppg CDcht total capacitance of the equivalent capacitance of the parasitic capacitances associated with the diode chains. It is called total chain capacitance in the following content. Cem equivalent parasitic capacitance of the multiplier module The complete model can be regarded as two capacitance networks in parallel, as shown in Fig.3–7. One network contains the structural capacitances Cppg between the push-pull capacitors in different stages and the ground. The equivalent capacitance of this network is capacitance Cppgt, which is equal to the sum of the capacitances Cppg. The other network contains the parasitic capacitances associated with the diodes in the multiplier, namely the structural capacitances Cdpp, Cdg and the voltage dependent capacitance Cj. The constant voltage sources are also included in the network to maintain the voltage on the capacitance Cj in the circuit reduction for the equivalent capacitance of the network CDcht, which is called a total chain capacitance. Consequently, the capacitance CDcht is dependent on voltage and is determined by several parameters of the network, which are the three groups of parasitic capacitances and the number of diodes per chain nd. The general expression for the capacitance CDcht is given as follows: CDcht =f (Cdpp , Cdg , C j (v), nd ) (3.1) Chapter 3 55 AC side AC side Cppgt Cem(v) CDcht(v) DC side DC side Fig.3–8: The equivalent parasitic capacitance of the multiplier Cem Consequently, the full network can be simplified, as shown in Fig.3–8, and the equivalent parasitic capacitance Cem can be expressed as follows: Cem= (v) Cppgt + CDcht (v) (3.2) Equation (3.2) holds for the multiplier with any stages. In this chapter, the analysis of the equivalent parasitic capacitance is focused on the two-stage multiplier shown at the beginning. To minimize the equivalent parasitic capacitance Cem, according to Equation (3.2), the two parts should be decreased respectively. 1. The linear capacitance Cppgt To decrease the capacitance Cppgt, it is clear that the structural capacitance Cppg should be decreased. 2. The voltage-dependent capacitance CDcht The total chain capacitance CDcht can be influenced by the four parameters of the network, as shown in Equation (3.1), in an unobvious way. It is not easy to see how to decrease the capacitance CDcht. Consequently, the following analysis focuses on obtaining the analytical expression of the total chain capacitance CDcht that helps to clarify its minimization. 3.5 Analytical expression of the total chain capacitance As addressed in the last section, the total chain capacitance CDcht is the key part of the equivalent parasitic capacitance of the multiplier. It is influenced by the four parameters of the capacitance network in an unobvious way, resulting in a vague idea of its minimization. In this section, the analytical expression of the total chain capacitance is presented, and its derivation elaborated, which helps to clarify the minimization. 56 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier Chain capacitance + Vpk _ CDch2(v) iDch2 vac+ 2Vpk _ + + irect+ vDch2 _ vDch3 CDch3(v) vDch4 + Vpk iDch1 + _ AC side CDch1(v) + vDch1 _ 3.5.1 + -Vpk _ iDch4 Dch1 + _ _ 2Vpk Dch2 Stage 1 + iDch3 DC side CDch4(v) _ 2Vpk Stage 2 Fig.3–9: The division of the total chain capacitance CDcht for the two-stage multiplier The total chain capacitance CDcht is composed of chain capacitance, which is the equivalent capacitance of the parasitic capacitances relevant to a diode chain. Fig.3–9 shows the four chain capacitances, CDch1, CDch2, CDch3, CDch4, in the two-stage multiplier. CDch1 signifies the chain capacitance of the diode chain Dch1. The other notations have a meaning analogous to CDch1. In steady state, the input voltage of the multiplier vac+, which swings from –Vpk to Vpk, can generate time-varying voltage across the chains, such as vDch1, charging or discharging the chain capacitances in the non-conductive intervals of the multiplier. The chain voltage has the following relations: vDch1 = vDch3 = Vpk − vac+ vDch2 = vDch4 = Vpk + vac+ (3.3) Before the analysis of equivalent capacitances, two conditions are listed below to judge whether two capacitance networks that consist of voltage dependent capacitances are identical: 1. The network structures and the linear capacitances should be the same. 2. The voltage on the voltage-dependent capacitances should be the same at a given port voltage. Each stage in the multiplier has the same structure of capacitance network and structural capacitances. Besides, as aforementioned, the voltage behaviour in each stage is also the same in steady operation, which means the corresponding junction capacitances in each stage are the same at a given voltage vac+. Consequently, the capacitance network is identical at any given voltage vac+ in each stage. The chain capacitances have the relations below: Chapter 3 57 CDch1 = (vDch1 ) CDch3 = (vDch3 ) CDch1 (Vpk − vac+ ) CDch= CDch= CDch 2 (Vpk + vac+ ) 2 (vDch2 ) 4 (vDch4 ) (3.4) To obtain the equivalent capacitance for a network consisting of voltage-dependent capacitances and constant voltage sources, basic definitions of equivalence should be utilized. For the one-port network as shown in Fig.3–9, the voltage-current characteristics of the equivalent capacitance should be the same as that at the port of the network. The input current of the network irect+ is equal to: −iDch1 + iDch 2 − iDch3 + iDch 4 irect + = =2(−iDch1 + iDch 2 ) = 2(−CDch1 (vDch1 ) (3.5) dvDch1 dv + CDch 2 (vDch 2 ) Dch 2 ) dt dt For the equivalent capacitance CDcht, the current flowing through should be: irect + = CDcht (vac + ) dvac + dt (3.6) Thus: CDcht (vac + ) dvac + dv dv = 2(−CDch1 (vDch1 ) Dch1 + CDch 2 (vDch 2 ) Dch 2 ) dt dt dt (3.7) Based on Equation (3.7), the following can be obtained: CDcht (vac + ) 2(CDch1 (vDch1 ) + CDch 2 (vDch 2 )) = = 2(CDch1 (Vpk - vac + ) + CDch 2 (Vpk + vac + )) (3.8) The total chain capacitance CDcht is the sum of chain capacitances CDch1 and CDch2 timed by stage amount of the multiplier. There is a non-conductive interval in each half cycle of a cycle. The capacitance-voltage (C-V) curve of CDcht is not necessarily the same in the two intervals. The C-V curve of CDch1 or CDch2 can change in the two non-conductive intervals because the capacitance network of CDch1 or CDch2 can be different. The capacitances CDch1 and CDch2 will be discussed below to see whether CDcht will change in the two non-conductive intervals in a cycle. Fig.3–10 shows the intervals and capacitance networks for the diode chains Dch1 and Dch2 in a simple case. 58 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier charging discharging AC side + Vpk vac+ vDch2 -Vpk _ 2Vpk Cdpp CDch1(v) 0 DC side + 2Vpk 0 Dch2 Cdg DC side vDch2 vDch1 CDch2(v) vDch1 t1 t2 t3 t4 half cyclehalf cycle Dch1 _ Cdg Cdpp AC side Fig.3–10: An example of the capacitance networks for the diode chain Dch1 and Dch2, which consist of three diodes respectively In the non-conductive interval in the first half cycle, namely from t1-t2, the voltage vac+ increases from –Vpk to Vpk. Meanwhile the voltage vDch2 increases from 0 to 2Vpk and voltage vDch1 has inverted swing. With regard the chain Dch2, at t1, the conducting diodes are going to be blocked and the voltage on the junction capacitances is zero. As vDch2 increases, the junction capacitances are charged till vDch2 reaches 2Vpk. The chain Dch2 undergoes a charging transition during this interval. At t2, the diodes are in deep block state and the maximum blocking voltage on the junction capacitance will be conserved as the initial voltage on them at t3, namely the beginning of the non-conductive interval in the next half cycle. In the case of the chain Dch1, the deeply blocked diodes will be discharged at time t1. The initial voltage on the diodes is what is conserved at the end of the non-conductive interval in the previous half cycle, just like Dch2. From t1 to t2, the junction capacitances are discharged until vDch1 reaches 0. The chain Dch1undergoes a discharging transition during this interval. In the non-conductive interval in the second half cycle, namely from t3-t4, the junction capacitances in the chain Dch2 are discharged from the initial voltage conserved at t2. The Dch2 then undergoes a discharging transition. In contrast, the junction capacitances in the chain Dch1 are charged from 0. The Dch1 then undergoes a charging transition. In Fig.3–10, it can be seen that the diode chains Dch1 and Dch2 have inversed structures of capacitance networks. In the individual charging transitions, the junction capacitances in both chains Dch1 and Dch2 are charged from the initial voltage 0. Due to this inversed structure, the voltage along the chains Dch1 and Dch2 should also be inversed. Thus, if the capacitance Chapter 3 59 network of the chain Dch1, for example, is inversed by 180°, it becomes the same as the network of the chain Dch2. Thus, the chain capacitances CDch1 and CDch2 is the same at any given port voltage. Consequently, the C-V curves of capacitances CDch2 in t1-t2 and CDch1 in t3-t4 are the same. Further, the voltages on the junction capacitances in the chain Dch2 at t3 are the same as those in the chain Dch1 at t1. It means that the initial voltages on the junction capacitances in both chains are the same in the individual discharging transitions. Similar to that in the charging transitions, the capacitance network of Dch2 in t3-t4 is the same as that of Dch1 in t1-t2. Consequently, the C-V curves of capacitances CDch1 and CDch2 are the same in each discharging transition. In conclusion, for the complementary diode chains Dch1 and Dch2, the capacitance networks of the two chains are identical in the charging or discharging transitions, which further means that the C-V functions of the chain capacitances are the same. Thus, the total chain capacitance CDcht can be simplified as: CDcht (= vac+ ) 2(CDch 2 (Vpk − vac+ ) + CDch 2 (Vpk + vac+ )) (3.9) Now, the total chain capacitance CDcht can be expressed as the sum of one chain capacitance in the charging and discharging transitions in a whole cycle. Thus, even if the capacitance network of one chain changes in the two transitions, the capacitance CDcht will be the same. In the same way, it can be proved that the other half of the multiplier has the same capacitance network. As a result, the total chain capacitances are the same for the upper and lower half of the multiplier. 3.5.2 Chain capacitance without avalanche breakdown of diode The total chain capacitance CDcht can be expressed as a function that is only determined by one chain capacitance, such as the capacitance CDch2 that is shown in Equation (3.9). Thus, as long as the C-V function of the capacitance CDch2 is obtained, then the expression of the total chain capacitance CDcht can be obtained as well. Consequently, the derivation of the C-V function of the chain capacitance CDch2 will be described in this section. Due to the presence of the structural capacitances Cdpp and Cdg, the voltage on diodes along the chain Dch2 is unbalanced, which can cause avalanche breakdown to some diodes. The voltage imbalance will be analyzed and presented in the next sub-section. First, analysis of the 60 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier multiplier without avalanche breakdown is addressed. At the end, the chain capacitance for the circuit with the breakdown will be analyzed in sub-section 3.5.4. AC side node nd 2Vpk vDch2=Vch2 ik+1k vDch2=Vch1 indk 0 tVch1 tVch2 ikk-1 node k ik0 Cj(k) Cdpp DC side Cdg node 0 Fig.3–11: The model of parasitic capacitances for the diode chain Dch2 Fig.3–11 illustrates the capacitance network for the diode chain Dch2. As discussed in the last sub-section, the junction capacitances along the chain are charged and discharged respectively in each half cycle between zero and the maximum blocking voltage. In the charging and discharging transitions, the network structure remains the same, only with inverted current in each branch. Besides, the initial voltage along the chain of one transition is the final voltage distribution of the other one. Thus, the voltage behavior along the chain is inverted in the two transitions. It means that, at a given chain voltage, the voltage distribution on the junction capacitances is the same in both transitions. Consequently, the value of the junction capacitances is the same. Thus, the capacitance network remains the same in the two transitions and the chain capacitance CDch2 will be the same. In other words, the C-V curves of the chain capacitance CDch2 are exactly the same in the charging and discharging transitions. It is hard to derive the chain capacitance CDch2 by network transform. Here, a simple method is utilized to solve the problem from the angle of exchanged energy. The detailed derivation and the analytical expression of CDch2 are shown in Appendix A.5. Chapter 3 61 20 5 (pF) 1 0 0 15 2 4 v 6 Dch2 (kV) 8 10 12 C 5 0 -6 (v Dcht ac+ 10 Dcht 2 ,C Dch2 3 C C Dch2 (pF) 4 C (V -v pk -4 -2 Dch2 (a) ac+ v ) ac+ ) C (V +v pk 2 4 Dch2 0 (kV) ac+ ) 6 (b) Fig.3–12: For the multiplier without avalanche breakdown of diodes, (a) C-V curve of the chain capacitance CDch2 with vDch2 as the variable; (b) C-V curve of the total chain capacitance CDcht with vac+ as the variable Fig.3–12 (a) shows the C-V curve of the chain capacitance CDch2. As the chain voltage vDch2 rises, the junction capacitances along the chain Dch2 are charged. Accordingly, the capacitance CDch2 decreases because the junction capacitances decrease. As mentioned before, this C-V curve remains the same during the charging and discharging transitions, which does not happen if some diodes go into avalanche breakdown. Based on Equation (3.9), the total chain capacitance CDcht can be obtained by shifting and mirroring the C-V curve of the capacitance CDch2 along the x-axis. The C-V curve of the total chain capacitance CDcht is exhibited in Fig.3– 12 (b). 3.5.3 Unbalanced voltage distribution along chain The voltage across the diodes along the chain is not evenly distributed due to the presence of the structural capacitances Cdpp and Cdg. The unbalanced voltage can make some diodes in chain go into avalanche breakdown, which changes the capacitance network of the chain and accordingly changes the chain capacitance. The voltage imbalance is analyzed by taking the chain Dch2 as an example, which is shown in Fig.3–11. The other diode chains have the same unbalanced voltage. 62 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier AC side Cdg Cdpp DC side node k Cj(k+1) Cj(k) Fig.3–13: Charge flow along the diode chain in the charging transition When the chain voltage vDch2 is zero, the diodes in the chain conduct and the voltage across them is zero as well. As the voltage vDch2 increases, the diodes become blocked and their junction capacitances are charged. The charge flows from the AC side to the DC side. Due to the presence of the capacitances Cdpp and Cdg, the charge is not equally accumulated on each junction capacitance. Fig.3–13 shows the charge flow along the chain Dch2. Regarding the node k, the charge flowing through comes from two sources. One source of charge comes directly from the AC side, through the capacitance Cdpp and then to the node k. The other source comes from the junction capacitance Cj(k+1). After passing through the node k, the charge again splits into two outputs. One flows from the capacitance Cdg to the DC side, and the other flows to the junction capacitance Cj(k). According to the charge flow, the charge passing the capacitances Cj(k+1) and Cj(k) will be the same only if the charges passing the capacitances Cdpp and Cdg are equal to each other. However, that does not apply to all the nodes along the chain. Consequently, the structural capacitance Cdpp can add extra charge to the junction capacitance and the capacitance Cdg can absorb charge from the junction capacitance, which causes the unequally accumulated charge on the capacitance Cj. As a result, the voltage across the junction capacitance is not evenly distributed either. At the end of the charging transition, namely t2 as shown in Fig.3–10, the unbalanced voltage is conserved until the next half cycle when the chain is going to be discharged at time t3. In the discharging transition, the charge flows in an inverted direction in a similar way as shown in Fig.3–13 and in the end the voltage along the chain returns to zero. 63 normalized voltage across the diode Chapter 3 10 1 Schottky diode nd=12 Vpk=6kV Cdg=0.5pF,Cdpp=0 Cdg=0pF,Cdpp=0.5pF Cdg=0.2pF,Cdpp=0.2pF 0 10 10 -1 0 2 4 6 8 diode numbering 10 12 (a) normalized voltage across the diode 1 10 nd=12 nd=50 0 10 -1 10 0 Schottky diode Vpk=6kV Cdg=0.2pF Cdpp=0.2pF 10 20 30 diode numbering 40 50 (b) Fig.3–14: Voltage across the diodes along the diode chain Dch2, (a) the effect of different structural capacitances Cdpp and Cdg; (b) the effect of different number of diode per chain Fig.3–14 illustrates the voltage distribution along the diode chain Dch2 in several specific cases. The normal voltage is the average chain voltage that is the voltage vDch2 over the number of diodes per chain. Fig.3–14(a) shows that the voltage becomes more unbalanced if the difference between the structural capacitances Cdpp and Cdg grows larger. It is easy to understand based on the analysis above. The other highlight is that, if the values of the two capacitances are swapped, the voltage is similarly unbalanced. However, the “direction” of the voltage imbalance is inverted. If the capacitance Cdg is larger than the capacitance Cdpp, the diodes closer to the AC side are likely to have higher voltage. On the other hand, the diodes 64 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier closer to the DC side are subject to higher voltage. In addition, Fig.3–14(b) shows that the voltage becomes more unbalanced when the number of diodes increases. The reason is that more diodes lead to more structural capacitances, which can add or absorb more charge to the junction capacitance at the end of the chain. In practice, all the diodes in the multiplier are designed with the same voltage rating that is equal to the average chain voltage. Due to the unbalanced voltage distribution, the diodes that have higher voltage are more likely to go into avalanche breakdown. Avalanche diodes are chosen to handle the avalanche energy. The breakdown changes the capacitance network of the chain and therefore the chain capacitance. In the following sub-section, the effect of avalanche breakdown of the diode on the chain capacitance is addressed. 3.5.4 Chain capacitance with avalanche breakdown of diode In this section, the chain capacitance for the multiplier with avalanche breakdown of diodes is analyzed. The analysis is conducted by still taking the diode chain Dch2 as an example. The other chain capacitances have the same C-V function as the chain Dch2. AC side AC side node nd diode nd diode nd Cdg Cdpp node 0 DC side (a) DC side (b) Fig.3–15: The change of the capacitance network of the diode chain Dch2 caused by breakdown, (a) the network before breakdown occurs; (b) the network after breakdown occurs When the diode chain is being charged, the chain voltage vDch2 increases as the voltage across the junction capacitances keep rising. As mentioned before, if the structural capacitances Cdg and Cdpp are considered to be the same, the diodes at the two furthest ends of the chain will have highest voltage compared to the others. Once the voltage exceeds the breakdown voltage VBR of the diode, those diodes go into avalanche breakdown and the voltage across them is clamped to VBR. Then, if the chain voltage keeps increasing, more diodes at each end are likely Chapter 3 65 to go into breakdown, one by one along the chain until the chain voltage reaches the maximum blocked voltage 2Vpk. The breakdown of diode can change the structure of the capacitance network of the diode chain. Fig.3–15 illustrates the change when the two diodes at the furthest ends of the chain go into breakdown. Before the breakdown, the current flows through the junction capacitance and the network is exactly as has been analyzed in sub-section 3.5.2. However, after the breakdown, the current flows directly through the diodes and the voltage across the diodes is clamped to be constant. As a result, the diodes can be modeled as constant voltage sources, as shown in Fig.3–15 (b). The constant voltage sources will cut short the structural capacitances as well as the junction capacitances that are in parallel. Consequently, the breakdown leads to fewer junction capacitances in series and more structural capacitances directly connected across the chain compared to those in the normal network, which increases the chain capacitance. 10 C Dch2 (pF) charging transition 0 0 discharging transition Schottky diode Cdpp=0.2pF Cdg=0.2pF Vpk=18kV nd=50 10 20 vDch2(kV) 30 40 Fig.3–16: Different C-V curves of the chain capacitance CDch2 in charging and discharging transitions After breakdown occurs, the network consists of both capacitances and constant voltage sources. The chain capacitance is defined and solved in the same way as that in the case without the breakdown. Firstly, the voltage distribution along the chain is obtained based on Equation (A.15). Here, only the voltage on the electrical nodes that are not associated with the breakdown diodes are calculated. The voltage on the other nodes can easily be obtained according to the breakdown voltage VBR. After the voltage distribution has been obtained, the energy swing in the parasitic capacitances between any two instants can be obtained by the Equation (5.2). Besides, the breakdown diodes absorb energy as well. This part of energy 66 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier swing should also be included and can be calculated by multiplying the VBR by the integration of current that passes the breakdown diode over time. The C-V curve of the chain capacitance CDch2 in the charging transition is shown in Fig.3–16. The steps in the curve are caused by considering abrupt breakdown in the calculation. The figure highlights that the C-V curves of the capacitance CDch2 are different in the charging and discharging transitions, which is because of the different capacitance networks of the chain in the two transitions. The charging transition ends when the chain voltage vDch2 stops increasing and the unbalanced voltage across the junction capacitances will be conserved until the beginning of the discharging transition. The conserved unbalanced voltage serves as the initial voltage of the junction capacitances for the discharging. Once the voltage vDch2 decreases, breakdown disappears immediately and the capacitance network of the chain goes back to the structure that is shown in Fig.3–15(a). As the voltage vDch2 keeps decreasing, the diodes that underwent previous breakdowns go to conduction earlier than the others. Once the diodes conduct, they are shorted in the capacitance network, which is similar to the case when they go to breakdown. Analogous to what happens in the charging transition, the network changes from Fig.3–15(a) to Fig.3–15(b), only with the constant voltage sources replaced by short circuits. It can be seen that the networks of the chain are quite different at certain chain voltages in the charging and discharging transitions respectively. Consequently, the C-V curves of the chain capacitance are different in the two periods. The capacitance CDcht can be obtained by adding the two curves and will be shown in the next section. 3.6 Dependence of the total chain capacitance Based on the analytical expression of the total chain capacitance CDcht, the dependence of the capacitance on the four parameters that are the junction capacitance Cj, structural capacitances Cdpp, Cdg and the number of diodes per chain nd, will be presented in this section. The dependence on each parameter is separately elaborated, firstly for the multiplier without avalanche breakdown of diode. The effect on the dependence of the breakdown of the diodes is discussed in the last part. As addressed in the last section, the total chain capacitance CDcht has a very complex expression including the four parameters. Thus, it is impossible simply to see the dependence of the capacitance CDcht on each parameter. To obtain the dependence, each parameter is swept in a reasonable range, which is obtained based on 3D FE simulation, with the others fixed. Chapter 3 67 Table 3–5 exhibits the range. Although, in the following, the dependence is illustrated for specific cases, the principle holds in general. Table 3–5: The range of each parameter of the capacitance network for the analysis of the capacitance CDcht Parameter Range Junction capacitance of diode: Cj 1. SiC Schottky diode; Breakdown voltage (VBR): 4.5kV; Cj0=299pF, φbi=1.353V 2. SiC Schottky diode; Breakdown voltage (VBR): 1.2kV; Cj0=144pF, φbi=0.926V Structural capacitances Cdpp 0pF to 0.5pF Cdg 0pF to 0.5pF Number of diodes per chain: nd: 4 to 50 Voltage Voltage applied across the capacitance CDcht: vac+ -Vpk to Vpk (Vpk: 0.6kV to 18kV) The capacitance-voltage (C-V) characteristic of junction capacitance of diodes can usually be expressed by a function with three variables that are the capacitance at zero-bias voltage Cj0, the built-in potential φbi and the voltage applied. However, the Cj0 and φbi for each diode depend on the intrinsic character of the diode, such as the material of the semiconductor and the interior structure. As a result, it is impossible to find a general analytical expression for the junction capacitances for various diodes. Even if a general expression, such as that for Schottky diodes, is used, it will still take a big computational effort to sweep all the parameters in the expression, which is not necessary for obtaining the qualitative dependence of the capacitance CDcht. Thus, the swing of the junction capacitance is represented by junction capacitances of two specific diodes as shown in Table 3–5, in which one is relatively large and the other one is small. The SiC Schottky diode is selected as the representative diode because it holds a typical C-V curve for general junction capacitances of diodes. It is crucial to mention that some combinations of the parameters are not realistic in circuit design. For example, when the peak voltage of the cascade input is 0.6kV, nobody will use 50 68 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier diodes of 4.5kV connected in series. However, it is easy for mathematical analysis for the dependence by sweeping the parameters in certain range. By doing that, a complete picture of how the capacitance CDcht depends on each parameter can be obtained, which includes the situation in realistic circuit designs. 3.6.1 Dependence on the junction capacitance The junction capacitance is determined by both the properties of the diode and the voltage applied. Thus, the dependence of the capacitance CDcht on the junction capacitance is discussed in two parts. One is about how the voltage influences the capacitance CDcht, and the other part is about the influence of different diodes. • The influence of the voltage Equation (3.9) shows that the capacitance CDcht can be influenced by the input voltage vac+ and its peak value Vpk. In an ideal two-stage multiplier, the output voltage is equal to 4Vpk, thus Vpk can also reflect the output voltage level. In the following content, firstly the voltage dependence is observed with a given output voltage, and then the effect of different output voltage will be addressed. 40 Vpk=6kV 20 C Dcht (pF) 4.5kV SiC Schottky diode Cdpp=0.2pF Cdg=0.2pF 30 nd=12 10 0 -6 -4 -2 0 2 vac+ from -Vpk to +Vpk (kV) 4 6 Fig.3–17: The C-V curve for the total chain capacitance CDcht at a given output voltage of the multiplier Fig.3–17 exhibits the dependence of the capacitance CDcht on the multiplier input voltage vac+. The C-V curve resembles a parabola with an opening at the top. The parabola shape is created by the two inverted behaviors of the diode chains. When the voltage vac+ increases from –Vpk to Chapter 3 69 Vpk, as shown in Fig.3–10, the junction capacitances in half diode chains, such as Dch1, are discharged, leading to increasing chain capacitances. Meanwhile, the junction capacitances in the other half diode chains, such as Dch2, are charged, leading to decreasing chain capacitances. In total, the two inverted behaviors of the diode chains lead to the total chain capacitance CDcht firstly decreasing and then increasing at the end. 40 Vpk=6kV Vpk=18kV 20 C Dcht (pF) 30 Vpk=0.6kV 4.5kV SiC Schottky diode 10 C =0.2pF dpp Cdg=0.2pF n =12 0 d 10 0 -10 -20 vac+ from -Vpk to +Vpk (kV) 20 Fig.3–18: The capacitance CDcht at different output voltages of the multiplier Fig.3–18 exhibits how the output voltage of the multiplier influences the total chain capacitance CDcht. Firstly, the multiplier with higher output voltage has a wider input voltage swing because the input voltage vac+ swings from –Vpk to Vpk. Secondly, the multiplier with higher output voltage has a lower capacitance CDcht. Suppose that there are two multipliers with voltage Vpk1 and Vpk2 respectively, and Vpk1 is bigger than Vpk2. Then, the chain voltage for the multiplier with the voltage Vpk1, no matter whether that is Vpk1+vac+ or Vpk1-vac+, is always larger than that relevant to Vpk2. Consequently, according to Equation (3.9), the total chain capacitance CDcht(vac+|Vpk1) is always smaller than the capacitance CDcht(vac+|Vpk2), because the chain capacitance is inversely proportional to the chain voltage. • The influence of different diodes 70 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier CDcht (pF) 40 Cdpp=0.2pF Cdg=0.2pF 30 nd=12 Vpk=6kV 4.5kV diode 1.2kV diode 20 10 0 -6 -4 -2 0 2 vac+ from -Vpk to +Vpk (kV) 4 6 Fig.3–19: The effect of different diodes on the capacitance CDcht Fig.3–19 exhibits the effect of different diodes on the total chain capacitance CDcht at a given output voltage. It can be seen that the 4.5kV diode makes a larger capacitance CDcht than the 1.2kV diode does. The reason is that, in our case, the junction capacitance of the 4.5kV diode is larger than that of the 1.2kV diode at any voltage level. Moreover, because the chain capacitance is proportional to junction capacitance, a larger junction capacitance creates a larger chain capacitance, namely a larger total chain capacitance CDcht. It is worth mentioning that, in reality, the diode with higher breakdown voltage VBR does not necessarily have a larger junction capacitance at any voltage level than the diode with lower VBR. Consequently, the former does not necessarily create a larger capacitance CDcht than the latter does. 3.6.2 Dependence on the structural capacitance Fig.3–20 illustrates how the structural capacitances Cdpp, Cdg influence the total chain capacitance CDcht. From the figure, it can be observed that: 1. The total chain capacitance CDcht increases as any of the structural capacitances Cdpp, Cdg increase. 2. The two structural capacitances have a symmetrical effect on the total chain capacitance CDcht. Chapter 3 71 40 CDcht (pF) 4.5kV SiC Schottky diode n =12 30 d Vpk=18kV Cdg=0, Cdpp=0 Cdg=0, Cdpp=0.5pF Cdg=0.5pF, Cdpp=0pF Cdg=0.5pF, Cdpp=0.5pF 20 10 0 -20 -10 0 10 vac+ from -Vpk to +Vpk (kV) 20 Fig.3–20: Dependence of the total chain capacitance CDcht on the structural capacitances Cdg, Cdpp 3.6.3 Dependence on the number of diodes per chain nd 40 CDcht(0) (pF) 4.5kV SiC Schottky diode Cddp=1pF Vpk=6kV 30 V =0 ac+ Cdpp=0, Cdg=0 Cdpp=0.5pF, Cdg=0 Cdpp=0, Cdg=0.5pF Cdpp=0.2pF, Cdg=0.2pF Cdpp=0.5pF, Cdg=0.5pF 20 10 0 0 10 20 nd 30 40 50 Fig.3–21: Dependence of the total chain capacitance CDcht on the number nd Fig.3–21 exhibits the dependence of the total chain capacitance CDcht on the number of diodes per chain nd in the complete model. Each point in the figure represents the capacitance CDcht when the input voltage vac+ is zero. It can be observed that: 1. If any of the structural capacitances Cdpp and Cdg is zero, the total chain capacitance decreases fast in the beginning and slowly later as the number of diodes increases. 2. If both the structural capacitances Cdpp and Cdg are not zero, the total chain capacitance decreases firstly and then increases proportionally to the number nd. 72 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier The trend in the figure can be qualitatively explained. It is caused by two opposite effects of junction capacitance Cj and structural capacitances Cdpp and Cdg. As can be seen in the capacitance model shown in Fig.3–6, as more diodes are added to a chain, more relevant structural capacitances and junction capacitances are added. The added structural capacitances have the effect of increasing the total chain capacitance but the added junction capacitances have the effect on decreasing it. Usually the structural capacitances in the multiplier module are smaller than 0.5pF and junction capacitances of diodes whose breakdown voltage is above 1kV are larger than 1pF. Thus, when the number nd is sufficiently small, junction capacitances can dominate the total chain capacitance. The condition needed to approximately judge whether nd is sufficiently small can be expressed as follows: C j (v ) nd  nd Cdpp (or Cdg ) (3.10) which means: nd  C j (v ) Cdpp (3.11) Thus, in this case, added junction capacitance leads to a decrease of the capacitance CDcht. Once nd becomes large, the decreasing effect from the added junction capacitances is softened and the increasing effect from the added structural capacitances is enhanced. If one of the structural capacitances is zero, the two opposite effects compensate for each other, resulting in slight change of the capacitance CDcht. However, if both the structural capacitances are present, then the increasing effect is stronger than the decreasing effect, which leads to an increase in the capacitance CDcht. Once the number nd is large enough, many junction capacitances are connected in a series pattern and their effective capacitance can become very small. Meanwhile many structural capacitances are added up and dominate the capacitance CDcht. The condition for this case is opposite to that when nd is small, which can be expressed as following: nd  C j (v ) Cdpp (3.12) The dependence is significant. The HV multiplier with many diodes per chain can have large total chain capacitance and in turn the equivalent parasitic capacitance of the multiplier is also large. The structural capacitances make a big role in the whole. If they are ignored and only the junction capacitances of diodes are considered, this usually leads to the wrong impression that Chapter 3 73 the equivalent parasitic capacitance Cem is small because of the series connected junction capacitances. For example, for a two-stage multiplier with 72kV output, about 50 diodes of 1kV are required to be connected in series per chain. Usually the Si diode is used instead of the LV SiC diode in industry because of the low price. If the equivalent parasitic capacitance is assessed including only the junction capacitances, its value is just around several pico farad or even smaller. However, the equivalent parasitic capacitance should be around tens of pico farad because of the structural capacitances that are caused by the dense packages. An important guideline can be obtained based on the new dependence. To minimize the capacitance Cem for the multiplier with many diodes per chain, the spatial structure of the module needs to be carefully designed to minimize the structural capacitances. If the multiplier has a small amount of diodes per chain, like when HV SiC diode is applied, the structural capacitances play a small role in the capacitance Cem and the junction capacitances play a major role in the whole. Thus, priority should be given to choosing small junction capacitances for the minimization. 3.6.4 Effect of the breakdown of diodes The total chain capacitance CDcht for the multiplier is discussed above ignoring avalanche breakdown of the diodes. However, the breakdown can occur in the multiplier, especially when a large number of diodes per chain present. As pointed out in Section 3.5.4, the breakdown leads to less junction capacitance in series and more structural capacitances directly connected across the chain, compared to the normal network. This can increase the chain capacitance. Further, once diodes go into breakdown in the charging transition, they will conduct first in the next discharging transition, which changes the capacitance network similarly and also increases the chain capacitance. Fig.3–22 (a) exhibits the increased capacitance CDcht by the breakdown. 74 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier 40 VBR=1.2kV Breakdown ignored C Dcht (pF) 30 20 1.2kV SiC Schottky diode Cdpp=0.2pF 10 C =0.2pF dg Vpk=18kV nd=50 0 -20 -10 0 10 vac+ from -Vpk to +Vpk (kV) 20 (a) 40 C Dcht (pF) 30 20 18kV 1.2kV SiC Schottky diode, VBR=1.2kV C 10 dpp=0.2pF Cdg=0.2pF Vpk=18kV nd=50 0 -20 vac+ -18kV -10 0 10 vac+ from -Vpk to +Vpk (kV) 20 (b) Fig.3–22: Effect of breakdown, (a) the increasing of the total chain capacitance CDcht induced by the breakdown of diodes (abrupt breakdown considered); (b) the mirrored C-V curves for CDcht in two half cycles The C-V curve of the capacitance CDcht is unsymmetrical vs. the input voltage vac+ in the nonconductive interval in half cycle. However, in the other half cycle, the capacitance CDcht has a mirrored C-V curve, as shown in Fig.3–22 (b). Thus, in summary, in one cycle there is no net charge accumulated on the parasitic capacitances, which is mandatory for the steady operation of the circuit. Chapter 3 75 The breakdown of the diodes does not change the dependence of the capacitance CDcht on the four parameters. However, it can increase the average level of the capacitance CDcht. The more diodes go into avalanche breakdown, the higher the average level the capacitance CDcht will have compared to the capacitance obtained in the multiplier ignoring the breakdown. Thus, for the multiplier with many diodes per chain, not only can the structural capacitances make a relevant equivalent parasitic capacitance Cem, but the breakdown can also further increase the capacitance Cem. 3.7 Validation In this part, the complete model of the parasitic capacitances and the analysis of the equivalent parasitic capacitance Cem are verified. Fig.3–23: The demonstrator of a two-stage symmetrical Cockcroft Walton multiplier Fig.3–23 shows a two-stage symmetrical Cockcroft Walton multiplier. It has the same topology as that shown in Fig.3–2 except for the diode with inverted polarity, which can generate positive direct voltage output. It is a low-voltage (LV) test module of a four-stage cascade multiplier for 144kV DC output. The LV demonstrator has the same configuration as the fullscale module, but with the diode voltage rating scaled down. The LV demonstrator consists of 12 bare diodes per chain, which are the 1.2kV SiC diode as shown in Table 3–5. The equivalent parasitic capacitance Cem of the demonstrator is obtained by assembling the multiplier in a LCC converter with no load. In no-load condition, the diodes are always in blocked state when the circuit operates steadily and correspondingly the multiplier can be replaced by the equivalent capacitance Cem,. In principle, a sinusoidal voltage vac+ is generated 76 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier in the converter as the input of the cascade multiplier that will charge and discharge the parasitic capacitances in the multiplier. Fig.3–24: Measurement platform Fig.3–24 shows the whole measurement platform. The LV multiplier is laid in a grounded container. In a real HV generator for medical X-ray machine, the container usually has insulation oil for cooling. However, the oil is not necessary for the LV test for the validation of the research. The small signal capacitance Cem is obtained through dividing the variation of the charge that flows into the multiplier by the variation of the input voltage of the multiplier. The measured current irect+ for charge calculation and voltage vac+ are denoted in Fig.3–24. The current to be measured is in the order of milli-ampere and the capacitance to be obtained based on the measured voltage and current is in the order of tens of pico farad. Consequently, relatively precise measurement is required. The instruments for the precise measurement are listed in Table 3–6. Table 3–6: Instruments for precise measurement Instrument Type Note Oscilloscope YOKOGAWA digital oscilloscope DLM2034 12bit resolution for acquiring data Current probe TECHTRONIX Active current probeTM502A minimum 1mA measureable current Voltage probe YOKOGAWA HV differential voltage probe700924 calibrated input capacitance: 14pF from 200kHz to 500kHz Chapter 3 77 0 -0.1 10 vac+ irect+ 0 0.2 0.4 0.6 0.8 1 1.2 1.4 irect+(mA) vac+(kV) 0.1 5 0 1.8 1.6 -6 t(sec) x 10 Cem (pF) 80 40 0 -0.06 -0.04 -0.02 0 0.02 0.04 vac+ from -Vpk to +Vpk (kV) 0.06 (a) 8 vac+ vac+(kV) 6 irect+ 0 4 2 -0.1 0 0.2 0.4 0.6 0.8 t(sec) 1 1.2 1.4 1.6 irect+(mA) 0.1 0 1.8 -6 x 10 Cem (pF) 80 40 0 -0.06 -0.04 -0.02 0 0.02 vac+ from -Vpk to +Vpk (kV) 0.04 0.06 (b) Fig.3–25: The input voltage vac+ and current irect+ of the multiplier and the equivalent parasitic capacitance Cem (blue stars), (including the input capacitance of the voltage probe) (a) the 78 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier voltage and current measured with 10MHz bandwidth; (b) the voltage and current Measured with 2MHz bandwidth Fig.3–25 shows the measured input voltage and current of the multiplier. Due to the leakage inductance of the transformer, the input current irect+ has ringing, as shown in Fig.3–25(a), superimposed on the ideal current waveform that should be generated by the sinusoidal input voltage vac+ and the voltage-dependent capacitance Cem. According to the measurements, the frequency of the ringing is at the magnitude of 10MHz and the maximum amplitude of them is around 3mA. However, the frequency of the main current is around 250kHz and the peak-peak value is around 16mA. Thus, it is reasonable to remove the ringing without deteriorating the main current waveform. Fig.3–25 (b) shows the waveforms by removing the ringing with limited bandwidth of the oscilloscope. By comparison, it can be seen that the C-V curves of the capacitance Cem, which are obtained by curve fitting, do not show much difference. 80 capacitance (pF) Measured Cem 40 Calculated Cem 20pF Calculated CDcht 0 -0.1 0.05 0 -0.05 vac+ from -Vpk to +Vpk (kV) (a) 0.1 0.15 Chapter 3 79 capacitance (pF) 80 Measured Cem 40 Calculated Cem 20pF Calculated CDcht 0 -0.2 -0.1 0 0.1 vac+ from -Vpk to +Vpk (kV) 0.2 0.3 (b) Fig.3–26: Measured capacitance Cem of the two-stage cascade multiplier with different output voltage, (a) output voltage: 0.5kV; (b) output voltage: 1kV The stars in Fig.3–26 are the measurement results for the equivalent parasitic capacitance of the demonstrator Cem operating at different output voltage. The voltage dependent behavior of the capacitance Cem is clear to see in Fig.3–26 (a) and (b). The figure also shows the calculated capacitance Cem as well as its voltage dependent part CDcht based on the complete model. The structural capacitances Cdg and Cdpp are both set as 0.15pF based on 3D FE simulation. The capacitance Cem is obtained in both cases, adding a capacitance of 20pF to the voltagedependent capacitance CDcht. From the figure, it can be seen that the calculated Cem fits the measurement results well. The demonstrator is also measured at 200V output to obtain a higher capacitance Cem that is shown in Fig.3–25 (b). The capacitance Cem also consists of the capacitance CDcht and the 20pF voltage-independent capacitance. The measurement results at different output voltage prove the model of the capacitance Cem that is composed of the voltage-dependent capacitance CDcht and the linear capacitance Cppgt. It is important to mention that there can be errors both in the measurement and the calculated results. On the one hand, regarding the measurement results, the main source that causes error is the measurement of the low current. Although a relatively precise current probe was used, it is hard to say how precisely the obtained current was measured because of the interference, which can be several mA, and is generated by the external environment as well as the instruments themselves. The inaccuracy caused by the interference can be improved by increasing the current level. On the other hand, the complex structure of the multiplier module 80 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier requires huge number of meshes to acquire accurate result in 3D FE field simulation. Thus, it is hard to obtain an accurate value of the large number of the structural capacitances. Besides, in some particular configurations of the multiplier module, each group of the structural capacitances can manifest large disperse values, which can cause deviation in the result calculated based on the assumption that they have the same value. As a result, the complete model of the parasitic capacitances is not intended to predict precise equivalent capacitance Cem. It is for the assessment of the magnitude of the capacitance Cem and very useful for the minimization of that capacitance. 3.8 Minimization of the equivalent parasitic capacitance In this section, the guidelines to minimize the equivalent parasitic capacitance of the multiplier are addressed based on the dependence analysis in the last section. The guidelines lead to the design procedure of the multiplier only in terms of minimization of the equivalent parasitic capacitance. A case study follows to apply the procedure in a real circuit design. 3.8.1 Guidelines for minimization The complete model allows assessment of parasitic capacitances in any configuration of the multiplier module and is very useful in minimization of the equivalent parasitic capacitance Cem. The guidelines for the minimization are listed as follows: 1. Given the same voltage rate, the push-pull and output capacitors with small surface size should be chosen. 2. If the number of diodes per chain is low enough that the junction capacitance of diode has a major influence on the capacitance Cem, for example, when HV SiC diode is applied, priority should be given to choosing small junction capacitance. 3. When the number of diodes per chain is high enough that the structural capacitances Cdpp, Cdg have a major influence on the capacitance Cem, for example, when Si diode is applied, priority should be given to careful geometry design to minimize the structural capacitances. The geometry design can be the optimization of, for example, the size of the soldering pads, PCB layout and arrangement of positions of components. According to the guidelines, the multiplier design can be improved aiming to minimize the equivalent parasitic capacitance without big effort. The iterative procedure of geometrical design and 3D EM simulation by trial and error can be avoided [Wan11]. Chapter 3 3.8.2 81 Design procedure Maximum output voltage of the multiplier Choose voltage rate for the push-pull and output capacitors Choose capacitors with small surface size Choose VBR for the diode Careful layout to minimize Cdpp/ Cdg Large Determine how large nd is with the estimation of Cj and Cdpp/ Cdg Small Choose diode with minimum Cj Medium 1. Choose diode with minimum Cj 2.Carefully layout to minimize Cdpp/ Cdg No Does Cem satisfy the design requirement? Yes Done Fig.3–27: The flowchart of minimization of the equivalent parasitic capacitance Cem The dependence of CDcht on nd gives important criteria to the minimization. Fig.3–27 shows the design procedure for the multiplier only in terms of minimization of the capacitance Cem. The other aspects, such as losses and cost, are not considered. 82 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier 1. The output voltage of the multiplier Vo is given before the design. According to the maximum Vo, voltage rate of the push-pull and output capacitors can be determined. Different voltage rates lead to different numbers of capacitors connected in series in the multiplier. At any voltage rate, the capacitor with a small surface should be chosen to make Cppg small, which consequently minimizes the total capacitance Cppgt. However, no simple rules have been obtained so far as a result of our work in order to compare and minimize the capacitance Cppgt in configurations of capacitors with different voltage rates. The comparison can only be made in each case with values of structural capacitances, which can be obtained by 3D FE field simulations. 2. Just as in step 1, breakdown voltages of the diodes can also be determined according to the maximum Vo. If a diode with high VBR is chosen such as the HV SiC diode, the number nd can be small. On the other hand, if a diode with low VBR is chosen, such as the Si diode, the number nd can be large. Different numbers can lead to different rules for the minimization of CDcht. Just as in step 1, no simple rules have been obtained by our work so far in order to compare and minimize the capacitance CDcht in configurations of diodes with different VBR. This is because the breakdown voltage of diode has no necessary relation to the junction capacitance and further the capacitance CDcht. In addition, diodes with different breakdown voltages may have different packages, which may lead to different structural capacitances and further the capacitance CDcht as well. 3. The capacitance CDcht changes with voltage in half cycle. However, if the junction capacitances or the structural capacitances dominate CDcht when CDcht is at a minimum, this dominance holds for most part of the half cycle. Thus, the conditions, which are listed in Equation (3.11) and (3.12), can still be utilized to approximately determine whether the number nd is sufficiently large or small. The chain voltage at this instant is Vpk. The average voltage can be utilized to approximately determine Cj, which is Vpk/nd, although junction capacitances along a chain have different voltages. • If nd is sufficiently small, priority should be given to decreasing Cj to minimize CDcht. In this case, designers should choose diodes at a given breakdown voltage with Cj as small as possible. • If nd is sufficiently large, priority should be given to decreasing structural capacitances to minimize CDcht. In this case, designers should design the layout and configuration of the multiplier module carefully to obtain minimum structural capacitances. Chapter 3 83 If nd is medium, both Cj and structural capacitances need to be decreased to minimize • CDcht. 4. After the above steps, the capacitance Cem has been obtained. If it does not satisfy the requirements, designers need to go back to step 1 or 2 to choose capacitors or diodes with different voltage rates, and then follow the procedure again. 3.8.3 Case study In this section, the minimization of CDcht following the above procedure for a two-stage multiplier is addressed. The output voltage of the multiplier in medical X-ray machines usually has a wide range. Here the maximum output voltage is assumed to be 72kV and the minimum is 12kV. According to the maximum voltage, 3 SiC diodes can be available, which are shown in Table 3– 7. Both structural capacitances Cdpp and Cdg are assumed as to be 0.3pF. Table 3–7 also shows the parameters required to judge how large nd is. Table 3–7: Parameters for assessment of nd VBR 1.2kV 4.5kV 10kV Cj0=144pF, φbi=0.926 Cj0=299pF, φbi =1.35 Cj0=1020pF, φbi =3.85 nd 40 12 5 (Cj(18kV/nd)/Cdpp)0.5 6.3 5.5 10.5 (Cj(3kV/nd)/Cdpp)0.5 10 8.5 16.5 Cj= C j0 1 − v / φbi It is clear that if the 1.2kV diode is chosen, the number nd is large enough, especially when the output voltage is 72kV, which means the structural capacitances dominate the capacitance CDcht. The layout and configuration of this module should be carefully designed to have small structural capacitances. Fig.3–28(a) shows that by decreasing the structural capacitance from 0.3pF to 0.1pF, the capacitance CDcht is decreased by almost 40%. 84 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier 40 Cdpp=0.3pF Cdg=0.3pF 20 Cdpp=0.1pF Cdg=0.1pF C Dcht (pF) 30 10 0 -20 -10 0 10 vac+ from -Vpk to +Vpk (kV) 20 (a) Cdpp=0.3pF Cdg=0.3pF 80 Cdpp=0.1pF Cdg=0.1pF C Dcht (pF) 120 40 0 -3 -2 1 -1 0 vac+ from -Vpk to +Vpk (kV) 2 3 (b) Fig.3–28: Decrease of CDcht by changing the structural capacitances in two cases, (a) 1.2kV diode, Vo=72kV; (b) 10kV diode, Vo=12kV In another extreme case when 10kV diode is chosen, especially when the output voltage is 12kV, the number nd is quite large, which means the junction capacitances Cj dominate the capacitance CDcht. Fig.3–28 (b) illustrates that the change of structural capacitances has hardly any influence on the capacitance, CDcht in this case. Thus, if another 10kV diode can be selected with much lower Cj, then CDcht tends to decrease to a large extent. With regard to the Chapter 3 85 cases shown in the table, both junction capacitances and structural capacitances should be decreased to minimize the capacitance CDcht. In addition, from Table 3–7, it can be seen that the absolute number nd does not necessarily reflect that it is sufficiently large or small. It has to be compared to the parameter on the right hand side of the Equation (3.11) and (3.12). For example, when the 10kV diode is employed and the multiplier operates at 18kV output voltage, although there are only 5 diodes per chain, this does not necessarily mean the number is sufficiently small or that the junction capacitances dominate the capacitance CDcht. The reason is that at high output voltage, the junction capacitances are usually small and even if there are only several diodes connected in series, the structural capacitances still play a role in the capacitance CDcht. 3.9 Comparison of multipliers with Si and SiC diodes In this section, the equivalent parasitic capacitance Cem of the multiplier with Si and SiC diodes are compared. It is interesting to see whether the volume reduction in the SiC case will lead to higher capacitance Cem than in the Si case. The comparison is made based on the example addressed in the case study. It is assumed that the Si diode has 1.2kV breakdown voltage and the junction capacitance is the same as that of 1.2kV SiC diode shown in Table 3–7. The two SiC diodes are the same as shown in that table. The linear part of the equivalent capacitance Cppgt is assumed to be the same in the three cases. Thus, the comparison concentrates on the total chain capacitance CDcht. The volume reduction of the multiplier with SiC diode is simply because of the reduction of diode amount. This can lead to higher structural capacitances Cdg and Cdpp due to the average shorten distances between the diodes and other components, such as the grounded container and the push-pull capacitors. Besides, the high voltage SiC diode usually has larger junction capacitance than the low voltage Si diode. One’s first impression is that the increased structural and junction capacitances can possibly cause a higher equivalent capacitance Cem. However, this is not necessarily so. 86 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier SiC, 10kV, Cdg=Cdpp=0.4pF CDcht (pF) 60 40 20 0 -20 Si, Cdg=Cdpp=0.2pF SiC, 4.5kV, Cdg=Cdpp=0.3pF -15 -10 -5 0 10 5 15 vac+ from -Vpk to +Vpk (kV) 20 (a) 80 SiC, 10kV, Cdg=Cdpp=0.4pF CDcht (pF) 60 40 Si, Cdg=Cdpp=0.2pF 20 0 -3 SiC, 4.5kV, Cdg=Cdpp=0.3pF -2 -1 0 1 vac+ from -Vpk to +Vpk (kV) 2 3 (b) Fig.3–29: Comparison on CDcht between a two-stage multiplier with Si and SiC diodes, (a) Vo=72kV; (b) Vo=12kV Fig.3–29 shows the total chain capacitance CDcht in the three cases respectively when the output voltage Vo is 72kV and when it is 12kV. The structural capacitances Cdg and Cdpp are set as 0.2pF in the Si-type multiplier, and 0.3pF and 0.4pF respectively in the 4.5kV and 10kV multipliers. Smaller volume can lead to higher structural capacitance. However, the structural capacitances do not increase proportionally with the reduction of the dimensions of the module. They are greatly influenced by the size of the soldering pads and package of diodes and the Chapter 3 87 distance between the diodes and other objects. If the distance is much larger than the dimension of the pad and diode, the reduction of the distance increases the structural capacitances slightly. Thus, in the three cases, if the sizes of diodes and pads are assumed to be the same, it is reasonable to increase structural capacitances by 0.1pF as the volume decreases. It can be seen that the 10kV SiC-type multiplier has the highest CDcht in both cases, and the 4.5kV-type multiplier has the lowest CDcht rather than the Si-type multiplier as appeared during the first impression. Although the structural capacitances in the 4.5kV SiC case are larger than those in the Si case, the amount is much smaller. The structural capacitances are arranged in a parallel pattern in the network, thus the effective part in the capacitance CDcht originating from the structural capacitances can be smaller in the 4.5kV SiC case. In addition, the junction capacitances of the 4.5kV SiC diode are not much larger than those of the Si diode. It leads to lower capacitance CDcht in the 4.5kV SiC-type multiplier. However, in the 10kV SiC-type multiplier, although the structural capacitances are the biggest, the amount is so small that they have little influence on the capacitance CDcht, as mentioned in the last section. The large CDcht in this case is largely determined by the large junction capacitance. It is obvious that the capacitance CDcht changes greatly as the output voltage changes. The capacitance CDcht and in turn the capacitance Cem depends on the junction capacitance, the structural capacitances and the number of diodes per chain. The dependence cannot be simplified. Different diodes have different junction capacitances and correspond to different numbers nd. Different module structure leads to different structural capacitances. The value of the capacitance Cem cannot be determined only by considering the structural capacitances or/and junction capacitances. Thus, it is hard to make quick accurate comparison of the magnitude of the capacitance Cem in the modules with different diodes. The volume reduction of the multiplier module by employing SiC diodes does not necessarily lead to higher capacitance Cem. Although simple rule are hard to obtain, a rule of thumb can be used for a quick estimation. The diodes with extremely high breakdown voltage, such as 10kV, or low breakdown voltage, such as 1.2kV, can lead to a too large or small number nd. In these cases, the capacitance Cem can be high because of the possibly too large junction capacitances and too many structural capacitances respectively. By using the diodes with breakdown voltage in between, it is possible to lower the capacitance Cem. 88 Equivalent parasitic capacitance of symmetrical Cockcroft Walton multiplier 3.10 Conclusion In HV generators in the medical X-ray machine, the cascade voltage multiplier adds new parasitic capacitances to the resonant tank. The parasitic capacitances include not only junction capacitance of diode but also structural capacitances in the module. The equivalent parasitic capacitance Cem, which is usually of tens of pico farad or even higher, can add a substantial extra part to the parallel resonant capacitance. Thus, sufficient design margin should be left for the parallel resonant capacitance. It is crucial to reduce the risk of exceeding the margin by minimizing the equivalent parasitic capacitance. The complete model gives a full description of the distribution of the parasitic capacitances in any configuration of the multiplier module. It offers access to analytical analysis and optimization of the equivalent parasitic capacitance, which avoids the time-consuming iterative process of geometrical design of the module and 3D FE simulation. Although a complete model is proposed for the symmetrical C.W. multiplier, similar models with the same four groups of parasitic capacitances can be obtained for other types of cascade voltage multipliers. The dependence of the equivalent parasitic capacitance Cem on different parameters shows the principle for minimization. The guidelines and the procedure for the minimization can help designers complete the minimization step by step. The number of diodes per chain in the multiplier is the criteria to determine the approach to minimizing the capacitance CDcht. The number should be judged by considering the junction capacitances and structural capacitances to determine whether they are sufficiently small or large. If the number nd is sufficiently small, like a multiplier with HV SiC diode, diodes with small junction capacitance should be picked. If it is sufficiently large, like a multiplier with Si diode, the spatial structure of the multiplier module should be carefully designed to decrease the structural capacitances. Otherwise, both aspects should be considered. The volume reduction of the multiplier module by employing SiC diodes, does not necessarily lead to higher capacitance Cem. It is hard to make quick, accurate comparison of the magnitude of the capacitance Cem in the modules with Si and SiC diodes. However, a rule of thumb can be used for a quick estimation. Given the output voltage of the multiplier, the diodes with extremely high breakdown voltage or low breakdown voltage can lead to high capacitance Cem. By using the diodes with breakdown voltage in between, it is possible to lower the capacitance Cem. Chapter 4 Electric field reduction in the multiplier module The parasitic capacitances in the symmetrical multiplier module have been elaborated in Chapter 3. In this chapter, another issue with regard to the multiplier that operates in the steady state will be addressed. The issue is electric field reduction. The knowledge obtained in Chapter 3 will be used in this chapter to obtain a simple technique for field reduction. 4.1 Introduction Apart from the influence of the parasitic capacitances on the steady circuit behavior, there is another factor to be considered --- insulation in the module. Usually, the output voltage of the multiplier is above 100kV. In the circuit module, the high voltages are applied on the electrodes of the diodes and the output capacitors as well as the associated soldering pads. The high voltages can induce a strong spatial electric field in PCBs and insulation media. The strong field can cause dielectric breakdown of the dielectrics. Thus, in practice, the strength of the field should be contained during circuit operation. In the medical X-ray machine, the multiplier module is usually filled with insulation oil that has a higher breakdown voltage than the air to stand the high electric field strength. The dielectric strength of the air is 3×106 V/m [Tip87], and that of the insulation oil is usually 10 times higher. Table 4–1 shows the dielectric strength of three typical commercial insulation oils. 90 Electric field reduction in the multiplier module Table 4–1: Dielectric strength of commercial insulation oils Shell DIALA oil AX CrossTrans 206 Insulation oil Caltex transformer oil BSI Dielectric breakdown voltage (kV) Test method: D1816 60Hz, VDE electrodes, 1.02mm gap 28 36 30 Approximate electric field strength for breakdown (V/m) 2.8×107 3.6×107 3×107 The electric field strength shown in the above table is obtained by dividing the voltage by the measurement distance. This method cannot determine the breakdown field strength accurately, but can show its order of magnitude. In addition, the dielectric strength of the FR4 PCB is also around 2×107 V/m. Although the dielectric strength of the dielectrics is quite high, the designer should still be cautious. According to 3D FE simulation, the strength of electric field in the multiplier module can be above 2×107 V/m, as shown in Fig.4–1. This is close to the limit of the dielectrics. E (V/m) Fig.4–1: High strength of spatial electric field in the HV multiplier module obtained by 3D FE simulation Thus, it is crucial to investigate the distribution of the electric field in the module to identify the regions with high electric field strength and to take measurements to reduce the field strength if necessary. The investigation is even more significant for the module with SiC diodes, because the reduced volume may lead to higher electric field than that in the module with Si diodes. Chapter 4 91 In this chapter, the distribution of the electric field in the multiplier module is firstly shown. The distribution is obtained in a simulation model of the module without the push-pull and output capacitors, which simplifies the analysis of the distribution. Based on the analysis, a field shielding technique is proposed to reduce the electric field strength. The push-pull and output capacitors can be utilized to shield the strong electric field. By applying the technique, some simple layouts can be designed for the demonstrator to contain the electric field at a low strength. 4.2 Electric field distribution In this section, the distribution of the electric field strength in a 4-stage multiplier module is addressed. The reason for the high field strength in the module is investigated. AC side DC side 0 AC input C1 -18 D1 -54 C3 -90 C4 -126 D2 0 -36 D1_1 AC side C2 first stage second stage third stage fourth stage -72 -144 -108 DC output D2_1 0 AC input C1_1 -18 C2_1 -54 C3_1 -90 C4_1 -126 Grounded container Fig.4–2: A 4-stage multiplier and its voltage distribution for the spatial electric field simulation, unit: kV Fig.4–2 shows a 4-stage multiplier. In the figure, each capacitor, such as C1, and diode, such as D1, represents several components connected in series in reality. As mentioned in previous chapters, the voltages on the nodes at the DC side, namely the voltage potential at the two terminals of the output capacitors, are constant. The voltages on the nodes in each stage at the AC sides swing between the voltage potentials of the two terminals of the output capacitor in that stage. Consequently, the AC voltage induces an AC electric field in the module. Here the maximum strength of the static electric field is considered as the only factor that causes the breakdown. Thus, one operating point is chosen to obtain the distribution of the electric field. 92 Electric field reduction in the multiplier module In our case, the voltages when the AC inputs of the multiplier are zero, which are the numbers in Fig.4–2, are chosen and assigned for 3D FE field simulation. PCB1 PCB2 PCB3 PCB4 (a) Front view of the 3D model unit: kV soldering pads Top view of the 3D model 0 PCB1 -36 -36 PCB2 -72 -72 PCB3 -108 -108 PCB4 -144 de Dio in 1 -18 cha Dio de c hain 0 2 -36 Dio de c PCB1 hain 1_1 -18 ain ch iode 2_1 D (b) Fig.4–3: 3D simulation model for the 4-stage multiplier without push-pull and output capacitors and its voltage assignment, (a) 3D FE simulation model; (b) voltage assignment in the model Fig.4–3 shows the 3D simulation model for the 4-stage multiplier. The simplification of the model has been explained in Appendix A.4.1. Due to the small size of packages of the diodes compared to the soldering pads, the diode model is eliminated leaving only the soldering pad to Chapter 4 93 evaluate the distribution of the electric field. In the following content associated with this model, the diodes are represented by the soldering pads. The push-pull and output capacitors are not added here. The electric field is obtained firstly without them. By doing this, it is easy and clear to understand the distribution of the electric field. The capacitors will be added in a later stage and will be used as a tool to reduce the field. The fine meshes created in the model assure accurate simulation results. The voltage assignment in the model is shown in Fig.4–3 (b). The diodes in one stage of the multiplier are assembled on one board. The board PCB1 in the figure represents the PCB for the first stage and the other notations have a meaning analogous to the board PCB1. The dash lines in the left figure represent the connecting bars in reality, which are neglected in the simulation. The right picture in Fig.4–3 (b) shows the voltage distribution on the diodes on the board PCB1. The other boards have the same rule of voltage distribution. The voltage along one diode chain is supposed to distribute evenly and each diode in the chain has the same voltage. PCB2 PCB3 PCB4 E (V/m) PCB1 Fig.4–4: Distribution of electric field strength on the four PCBs 94 Electric field reduction in the multiplier module Fig.4–4 exhibits the distribution of electric field strength in the four boards. Two interesting rules can be observed from the figure. Firstly, the field strength between the diodes is much smaller than 2×107 V/m. In the simulation, the voltage across the diode chain is set as 18kV, which means that the voltage on each diode is 1.5kV. Thus, the voltage difference on the adjacent pads in the model is 1.5kV and the distance between them are around 4mm. The magnitude of the field strength caused by the voltage difference is approximately 3.75×105V/m, which is almost 50 times smaller than the limit, 2×107 V/m. In the worst case when the diode chain has the maximum blocked voltage 36kV, the magnitude of the field strength is just 7.5×105 V/m, which is still far below 2×107 V/m. Even if the distances between the diodes decreases further to 1mm, the field strength is still just 3×106 V/m, which is far from the limit. As a result, the voltage differences between the diodes are not the reason to the strong electric field. Secondly, it can be seen that the field closely around the diodes on the board PCB4 has the highest strength, which is above 2×107 V/m. From the discussion above, this high strength is not likely to be caused by the layout of the diodes. It can be caused by the significant voltage difference between the diodes and the grounded container. The reason to the high strength of electric the field is to be discovered as follows. … Diodes … … Diodes … Diode :D1 _ Cdd + Diode :D1 vdd + Electric field vdg Grounded container (a) _ Cdg Grounded container (b) Fig.4–5: Representation of the spatial electric field around the diode, (a) general distribution of electric field around a diode D1 in the module; (b) general distribution of parasitic capacitances associated with a diode D1 Fig.4–5 (a) shows a general distribution of spatial electric field associated with one diode. The field distribution and strength in the region near the diode are influenced by the geometry, such as layout of the diode as well as other components and the structure of the grounded container, Chapter 4 95 and voltages on the components. Because the diodes have small physical size compared to the grounded container, the field concentrates in the close region near the diodes and decays fast with spatial distance. The distribution of the electric field all over the module is complex due to the complicated 3D configuration of the module. Thus, it is hard to see which geometry and voltage determine the high strength by looking at the line integration relation between the electric field and voltage potential. Since the parasitic capacitances, which relate to the electric field, were obtained in Chapter 3, the reason for high field strength can be explained by looking at the capacitances. Generally, there are two types of structural capacitances associated with one diode, which are the structural capacitances between diodes Cdd and the structural capacitance between the diode and the grounded container Cdg, as shown in Fig.4–5 (b). The relation between the parasitic capacitances and the electric field on the surface of the diode is given as: Q= Cdg vdg + ∑ Cdd vdd = ε ∫ E ⋅ dS S (4.1) in which: E signifies the electric field on the surface of the diode ε is the permittivity of dielectric S signifies a surface enclosing the diode Q signifies the charges on the surface of the diode vdg signifies the voltage difference between the diode and the grounded container vdd signifies the voltage difference between difference diodes It was discovered in Chapter 3 that the structural capacitances Cdd between the diodes that are not adjacent are so tiny that they can be neglected, which means that the diodes far away hardly influence the electric field. Each diode in the layout in Fig.4–3 (b) has 2~4 adjacent diodes with capacitance Cdd. Based on simulation, the capacitance Cdd is between 0.6pF to 1pF and the capacitance Cdg is usually around 0.25pF. Considering the extreme case, the sum of the capacitance Cdd, which is 4pF, is 16 times the capacitance Cdg. The voltage across the adjacent diodes in the topology is 1.5kV in the above field simulation. Thus, the term ∑Cddvdd in Equation (4.1) is approximately 6. While the voltage vdg for the diodes in the fourth stage is at least 108kV, which is 72 times vdd. Thus in Equation (4.1), the product Cdgvdg is about 27, which is 4.5 times larger than the term ∑Cddvdd. Even if the voltage vdd is 3kV when the input voltage of the multiplier swings to the peak, the former product is still 2.25 times the later one. In short, the charge Q is mainly determined by Cdg and vdg, namely by the geometry associated 96 Electric field reduction in the multiplier module with the diode and the container and the voltage in between. With Equation (4.1), this further means that the electric field close to the diode is mainly influenced by Cdg and vdg, which results in a strong field in the close region of diodes on the board PCB4. In short, the close region around the diodes on the board PCB4 has the strongest field, which is mainly caused by the high voltage difference vdg between the diodes and the ground. In general, on the one hand, the volume reduction of the module by replacing Si diodes with SiC diodes does not lead to significant reduction of the average distance between diodes and the container. On the other hand, the reduction of the distance increases the capacitance Cdg slightly, if the distance is much larger than the dimension of the pad and diode. As a result, the capacitance Cdg in the SiC-type module can be slightly larger than that in the Si-type module, meanwhile the voltage vdg remains the same in the two modules. Thus, the volume reduction in the SiC-type module will not significantly increase the highest field strength. 4.3 Electric field reduction Since the reason of the high field strength has been discovered, this section presents a simple technique to reduce it. 4.3.1 Principle As stated above, the spatial electric field becomes stronger closely around the diodes and their soldering pads in a higher stage of the multiplier, and the strong field is predominantly associated with the capacitance Cdg and voltage vdg. Trace Cdt _ vdt _ (a) + + vdg Diode + Diode vdg Cdg Grounded container _ Cdg_t Grounded container (b) Fig.4–6: The principle of reducing the electric field, (a) parasitic capacitance before adding the shielding trace; (b) parasitic capacitances after adding the shielding trace Chapter 4 97 Field reduction can be realized by adding a copper trace, which is applied with a constant voltage, around the diodes on PCBs. The shielding trace is intended to reduce the main contribution to the strong electric field, which is the product of Cdg and vdg as shown in Equation 4.1. Because of the relatively short distances between the nearby diodes, the structural capacitances between the diodes Cdd are hardly influenced by the trace and are supposed not to change. Fig.4–6 shows the principle of the reduction. The electric field Ent associated with the product Cdgvdg in the case without trace, as shown in Fig.4–6 (a), is: Cdg vdg ε ∫ Ent ( x, y,z ) ⋅ dS = S (4.2) Ent signifies the electric field on the surface of the diode in the case without shielding trace By adding the trace, the electric field between the diode and grounded container can be shielded, which results in the reduction of the structural capacitance Cdg to Cdg_t. Meanwhile a new structural capacitance Cdt is added. The voltage on the shielding trace can be set to any value between the two DC voltages at the terminals of the output capacitor in one stage. In practice, it is easy to connect the trace to one of the terminals of the output capacitor. When adding the trace, the electric field becomes: ε ∫ E t ( x, y,z ) ⋅= dS Cdg _ t vdg + Cdt= vdt ε ∫ rE Ent ( x, y,z ) ⋅ dS S S (4.3) in which: Et signifies the electric field on the surface of the diode in the case with shielding trace, and when the influence of the rest diodes is ignored. rE signifies the reduction factor of the electric field vdt signifies the voltage difference between the diode and the trace Because of the relatively small size of the diode and its soldering pad, the shape of the electric field in the close region around the diode is not supposed to change dramatically. The distribution of the field can be assumed as constant, which means the spatial dependence of the field E(x, y, z) doesn’t change. Thus, the field in the space with shielding trace Et can be expressed as the field Ent multiplied by a scalar factor rE. Based on the above equation, the trace can be regarded to have two opposite effects on the field close to the diode, which are reflected by the two terms on the right hand side of Equation (4.3). The capacitance Cdg_t is smaller than the capacitance Cdg in Equation (4.2) because the trace can shield the electric field between the diode and the grounded container. Thus, the value of 98 Electric field reduction in the multiplier module the term Cdg_tvdg is smaller than that of the term Cdgvdg. This indicates an effect that is reduction of the field by the trace. However, the term Cdtvdt appears as a new source to the electric field mathematically. This indicates an effect that is enhancement of the field by the trace. To reduce the electric field, the trace should be designed in total, to have a net effect of reduction, which means that the parameter rE should be smaller than 1. To clearly express rE, several parameters are defined as follows: = rCstru Cdg _ t Cdg = ; aCstru Cdt vdt = ; rv Cdg vdg (4.4) in which: rCstru is the reduction factor of the structural capacitance Cdg by adding the trace aCstru represents the ratio of the new added structural capacitance Cdt to the original structural capacitance Cdg rv is the ratio of the voltage vdt to vdg By using these parameters, rE is given as: (4.5) = rE rCstru + aCstru rv As long as the factor rE is smaller than 1, the strength of the electric field can be reduced. The parameters rCstru, aCstru, are determined by the geometry of the module, which will be discussed in the next part in a specific structure. However, the parameter rv is determined by the voltage that is assigned to the trace, which can be discussed in a general way. rv 0.5 0.4 vtg|PCB4 = -108kV rv 0 vtg|PCB3 = -72kV -0.1 0.3 -0.2 0.2 -0.3 0.1 -0.4 0 -144 -108 -72 -0.5 -144 vtg|PCB3 = -108kV vtg|PCB4 = -144kV -108 vdg vdg (a) (b) -72 Fig.4–7: Parameter rv for the boards PCB3 and PCB4, (a) vtg| PCB3 = -72kV, vtg| PCB4 = -108kV; (b) vtg| PCB3 = -108kV, vtg| PCB4 = -144kV. The symbol vtg signifies the voltage difference between the shielding trace and the grounded container. vtg = vdg - vdt Chapter 4 99 Fig.4–7 shows the curve of rv for the diodes in the third and fourth stages of the multiplier. The field associated with the first and second stage is much weaker than that associated with the last two stages, thus the field reduction by adding the traces is not intended for them. Two sets of voltage are applied to the traces. The two sets are respectively for the cases when the trace on each stage is connected to the low or high DC voltage at the terminals of the output capacitor. The different curves of rv are respectively shown in Fig.4–7 (a) and (b). If the traces are connected to the low absolute DC voltage, the voltages vtg of the traces on the boards PCB4 and PCB3 will be -108kV and -72kV respectively. In this case, the parameter rv is always below 0.35. This means the enhancement effect of the field by the trace is well contained. If the traces are connected to the high absolute DC voltage, as shown in Fig.4–7 (b), the parameter rv is negative. Based on Equation (4.5), this set of voltages can have a better shielding effect. In this case, the voltage on the trace is lower than that on the diodes. The voltages on the traces are intended to induce electric fields whose direction is opposite to fields from the ground to the diodes. Consequently, the electric field is more reduced than that in the former case. 4.3.2 Case study In this section, a simple case regarding the reduction of the electric field by adding the shielding trace is discussed. Front view of the 3D model unit: kV 0 -36 -72 -108 PCB1 PCB2 PCB3 PCB4 Top view of the 3D model -126 -36 -72 -108 -144 -144 -108 -126 PCB4 Fig.4–8: The voltage assignment in the 3D simulation model for a simplified 4-stage multiplier without push-pull and output capacitors 100 Electric field reduction in the multiplier module Fig.4–8 shows the voltage assignment in the 3D simulation model for a simplified 4-stage multiplier without push-pull and output capacitors. The configuration of the 3D model and voltage assignment is similar to that shown in Fig.4–3. There are two differences. The first one is that only 4 diodes are used in the simplified multiplier, which simplifies the 3D modeling and speeds up the simulation. Accordingly, the layout of the diodes is adjusted. In this case, the voltage difference between two diodes is 4.5kV when the input voltage of the multiplier is zero. The second difference is that a diode model is also added in the simulation, which can give a more realistic result compared to that obtained by the model with only soldering pads. In the simple case, even with the diode model, the 3D FE simulation is also fast. The detailed diode model is shown in Appendix A.4.1 vdg = -144kV vdg = -108kV PCB4 (a) vtg = -144kV PCB4 (b) Chapter 4 101 vtg = -108kV PCB4 E (V/m) (c) (d) Fig.4–9: Reduction of the electric field on the board PCB4 by adding a shielding trace, (a) field strength without shielding trace; (b) field strength with shielding trace, vtg = -144kV; (c) field strength with shielding trace, vtg = -108kV; (d) color map Fig.4–9 shows the distribution of the electric field strength on the board PCB4. Two voltages are assigned on the traces to compare the effect of field reduction. It is clear that the strong electric field closely around the soldering pads is attenuated by adding a shielding trace surrounding the diodes in both cases. The field reduction can be judged by examining the parameter rE, as shown in Fig.4–10. The xaxis represents each diode in the upper half legs on the board PCB4 in Fig.4–8. For example, the value -108 indicates the diode whose cathode has a voltage of -108kV. The y-axis shows the values for the parameters shown in Equation (4.4) and (4.5). The parameters quantitatively indicate the reduction of the field by adding the trace approximately. Their meaning was explained in the last section. The case in which the voltage on the trace is -108kV is denoted as vtg = -108kV in the figure, and the other case with -144kV is denoted with similar notation. 102 Electric field reduction in the multiplier module rCstru aCstru rE , vtg=-144kV rE , vtg=-108kV vdg (kV) Fig.4–10: Parameters rCstru, aCstru, rE in Equations (4.4) and (4.5) From the figure, it can be seen that by adding the shielding trace, the structural capacitances Cdg decreases to around its 35%, and rCstru is around 0.35. The new added structural capacitance Cdt is around 60% of the original Cdg, and aCstru is around 0.6. However, the product aCstrurv can be lowered by adding the proper voltage on the trace. When the voltage vtg is -108kV, the product is below 0.15. Thus, the reduction factor of electric field rE is below 0.5, which means the field is much reduced. If -144kV is assigned on the trace, the product aCstrurv becomes negative. Consequently, the parameter rE becomes even smaller than that obtained in the case with -108kV. As a result, the field strength is even lower. It can be observed by comparing Fig.4–9 (b) and (c). In this case study, the soldering pads have sharp corners, where the electric field concentrates more densely than in the field obtained in section 4.2 where pads are with round corners. As a result, the maximum strength of the electric field in the simple case is set as 6×107 V/m, which is also larger than that in the previous simulations. From Fig.4–9, it can also been observed that the electric field around the shielding trace can be high because of the high voltage. But, it can be weaker than that around the diodes with the same voltage. There are two ways to further constrain the electric field around the trace. The first one is make the curvature of the trace corner less than the diode pads. This method is quite reasonable because large surface can be used to place the trace to decrease its curvature. The other way is use multiple traces with gradually decreased voltage. This can decrease the localized high filed strength around the traces based on the same principle shown in this section. Fig.4–11 shows the field reduction around the trace with -144kV by adding another Chapter 4 103 shielding trace with -108kV. The color map here is adjusted for comparison with that in Fig.4– 9 to emphasize the reduction effect of the field around the trace. vtg = -144kV vtg = -108kV vtg = -144kV PCB4 PCB4 E (V/m) (a) (b) Fig.4–11: Reduction of the electric field around the shielding trace by adding multiple traces with gradually decreased voltages, (a) field strength; (b) color map In principle, more shield traces can be added until the voltages on the trace decrease to zero. However, the layout and configuration of the practical multiplier module has to be considered. Usually on one PCB board, such as PCB4, the DC potential varies from -108kV to -144kV. Thus, if it is intended to apply a voltage below -108kV on the shielding trace, this must be provided by another board, which will complicate the connections. 4.4 Demonstrator In this case, the demonstrator, in which the field strength is reduced by the simple shielding technique proposed in the last section, is discussed. The demonstrator for a LV test module of 2-stage multiplier with SiC diodes was shown in Fig.3–23. The full-size setup has four stages, and its structure is similar to that of the LV test module. The maximum output voltage of 4-stage multiplier is supposed to be -144kV. 104 Electric field reduction in the multiplier module 0 PCB1 V/3 2V/3 PCB2 V Dielectric PCB3 PCB4 Electrodes capacitors (a) (b) Fig.4–12: 3D simulation model of the demonstrator, (a) 3D model for the 4-stage multiplier; (b) cross section of the simplified 3D model of the push-pull and output capacitors Fig.4–12 (a) shows the 3D simulation model of the demonstrator. The model is the same as that shown in Fig.4–3 except that the push-pull and output capacitors are added. The 3D model of the capacitors is shown in Appendix A.4.1. The cross section of the capacitor model is shown in Fig.4–12 (b). In the model, a capacitor has four groups of electrodes. In reality, due to the interleaving pattern of the electrodes, the capacitor is realized with an internal series connection of six capacitors. The internal electrodes are neglected because they do not influence the spatial electric field much, which is also shown in Appendix A.4.1. The surface voltage potential varies step-wise along the electrodes from one capacitor terminal to the other. The steps are 0-V/3-2V/3-V, where V signifies the terminal voltage of the capacitor. Six capacitors are connected in series to comprise one push-pull or output capacitor except for the capacitors C1 and C1_1. As mentioned in Chapter 2, the value of these two capacitors is half of the others. Thus, only three capacitors are required for C1 and C1_1. Thus, the board PCB1 has three capacitors for C1 and C1_1 per half board and three capacitors for C2 and C2_1 per the half board. The configuration is the same as that of other boards. Thus, only half of the board PCB4 has the push-pull capacitors. Chapter 4 105 18 C2 C1 0 -18 -18 -54 -36 0 -18 -36 capacitors B1 0 18 0 -36 -18 -36 0 -18 C1_1 diodes -18 -36 C2_1 -54 Fig.4–13: Voltage assignment in the 3D model of the demonstrator, the board PCB1 for example, unit: kV The voltage assignment in the 3D model of the demonstrator is also the same as that in Fig.4–3 except for the newly added voltages for the capacitors. As before, the voltages when the input voltage of the multiplier is zero are selected to assign in the model. Fig.4–13 shows the voltage assignment for the first stage and the other stages have similar voltage assignment. Regarding one stage, the voltage potentials on the electrodes of the output capacitors are constant, which vary step-wise from the DC input to the DC output of that stage. The voltage potentials on the electrodes of the push-pull capacitors swing up and down in a certain range between the DC input and the DC output of that stage. Fig.4–13 shows the swings for the first stage. As a result, the electrodes of the capacitors work as the shielding trace that can reduce the strong electric field closely around the soldering pads. vdg = -144kV vdg = -72kV PCB3 PCB4 vdg = -108kV vdg = -108kV (a) 106 Electric field reduction in the multiplier module vdg = -144kV vdg = -72kV PCB4 PCB3 vdg = -108kV vdg = -108kV E (V/m) (b) (c) Fig.4–14: Reduction of the electric field after adding the push-pull and output capacitors, (a) field strength on the boards PCB3 and PCB4 without capacitors; (b) field strength on the boards PCB3 and PCB4 with capacitors; (c) color map Fig.4–14 shows the simulation results. The electric field is attenuated for the boards PCB3 and PCB4 after the push-pull and output capacitors are added. Only half of the board PCB4 has the push-pull capacitors, thus the electric field around the diodes on the right half board is not well attenuated. This problem can be solved by adding a shield trace surrounding half the diodes or adding a shielding plate on the bottom of the module, as is shown below. Chapter 4 107 Shielding trace with voltage = -144kV Shielding plate with voltage = -144kV (a) (b) Fig.4–15: Models for further field reduction, (a) adding a metal trace surrounding half the diodes on the board PCB4; (b) adding a metal plate at the bottom of the 4-stage multiplier In Fig.4–15 (a), the voltage on the shielding trace is set to -144kV. The trace surrounds just half the diodes on the board PCB4. Otherwise, the distances between the trace and the diodes on the left half board might be too small because of the small size of the board. This can lead to high electric field strength in between because the large voltage differences between the traces and the diodes. In addition, the distance between the trace and the capacitors, which are on the other side of the board, is just the thickness of the board. This small distance can further induce strong electric field inside PCBs and the spatial region around. For the same reason, the plate and the capacitors on the board PCB4 should also be kept within sufficient distance to avoid strong electric field in between, as shown in Fig.4–16 (b). vdg = -144kV vdg = -72kV PCB3 PCB4 vdg = -108kV vdg = -108kV (a) vtg = -144kV 108 Electric field reduction in the multiplier module vdg = -144kV vdg = -72kV PCB3 PCB4 vdg = -108kV vdg = -108kV E (V/m) (b) (c) Fig.4–16: Further reduction of the electric field on the board PCB4 after adding a shielding trace or plate; (a) field strength on the boards PCB3 and PCB4 with shielding trace on the board PCB4; (b) field strength on the boards PCB3 and PCB4 with only shielding plate at bottom; (c) color map Fig.4–16 shows the simulation results with regard the further field reduction by adding the shielding trace and plate. It can be seen that the strong electric field around the diodes with high voltages on the board PCB4 is attenuated. The shielding metals should be put at a proper distance from the diodes. If they are too close, strong electric field can be induced. If it is too far, the reduction can be very weak. The safe distance should be larger than that obtained by the dividing the maximum voltage difference between the shielding metal and the components over the critical field strength. Chapter 4 109 PCB4 Without capacitors PCB4 With capacitors (a) PCB4 PCB4 Capacitors + shielding plate at bottom Capacitors + shielding trace on PCB4 E (V/m) (b) (c) Fig.4–17: Comparison of the field reduction by different methods, (a) by adding push-pull and output capacitors only; (b) by adding the capacitors and a shielding trace or shielding plate; (c) color map Fig.4–17 shows the comparison of the field reduction. It is clear that the strong electric field around the diodes on the board PCB4 can be attenuated by adding the push-pull and output capacitors. In addition, they can be further attenuated by adding a shielding trace on the board PCB4 or plate below the board PCB4. 110 Electric field reduction in the multiplier module vdg = -144kV vdg = -144kV vtg = -108kV PCB4 PCB4 vdg = -108kV vtg = -144kV vdg = -108kV vtg = -144kV E (V/m) (a) (b) Fig.4–18: Reduction of the electric field around the shielding trace with -144kV If the field around the shielding trace is stilled regarded to be high, another shield trace with decreased voltage can be added to attenuate the field strength. Fig.4–18 shows the reduction by adding another shield trace with -108kV. The color map here is adjusted for comparison with that in Fig.4–16 to emphasize the reduction effect of the field around the trace. 4.5 Conclusion In the HV multiplier module, the strongest spatial electric field is present in the space close to the diodes and the soldering pads in the highest stage. The high electric field strength is caused by the large voltage difference vdg between the diodes and the grounded container. The volume reduction in the SiC-type module can lead to a slighter larger structural capacitance Cdg than that in Si-type module, meanwhile the voltage vdg remains the same in the two modules. Thus, the volume reduction in the SiC-type module will not significantly increase the highest field strength. A simple approach is proposed to reduce the electric field. The approach is to add a shielding metal with proper voltage near the space where the strong field is present. The push-pull and output capacitors in the multiplier work as shielding metals. A good layout can help to reduce Chapter 4 111 the field strength. A simple case and the demonstrator have shown application of the method and reduction of the electric field strength. 112 Electric field reduction in the multiplier module Chapter 5 Parasitic modeling in case of the fast transient EM field In Chapter 3 and 4, the parasitic related issues were introduced for the HV multiplier that operates in steady state. In this chapter, the parasitic issue related to fast transient behaviors of the multiplier will be discussed. 5.1 Introduction As introduced in Chapter 2, the arc-over in an X-ray tube results in a short-circuiting of the load of the HV generator. Consequently, large current pulses and voltage spikes can be provoked in the circuit. To limit the current peaks and damp the oscillations, a damping resistor can be added in the main discharging loop, which consists of the output capacitors of the generator, the HV cable and the X-ray tube [Bey06]. io HV cable Rdp Cathode of t=0 X-ray tube Grounded container RL Anode of X-ray tube Multiplier (a) 114 Parasitic modeling in case of the fast transient EM field io Lpa + Co1 Lpa Rdp Cathode of t=0 X-ray tube Grounded container RL Anode of X-ray tube Multiplier (b) Fig.5–1: The secondary side of the HV generator in arc-over event, (a) simplified block diagram; (b) equivalent circuit in the transient interval 1 in Fig.2–26, obtained after adding the parasitic inductances Fig.5–1 (a) shows the simplified block diagram for the secondary side of the HV generator in an arc-over event. Generally, the multiplier consists of diodes and capacitors that are placed in a grounded container. The damping resistor Rdp is placed between the output of the multiplier and the HV cable, which connects the multiplier to the X-ray tube. When arc-over occurs, the tube becomes short-circuited, which provokes current pulses and voltage spikes. Due to good grounding, the transient current pulses flow at the secondary side of the generator, namely the multiplier side [Zha95]. Based on the circuit analysis in Chapter 2, the transient behaviors of the circuit are associated with the transient discharging problem of the capacitor, as shown in Fig.5–1 (b). io(t) io(t) tpulse >> tr 0 tr tpulse t tpulse >> tr 0 tr (a) t tpulse (b) Fig.5–2: Typical transient current pulses, (a) with lumped element model of the transmission line; (b) with continuous model of the transmission line Chapter 5 115 Fig.5–2 (a) shows a typical transient current pulse in a capacitor discharging circuit, such as in Fig.5–1 (b). The transmission line effect of the cable is not considered and the cable is modeled as an inductor. The duration of the pulse tpulse is around hundreds of nano seconds or longer, whereas the rise time of the pulse tr is only about several nano seconds. Thus, by quick impression, the bandwidth of such a pulse, which is much influenced by the steepest slope of the waveform, can enter the upper MHz range, The highest frequency of interest in the bandwidth can be set as approximately 1/tr. If tr is 15ns, by quick estimation, the minimum wavelength of EM field resulted from this pulse can be 3m in the insulation oil in the container, the relative permittivity of which εr is 2.2. With regard to the multiplier module, the physical dimension is usually about half a meter, excluding the HV cable. Consequently, a quarter of the minimum wavelength is approaching the physical dimensions of the electrical component. In other words, the maximum frequency of the EM field exceeds the quasi-static range [Maq72]. As a result, the usage of lumped element models of the components is not accurate to handle the circuit analysis in a system with such a high frequency. A high-order circuit model is required for accurate circuit analysis. By taking the cable as an example, the length of which is set as 1m, Fig.5–2 (b) shows the pulses by employing the continuous model of the cable. Obviously, oscillations are present, which cause a deviation from the waveform in Fig.5–2 (a). Capacitors AC+ Diode DC out DC in PCB AC- Grounded container (insulation oil inside) Fig.5–3: The structure of a one-stage multiplier module Thus, the multiplier module, as shown in Fig.5–3, cannot be simply represented by the equivalent circuit in Fig.5–1 (b) in the transient interval. High-order circuit models of the discrete components and parasitic elements in the multiplier module need to be developed. The high-order circuit model of discrete capacitors was proposed in [Sul01]. The parasitic elements 116 Parasitic modeling in case of the fast transient EM field in the module are associated with the 3D structure of the module, which is usually quite complex. No simple general method is found to obtain the high-order circuit model of the structural parasitics. Thus, in this chapter the focus is mainly on the modeling of the structural parasitics in the module. In this chapter, the circuit modeling of the parasitics in the multiplier module when the frequency of EM field is just above quasi-static range, is addressed, which is defined as the beginning of the intermediate frequency range. Firstly, the basic concepts of a lumped element and a continuous model are introduced. A new concept of lumped multi element (LME) model is proposed for the circuit modelling in the intermediate frequency range. After that, different procedures to derive circuit models are summarized. It is found that the procedure that involves the power series approach [Maq72] in the first step, which is a tool to solve the time-varying field, is a good way to derive the LME model. The application of the approach is extended from a sinusoidally single frequency system to the general pulsed case, which involves a continuous spectrum system. An example of a single-turn inductor with pulsed source is taken to demonstrate the calculations of fields and derivations of LME models. After that, the procedure is applied to the multiplier module, which has a complex 3D structure. The fields are calculated, from which the LME model of the parasitics is derived. 5.2 Circuit modeling in the intermediate frequency range In this section, the basic concepts of lumped element, lumped multi element, and continuous models of electrical components are introduced. After that, general procedures of circuit model ling are summarized. The procedure that involves the power series approach is chosen as the best way to obtain an LME model. 5.2.1 Lumped element, lumped multi element and continuous models In electrical engineering, the lumped element model is proposed in contrast to the continuous model of electrical circuits. For a given electrical component, both lumped element and continuous models can be used to describe the voltage-current characteristics. It is the electrical size of the structure of the component, which is the size in terms of the minimum wavelength of interest in the bandwidth of the EM field over which the model must be valid, that indicates the sophistication and complexity of the required model. [Sch08] Chapter 5 117 Electrical component/system Perfect conductor ... ... Circuit models lumped element model 0 static and quasi-static range LME model intermediate frequency range continuous model wave range frequency of field Fig.5–4: Lumped element, lumped multi element (LME) and continuous models Fig.5–4 shows how the model changes for a parallel-plate, as the frequency of the EM field increases. The frequency spectrum is divided into three approximate ranges, according to the electrical size of the structure. These are the static and the quasi-static range, the intermediate frequency range and the high frequency range. When the frequency is in the lowest range, the lumped element model of a capacitor, as defined in static fields, is valid to describe the terminal voltage-current characteristics in the circuit with the parallel-plate. The electrical size of the parallel-plate is so small that the physical dimension is much smaller than the wavelength of the field. In this case, Maxwell’s equations can be simplified by a static or quasi-static approach. In the lumped element model of an electrical component, there is no concept of wavelength or even physical size. Any phase shift is strictly due to the reactance of the element, not its physical size. [Swa03] The lumped element model simplifies the description of the behavior of spatially distributed physical systems into a topology consisting of discrete entities. When the frequency is in the highest range, namely the wave range, the lumped element model is no longer valid and a continuous model has to be adopted to model the electrical component and to analyze the circuit. The parallel-plate has a large electrical size and the physical dimension can be several times the wavelength of the field or even longer. In this case, Maxwell’s equations have to be solved completely to obtain an accurate result for the fields. In this extreme case, the parallel-plate should be modelled as infinite number of unit lumped networks in cascade. It then becomes a transmission line. The continuous model is indeed often 118 Parasitic modeling in case of the fast transient EM field used to describe the transmission line, thus it is also sometimes called a transmission line model. The lumped element and continuous models in their respective frequency ranges have been well studied. However, if the frequency is in between, not many references are found that describe the relevant circuit model. When frequency enters the intermediate frequency range, the physical dimensions of the parallel-plate approach the wavelength of the field. Phase shift will be present in space, which leads to reactance in the model. The extra reactance is usually called parasitic, such as parasitic capacitance or inductance, because these are not intended when designing the component. In this situation, the parallel-plate can’t be modeled as a lumped capacitor. More lumped elements are required in the model to accurately describe the terminal voltage-current characteristics. Usually people refer to lumped element models as the model consisting of only one element, such as the capacitor model in Fig.5–4 [Maq72] [Kul10]. However, the model in the intermediate frequency range contains more than one element. Thus, it is called the lumped multi element (LME) model in this thesis. As frequency increases, more elements may be needed in the model. However, the number of elements will not be so large that the complexity of the LME model is comparable to that of the continuous model. When that happens, it is meaningless to distinguish between the LME model and the continuous model. The boundaries between different frequency ranges can be fuzzy [Maq72][Swa03]. In this chapter, the boundaries are given by the rule of thumb obtained from the analysis in Appendix B.2, which may help to gain a quick impression. The boundaries are given in Table 5–1: Table 5–1: The boundaries of the different frequency ranges. λ signifies the wavelength of the field and l signifies the physical dimension of the electrical structure. Wavelength ranges Frequency ranges Model l < 0.1λ static and quasi-static range Lumped element 0.1 λ 0.5 λ wave range Continuous It is crucial to emphasize that the above rules are derived in a system with sinusoidal fields that have a single frequency. In a system with fields that have a continuous spectrum, such as Chapter 5 119 pulsed fields, the characteristic length of the fields in the system should be used to replace λ. This is the wavelength at the highest frequency of interest in the spectra of all involved field quantities. The lumped element and continuous models have been well studied, but the LME model is not sufficiently researched, particularly not for a system with fields that have continuous spectra. Thus, the procedures to derive the LME model will be introduced in the next sub-section. 5.2.2 Procedures of circuit modeling In this section, the focus is on the procedures to derive the LME model. The approaches to circuit modelling in the quasi-static and wave range have been extensively studied, and are not treated again in this thesis. Electrical component St ell w ot sn i e n tur w uc kno Str ruc tu kn re is ow w n ell Circuit model for one section EM field kth-order circuit model Fig.5–5: General ways to obtain an LME model of an electrical component As addressed in the last section, the LME model refers to the circuit model that usually consists of more than one element per physical component. In this thesis, the order of circuit model indicates the sophistication and complexity of the required model. The zero-order circuit model often refers to perfect conducting lines. The first-order circuit model is the lumped element model of a physical component in the static and quasi-static case [Maq72]. The LME model refers to the model with an order equal to or larger than 2, but not very high. The continuous model has an infinite order. Generally speaking, there are two ways to obtain the LME model of a component, as shown in Fig.5–5. The LME model is called the kth-order circuit model in the figure. If the physical structure of the electrical component is well known and studied, such as the parallel-plate 120 Parasitic modeling in case of the fast transient EM field transmission line, the lumped circuit model is already known. Then, the circuit model can be derived just by adding more elements to the model until it sufficiently describes the terminal voltage-current characteristics of the component. However, if the physical structure of the component is not well known, the EM field associated with the structure has to be calculated as a first step. The LME model can only be derived from the results of the field. Electrical component Electrical component kth-order circuit model k starts from 0 External excitations + External excitations k=k+1 ∆v(t) < error ∆i(t) < error + Full wave solutions: E(x,t), H(x,t)... v(x,t), i(x,t)... No Distributed element model Yes kth-order circuit model (a) kth-order circuit model (b) Fig.5–6: The procedures to obtain an LME model of an electrical component, (a) the structure is well known; (b) the structure is not well known Fig.5–6 details the procedures to obtain the LME model for an electrical component. The electrical structure should be given in the beginning. If the structure is well known, the kth-order circuit model can be established by adding elements one by one. Usually, the process can start from, for example, the zero-order circuit model, which for a lossless transmission line can be a capacitor or inductor. Whenever the kth-order circuit model is obtained, the terminal voltage and current of the component in a circuit can be calculated based on Kirchhoff voltage and current laws. Then, the voltage and current obtained in kth-order circuit model are compared with that obtained in (k-1)th-order model. If the difference is within the required error, then the kth-order circuit model is accurate enough to describe the circuit attributes and the increase of the order is stopped. If not, the order will be increased until the difference meets the criterion. Chapter 5 121 If the structure is not well known, the EM field associated with the structure has to be calculated as a first step. To do that, the initial and boundary conditions have to be known, which are usually given by the external excitations. The time-varying fields can always be obtained by solving Maxwell’s equations with full wave solutions. Analytical solutions can be obtained for simple structures, the number of which is quite limited. For most structures, numerical calculation has to be performed. The calculation can be very mathematically complex [Sch08]. However, the exact solutions of fields and other quantities, such as voltage and current, can be obtained after the calculation. Based on the results, the continuous model can be derived. After that, the continuous model can be simplified as LME model if the frequency is in the intermediate range and if it is necessary. Electrical structure External excitations + Power series solutions: E(x,t)k, H(x,t)k... v(x,t)0..k, i(x,t)0..k... k=k+1 H(x,t)k/H(x,t)k-1 < error E(x,t)k/E(x,t)k-1 < error or v(t)0..k -v(t)0..k-1 < error i(t)0..k -i(t)0..k-1 < error No Yes kth-order circuit model Fig.5–7: The procedure, including the power series approach, to obtain an LME model of an electrical component The mathematical complexity of solving Maxwell’s equation in full wave solutions can be quite high for a complex structure. In addition, it is sometimes not necessary to run the full wave calculation for a system with sufficiently low frequency. Thus, a mathematically more simple method was proposed to calculate the time-varying fields in systems having quasi-static or intermediate behavior [Maq72]. The method is called the power series approach. Appendix 122 Parasitic modeling in case of the fast transient EM field B introduces this method. Fig.5–7 shows the basic procedure to calculate the fields and derive the LME model. To put it simply, by this approach, the electric (E) and magnetic (H) fields as well as other field quantities, such as charge ρ, are expanded into power series. In general, the field quantities, such as E, H, ρ, can be expanded into the frequency domain For example: ∞ E( x, y, z , t ) = ∫ E( x, y, z, ω )e jωt dω −∞ (5.1) Thus, they can be expressed as a function with five independent variables, x, y, z, ωt and ω, as: E( x, y, z , ωt , ω ); H ( x, y, z , ωt , ω ); ρ( x, y, z, ωt , ω ); (5.2) where x, y, z are the spatial variables, t is time variable, ω is the frequency variable. The frequency ω appears twice in the functional dependence of the fields. The behaviors of fields that oscillate in time are influenced by the product of variables ω and t. The behaviors of fields that change their shapes in space at a fixed time t are influenced by the variable ω. In other words, the amplitudes (or overall shape) of the fields depend directly on the particular frequency ω at which the fields spatially oscillate. This dependence is the key knowledge behind the electrical size that determines the circuit models. By expanding each field amplitude at a fixed point in time and space into power series in ω, the knowledge underlying for the relation between electrical size and circuit models can be discovered. The expansion of the power series is around ω = 0. After the expansion, each quantity can be expressed as: E( x= , y, z ,τ , ω ) E0 ( x, y, z,τ ) + E1 ( x, y, z,τ , ω ) + E2 ( x, y, z,τ , ω ) + ⋅⋅⋅ (5.3) H (= x, y, z ,τ , ω ) H 0 ( x, y, z ,τ ) + H1 ( x, y, z,τ , ω ) + H 2 ( x, y, z,τ , ω ) + ⋅⋅⋅ (5.4) where τ = ωt. Each of the terms in the above expansion represents one order of the field. Generally, they can be expressed as: = E( x , y , z , τ , ω ) ∞ ∑ E ( x, y , z , τ , ω ) k =0 = H ( x, y , z , τ , ω ) k ∞ ∑H k =0 k ( x, y , z , τ , ω ) k = 0,1, 2, ⋅⋅⋅ (5.5) k = 0,1, 2, ⋅⋅⋅ (5.6) where Ek and Hk are the kth-order of the electric and magnetic fields, respectively. It is noticed that there is no variable ω in each zero-order field. Chapter 5 123 By the power series approach, it can be found that the kth-order electric field is determined by the time derivative of (k-1)th-order magnetic field as: ∇ × Ek = − ∂B k -1 ∂t (5.7) Other quantities have similar relations, which are shown in Table B–1. This basic law in the power series approach requires that the field quantities should in principle be infinitely often differentiable. In practice, the quantities should at least be differentiable in quite a number of orders. In addition, because in most cases numerical computations are performed, any order derivatives of the field quantities should be easily numerically computable. Moreover, the field quantities must be plotted numerically for easy comparison of each order. However, in electric circuits, all the signals start from zero. Thus, the signals and the resultant field quantities contain a step function in their expressions. The derivative of the step function is the delta function, which cannot be numerically plotted [Sch08]. To obtain a high-order circuit model of a given structure, this limitation can be solved by using proper sources. For example, the Gaussian pulse, which can meet the requirements mentioned above, is a good excitation for the computation of the power series approach. The structure of interest in the original circuit can be taken out and be excited with a Gaussian pulse. Then, the high-order circuit model is derived in the new system and will be put back in the original circuit to check whether it is accurate enough. By doing so, electrical structures in any circuits can be modeled by using the power series approach. The series expansion can be obtained starting from the zero-order terms. The zero-order fields and other quantities are basically staticlike, which means that the effects of time-variation of the fields are neglected. Once the zero-order terms are obtained, the first-order quantities can be solved in the same staticlike way. The quasi-static fields are described by the zero-order terms of both E and H fields and the first-order term of one of them. It means that the timevariation of E or H field is neglected, which is exactly the basic definition of quasi static [Kra92]. Similarly, the higher order terms can be calculated step by step. If all the terms in the expansion are solved and summed up, the exact solution of the EM field is obtained, which is the same as the direct wave solution of Maxwell’s equations. However, it is not necessary to calculate all the terms. As shown in Fig.5–7, in each iteration, the kth-order quantities are compared with the (k-1)thorder quantities. If the former quantities are much smaller than the later quantities, the iterative calculations stop. The field quantities up to and including the kth-order quantities can be, in the 124 Parasitic modeling in case of the fast transient EM field end, utilized to derive the kth-order circuit model of a given electrical structure. The iteration does not always converge. In this thesis, only the systems in which the iterative calculations converge are considered. For the rest of the systems, full wave calculation can always be used to solve the fields. Usually, in a system with high frequency, the order of field quantities becomes high when the results should be accurate. However, if the frequency in a system is just in the beginning of the intermediate frequency range, high-order quantities are usually negligible compared to the low order quantities. Thus, limited terms in the right hand side of Equation (5.3) and (5.4) are required for accurate results. From the above introduction, it can be seen that the power series approach actually gives the underlying reasons why the kth-order circuit model is valid for a structure with given electrical size. This is one of the outstanding advantages of the power series approach. The other one is that in the step by step derivation of each order term, the calculations are all staticlike. The mathematical complexity decreases much compared to that of the solution of the partial derivative equations in the full wave approach. Thus, in the numerical calculations, it is possible to save resources and speed up the processes. However, once the required order becomes high, the advantage of low mathematical complexity is lost. Then, the problem can no longer be solved by the power series approach. The approach is suitable for the calculation of fields in the beginning of the intermediate frequency range and for the derivation of LME model. 5.2.3 System with continuous spectrum excitations In this section, the principle to derive the LME model using the power series approach to a system with continuous spectrum excitations is introduced. Reference [Maq72] shows the derivation of the fields and LME models by the power series approach in a system with sinusoidally varying single-frequency fields. The example is also shown in Appendix B.2. The derivation shows that the frequency range in a system and the order of circuit model of a given structure can be estimated by observing the ratio of physical dimensions of the structure l to the wavelength of the frequency λ. The estimation is shown in the last part of Appendix B.2. The ratio l/λ is quite widely used to obtain a quick impression on whether an arbitrary system is in the wave range or in the quasi-static range. However, the wavelength is confusing in a system with continuous spectrum excitations, such as non-periodic excitations. The excitations usually lead to continuous spectrum fields. Chapter 5 125 Consequently, a problem arises regarding which frequency in the spectrum should be used to determine the wavelength λ. Usually a bandwidth is determined and the maximum frequency in the bandwidth is chosen to calculate the wavelength. Fig.5–8 shows a simple system with a pulsed voltage source as: is(t) + 0.318nC vs(t) 0.318nH _ Fig.5–8: A LC circuit with pulsed voltage source vs (t ) =e − at (5.8) t ≥ 0, a =6.3 ×106 By using the Fourier transformation, the voltage source in frequency domain is found as: ∧ vs ( jω ) = 1 a + jω (5.9) -7 |vs(ω)|(V) 1× 10 -8 |is(ω)|(A) 1× 10 1× 10-9 1× 10-10 1× 10-11 1× 107 1× 109 1× 108 1× 1010 f (Hz) Fig.5–9: Magnitude spectrum of the voltage and current The magnitude spectrum is shown in Fig.5–9. If the bandwidth extends to where the magnitude of the voltage source decays to one-tenth of that when ω=0, the maximum frequency in the bandwidth is 100MHz. However, the magnitude spectrum of the current in the system is observed as having a peak at a frequency of 500MHz as shown in Fig.5–9. This is because of 126 Parasitic modeling in case of the fast transient EM field the resonance of the inductor and capacitor. In this simple case, the bandwidths of the voltage and current are different. From this simple example, it can be seen that the bandwidths of different fields or signals can be different in a system that has an excitation with a continuous spectrum. Thus, it is confusing to use the definition of wavelength λ. In this case, to determine the order of circuit model the parameter λ should be defined as the characteristic length of all fields. This is the minimum wavelength in the bandwidths of all fields. What is different from the sinusoidally singlefrequency system is that the characteristic length of the field is difficult to know without the prior knowledge of the circuit models. Thus, the ratio l/λ cannot be obtained to determine the order of circuit model. It is like a chicken-and-egg problem. It makes the ratio l/λ difficult to use to determine the order of circuit model in the continuous spectrum system. However, the power series approach is still valid to derive the LME model in such a system. The iterative calculations of fields and other quantities are the same as shown in Fig.5–7. In a sinusoidally single-frequency system, only the magnitude and phase of the quantities change in the iterations, namely as the order of circuit model increases. The frequency of the field quantities does not change. That is why the ratio l/λ can easily be used to determine the order of circuit model. However, in a continuous spectrum system, the time-domain shapes of the quantities change in the iterations. This further means that their spectra also change. In this case, to determine the order of the circuit model, the voltage and current shapes in time domain should be compared. However, the criteria of the comparison, which are dependent on applications, can be complicated. Rdp + Lpae Coe _ L0/2k L0/2k + vTLin + t=0 Transmission line iTLin C0/k U0 _ U0 L0/2k L0/2k + C0/k _ U0 _ Fig.5–10: An example of capacitor discharging circuit for circuit modeling of the transmission line Chapter 5 127 Fig.5–10 shows an example to illustrate how the voltage and current changes as the circuit model develops in a continuous spectrum system. The basic topology of the circuit is the same as shown in Fig.5–1 (b). The circuit parameters are shown in Table 5–2, Table 5–3 and Fig.5– 11. Table 5–2: Circuit parameters Co1 (nF) Lpa (nH) Rdp (Ω) U0 (kV) 1 300 150 -100 Fig.5–11: Structure of the coaxial cable Table 5–3: Parameters of the coaxial cable a (mm) b (mm) l (m) εr µr 0.5 2.3 1 5.95 1 L0 (nH) C0 (pF) Z0 (Ω) velocity (m/s) Td (delay time) (ns) 302.5 100 55 1.8×108 5.5 The coaxial cable is a typical transmission line. It can be modeled by cascading an infinite number of unit T-networks, which consist of two inductors and one capacitor. Inductance L0 and capacitance C0 are respectively the per-unit-length inductance and capacitance of the transmission line. The increase of the number of T-networks represents the increase of the order of circuit model. The order of circuit model is equal to the sum of the number of 128 Parasitic modeling in case of the fast transient EM field inductors and capacitors. The two inductors that are in the middle of two cascaded T networks are count as one. Before the short-circuiting at the output, the capacitor Co1 and the transmission line have been charged to DC voltage U0. The short-circuiting can be replaced by a step down voltage source, which jumps from U0 to 0 at the end of the line. By means of this replacement, the circuit can be regarded to have a non-periodic voltage source that will stimulate continuous spectrum waves in the system. Through circuit simulation, the input voltage and current of the transmission line can be obtained in the circuits with different order models. The waveforms are shown in Fig.5–12. iTLin 0 continuous model 3rd-order model 0-order model 9th-order model 10ns 20ns t (ns) 30ns 40ns 50ns 40ns 50ns (a) vTLin continuous model 3rd-order model 0-order model 9th-order model 0 10ns 20ns t (ns) 30ns (b) Fig.5–12: Waveforms in circuits with different order models, (a) input currents of the transmission line; (b) input voltages of the transmission line Chapter 5 129 Fig.5–12 shows that the time-domain shapes of voltage and current in the circuit change as the circuit model develops. The high order circuit model results in waveforms that are approaching those generated in the circuit with the continuous model. However, the criteria of accuracy depend on the applications. For example, if the maximum current peak is the performance of interest, then the 3rd-order model is good enough. However, if the maximum voltage peak and first transient time are the most interesting parameters, then the 9th-order model should be utilized rather than the 3rd-order model. In short, in a continuous spectrum system, the overall shapes of fields and other quantities, such as voltage and current, change with the iterations of the power series approach. The iteration can be terminated by comparing the time-domain quantities. The parameters of interest in the comparison are dependent on the applications. 5.3 A single-turn inductor with pulsed source As addressed in the last section, the LME model of an electrical component can be derived through the procedure involving a power series approach. This approach was developed and applied in a sinusoidally single-frequency system in [Maq72]. However, it has not been applied in a continuous spectrum system, which is a more general case. Thus, in this section the derivation of fields and circuit models by the power series approach in a continuous spectrum system will be addressed. σ=∞ x conductor y=-w + vs(t) is(t) _ z=-l K(t) air d Kr(t) K(t) z 2 Kr(t) = e-a(t-t1), at z = 0 y Fig.5–13: The structure of a single-turn inductor The derivation is elaborated for a single-turn inductor, which is used as an example. Fig.5–13 shows the structure, which is the same as that in Appendix B.2. The inductor consists of two perfect conductors, which are perfectly conducting, arranged in parallel and joined at one end by a third perfect sheet. The width and length of the plates are much larger than the separation 130 Parasitic modeling in case of the fast transient EM field distance so that the fields and other quantities inside the configuration are independent on x and y. The E field has only an x component and the H field has only a y component [Maq72]. The inductor is excited by a current source at one end (z=-l) to maintain the reference surface current density: K r (t ) = −i x K r (t ) = −i x exp(−a(t − t1 ) 2 ) ,t ≥ 0 (5.10) at z = 0 where a and t1 are taken as positive, and t1 is time shift from the origin. It should be large enough to make Kr(0) approximately zero. The Fourier transform of the pulse is then given as: ∧ Kr(= jω ) F ( K r (t )) ≈ exp(− jωt1 ) π ω2 exp(− ) a 4a (5.11) The shifted Gaussian pulse is shown Fig.5–14. 1.2 1 1 t1 = 28.5ns 0.8 0.4 F a = 1.23× 10-16 π a 1.5× 10-8 Kr(0) = 4.5× 10-5 0.6 1× 10-8 0.5× 10-8 0.2 0 2× 10-8 a = 1.23× 10-16 e −2 e −4 20 t1 40 4 = ∆t 2 = 36ns a 60 -1000 80 t (ns) -500 0 π a 500 ∆ω= 8 a= 888M 1000 ω (Mrad/s) Fig.5–14: Shifted Gaussian pulse and its Fourier transform The bandwidth is defined by the points where the maximum magnitude falls to approximately 0.01 of the maximum value. The parameter a is set to give a bandwidth of 444Mrad/s, that is 70MHz, as shown in Fig.5–14. Accordingly, the width of the pulse, which is also defined by the points where the maximum magnitude in time domain decreases to its 0.01, is 36ns. The Gaussian pulse is chosen because any of its derivatives can be easily calculated numerically, and in particular, these can be plotted numerically. Other time domain functions of which the derivatives can be easily calculated numerically can also be chosen as the excitations to derive fields by power series approach. We will give one alternative as an Chapter 5 131 example. Fig.5–15: Typical current pulse in RLC discharging circuit and its Fourier transform The Gaussian pulse has similar bandwidth to the exponential current pulse in a typical RLC discharging circuit, as shown in Fig.5–15, if they have the same rise time. The exponential current pulse is given as: = i (t ) m(exp( p1t ) - exp( p2t )) t ≥ 0 (5.12) where m, p1, and p2 are dependent on the values of all the components in the RLC circuit [Kul10]. Next, each order fields and circuit models are derived with the reference kept in a general function in time domain. In the end, the fields are calculated and plotted with the reference as the Gaussian pulse. 5.3.1 Transient EM fields in the inductor All the laws required in power series approach are listed in Table B–1. The key relations in the derivation are given as: ∇ × Ek = − µ0 ∇ × Hk = ε 0 ∂H k −1 ∂t (5.13) ∂E k −1 ∂t th These two equations show that the k -order E and H field are respectively determined by the time derivative of (k-1)th-order H and E magnetic field, which has been obtained beforehand and can be considered as given source terms. Next, the recursive calculation starts from the zero-order fields. 132 Parasitic modeling in case of the fast transient EM field The boundary conditions in the calculations of each order fields are the same as those in the example shown in Appendix B.2, which has been elaborated in [Maq72]. They will not be repeated here. 5.3.1.1 Zero-order fields The zero-order fields can be derived directly from the current excitations. The surface current flows in a clockwise direction. The zero-order field relations are identical in form to their static counterparts, thus the zero-order fields can be derived based on the rules obtained in the static field. The H0 and E0 fields are given as: 5.3.1.2 H 0 (t ) = −i y K r (t ) (5.14) E0 ( t ) = 0 (5.15) First-order fields Once the zero-order H0 field is obtained, the first-order E1 field can be derived from the zeroorder sources as: ∇ × E1 = − µ0 ∂H 0 ∂t (5.16) Since the E field only has an x direction component, then: iy ∂E1x dK (t ) = i y µ0 r dt ∂z (5.17) From the boundary conditions, the solution of first-order E1 field can be found as follows: E1 ( z,t ) = i x µ0 z dK r (t ) dt (5.18) Since the E0 field is zero, there are no zero-order charges on the plate. This further leads to the first-order surface current density being equal to zero. Thus, the first-order H field is given as: (5.19) H1 (t ) = 0 Consequently, the resulting fields of the inductor correct up to and including the first-order terms are: E0,1 = E0 + E1 = i x µ0 z dK r (t ) dt H 0,1 = H 0 + H1 = −i y K r (t ) (5.20) (5.21) Chapter 5 133 Further, the source voltage and current can be obtained as: d dK (t ) − ∫ mag(E0,1 ) z = − l dx = µ0 ld r vs (t )0,1 = dt x =0 w is (t )0,1 = − ∫ mag(H 0,1 ) z = − l dy = wK r (t ) (5.22) (5.23) y =0 The voltage and current in frequency domain can then be obtained as: ∧ ∧ Vs ( jω )0,1 = j µ0 ld ω K r ( jω ) ∧ ∧ I s ( jω )0,1 = w K r ( jω ) (5.24) (5.25) Further, the first-order input impedance is obtained as: ∧ Vs ( jω )0,1 µ ld = j= ω 0 Z= jω LDC in ( jω )1 ∧ w I s ( jω )0,1 ∧ (5.26) Obviously, the impedance represents a DC inductor as defined in the static case. The result is basically the same as that obtained in a sinusoidally single-frequency system, as shown in Equation (B.29). The difference is that there ω is a fixed frequency determined by the sinusoidal source, while here ω can represent any frequency in a continuous spectrum of the source. 5.3.1.3 Higher-order fields When the first-order E1 field has been obtained, the second-order H2 field can be derived based on the law: ∂E1 ∇ × H2 = ε0 ∂t (5.27) Since the H field has only a y direction component, then: ∂H 2y d 2 K r (t ) ∂E1x −= ix i= i x ε 0 µ0 z xε 0 dt 2 ∂z ∂t (5.28) The boundary conditions for the H2 involve the second-order surface current density K2. This can be obtained from the E1 field [Maq72]. Equipped with the boundary conditions, the solution of the H2 field can be obtained as: H 2 ( z , t ) = − i y ε 0 µ0 z 2 d 2 K r (t ) 2 dt 2 (5.29) 134 Parasitic modeling in case of the fast transient EM field Because the first-order H1 field is zero, the second-order E2 field is curl- and divergence-free. In addition, the tangential component of E field at z=0 should be zero. Thus, the E2 field all over the structure should also be zero, which is given as: E2 ( t ) = 0 (5.30) Following the same pattern as before, the kth-order Ek and Hk field can be obtained as: Ek ( z= , t) ix k µ0 ( ε 0 µ0 z ) d k K r (t ) dt k k! ε0 H k ( z , t ) = −i y ( ε 0 µ0 z ) k d k K r (t ) k! dt k By replacing Kr(t) with Acosωt, Equations = k 1,3,5 ⋅⋅⋅ k = 0, 2, 4 ⋅⋅⋅ (5.31) (5.32) (5.31) and (5.32) directly become the results obtained in the sinusoidal system, as shown in Equations (B.37) and (B.38). 5.3.1.4 Total EM fields When the fields in each order have been obtained, the exact E and H fields are respectively given by infinite sums over the terms of each order and are given as: E( z= , t) ix k µ0 ∞ ( ε 0 µ0 z ) d k K r (t ) ∑ dt k ε 0 k =1 k! ( ε 0 µ0 z ) k d k K r (t ) k! dt k k =0 ∞ H ( z , t ) = −i y ∑ = k 1,3,5 ⋅⋅⋅ k = 0, 2, 4 ⋅⋅⋅ (5.33) (5.34) From the above equations, the limitations of the power series approach, which have been mentioned separately before, can be listed as: • The source or the field quantities should be, in principle, infinitely differentiable. Any order derivatives should be easily numerically computable. It is also important that they can be plotted numerically. • The power series of the field quantities must converge. • The power series approach is not suitable for high-frequency systems in which accurate field computations require sums of many terms. This can bring more mathematical complexity in computation than the full-wave approach does. Chapter 5 5.3.2 135 LME circuit model The circuit model can be derived from the results of the fields obtained for each order. The source voltage and current correct up to and including the k1th-order can be derived from the corresponding fields as: k µ0 k (− ε 0 µ0 l ) d k K r (t ) k = 1,3,5 ⋅⋅⋅ ∑ ε 0 k =1 k! dt k 1 vs 0..k1 (t ) = −dmag(E( z , t )) = −d (− ε 0 µ0 l ) k d k K r (t ) dt k k! k =0 k1 is 0..k1 (t ) = − wmag(H ( z , t )) = w∑ k = 0, 2, 4 ⋅⋅⋅ (5.35) (5.36) In frequency domain, the voltage and current are given as: k ( − ε 0 µ0 l ) k µ0 ∧ K r ( jω )∑ ( jω ) k ε0 k! k =1 ∧ 1 V s 0..k1 ( jω ) = −d ∧ ∧ k = 1,3,5 ⋅⋅⋅ ( − ε 0 µ0 l ) k ( jω ) k = k 0, 2, 4 ⋅⋅⋅ k! k =0 k1 jω ) w K r ( jω )∑ I s 0..k1 (= (5.37) (5.38) The k1th-order input impedance is the result of the frequency domain voltage over the current. The general expression of the input impedance is given by putting k1 to infinite: ∧ Z in ( jω ) = ∧ Vs ( jω ) ∧ I s ( jω ) ( β l ) + ( β l ) − ⋅⋅⋅ βl − l 3! 5! = jZ = jZ 0 tan(2π ) 0 2 4 λ βl) (βl) ( + − ⋅⋅⋅ 1− 2! 4! 3 5 (5.39) where Z0 = d µ0 w ε0 (5.40) 2π (5.41) λ= ω Obviously, the input impedance is the same as that obtained in the sinusoidally singlefrequency system, as shown in Equation (B.43) except for the meaning of frequency ω. The two impedances refer to the same circuit model for the single-turn inductor. The result shows the common knowledge that the continuous circuit model of an electrical component is independent on the sources. The kth-order LME model can be obtained based on the kth-order impedance. The first- to the fourth-order circuit models are shown in Fig.B–2. 136 5.3.3 Parasitic modeling in case of the fast transient EM field Numerical results In this section, the numerical results of the fields, source voltages and currents obtained in specific structures excited by the shifted Gaussian pulse are shown. By comparing these quantities in time domain, the circuit model in a specific case can be determined. Table 5–4: Parameters of the single-turn inductor w (mm) d (mm) l (m) εr µr 1 0.1 1 1 1 L0 (nH) C0 (pF) Z0 (Ω) velocity (m/s) Td (delay time) (ns) 125.6 88.5 37.67 3×108 3.33 Table 5–4 shows the parameters of a specific single-turn inductor. The E and H fields for each order are shown Fig.5–16. |H0(-l , t)| |H2(-l , t)| |H4(-l , t)| |H6(-l , t)| |H8(-l , t)| Magnitude (A/m) Magnitude (V/m) |E1(-l , t)| |E3(-l , t)| |E5(-l , t)| |E7(-l , t)| |E9(-l , t)| t (s) t (s) Fig.5–16: Magnitudes of E and H fields for each order when l=1m The fields are shown in time domain. It can be seen from the figure that the third-order E3 field is approximately 10 times smaller than the first-order E1 field near its peak. This indicates that the E3 field is small enough to neglect. As a result, the total E field will be approximately equal to the sum of the E1 and the E3 or only to the E1. The higher order E fields can be all neglected in the summation. Similarly, the H field is approximately equal to the summation of the H0 and H2, and the higher H fields can all be neglected as well. Chapter 5 137 is 0(t) is 0..2(t) is 0..4(t) is 0..6(t) is 0..8(t) Current (A) Voltage (V) vs 0,1(t) vs 0..3(t) vs 0..5(t) vs 0..7(t) vs 0..9(t) t (s) t (s) Fig.5–17: Source voltages and currents up to and including different orders when l=1m Fig.5–17 shows the source voltages and currents correct up to and including certain order fields. The results follow from the analysis above. The voltage and current based on the sum of zeroorder and first-order fields are denoted as vs 0,1(t) and is 0,1(t), respectively, and marked as red curves. The quantity is 0,1(t) is the same as is 0(t) as there is no first-order H1 field. There are only small differences around the peaks between the vs 0,1(t) and vs 0,3(t) as well as the counterpart of the current. Regarding the voltage and current related to the higher order fields, they cause hardly any difference from vs 0,3(t) and is 0,3(t). Based on the principle of power series approach, the results show that for l = 1m the first-order circuit model is good enough for the single-turn inductor. Precise results can be obtained if the third-order LME model is applied. The precision is dependent on the applications. The above voltage and current waveforms derived through the power series approach can be checked against circuit analysis in numerical circuit simulators, such as LTSPICE. (a) 138 Parasitic modeling in case of the fast transient EM field ir(t) (A) is(t) (mA) vs(t) (V) t (ns) t (ns) (b) Fig.5–18: The source voltage and current by circuit simulation, (a) circuit topology in LTSPICE; (b) waveforms Fig.5–18 shows the circuit in the simulator LTSPICE. The lossless transmission line model in the simulator directly follows the analytical continuous model. Thus the voltage and current obtained in the circuit are the exact solutions rather than approximate power series solutions. In the theoretical derivation of fields and other quantities by the power series approach, the current at the terminated sheet of the inductor is maintained as reference, which can’t be realized in LTSPICE. Thus, the check is done in another way. In the simulator, only the source current is(t) can be determined by the user. It is adjusted by observing the output current ir(t). The current is(t) in Fig.5–18 (b) is determined when the output current ir(t) is the same as the reference current Kr(t) shown in Fig.5–14. Then the source voltage is compared with the result obtained through the power series approach. Only when the LME model can reproduce the continuous model well, can the source voltage, source current and the terminated current match each other. Fig.5–18 (b) shows the well-matched waveforms, which can be compared to vs 0,3(t) and is 0,3(t) in Fig.5–17 and the shifted Gaussian pulse in Fig.5–14. This proves that the third-order circuit model, which contains two inductors and one capacitor shown in Fig.B–2, is accurate enough to replace the continuous mode in this case. This result can be also demonstrated in LTSPICE by replacing the continuous model with the third-order circuit model. It leads to the same waveforms. For a length l of 3m, the fields as well as voltage and current are recalculated by the power series approach. The results are shown in Fig.5–19. Chapter 5 139 |H0(-l , t)| |H2(-l , t)| |H4(-l , t)| |H6(-l , t)| |H8(-l , t)| Magnitude (A/m) Magnitude (V/m) |E1(-l , t)| |E3(-l , t)| |E5(-l , t)| |E7(-l , t)| |E9(-l , t)| t (s) t (s) Fig.5–19: Magnitudes of E and H fields in each order when l=3m is 0(t) is 0..2(t) is 0..4(t) is 0..6(t) is 0..8(t) Current (A) Voltage (V) vs 0,1(t) vs 0..3(t) vs 0..5(t) vs 0..7(t) vs 0..9(t) t (s) t (s) Fig.5–20: Source voltages and currents up to and including different orders when l=3m Obviously, more terms in the series expansion should be included to find the accurate results for the fields as well as for the voltage and the current than those when l=1m. Here, the 9thorder E fields become approximately 4 times smaller than the 7th-order E fileds around its peaks. Higher order E fields can become even smaller and can be neglected. It can be observed in Fig.5–20 that the shapes of vs 0..9(t) does not change compared to vs 0..7(t), while the current is 0..8(t) still changes quite a bit compared to the current is 0..6(t). To obtain more accurate results, more orders of the field should be included in the expansion. The maximum frequency in the bandwidth of the reference pulse Kr(t) is 70MHz as defined at the beginning of this section. The resultant period is 14.3ns. The length 1m corresponds to 3.33ns propagation time of fields and 3m relates to 10ns in the inductor. Based on the experience obtained in the sinusoidally single frequency system, the order of circuit model can be judged by directly looking at the ratio l/λ. Then a 1m inductor has the ratio 0.23 and 3m inductor has the ratio 0.7. Based on Fig.B–3, the series expansion of fields that are correct up 140 Parasitic modeling in case of the fast transient EM field to and including the third-order fields can lead to an accurate result in the 1m case. However in the 3m case, the series expansion of fields that are correct up to and including the ninth-order fields can still not be accurate enough for the complete solution. The facts are the same as those obtained in the continuously spectrum system. The coincidence is due to the fact that all the field quantities in the single-turn inductor with pulsed source have similar bandwidths as the source. The coincidence is not valid for all given systems. However, the ratio l/λ based on the minimum wavelength in the bandwidth of the given source can be used to gain a quick impression of a system and how many order circuit models are required. The accurate order of the circuit model should be obtained through the iterative calculations required by the power series approach for less well-known structures. 5.4 The modeling of parasitics in the multiplier module In the previous sections, the power series approach and the procedure that describes the approach to obtain the LME model of an electrical component are introduced. In this section, the procedure will be applied to the multiplier module to obtain the LME model of the structural parasitics at a modular level. 5.4.1 Modeling of a structure without sources at terminals The circuit modeling of the multiplier module can be complex because: 1. It has a complicated 3D structure. 2. There are multi terminals of the multiplier. 3. There are no sources connected to terminals. irect+ . 2 C1 iD1 . D1 4 . iD2 D2 Co1 io iCo1 D1_1 irect- 3 5 C1_1 iD2_1 iD1_1 D2_1 Grounded container Multiplier module (a) t=t1 Rdp 1 RL Chapter 5 141 Container capacitors DC out DC in 4 diodes AC + 2 1 AC- 3 5 (b) Fig.5–21: A one-stage multiplier module for parasitic modeling in the transient case, (a) circuit diagram; (b) structure of the module Fig.5–21 shows a one-stage multiplier for parasitic modeling in the transient case. The circuit and the transient behaviors were shown in Section 2.5 in Chapter 2. After the output is shorted at time t1, current pluses will be present in the transient period, as shown in Fig.2–25. In different transient intervals, there are different branches in the multiplier that conduct the current. The structures inside the module can therefore be considered being different during different time intervals. However, the principle of circuit modeling is the same. Thus, next, the structure in the transient interval 3 will be taken as an example to conduct the modeling. In this thesis, only the spatial structure, including the component packaging, layout and the module construction, is considered for the parasitic modeling. The parasitics of the components are excluded because they can be found in the datasheet of the manufacturer. Fig.5–21 (a) exhibits the circuit diagram. It is crucial to emphasize that the capacitor and diode in the multiplier represent several components connected in series, in practice due to high voltage. This can be observed in the PCB layout shown in Fig.5–21 (b). In the transient interval 3, the current flows through terminal 1 into the multiplier. Three branches are present in the multiplier for the current. One consists of the diode D2 and capacitor C1 and terminal 2. One consists of the diode D2_1 and capacitor C1_1 and terminal 3, and, the other consists of the capacitor Co1 and terminal 4. Then the current flows out of the multiplier to the external circuit and then the ground. The container is connected to the ground through terminal 5 to maintain zero potential for safety. 142 Parasitic modeling in case of the fast transient EM field is1(t) 1 External circuit is2(t) 2 3 Multiplier module is3(t) 1 2 3 4 4 5 5 (a) Multiplier module (b) Fig.5–22: Block diagram of the multiplier module and the external circuits, (a) the module with no sources connected to the terminals; (b) the module with current sources connected to the terminals The procedure to obtain the LME model starts with the given electrical structures and external excitations. The structure of the multiplier module is already known. However, there are no sources directly connected to the terminals of the multiplier module as shown in Fig.5–22 (a). This further means that there are no fixed voltage or current as references in the iterative calculations of the power series approach. Thus, to obtain the kth-order fields and other quantities, the whole external circuit has to be combined with (k-1)th-order terminal voltage and current to perform the calculation. The mathematical complexity depends much on the complexity of the external circuit, which can be very high. A simple method is proposed to solve this problem. The principle is that, in most cases, circuit models of a structure do not depend on the external circuits. Thus, the multiplier module can be taken out of the original system and be connected to simple voltage or current sources at the terminals. In the case of the one-stage multiplier module, current sources are added, as shown in Fig.5–22 (b). Three current sources are connected between terminal 5 and terminals 1, 2, 3. Terminal 4 is directly connected to terminal 5 according to the real connection in the multiplier. It is important that in the new system, the sources should not over-constrain the system. The source can be single-frequency sinusoidal or pulse. In both cases, the circuit models in different orders can be derived. However, Gaussian pulse is preferred because it resembles the real current pulse in the multiplier better than the sinusoidal current source. Then, the circuit models are put back into the original system to perform the circuit calculations, which are usually done in a circuit simulator. By comparing the time-domain voltage and current waveforms, the order of the circuit model can be confirmed. Chapter 5 143 (a) (b) Fig.5–23: Circuit connections that should be avoided It should be emphasized that two basic laws should not be broken when connecting the sources to a structure. They are that the voltage source should not be shorted and the current source should not be opened, as shown in Fig.5–23. Otherwise, infinite high current and voltage will be obtained in the subsequent calculations, which brings mathematical problems. Structure Structure Fig.5–24: A limitation of connections of different external circuits to a structure There is another issue when connecting a structure to external sources. If a structure in original system has two open-ended terminals, it is preferred that they are not shorted in the new situation, as shown in Fig.5–24. People usually do not intend to do this. However, it is important to mention that the low-order circuit models can be different, especially the circuit model in quasi-static range. For example, if the structure is a set of two-parallel plates, which are perfect conductors, the quasi-static circuit model is a capacitor. However, if the plates are connected with a current source at one end and are shorted at the other end, then the quasistatic model becomes an inductor, as discussed in the last section. Thus, in the low-frequency case, the conversion shown in Fig.5–24 can generate mistakes. However, in the high-frequency case, as the order of the circuit model increases, the difference in the circuit models that are developed in both configurations becomes small. 144 5.4.2 Parasitic modeling in case of the fast transient EM field Procedure for modeling the parasitics This section addresses the procedure of modeling the parasitics in the multiplier module. The key step, which is the field calculation by the power series approach, is basically the same as that applied in the single-turn inductor. However, for the multiplier module, simplification of the 3D structure is necessary first. In addition, the extraction of the circuit model based on the field results can be more complex than the simple case. 5.4.2.1 Simplification of the structure z=0 is2(t) 2 iD2(t) 4 iCo1(t) is1(t) io(t) is3(t) 3 iD2_1(t) 1 y 5 z x Fig.5–25: Simplification of the structure of the multiplier module The real structure of the multiplier model, as shown in Fig.5–21 (b), is complicated. Thus, simplification of the structure is necessary. Fig.5–25 shows the simplification. The three conducting branches in the transient interval 3 are simplified as three perfect conducting lines. The three lines simply represent the package of the components and the connecting traces on the PCB or other wires. The thickness and width of the connections are eliminated. The focus is on structural parasitics, thus the discrete components in the conducting branches are neglected as well. Chapter 5 145 Point charge Reference position of line current Fig.5–26: Discretization of the structure Fig.5–26 shows further simplification of the three perfect lines for the calculation of EM fields. The lines are chopped into pieces. The pieces are simplified as point charges and line currents, respectively, for electric and magnetic field calculation. The black dots in the figure show the reference positions of the line currents when they are used as source for magnetic field calculation. With this simplification, the static-like calculation of the fields in each iteration of the power series approach can be done in the simplest ways. The zero-order electric field can be calculated with the adapted Coulomb’s law that is suitable for E field in a grounded container. The magnetic field can be calculated with the Biot-Savart law [Kra92]. 5.4.2.2 Field calculation Once the structure and external excitations have been obtained, the field calculation can start. The steps are the same as those carried out in the simple-turn inductor. Firstly, the zero-order fields need to be calculated. Since the currents in the structure have already been given and the container is not present as a boundary for the zero-order magnetic field H0, it can be easily obtained from the Biot-Savart law. There is no electric field E0, which is the same situation as that in the single-turn inductor. According to the past experience, there should be no first-order field H1 in the container. To obtain the E1 field, the first-order laws can be utilized, which are shown below: ∇ × E1 = − µ0 ∂H 0 ∇ ⋅ E1 = 0 ∂t (5.42) (5.43) Since H0 has been obtained, the term with the time-derivative of H0 can be considered as a given source of the E1 field. Then the E1 field has the same mathematical equation as the static 146 Parasitic modeling in case of the fast transient EM field magnetic field generated by a steady current. This indicates that the Biot-Savart law may be valid to obtain E1. However, the boundary conditions for E1 are different from those for H0 because of the grounded container. Thus, the Biot-Savart law may have to be adapted for the E1. Once E1 is obtained, the first-order surface charge and surface current on the container can also be obtained. Once the first-order fields and other quantities are obtained, the second-order field H2 can be obtained by regarding the term with the time-derivative of E1 as given source. Unlike the H0 field, the container has first-order surface current, which adds boundary conditions for H2. Thus, the Biot-Savart law also needs to be adapted for the H2 field in the grounded container. Once the analytical equations have been developed for E1 and H2, the higher order fields can be obtained in the same pattern in an iterative way. The development of the analytical equations to solve E1, for example, and the numerical computation of the fields in each order are part of future work. 5.4.2.3 Extraction of the LME model Once the fields and quantities, such as terminal voltage, are obtained in the multiplier, the circuit model of the parasitics can be derived. From the experience in the single-turn inductor, the input impedance can be obtained from the terminal voltage and current. However, in the case of the multiplier, there are several drawbacks associated with the input impedances. 1. The multiplier module is a 5-terminal network. The network can be described by an impedance matrix, which is well known as the H parameter for two-port networks. It can be complex to obtain the circuit model based on the impedance matrix through circuit synthesis [Ver82]. 2. The impedance matrix at the terminals can only reflect the terminal characteristics, but leave the element topology inside the structure unknown. It can be interesting in some applications to know where the large parasitics are located inside the module. Thus, another simple way is proposed to obtain the LME model of the structure from the field results. This involves the division of the entire space associated with the structure into subspaces, in which the fields have no phase shift with the physical size. It further means that in each sub-space, the structure can be modeled as a lumped element model, defined by: Chapter 5 147 Sub-space Sub-space l S E field H field l Q I S Fig.5–27: Calculation of capacitance and inductance in one sub-space C= Q = V ε ∫∫ E ⋅ dS S (5.44) ∫ E ⋅ dl l φ L= = I µ ∫∫ H ⋅ dS S (5.45) ∫ H ⋅ dl l where S is a closed surface in the E field case that encloses the charge, and is a surface in the H field case that covers the inductance loop of interest. Moreover, l is the contour for the line integral of the E and H fields. Fig.5–27 shows the principle to calculate capacitance and inductance in one sub-space. The calculations of the capacitance and inductance are based on their definition in the static field. Here, only the principle is shown. However, in a specific structure, the division of the entire 3D space can be complex if the spatial distribution of fields is complicated. This is part of future work. The principle of this approach is similar to the idea of the finite element (FE) method. It has to be emphasized that this approach is only effective in a structure where the frequency is in the intermediate range, because the amount of the sub-spaces then stays small. Otherwise, once the frequency is so high that the characteristic length of the field is very close to or smaller than the physical dimensions, the dimensions of the sub-spaces can be so small that too many element models must be present in the network. In this situation, the mathematical complexity can be high. 148 Parasitic modeling in case of the fast transient EM field 5.5 Conclusion A theoretical development is presented for the circuit modeling of an electrical component or system in the beginning of the intermediate frequency range, which is just above the quasistatic range. The procedure includes the power series approach and it is mathematically simple to obtain the LME model compared to the full wave approach. The iterative static like calculations of fields and other quantities decrease the mathematical complexity of the power series approach. In addition, it gives the underlying reason why the kth-order circuit model is valid for a structure with given electrical size. The extension of the power series approach to continuous spectrum systems provides an extension from sinusoildally single frequency systems towards real cases involving pulsed quantities. In such a system, the different orders of time-domain fields and other quantities should be compared to determine the number of the iterative calculations, and this further determines the order of the circuit model. The single-turn inductor with pulsed source demonstrates the steps of the procedure. The modeling of the parasitics in the multiplier shows how to perform the power series procedure in a general electrical structure that has multiple terminals and 3D complicated geometry. The work serves as theoretical foundation for future circuit modelling in specific applications. The circuit modeling in high frequency range is not limited to the applications of shortcircuiting. It becomes more and more significant in power electronics since the switching frequency keeps rising. Particularly, the emerging applications of wide band semiconductors, such as SiC and GaN, will definitely push the frequency of converters to a much higher level compared to the Si devices. It is inevitable that there will be problems when modelling the parasitics in the high frequency range in the future applications in power electronics. Chapter 6 Conclusions and recommendations 6.1 Conclusions As mentioned in Chapter 1, parasitic related issues in the HV multiplier module of the HV generator in medical X-ray machines are addressed in this thesis. As a result of the inevitable replacement of Si devices by wide bandgap devices such as SiC diodes, the HV generator will have increased switching frequency and reduced volume. The trends will probably result in a stronger influence of parasitics on circuit operations, which is often omitted in the design. In the thesis, fundamental researches on the modeling of parasitics in a symmetrical C.W. multiplier at modular level are described. There are three objectives in the thesis, which are to determine the influences of the parasitic capacitances on the steady-state circuit operations, to contain the electric field strength in the module, and to model the parasitics in case of the fast transient EM field. The objectives are fulfilled through detailed research into the following three aspects. Parasitic capacitances in the multiplier module in the steady state (Chapter 3): In Chapter 3, parasitic capacitances of the multiplier module are described. The role of the parasitic capacitances in the circuit operations is firstly determined. Then, the complete model of the parasitic capacitances is established and the equivalent parasitic capacitance Cem is analyzed in detail. Based on the analysis, the approaches to minimize the capacitance Cem are proposed. Finally, the capacitance Cem is compared in the modules utilizing Si and SiC diodes respectively. The main findings are listed below. • Role of the parasitic capacitances The parasitic capacitances in the multiplier module are part of the parallel resonant capacitance in the LCC. They make the resonant frequency of the LCC lower than the designed one if 150 Conclusions and recommendations omitted, which can further change the designed circuit behavior. Consequently, it is crucial to minimize them. • Complete model of the parasitic capacitances A complete model of the parasitic capacitances is proposed for any configuration of the multiplier module. It gives a full description of the distribution of the parasitic capacitances. Based on the model, analytical analysis can be conducted on the equivalent parasitic capacitance of the multiplier Cem, as it is convenient to quickly estimate the magnitude of Cem before designing the physical module. The capacitance Cem can be regarded as two capacitances in parallel, which are the linear capacitance Cppgt and the non-linear total chain capacitance CDcht. The two parts should be decreased respectively to minimize the equivalent parasitic capacitance Cem. • Dependence of the total chain capacitance CDcht on different parameters There are four parameters that determine the total chain capacitance, which are the junction capacitance of diodes Cj, structural capacitance Cdg, Cdpp and the number of diodes per chain nd. The capacitance CDcht is proportional to the three parasitic capacitances. However, as nd increases, it decreases if nd is small enough, and it increases if nd is large enough. The number nd should be judged by considering the junction capacitances and structural capacitances to determine whether it is sufficiently small or large. The dependence on nd yields important criteria to determine the approach of minimizing the capacitance CDcht. In addition, the effect of breakdown of diodes on the capacitance CDcht is also investigated. This increases the capacitance CDcht without changing the dependence of CDcht on the four parameters. • Minimization of the equivalent parasitic capacitance Cem The guidelines and the procedure for the minimization are proposed. These can help designers complete the minimization step by step. The push-pull and output capacitors with small surface size are always preferred for minimum capacitance Cppgt. The number nd should be checked before minimizing the capacitance CDcht. If the number nd is sufficiently small, like in the multiplier with HV SiC diodes, diodes with small junction capacitance should be picked. If it is sufficiently large, like multipliers with Si diodes, the spatial structure of the multiplier module should be carefully designed to decrease the structural capacitances. Otherwise, both aspects should be considered. Chapter 6 • 151 Comparison of the capacitance Cem in the module with Si and SiC diodes The volume reduction of the multiplier module by employing SiC diodes does not necessarily lead to higher capacitance Cem. The capacitance Cem depends on the junction capacitance, the structural capacitances and the number of diodes per chain. It is difficult to make a quick accurate comparison of the magnitude of the capacitance Cem in the modules with Si and SiC diodes. However, a rule of thumb can be used for a quick estimation. If the output voltage of the multiplier is known, the diodes with extremely high breakdown voltage or low breakdown voltage can lead to high capacitance Cem. By using the diodes with breakdown voltage in between, it is possible to lower the capacitance Cem. Electric field in the multiplier module in steady state (Chapter 4): Because there are strong electric fields in the HV multiplier module, they should be contained to avoid breakdown of the insulation oil in the grounded container. In Chapter4, a simple shielding technique is introduced for use in the field reduction. Firstly, the distribution of the electric field strength is analyzed based on the results obtained through 3D FE field simulation. The distribution can be expressed as a function containing parasitic capacitances. Then, a simple shielding technique is proposed to reduce the field based on the expression. The main findings are listed below: • Distribution of the electric field strength The distribution of the field strength is studied in a 4-stage symmetrical C.W. multiplier module. The strongest spatial electric field is present in the space close to the diodes and the soldering pads. The high electric field strength is caused by the large voltage difference between the diodes and the grounded container. The volume reduction in SiC-type module can lead to a slighter larger structural capacitance Cdg than that in Si-typed module, meanwhile the voltage vdg is kept the same in the two modules. Thus, the volume reduction in the SiC-typed module will not significantly increase the highest field strength. • Reduction of the field strength A simple approach is proposed to reduce the electric field. The approach is to add a shielding metal with proper voltage near the space where the strong field is present. Simulation results show that the field can be reduced by applying this approach. The push-pull and output 152 Conclusions and recommendations capacitors in the multiplier work as shielding metals. Good layout of them can help to reduce the field strength. Parasitics in the multiplier module in the fast transient period (Chapter 5): In Chapter 5, the theoretical principle of circuit modeling of the parasitics in the intermediate frequency range is addressed. In this range, the low-order lumped element model is not accurate enough and the high-order LME model is required. The power series approach is utilized for the circuit modeling. The approach is extended from the sinusoidally singlefrequency system to the continuous spectrum system for general applications. A simple case of inductor demonstrates the procedures to obtain the LME model through the power series approach, and the key steps are addressed to obtain the parasitics in the multiplier module. The main findings are listed below: • The procedure of circuit modeling in the intermediate frequency range The general procedures of circuit modeling are briefly reviewed. In the beginning of the intermediate frequency range, namely just above quasi-static range, the procedure that includes the power series approach is mathematically simpler for obtaining the LME model than the one that contains the full wave approach. The iterative staticlike calculations of fields and other quantities can to a large extent decrease the mathematical complexity of computation in the power series approach. In addition, it reveals the underlying reason why the kth-order circuit model is valid for a structure with given electrical size. • Application of power series approach in the continuous spectrum system The power series approach has so far only been applied in the sinusoidally single-frequency system, which puts limitations on its applications in reality. The extension of the power series approach to the continuous spectrum systems gives generality to the applications. In such a system, the subsequent time-domain fields and other quantities should be compared to determine the number of the iterative calculations, which further determines the order of the circuit model. • The procedure of circuit modeling of the parasitics in the multiplier module The procedure to obtain the LME model has been demonstrated in a single-turn inductor with pulsed source. The circuit modeling of the parasitics in the multiplier module is basically the same. However, the computation, which can only be conducted numerically, will be much Chapter 6 153 more complex than that in the case of the inductor. The key steps have been addressed. The detailed computation and results will be part of the future work. 6.2 Recommendations for future research In this thesis, parasitic related issues in the HV multiplier module are addressed. Some aspects can be improved for better results. Besides, the approaches contained in this thesis can be used in other applications in power electronics. The recommendations are listed below. Practical design guidelines for the multiplier module with SiC diodes The approaches and findings addressed in this thesis are applicable in the multiplier module both with Si and SiC diodes. It will be interesting to make an overall comparison regarding the parasitic related issues between the modules with the two types of diodes. It will be valuable to obtain conclusions on the issues specifically in the module with SiC diodes, which can much help the design. General numerical computation program for circuit modeling in intermediate frequency range The fundamental theory has been developed for circuit modeling in the intermediate frequency range. The theory can reduce the mathematical complexity of deriving the LME model compared to the conventional full-wave computation. Thus, it can be of much interest to develop a general numerical computation program based on the theory for circuit modeling of given 3D structures in this frequency range. It may even be possible to develop commercial software after completion of the program. More experimental results The electric field strength is simulated during the study. It will be interesting to validate the simulation results by measurements of the field, which can be difficult. Besides, the theory and approaches of circuit modeling of the parasitics in the fast transient period is proposed. It will also be interesting to obtain the parasitics and examine their influences on circuit operations in the fast transient period. It would be interesting to conduct short-circuit experiments to validate the analysis, which is also difficult. Extension of the approaches to other systems in power electronics 154 Conclusions and recommendations The application of wide bandgap semiconductors, such as SiC and GaN MOSFETs, and the increase of the switching frequency, such as to megahertz, are two inevitable trends for the future power electronics [Wyk13][Per09]. The parasitic-related issues will become more important than before in the compact system with high operating frequency. The approaches contained in this thesis show potential to be applied in other power electronics fields. For example, the converters utilizing GaN and MOSFET can easily operate at megahertz due to the fast switch transient [Reu12][Wan14]. The switching speed is capable of reaching 5ns [Abd11]. Consequently, the parasitic inductances in the switching loop become significant and relevant to the circuit performances [Hua13][Liu13]. In such a fast transient, the approaches of the power series approach can be used to obtain the LME model for complex circuit structure for accurate circuit analysis. Another example is the high power motor drives. The parasitic inductances and capacitances coupled in the switching loops usually cause voltage spikes and high-frequency oscillations [Xun13]. As the power capability of the system keeps increasing, the overall module will have a more complicated structure than before. The principle contained in Chapter 3 can be utilized to obtain parasitics at modular level so as to thoroughly investigate their influences. Appendix A Parasitic capacitances in the HV multiplier module A.1 Steady-state operation of the multiplier with parasitic capacitances The steady-state operation of the principle multiplier was introduced in Section 2.5. In this section, the steady-state operation of the multiplier with parasitic capacitances is addressed. Cs irect+ . vcc2+ vcc1+ Cpa Cpa vac+ . iCTS CTS Dch1 Dch4 Dch2 Dch3 vCo1 . CTS vo Cpa vac- Ls Dch1_1 Dch2_1 Cpa Dch3_1 vcc1- vcc2- Dch4_1 Multiplier Fig.A–1: LCC with a two-stage symmetrical multiplier including parasitic capacitances Fig.A–1 shows the diagram of the LCC with the multiplier including parasitic capacitances. The circuit without parasitic capacitance was introduced in Section 2.5. The full-bridge input of the LCC is simplified as a squared voltage source. The parasitic capacitances of the windings of the transformer are added because they are usually utilized as part of the parallel resonant capacitance Cp. In practice, there are many diodes and capacitors connected in series in the multiplier to stand high voltage, which is shown in the figure. In principle, there are 156 Parasitic capacitances in the HV multiplier module parasitic capacitances Cpa between any two electrical nodes in the multiplier. The figure shows some of them as representatives. An assumption is made for the steady-state analysis: 1. The parasitic capacitances in the multiplier are small enough to make sure that the LCC can still enter steady state. It further means that the circuit still has the conductive intervals and non-conductive intervals. In addition, the push-pull and output capacitors can still be charged to have constant voltage, if they are assumed to be large enough. If the assumption is not valid for the LCC with parasitic capacitances, it indicates that the circuit can not operate properly. Then it needs to be re-designed. . Cpa Cpa . . Cpa Cpa Multiplier (a) . . . + - + Multiplier (b) Fig.A–2: Circuit diagrams in the conductive intervals, (a) role of parasitic capacitances; (b) equivalent circuit of the multiplier • Conductive intervals Appendix A 157 Once the circuit enters the conductive intervals, half of the diode chains conduct. Fig.A–2 shows an example of when the diode chain Dch1, Dch3, Dch2_1 and Dch4_1 conducts, The capacitors in the multiplier have constant voltage, thus they are replaced by the voltage sources. It can be seen that the currents from the transformer can always flow through a pass that consists of DC voltage sources. For time-varying current, the voltage sources can be regarded as short circuit. Consequently, any parasitic capacitances in the multiplier are shorted by the DC voltage sources. More precisely, they are either shorted by the large capacitors or by the conducting diodes. As a result, they have no influence on the circuit behaviors in the conductive intervals. The multiplier can still be simplified as DC voltage sources, which is the same as the principle multiplier. . Cpa Cpa . . Cpa Cpa Multiplier (a) . . Cem . Cem Multiplier (b) Fig.A–3: Circuit diagrams in the non-conductive intervals, (a) role of parasitic capacitances; (b) equivalent circuit of the multiplier 158 • Parasitic capacitances in the HV multiplier module Non-conductive intervals When the circuit enters non-conductive intervals, all the diodes are blocked. The multiplier is left with only capacitors. The load is shorted by the large output capacitors. The large push-pull and output capacitors are connected in a complicated way with the numerous parasitic capacitances. However, the complex capacitance network can be simplified as one capacitance Cem, as shown in Fig.A–3 (b). The capacitance Cem is named as equivalent capacitance of the multiplier. It is in parallel with the secondary winding of the transformer. Thus, it is part of the parallel resonant capacitance Cp. In non-conductive intervals, currents flow into the multiplier and charge the capacitance Cem. Based on the analysis of principle LCC, the capacitance Cem and CTS determine the resonant frequency of the circuit together with the inductance Ls and capacitance Cs. They further determine all the characteristics of the LCC. 1 Vpk 2 1 2 vac+ vcc1+ 0 -Vpk -2Vpk vCo1 vcc2+ vo -4Vpk Vpk vacvcc1- 0 -Vpk -2Vpk vCo1 vcc2vo -4Vpk iTS irect+ t1 t2 t3 t4 t5 Fig.A–4: Steady-state waveforms in the LCC with parasitic capacitances Fig.A–4 shows the steady-state waveforms, which are obtained in a specific network of parasitic capacitances. The network is the complete model of parasitic capacitances in the multiplier, which will be shown in Section 3.3. The waveforms look quite similar to those in Appendix A 159 the principle LCC, as shown in Fig. 2-21. The difference is that in the non-conductive intervals, there are currents flowing into the multiplier, and these are highlighted by the dotted circles. The fluctuations around the peaks of irect+ are caused by abrupt conductions of the diodes. The waveforms are obtained in the circuit simulator. The push-pull and output capacitors cannot be set as infinitely large, thus there are still time differences between the conductions of diodes in different stages. If all the components in the LCC with parasitic capacitances are the same as those in the principle LCC, the parallel resonant frequency of the former one is lower than the later one due to the presence of the parasitic capacitances. A lower resonant frequency can lead to different circuit behaviors from the design, which should be avoided. A.2 Simplification of the capacitance network of the multiplier In this section, the way to simplify the voltage-dependent capacitance network of the multiplier in the non-conductive interval is presented. The simplification is intended to obtain the equivalent capacitance of the network. It is a small signal input capacitance, the definition of which is introduced in Appendix A.3 [Kul10]. Cpa Cpp Cpp Cpa Cpa Cpa Cpa Co Cpa Cpp Cpa Cpa Cpa Cpa Co Cpa Cpp Fig.A–5: Numerous parasitic capacitances Cpa in the multiplier Fig.A–5 illustrates parts of the numerous parasitic capacitances in the multiplier. In the nonconductive intervals, the diodes are blocked. Then the network contains only the parasitic capacitance Cpa, the push-pull capacitors Cpp and the output capacitors Co. The capacitors Co are assumed sufficiently large to have much lower impedance than the load in the AC analysis. Consequently, the load is shorted by the capacitors Co and has no influence on the equivalent 160 Parasitic capacitances in the HV multiplier module impedance of the network. The two AC voltage sources at the inputs, which are in phase, represent the output of the transformer. The parasitic capacitances in the network can be divided into two types. One is voltagedependent capacitances and the other is linear capacitances. 1. The junction capacitances of the diodes are voltage dependent. They are denoted as Cj in the following analysis. 2. Besides the junction capacitances of diodes, the other parasitic capacitances are linear. They are relevant to the electric field outside electric components and are determined by the size of the conductive objects and the structure of the module. Thus, they are named as structural capacitances, which are denoted as Cstru in the following analysis. The structural capacitances are usually very small, which are at the magnitude of pico farad or even smaller. Meanwhile, the push-pull and output capacitors in the same network are usually at the magnitude of nano farad or even larger. These are the premise for the following simplifications. A.2.1 Step 1 of the simplification Cpp Cpp Cj(v) Cstru1 Cstru2 Cstru1 Co Cj(v) Cstru2 ∑Cstru2 Cj(v) ∑Cstru1 Cj(v) Co (a) (b) Fig.A–6: Simplification of structural capacitances between the diodes and the push-pull and output capacitors, (a) before simplification; (b) after simplification Fig.A–6 illustrates the first step of the simplification of the capacitance network. After this step, the structural capacitances between the diode and the push-pull and output capacitors can be much simplified. In the left figure, it can be noted that one electric node on the diode chain is connected by many structural capacitances to the large capacitors, namely the push-pull and output capacitors. In Appendix A 161 the multiplier, the large capacitors have constant voltage. In AC analysis of a linear capacitance network, constant voltage sources can be replaced by short circuits without changing the impedance of the network. However, in a network containing both voltage-dependent capacitances and linear capacitances, the replacement does not hold generally because it can change the initial voltage on the voltage dependent capacitances. Thus, the capacitors Cpp, Co, as shown in Fig.A–6, can’t be removed by short circuits. They should remain in the network to maintain the initial voltage on the junction capacitances Cj. Although short circuits can’t replace the large capacitors, the terminals of the structural capacitances, such as Cstru2, can move along the chain of large capacitors Cpp. Consequently, the structural capacitances between the node and the push-pull or output capacitors can be combined to form one capacitance because of the parallel position after the movement, as shown in Fig.A–6 (b). The movement does not change the voltages on the Cj. Because the output capacitors are connected to the ground, the bottom terminals of the capacitances Cstru1 can be all moved to the ground. The step 1 is proved as follows: Cpp F B Cj(v) Cstru2 Cj(v) C Cj(v) Cstru1 A Cstru2 Cj(v) Cstru2 Cj(v) Cstru1 Cstru1 Cj(v) D G E Co (a) (b) (c) Fig.A–7: Proof for Step 1. The nodes shown in (b) are the same as in (a) and (c). Fig.A–7 (a) illustrates a typical network in the multiplier. The push-pull capacitor Cpp and the output capacitor Co can be replaced by constant voltage sources, as shown in (b). In the network (b), by Kirchhoff’s current law: iBC + iAC = iCD + iCE (A.1) Thus, ∫ Q BC |t2 Q BC |t1 dQ + ∫ Q AC |t2 Q AC |t1 dQ = ∫ QCD |t2 QCD |t1 dQ + ∫ QCE |t2 QCE |t1 dQ (A.2) 162 Parasitic capacitances in the HV multiplier module where QBC|t1 signifies the charge stored in the capacitance Cj between nodes B and C at any time instant t1. The other notations have analogous meanings. According to the definition of dynamic capacitance, which will be shown in Appendix A.3, the above equation becomes: ∫ VBC |t2 VBC |t1 ∫ VBC |t2 VBC |t1 C j (v)dv +Cstru 2 ∫ VAC |t2 VAC |t1 C j (v)dv − ∫ VCD |t2 VCD |t1 dv = ∫ VCD |t2 VCD |t1 C j (v)dv +Cstru1 ∫ VCE |t2 VCE |t1 dv C j (v)dv = Cstru1 (VCE | t2 − VCE | t1 ) − Cstru 2 (VAC | t2 − VAC | t1 ) (A.3) (A.4) where VBC|t1 signifies the voltage between nodes B and C at time instant t1. The other notations have analogous meanings. VAC | t2 − VAC | t1 = VFC | t2 − VFC | t1 (A.5) VCE | t2 − VCE | t1 = VCG | t2 − VCG | t1 (A.6) Thus, the right hand side terms in Equation (A.4) become: ∫ VBC |t2 VBC |t1 C j (v)dv − ∫ VCD |t2 VCD |t1 C j (v)dv = Cstru1 (VCG | t2 − VCG | t1 ) − Cstru 2 (VFC | t2 − VFC | t1 ) (A.7) Based on the Equations (A.4) and (A.7), the movement of the terminals from A to F, E to G does not influence the voltages on the junction capacitances as long as the initial voltages across them, VBC|t1 and VCD|t1, are the same in the two networks. In the multiplier, the initial voltages on the junction capacitances are all zero due to the conduction of the diodes. Thus, step 1 of simplification does not influence the voltages on the junction capacitances, which further means that the terminal characteristics of the network remain the same. Appendix A 163 A.2.2 Step 2 of the simplification Cstru 5 Chain of push-pull capacitors Cj(v) Cstru 2 Cstru 1 Cstru 4 Chain of diodes Cstru 3 Chain of output capacitors Cstru 6 Fig.A–8: All possible positions of the structural capacitances after Step 1 After the first step of the network simplification, the structural capacitances in the multiplier module are reduced into six groups, which are exhibited in Fig.A–8. Table A–1 explains the meaning of each group. Table A–1: The six groups of the structural capacitances Group of the structural capacitances Cstru ① the structural capacitances across the diodes ② the structural capacitances between the diodes and the push-pull capacitors, which signify the equivalent capacitance ∑Cstru2 as shown in Fig.A–6 ③ the structural capacitances between the diodes and the ground, which signify the equivalent capacitance ∑Cstru1 as shown in Fig.A–6 ④ the structural capacitances between the push-pull capacitors and the ground ⑤ the structural capacitances across the push-pull capacitors ⑥ the structural capacitances across the output capacitors 164 Parasitic capacitances in the HV multiplier module The capacitance network shown in Fig.A–8 can be simplified further. Fig.A–9 illustrates an example of the simplification. 1) Cstru<0.01Cpp/2 Cstru 1 Cpp 2) v2 does not always follow v1 or v3 Cpp 3 2 1 Cpp Cpp 3 2 Fig.A–9: Simplification of structural capacitances across the push-pull capacitors The above figure shows a typical sub-network containing a structural capacitance and two push-pull capacitors. The sub-network has three terminals that are connected to an unknown external circuit. The left sub-network can be simplified into the right one as long as the two conditions that are shown in the figure are satisfied. • The first condition indicates that the capacitance Cstru should be much smaller than the equivalent capacitance of Cpp connected in series. The factor 0.01 indicates how small the capacitance Cstru should be. This depends on the expected accuracy error after the simplification. Here the error is around 1%. In the multiplier, the capacitance Cpp is more than 1000 times larger than the structural capacitances, thus this condition holds. • The second condition indicates that, if there is a time-varying current, it will not be forced to flow through the structural capacitance Cstru. If v2 always follow v1, the current will not flow through Cpp between node 1 and 2 and be forced to flow through Cstru. In the capacitance network as shown in Fig.A–5, the only components between 2 and 1 or 3 are parasitic capacitances. They can’t force the voltage at node 2 to always follow node 1 or 3. Thus, this condition is always satisfied in the multiplier. The two conditions ensure that a time-varying current never flows through the pass of highimpedance, namely the pass containing the small capacitance Cstru. Thus, the capacitance Cstru can be neglected in the AC analysis. The rule in the above simplification can be also applied to the cases with more push-pull capacitors connected in series. Consequently, group 5 of the structural capacitances can be neglected in the network. For the same reason, group 6 of the structural capacitances can be ignored as well. Appendix A 165 In the group 1, the structural capacitances between the diodes that are not nearby are usually very small, which is typically below 0.1pF. Further, the structural capacitances between the diodes that are far away can be much smaller than 0.1pF. Although the junction capacitance for some diodes can be around only 1pF when high voltage is applied, it is still at least ten times larger than the structural capacitances. Thus, those structural capacitances can be neglected without decreasing the accuracy much. It is worth mentioning that the structural capacitances between the nearby diodes can reach the magnitude of 0.5pF, which is comparable to the junction capacitances in some cases. Thus, it is not always accurate to neglect them. However, their effect on the equivalent capacitance of the network can be easily assessed by adding their capacitances to the junction capacitances. Thus, they are merged into the junction capacitances during the analysis in the following section. Chain of push-pull capacitors Cj(v) Cstru 2 Cstru 4 Chain of diodes Cstru 3 Chain of output capacitors Fig.A–10: Simplified capacitance network After the second step of the simplification, the numerous parasitic capacitances in the network can be simplified into four groups of capacitances that are shown in Fig.A–10. This simplified network can be utilized to create the complete model of the parasitic capacitances for the multiplier. A.3 Definition of capacitance In this section, two definitions of capacitance, which are important for the voltage-dependent capacitance, are introduced [Kul10]. A capacitor is a passive two-terminal electrical component, which is used to store energy of electric field. Capacitance is the ability of the capacitor to store the electrical charge. There are two ways to define the capacitance of the capacitor. 166 • Parasitic capacitances in the HV multiplier module Static capacitance C= Q V (A.8) in which: C signifies the capacitance Q signifies the charges stored in the capacitor V signifies the voltage between the electrodes of the capacitor • Dynamic capacitance C= dQ dV (A.9) In the case of linear capacitors, the capacitance is the same in the two definitions. The capacitance depends on the physical structure and permittivity of the dielectric of the capacitor. However, for nonlinear capacitors, such as voltage-dependent capacitors, the capacitance obtained by the definition of dynamic capacitance is different from that obtained by the definition of static capacitance. In this thesis, the dynamic capacitance is utilized to describe the capacitance of voltage-dependent capacitor. It is also called small signal capacitance. Any two conductors can be considered as a capacitor. The capacitance of the capacitor between the conductors in electrical systems, such as packages, windings, connecting bars, is usually so small that it can be neglected. Such an effect is not desirable for the intended purposes. It is usually called a parasitic capacitance or stray capacitance. In this thesis, the name of parasitic capacitance is preferred. A.4 3D FE filed simulation In this section, the 3D FE field simulation, which is intended to obtain the structural capacitances in the multiplier module, is introduced. Firstly, the 3D FE models of the module are introduced. After that, the results of the simulation are shown. A.4.1 3D FE models of the module Appendix A 167 Capacitors Diode DC in Soldering pads Connecting wires AC- PCB insulation oil Grounded container Fig.A–11: Schematic of a multiplier module The multiplier module used for analysis in Chapter 3 contains the diodes, the push-pull and output capacitors, grounded container, the insulation oil, PCB, soldering pads and connecting wires. Fig.A–11 shows the schematic presentation of the module. In the demonstrator shown in Fig.3–23, there are more components in the module, which are resistors for voltage balance of the capacitors and the bars connecting different PCBs. They are neglected in the schematic presentation as well as in the 3D model , because their surface sizes are so small that they have a weak influence on the structural capacitances. In Fig.A–11, each PCB module forms one multiplier stage. The circuit board is of FR4 material with relative permittivity εr of 4.4. There are 96 bare SiC diodes mounted on the soldering pads on one side of the PCB. They are connected by thin bonding wires. On the other side, 18 HV large capacitors are soldered for the push-pull capacitor and the output capacitors. The insulation oil has a relative permittivity εr of 2.2. To reduce the complexity of simulation, the structure of the module should be simplified in the 3D model. Because the goal of the simulation is to obtain the structural capacitances, the principle of the simplification is to keep approximate metal surface size of the components and their spatial positions as the reality. The diode and HV capacitor have the most complicated internal structures in the multiplier module. The simplification of their 3D models is addressed as follows. A.4.1.1 Simplification of the diode model 168 Parasitic capacitances in the HV multiplier module Fig.A–12: Internal structure of a junction barrier Schottky (JBS) SiC diode Fig.A–12 shows the internal structure of a JBS SiC diode from the Spanish institute CNMCSIC. When the diode is blocked, the semiconductor region can be regarded as the dielectric. W3 W2 W1 Anode T1 Semiconductor T2 T3 Cathode (a) W4 T4 (b) Fig.A–13: Simplified model of the diode and the soldering pad: (a) diode; (b) soldering pad The simplified model of the blocked diode is shown in Fig.A–13 (a) with the dimension given by the institute, which is shown in Table A–2 . The model of the pad is shown in Fig.A–13 (b). Table A–2: Dimensions of the simplified diode model and the pad model Concept Dimensions W1 Schottky contact width 700 µm W2-W1 Doping width 270 µm Appendix A 169 W3 Die width 2000 µm T1 Anode metal thickness 4.5 µm T2 Depletion layer thickness 45 µm T3+T1 Wafer thickness 396 µm W4 Soldering pad width 5000 µm T4 Soldering pad thickness 50 µm The internal structure of the diode is much simplified for the 3D simulation. This simplification does not influence the structural capacitances in the module. In the simulator, the capacitances are obtained by calculating the electric field and other relevant quantities in an electrostatic environment. Thus, the field can be examined to check the influence on structural capacitances by the internal structure of the diode. Diode PCB Grounded container Fig.A–14: A 3D FE model for proof of the diode model Table A–3: Energy of the spatial electric field in the module with different diode models εr of the semiconductor Total electric field energy(J) Energy in diodes(J) Spatial energy (J) 9.8 0.020134 0.003879 0.016255 980 0.40146 0.38501 0.01645 material (3 diodes per chain) 170 Parasitic capacitances in the HV multiplier module εr of the semiconductor Total electric field energy(J) Energy in diodes(J) Spatial energy (J) 9.8 0.052313 0.000771 0.051542 980 0.12545 0.073717 0.051733 material (16 diodes per chain) Fig.A–14 shows a 3D FE model that contains the diode model, PCBs and a grounded container. The model is to prove that the energy of the spatial electric field is only slightly influenced by the internal properties of the diode model. Table A–3 shows the simulation results. Two models are calculated. One has 3 diodes per chain and the other 16 diodes per chain. In both cases, the relative permittivity of the semiconductor material increases from 9.8 to 980 with the same voltage assignment. By doing so, the internal energy of electric field of the diodes increases by 100 times. However, it can be seen that the spatial energy changes little. The results further indicate that the structural capacitances are independent of the properties of the internal structure of the diode. They are much dependent on the surface size of the components in the multiplier model. Because the soldering pads have much larger surface size than the diodes, the diode model can even be completely neglected in the 3D simulation, if the whole 3D model is too complicated. A.4.1.2 Simplification of the capacitor model Fig.A–15: Schematic of the internal structure of a HV capacitor Fig.A–15 closely resembles the relationship of the internal elements in the HV capacitor. The capacitors are realized with an internal series connection of six capacitors, due to the interleaving pattern of the electrodes. The surface potential can be assumed to vary step-wise Appendix A 171 along the electrodes from one capacitor terminal to the other. The internal electric field is illustrated to show the step-wise connection. Electrode Dielectric (a) (b) Fig.A–16: Simplified models of the capacitor, (a) in interleaving pattern; (b) in simplified pattern Fig.A–16 shows two models of the capacitor. They are put in a 3D model of the module, which is shown in Fig.A–17. In a similar way, the energy of spatial electric field is calculated, in both cases to check the influence on structural capacitances by the internal structure of the capacitor model. In both cases, the relative permittivity of the dielectric increases from 1 to 1000. Table A–4 shows similar results as those in the module with different diode models. The energy of the spatial electric field does not change significantly. Consequently, the internal structure of the capacitor has weak influence on the structural capacitances. The model shown in Fig.A–16 (b) is the preferable one for the simulation of parasitic capacitances in this thesis. Table A–4: Energy of spatial electric field in the module with different capacitor models Cap model in (a), εr =1 Cap model in (a), εr =1000 Cap model in (b), εr =1 Cap model in (b), εr =1000 Energy in the capacitors (J) 4.7E-8 3.9E-5 1.7E-7 1.7E-4 Spatial energy (J) 5.0E-6 5.3E-6 5.1E-6 5.66E-6 A.4.1.3 3D FE model of the multiplier module Apart from the diodes and the HV capacitors, the simplifications of the others in the multiplier module are listed as follows: The bonding wires are eliminated from the 3D model. 172 Parasitic capacitances in the HV multiplier module • The voltage-balancing resistors are eliminated from the 3D model. • The pads in 3D model are only single sided. • All via holes in the PCB boards are eliminated from the 3D model. • The connecting bars and other small copper traces are eliminated from the 3D model. Diode Capacitor PCB Grounded container Fig.A–17: Simplified 3D FE model of the multiplier module With all the simplifications above, the 3D FE model of the multiplier module is created, as shown in Fig.A–17. The diode is created with the model in Fig.A–13 (b) and the capacitor is created with the model in Fig.A–16 (b). A.4.2 Simulation results In this section, the simulation results based on the 3D FE model shown in Fig.A–17 are presented. A.4.2.1 Accuracy of the 3D FE simulation Appendix A 173 (a) (b) Fig.A–18: Meshes and accuracy in the simulation, (a) meshes; (b) energy change vs. mesh amount The 3D FE numerical calculation is performed by commercial simulation software Ansoft Maxwell 3D. The simulation runs in the static solver. In this solver, the static electric field is calculated based on the 3D model and the voltage applied. The capacitance is obtained from the charge and voltage. The charge is calculated based on the static electric field that is calculated iteratively with the adaptively refined meshes. Fig.A–18 (a) shows the meshes in the 3D model. Fig.A–18 (b) shows the accuracy of the simulation results, which is reflected by energy change in the software. It increases as the number of meshes increases. Without simplifications of the model, the number of meshes easily goes beyond a million, which leads to long simulation time. A.4.2.2 Distribution of structural capacitances C-1 C-3 C-4 C-9 AC side + DC side D-12 D-13 D-60 D-61 D-1 D-24 D-49 D-72 D-48 D-25 D-73 D-37 D-36 AC side C-10 C-12 D-96 D-85 C-13 C-18 (a) D-84 174 Parasitic capacitances in the HV multiplier module C-1 C-3 C-4 C-6 D-1 D-12 D-13 D-24 D-48 D-37 D-36 D-25 C-15 C-13 C-12 C-10 C-7 C-9 C-16 C-18 (b) Fig.A–19: Number of the diodes and push-pull capacitors, (a) in topology; (b) in the 3D model Fig.A–19 shows the number of diodes and push-pull capacitors in the topology and the 3D model respectively. The diode is represented with the model of soldering pad only. The simplification of the structural capacitances in the module is addressed in Appendix A.2, the overall distribution is shown in Fig.3–5 and the complete model is shown in Fig.3–6. The values of each kind of structural capacitance are shown in the figure below. 2 1 C ppg (pF) 1.5 0.5 0 C-1 C-9 C-10 number of push-pull capacitors (a) C-18 Appendix A 175 2 1 C dg (pF) 1.5 0.5 0 D-1 D-25 D-48 number of diodes D-73 D-96 D-73 D-96 (b) 2 C dpp (pF) 1.5 1 0.5 0 D-1 D-48 number of diodes D-25 (c) Fig.A–20: Values of the structural capacitances, (a) Cppg; (b) Cdg; (c) Cdpp A.5 Derivation of chain capacitance It is hard to derive the chain capacitance CDch2, as shown in Fig.3–11, by network transform. Here, a simple method is utilized to solve the problem from the angle of exchanged energy. The derivation is based on Fig.3–11. Based on the definition of dynamic capacitance, the chain capacitance CDch2 is: CDch 2 (vDch 2 ) = dqDch 2 dvDch 2 (A.10) in which qDch2 is the charge flowing into the capacitance network of the chain Dch2. The energy that flows into the network between any two instants is: ∆EDch = 2 ∫ tVch 2 tVch1 vDch 2 ⋅ iDch 2 dt (A.11) 176 Parasitic capacitances in the HV multiplier module Hence: ∆EDch= 2 ∫ Vch 2 = ∫ Vch 2 Vch1 Vch1 vDch 2 ⋅ dqvDch 2 (A.12) CDch 2 (v) ⋅ vDch 2 ⋅ dvDch 2 ≈ (Vch 2 − Vch1 ) ⋅ ( Vch1 + Vch 2 V +V ) ⋅ CDch 2 ( ch1 ch 2 ) 2 2 Hence, CDch 2 ( Vch1 + Vch 2 2∆EDch 2 )≈ 2 (Vch 2 − Vch1 ) ⋅ (Vch1 + Vch 2 ) (A.13) Vch1 and Vch2 are any two voltages between zero and 2Vpk. Based on Equation (A.12) and (A.13), the closer the two voltages are, the more accurate the calculation of CDch2 will be. The energy swing of the chain ∆EDch2 between time tVch1 and tVch2 can be obtained by adding the energy swing on each parasitic capacitance in the chain. To do that, the voltage distribution on each electrical node along the chain should be known beforehand. According to Kirchhoff’s current law, it can be obtained that: ik +1k + in d k =ik 0 + ikk −1 (A.14) By integrating the current over time and applying Equation (A.10), the following relation can be obtained: ∫ Vndk |tVch 2 Vndk |tVch1 Cdpp dv + ∫ Vk +1k |tVch 2 Vk +1k |tVch1 C j (v)dv = ∫ Vkk −1 |tVch 2 Vkk −1 |tVch1 C j (v)dv + ∫ Vk |tVch 2 Vk |tVch1 Cdg dv (A.15) in which: Vnd k|tVch2 = Vnd|tVch2 – Vk|tVch2. Vk|tVch2 signifies the voltage at node k when the chain voltage is Vch2, namely at time tVch2. The other notations are analogous to Vnd k|tVch2. The capacitance Cdpp and Cdg is linear, thus the integral of them over voltage is easy to obtain. In the case of the junction capacitance, its analytical function containing the voltage should be known in order to solve the integration. Based on Equation (A.15), as long as the initial voltage distribution at time tVch1 along the chain is known, the final voltage distribution at time tVch2 can be obtained. Regarding the diode chain in the charging transition, the initial voltages on the nodes along the chain are all zero. In the case of the diode chain in the discharging transition, the initial voltages on the nodes are the same as the final voltage distribution along the chain in the charging transition. The voltage on Appendix A 177 node k at instant tVch2can be calculated recursively starting from the zero voltage at node 0, with the given chain voltage Vnd|tVch2. With the voltage distribution obtained, the energy swing during the two instants can easily be calculated as follows : ∆EDch 2 =∑ ∆ECpai =∑ ∫ i i VCpai |tVch 2 VCpai |tVch1 Cpai (v)dv (A.16) in which: Cpai means the ith parasitic capacitances in the network of a chain, including the structural capacitances and the junction capacitances. i: 1 to the total amount of parasitic capacitances in the network. ∆ECapi means the energy swing on ith parasitic capacitance during the two instants. VCpai|tVch1 means the voltage across the ith parasitic capacitance at the instant tVch1. In the end, the capacitance CDch2 is found to be: VCpai |tVch 2 2∑ ∫ Cpai (v)dv VCpai |tVch1 V +V i CDch 2 ( ch1 ch 2 ) ≈ 2 (Vch 2 − Vch1 ) ⋅ (Vch1 + Vch 2 ) (A.17) 178 Parasitic capacitances in the HV multiplier module Appendix B Power series approach for fast transient analysis B.1 The power series approach to time-varying fields In this section, the principle of the power series approach as introduced by [Maq72] is described. Generally, all the field quantities such as E, H, ρ, can be expressed as a function with five independent variables, x, y, z, ωt and ω, as: E( x, y, z , ωt , ω ); H ( x, y, z , ωt , ω ); (B.1) ρ( x, y, z, ωt , ω ); where x, y, z are the spatial variables, t is the time variable, and ω is the frequency variable. All EM fields will, in general, alter their shapes and behavior as a function of the frequency ω. The fields and all the other quantities can be expanded at a fixed point in time and space into a power series around ω = 0, as follows: , y, z ,τ , ω ) e0 ( x, y, z,τ ) + ωe1 ( x, y, z,τ ) + ω 2e 2 ( x, y, z,τ ) + ⋅⋅⋅ E( x= (B.2) H ( x= , y, z ,τ , ω ) h 0 ( x, y, z,τ ) + ωh1 ( x, y, z,τ ) + ω 2h 2 ( x, y, z,τ ) + ⋅⋅⋅ (B.3) where τ is defined as ωt. The expansion coefficient in the series is given as: = e k ( x, y , z , τ ) 1 ∂ k E( x , y , z , τ ) [ ]ω =0 ∂ω k k! k = 0,1, 2 ⋅⋅⋅ (B.4) If the power series of each quantity is substituted into Maxwell’s laws, recurrent relations between the quantities of different orders can be found. Here, the E and B field are taken as examples to show these relations. Faraday’s law is given as: 180 Power series approach for fast transient analysis ∇×E = − ∂B ∂t (B.5) Replace t by τ, then: ∇ × E = −ω ∂B ∂τ (B.6) Replace E field and B fields by the power series, then: ∇ × E = (∇ × e0 ) + ω (∇ × e1 ) + ω 2 (∇ × e 2 ) + ⋅⋅⋅ ∂b ∂b ∂b ∂B = -ω = ω ( 0 ) + ω 2 ( 1 ) + ω 3 ( 2 ) + ⋅⋅⋅ ∂τ ∂τ ∂τ ∂τ (B.7) Combine the terms with equal order, then: [(∇ × e0 ) + ω (∇ × e1 + ∂b 0 ∂b ) + ω 2 (∇ × e 2 + 1 ) + ⋅⋅⋅] = 0 ∂τ ∂τ (B.8) The above equation must be valid for all the frequencies ω, thus, each term on the left hand side should be separately equal to 0. Therefore: ∇ × ek = − ∂b k -1 ∂τ (B.9) Similar results can be derived from the basic Maxwell laws for the other quantities. Define: = E k ( x, y , z , τ , ω ) ω k e k ( x, y , z , τ ) k = 0,1, 2, ⋅⋅⋅ (B.10) = B k ( x, y , z , τ , ω ) ω k b k ( x, y , z , τ ) k = 0,1, 2, ⋅⋅⋅ (B.11) k = 0,1, 2, ⋅⋅⋅ (B.12) k = 0,1, 2, ⋅⋅⋅ (B.13) Then: ∞ ∑ E ( x, y , z , τ , ω ) = E( x , y , z , τ , ω ) k =0 H ( x, y , z , τ , ω ) = k ∞ ∑H k =0 k ( x, y , z , τ , ω ) ∇ × Ek = − ∂B k -1 ∂t (B.14) Based on the same procedure and Maxwell’s laws, all the resulting sets of equations can be derived, as shown in Table B–1. Appendix B 181 Table B–1: Relations of fields and other quantities in each order derived by the power series approach Zero order First order ∇ × E0 = 0 n × (EI − EII )0 = 0 ∇ × H0 = J0 n × (H I − H II )0 = K0 ∇ ⋅ D0 = ρ0 n ⋅ (DI − DII )0 = η0 ∇ ⋅ B0 = 0 n ⋅ (B I − B II )0 = 0 ∇ ⋅ J0 = 0 n ⋅ (J I − J II )0 + ∇ Σ ⋅ K 0 = 0 ∂B 0 − ∇ × E1 = n × (EI − EII )1 = 0 ∂t ∇ × H1 = J 1 + ∂D0 ∂t ρ1 ∇ ⋅ D1 = n ⋅ (DI − DII )1 = η1 0 ∇ ⋅ B1 = ∂ρ 0 − ∇ ⋅ J1 = n × (H I − H II )1 = K1 n ⋅ (B I − B II )1 = 0 ∂t ∂η 0 n ⋅ (J I − J II )1 + ∇ Σ ⋅ K 1 = − th k order n × (EI − EII ) k = 0 ∂B k −1 − ∇ × Ek = ∂t ∇ × Hk = Jk + ∂Dk −1 ρk ∇ ⋅ Dk = 0 ∇ ⋅ Bk = ∂ρ k −1 − ∇ ⋅ Jk = ∂t ∂t ∂t n × (H I − H II ) k = Kk n ⋅ (DI − DII ) k = ηk n ⋅ (B I − B II ) k = 0 ∂η k -1 n ⋅ (J I − J II ) k + ∇ Σ ⋅ K 1 = − ∂t B.2 Circuit modeling of a single-turn inductor In this section, circuit modeling of a simple example by applying the power series approach, based on [Maq72], is introduced. 182 Power series approach for fast transient analysis σ=∞ x conductor + vs(t) _ y=-w 1 is(t) 1' z=-l K(t) air d Kr(t) K(t) z y Kr(t) = Acosωt, at z = 0 Fig.B–1: The structure of a single-turn inductor The inductor consists of two perfect conductors, which are perfectly conducting, in parallel and joined at one end by a third perfect sheet. The inductor is excited by a sinusoidal current source at one end (z=-l) to maintain the reference surface current density: K r (t ) = −i x A cos ωt at z = 0 (B.15) The width and length of the plates are much larger than the separation distance so the fields and other quantities in the structure are independent on x and y. • Zero-order fields and circuit model: The zero-order fields can be derived directly from the current excitations. According to the zero-order relations, the magnitude of the surface current density K0(t) must be the same on the three plates. Thus: K 0 (t ) = A cos ωt (B.16) The surface current flows in a clockwise direction. The zero-order field relations are identical in form to that their static counterparts, thus the zero-order fields can be derived based on the rules obtained for the static field. The E0 and H0 fields follow as: H 0 (t ) = −i y K r (t ) = −i y A cos ωt (B.17) E0 (t ) = 0 (B.18) The zero-order fields and other quantities are basically staticlike, which means that the effects of time-variation of the time-varying fields are neglected. Thus, the circuit model of the singleinductor should be the inductance that is defined by the static laws, which is given as: LDC = µ0ld w (B.19) Appendix B • 183 First-order fields and circuit model: The first-order fields can be derived directly from the zero-order fields. The first-order E1 field can be derived from the zero-order H0 field by using: ∇ × E1 = − µ0 ∂H 0 ∂t (B.20) Then, the first-order E1 field can be obtained as: E1 ( z,t ) = −i x ( µ0ω z ) A sin ωt (B.21) The first-order H1 field can also be derived mainly from the zero-order E0 field that is zero. The first-order H1 field is therefore given as: H1 (t ) = 0 (B.22) In first-order fields, the variation of the zero-order fields is taken into account, which leads to a change of amplitude in space. According to (B.21), if the frequency ω is low, the contribution of the first-order fields to the total field is also low. As frequency increases, the contribution becomes larger. As a result, the fields of the inductor correct up to and including the first-order terms are: E0,1 = E0 + E1 = −i x ( µ0ω z ) A sin ωt (B.23) H 0,1 = H 0 + H1 = −i y A cos ωt (B.24) The fields E0,1 and H0,1 show an exact quasi-static behavior. Considering both the zero-order and first-order fields, the circuit model of the inductor can be derived based on the terminal voltage and current, which are given as: d vs (t )0,1 = µ0 Aωld sin ωt − ∫ mag(E0,1 ) z = − l dx = (B.25) x =0 w is (t )0,1 = wA cos ωt − ∫ mag(H 0,1 ) z = − l dy = (B.26) y =0 The phasor representations of vs and is are: [Vs ]0,1 = j µ0 Aωld (B.27) [ I s ]0,1 = wA (B.28) Thus, the input impedance to the system correct up to and including first-order contributions is: 184 Power series approach for fast transient analysis = Z in0,1 [Vs ]0,1 µ0ld = jω = jω LDC [ I s ]0,1 w (B.29) It is found that for quasi-static fields the single-turn inductor structure can still be modelled as an inductance that is the same as that is obtained for the static field. This fact is well known and widely used by people. However, the underlying knowledge is not as popular as the conclusion. By means of the power series approach, it becomes clear that the validity of the circuit model is directly related to the ability of the quasi-static fields to serve as good approximations of the exact time-varying fields generated in the system. • Second-order fields and circuit model: The second-order fields can be derived directly from the first-order fields, which are directly given as follows: E2 (t ) = 0 H 2 ( z,t ) = i y ( µ0ε 0ω 2 z 2 ) A cos ωt 2 (B.30) (B.31) The second-order input impedance can also be derived based on the terminal voltage and current, which are the line integral of E and H fields that correct up to and includes the secondorder terms, respectively. The input impedance to the system correct up to and including second-order contributions is: Z in0,1,2 = jω LDC ω 2 LDCCDC 1− 2 (B.32) in which CDC is defined as the quasi-static capacitance of the parallel-plate structure without the shorting plate at z=0: CDC = ε 0 wl d (B.33) It is clear that the second-order terms add extra contributions to the impedance compared to the first-order impedance shown in (B.26). The second-order impedance is equal to the first-order impedance only if the extra contribution is so small that it may be neglected. This means, looking back at the field, that the second-order fields are negligible, which leads to the criterion l<<λ. The criterion is well known and used to determine whether the field is in the quasi-static range. Appendix B 185 Once the frequency is above the quasi-static range, which means the second-order terms are not negligible, the lumped element model of an inductance is not valid any more. In this situation, more elements should be added. For this particular case, the impedance is represented by the parallel network of the inductance LDC and a capacitance, as shown in Fig.B–2 (a). The capacitance is one half of CDC : First order model LDC (a) 1 C 2 DC Second order model LDC (b) 1 LDC 3 2 L 3 DC 1 C 2 DC Third order model (c) 2 LDC 3 1 C 4 DC 1 L 3 DC 3 C 4 DC Fourth order model (d) Fig.B–2: Different order circuit models of the single-turn inductor, (a) first order; (b) second order; (c) third order; (d) fourth order; • Third-order fields and circuit models: 186 Power series approach for fast transient analysis The third-order fields can be derived directly from the second-order fields. E3 ( z,t ) = i x (ω 2 µ0 2ε 0 z3 ) A sin ωt 6 (B.34) (B.35) H 3 ( z,t ) = 0 The third-order input impedance can also be derived based on the terminal voltage and current, which are the line integral of E and H fields that correct up to and includes the third-order terms respectively. The input impedance to the system correct up to and including third-order contributions is: Z in0,1,2,3 = ω 2 LDCCDC ) 6 2 ω LDCCDC 1− 2 jω LDC (1 − (B.36) By considering the third-order fields, another extra contribution is added to the impedance compared to the second-order impedance shown in Equation (B.36). Only if the extra contribution is negligible, will the third-order impedance become the same as the second-order impedance. . By looking at the field, the condition means the field E3 should be much smaller than E1. The third-order circuit model is shown in Fig.B–2 (c). • Higher-order fields and circuit model: The fourth and higher order fields can be found with a fixed pattern that follows from the fact that all odd-orders of H fields and all even-orders of E fields are zero in this system. The kthorder terms of fields can thus be derived as: Ek ( z,t ) = −i x A sin ωt k -1 µ0 (β z )k (−1) 2 ε0 k! k H k ( z,t ) = −i y Acosωt (−1) 2 (β z )k k! k = 1,3,5 ⋅⋅⋅ k = 0, 2, 4 ⋅⋅⋅ (B.37) (B.38) in which: β = ω ε 0 µ0 (B.39) The fourth- and fifth-order circuit model can be derived from the fields correct up to and including the corresponding order. The exact E and H fields are respectively given by infinite sums over the terms given by Equations (B.37) and (B.38). The resulting infinite series are reducible to the simple closed forms. Appendix B 187 ∞ k -1 µ (β z )k [∑ (−1) 2 ] ε k! ∞ 0 x k = k 0= 0 k 0 E( z,t ) = ∑ E ( z,t ) = −i = −i x A sin ωt H ( z,t ) = ∞ ∑H A sin ωt k = 1,3,5 ⋅⋅⋅ (B.40) µ0 sin β z ε0 ∞ k 2 k ( z,t ) = −i y Acosω t[ ∑ ( −1) = k 0= k 0 (β z )k ] k! k = 0, 2, 4 ⋅⋅⋅ (B.41) = −i y Acosωt cosβ z These closed forms are exactly the same as the wave solution of Maxwell’s equations. Now it is clear that the fields correct up to and including certain order terms are the approximation of the exact solution. It is the electrical size of the structure, which is represented by βz in Equations (B.40) and (B.41), that determines the order of fields that should be considered. With a given physical dimension z, it becomes the frequency ω that determines the order. As addressed above, when the frequency ω is low, as in the quasi-static range, the fields of the second-order and higher orders are negligible. The lumped element model of the electrical structure is valid in this range. As high order terms of the fields become relevant, the frequency enters the above quasi-static range, which is also called the intermediate frequency range in this thesis. Accordingly, the resulting fields lead to LME models of the electrical structure. However, if the order of fields that should be included in the total fields becomes very high, the power series approach is no longer a good way to obtain the results of fields. In this situation, the series expansion can encounter problems, such as slow convergence or even divergence. In this case, the wave solution can be more direct and mathematically simple, and the continuous model has to be adopted. In short, the power series approach is designed for the low-frequency systems, such as quasistatic and intermediate frequency systems. • The boundaries of the frequency ranges Through the single-turn inductor example, the boundaries of the frequency ranges can be approximately obtained. According to Equations (B.37) and (B.38), magnitudes of each order of E and H fields are as listed Table B–2. Table B–2: Magnitudes of each order of E and H fields magnitude of each order of E field magnitude of each order of Η field 188 Power series approach for fast transient analysis E1 -A sin ωt µ0 (β z) ε0 H0 -Acosωt E3 A sin ωt µ0 ( β z )3 ε 0 3! H2 Acosωt (β z )2 2! E5 -A sin ωt µ0 ( β z )5 ε 0 5! H4 -Acosωt (β z )4 4! E7 A sin ωt µ0 ( β z ) 7 ε 0 7! H6 Acosωt ( β z )6 6! E9 A sin ωt µ0 ( β z )9 ε 0 9! H8 Acosωt ( β z )8 8! … … … … From the table, it is clear that the magnitudes of different order fields depend on the term (βz)k/k!. Besides the polarity, this is the only variable part in the magnitudes of each order of E and H fields. This variable part determines the relative magnitude of different order fields, which further determines the order that should be included in the total fields. As a consequence, the boundaries of the frequency ranges can be obtained by looking at the significance of different orders of the fields. 1 (βz) (βz)2/2! (βz)3/3! (βz)4/4! (βz)5/5! (βz)6/6! (βz)7/7! 8 (βz)9/9! (βz) /8! l/λ l/λ (a) (b) Fig.B–3: The variable parts in the magnitudes of different order fields, (a) H fields; (b) E fields Fig.B–3 shows the variable parts in the magnitude of different order fields. The simple λ stands for the wavelength of the field, which is equal to 2π/β. We distinguish the following situations: Appendix B 189 l < 0.1 λ: The H2 and E3 can easily be 10 times smaller than H0 and E1 respectively. The fields correct up to and including the first-order fields can be a good approximation of the exact solutions. This is a well-known rule of thumb for the determination of the boundaries of the quasi-static fields. 0.1 λ < l < 0.5 λ: In this range, high order terms of fields become large and cannot be neglected. This is defined as the intermediate frequency range. From the figure, it can be seen that the H8 and E9 are 5 times smaller than the H6 and E7 respectively. Thus, they are not sufficiently small to neglect. As the physical dimension is around half a wavelength, at least 9th-order fields should be included. It further means that at least the 9th-order circuit model should be used to accurately replace the continuous model. Actually, people may not intend to use the power series approach to calculate the fields when 9th-order terms are required, although the approach can do this. The power series approach is more suitable to calculate fields that only require a few orders. It is hard to say in which range that the power series approach is convenient. For example, from Fig.B–3, we can see that if l < 0.2 λ, the power series approach shows its mathematical simplicity since only 4 orders are required. l > 0.5 λ: In this range, at least 10 orders of the fields should be calculated to reach an accurate result. This is usually defined as the wave range, in which the wave solution of Maxwell’s equation can be more direct and easier to apply than the power series approach. It is crucial to emphasize that the above provides just a rough division of the frequency intervals. It can give people a quick estimation about the frequency range, from which people can decide to choose their approach to calculate the field and to derive the circuit model. The division of the frequency range can also be proven by comparing the input impedance of the inductor as obtained from the wave solution (Zin) and the power series solution (Zin_ps) respectively. The respective impedances are shown as: Z in = jZ 0 tan(2π Z in_ps = jZ 0 βl − (βl) 3 + l ) λ (βl ) (B.42) 5 − (βl ) 7 + ⋅⋅⋅ 3! 5! 7! 2 4 6 ( β l ) + ( β l ) − ( β l ) + ⋅⋅⋅ 1− 2! 4! 6! (B.43) where Z0 is the characteristic impedance of the transmission line. This is taken as 1 for comparison. If the sum goes to infinity in Equation (B.43), the impedance Zin_ps becomes 190 Power series approach for fast transient analysis exactly the same as Zin in Equation (B.42). However, for the comparison of the difference between the two impedances several terms are taken. |Zin| |Zin_ps| l/λ (a) |Zin/Zin_ps| l/λ (b) Fig.B–4: Comparison of the input impedance of the inductor obtained from the full wave solution and from the power series solution (the 9th-order model), (a) the magnitudes of the impedances; (b) the ratio of the magnitudes From Fig.B–4, the boundaries of the frequency ranges can also be observed. In the comparison, fields including up to the 9th-order are used in the power series solutions. When l < 0.5λ, the two solutions match each other well. The spike in Fig.B–4 (b) occurs at l = 0.25λ. In that case, the input impedance of the inductor is infinitely high, and can be replaced as a parallel network of a resonant inductor and a capacitor. After l /λ = 0.6, the results deviate significantly. References [Abd11] E. Abdoulin, S. Colino, A. Nakata, “Using Enhancement Mode GaN-on-Silicon Power Transistors”, Efficient power conversion corporation, 2011. [Bea81] Y. Beausejour, F.A.M. Rizk, “Feedback-Controlled Cascade Rectifier Source for HV Testing of Contaminated DC Insulators”, Power Apparatus and Systems, IEEE Transactions on, vol. pas-100, issue 7, pp. 3525-3534, 1981. [Bel92] M.D. Bellar, E.H. Watanabe, A.C. Mesquita, “Analysis of the dynamic and steady-state performance of Cockcroft-Walton cascade rectifiers”, Power Electronics, IEEE Transactions on, vol. 7, issue 3, pp. 526-534, 1992. [Bela92] R. Beland, “High voltage power supply and regulator circuit for an X-ray tube with transient voltage protection”, US patent, patent Nr. US 5241260, filed on Aug. 31, 1993. [Bel04] F. Belloni, P. Maranesi, M. Riva, “Parameters optimization for improved dynamics of voltage multipliers for space”, Power Electronics Specialists Conference, 2004. PESC 04, vol. 1, pp. 439-443, 2004. [Bel05] R. Beland, St. M. Lac, “High voltage X-ray generator”, US patent, patent Nr. US 7375993 B2, filed on May 20, 2008. [Bey06] W. Beyerlein, W. Kurhnel, “High-voltage supply for an X-ray device”, US patent, patent Nr. US 7110499 B2, Date of patent: Sep. 19, 2006. [Bha91] A.K.S. Bhat, “Analysis and design of a series-parallel resonant converter with capacitive output filter”, Power Electronics, IEEE Transactions on, vol. 27, no. 3, pp. 523-530, 1991. [Bie08] J. Biela and J.W.Kolar, “Using transformer parasitics for resonant converter- A review of the calculation of the stray capacitance of transformers”, IEEE Transactions on Industry Application, vol. 44, No.1, pp. 223-233, 2008. 192 References [Bou40] A. Bouwers etc., “Voltage multiplier”, US patent, no. 2 213 199, 1940. [Bru71] J.S. Brugler, “Theoretical performance of voltage multiplier circuits”, Solid-State Circuits, IEEE Journal of, vol. 6, issue 3, pp. 132-135, 1971. [Bus02] J. Bushberg, “The essential physics of medical imaging”, ISBN 0-683-30118-7, 2nd edition, 2002. [Cav03] F.S. Cavalcante and J.W. Kolar, “Design of a 5kW High Output Voltage SeriesParallel Resonant DC-DC Converter”, IEEE PESC 2003, vol. 4, pp. 1807-1814. [Cav06] F.S. Cavalcante, “High output voltage series-parallel resonant DC-DC converter for medical X-ray imaging applications”, Ph.D thesis, ETH, Zurich, 2006. [Coc32] J.D.Cockcroft, E.T.S. Walton, “Experiments with High Velocity Positive Ions.(I) Further Developments in the Method of Obtaining High Velocity Positive Ions”, in Proc. of the Royal Society of London. Series A, vol.136, no.830, pp.619630,1932. [Col03] R. Collier, "Transmission lines", ISBN: 978-1-107-02600-1, 2013. [Dal07] L. Dalessandro, F.S.Cavalcante, J.W.Kolar, “Self-capacitance of high voltage transformers”, IEEE Transactions on Power Electronics, vol. 22, no. 5, pp. 20812092, 2007. [Dai96] N.Dai, F.C.Lee, “Characterization and analysis of parasitic parameters and their effects in power electronics circuit”, Power Electronics Specialists Conference, 1996. PESC '96 Record., 27th Annual IEEE, pp. 1370-1375, vol.2, 1996. [Du 10] Y. Du, G. Wang, J. Wang, S. Bhattacharya, A.Q. Huang, “Modeling of the impact of diode junction capacitance on high voltage high frequency rectifiers based on 10kV SiC JBS diodes”, Energy Conversion Congress and Exposition (ECCE), 2010 IEEE, pp. 105-111, 2010. [Eve53] E. Everhart, P. Lorrain, “The Cockcroft-Walton voltage multiplying circuit”, Review of Scientific Instruments, vol. 24, issue 3, pp. 221-226, 1953. [Fur94] A.D. Furbee, L. Miller, C.F. Bauer, “X-ray tube arc suppressor”, US patent, patent Nr. 5347571, Date of patent: Sep. 13, 1994. 193 [Gon13] X. Gong, “Conduced EMI in inverters with SiC transistors”, Ph.D dissertation, Delft university of technology, 2013. [Gre20] H. Greinacher, “Erzeugung einer gleichspannung vom vielfachen betrage einer wechselspannung ohne transformator”, Bulletin des schweiz, Elektrotechn, Vereins 11, 1920. [Gre21] H. Greinacher, “Ueber eine neue Methode, Wechselstrom mittels elektrischer Ventile und Kondensatoren in hochgespannten Gleichstrom zu verwandeln”, Zeitschrift f. Physik 4, 1921. [Hei65] W. Heilpern, “Kaskadengeneratoren zur partikelbeschleunigung auf 4 MeV”, Helv. Phys. Acta, vol. 28, pp. 288-292, 1965. [Hua13] X. Huang, Q. Li, Z. Liu, F.C. Lee, “Analytical loss model of high voltage GaN HEMT in cascode configuration”, Power Electronics, IEEE Transactions on, issue 99, 2013. [Iqb14] S. Iqbal, “A hybrid symmetrical voltage multiplier”, IEEE Trans. on Power Electronics, vol. 29, No. 1, pp. 6-12, 2014. [Ive99] G. Ivensky, A. Kats, and S. Ben-Yaakov, “An RC load model of parallel and series-parallel resonant DC-DC converters with capacitive output filter”, Power Electronics, IEEE Transactions on, vol. 14, no. 3, pp. 515-521, 1999. [Joh88] S.D. Johnson, A.F. Witulski, R.W. Erickson, “Comparison of resonant topology in high-voltage DC application”, IEEE Trans. on Aerospace and Electronic Systems, vol. 24, pp. 263-273, 1988. [Joh88] S.D. Johnson, R.W. Erickson, “Steady-state analysis and design of the parallel resonant converter”, IEEE Trans. on Power Electronics, vol. 3, no. 1, pp. 93-104, 1988. [Kaz95] M.K. Kazimierczuk, D. Czarkowski, “Resonant power converters”, ISBN 0-47104706-6, 1995. [Kim95] Y.J.Kim, S. Nagai, H. Takano, Y. Murakami, “Comparative performance evaluations of high-voltage transformer parasitic parameter resonant inverterlinked high-power DC-DC converter with phase-shifted PWM scheme”, Power 194 References Electronics Specialists Conference, 1995. PESC '95 Record., vol.1, pp. 120-127, 1995. [Kob10] I.C. Kobougias, E.C. Tatakis, “Optimal design of a half-wave Cockcroft-Walton voltage multiplier with minimum total capacitance”, Power Electronics, IEEE Transactions on, vol. 25, issue. 9, pp. 2460-2468, 2010. [Kra92] J.D. Kraus, “Electromagnetics”, International edition, ISBN: 0-07-035621-1, 1992. [Kre90] E. Krestel, Imaging Systems for Medical Diagnostics, Siemens/Publicis, ISBN 38009-1564-2, 1990. [Kul10] N. Kularatna, “Electric circuit”, ISBN: 9789350430606, 2010. [Li 07] J. Li, Z. Niu, Z. Zhang, D. Zhou, “Analysis of resonant converter with multiplier”, Industrial Electronics and Applications, 2007. ICIEA 2007. 2nd IEEE Conference on, pp. 326-331, 2007. [Liu13] Z. Liu, X. Huang, F.C. Lee, Q. Li, “Simulation model development and verification for high voltage GaN HEMT in cascode structure”, Energy Conversion Congress and Exposition (ECCE), 2013 IEEE, pp.3579-3586, 2013. [Lue07] P. Luerkens, “Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier”, International patent, No. WO 2007/017793 A1, publication date 2007. [Lue11] P. Luerkens “High voltage silicon-carbide components in Medical X-ray applications” 2nd technical workshop of SmartPM project, Birmingham, 2011. [Lun01] A. Lunding, H. Osterholz, “High voltage power and single pole voltage power supply with small ripple”, US patent, patent Nr. US 6563717B2, filed on Sep. 26, 2001. [Maq72] L.M. Maqid, “Electromagnetic field, energy, and waves”, ISBN: 0-471-56334-X, 1972. [Mar08] J.A. Martin-Ramos, A.M. Pernia, J. Diaz, F.Nuno, J.A. Martinez, “Power supply for a high-voltage application”, IEEE Trans. on Power Electronics, vol.23, pp.1608-1619, 2008. 195 [Mat05] H. Matsunami, “Current SiC technology for power electronic devices beyond Si”, The Symposium K Proceedings of the 3rd International Conference on Materials for Advanced Technologies, vol. 83, issue 1, pp. 2-4, 2005. [Pau05] C.R. Paul, “Electromagnetic compatibility”, ISBN: 0471755001, 2006. [Per09] D.J.Perreault, J.Hu, J.M.Rivas, Y.Han, O.Leitermann, R.C.N. Pilawa-Podgurski, A. Sagneri, C.R.Sullivan, “Opportunities and challenges in very high frequency power conversion”, Applied Power Electronics Conference and Exposition, 2009. APEC 2009, pp.1-14, 2009. [Ran82] V.T. Ranganathan, P.D. Ziogas, V.R. Stefanovic, “A regulated DC-DC voltage source converter using a high frequency link”, Industry Applications, IEEE Transactions on, vol. IA-18, no. 3, pp. 279-287, 1982. [Ras01] M.H. Rashid, “Power electronics”, ISBN: 0-12-581650-2, 2001. [Rei65] G. Reinhold, K. Truempy and J. Bill, “The symmetrical cascade rectifier, An accelerator power supply in the megavolt and milliampere range”, Proceedings of the 1st IEEE Particle Accelerator Conference., vol. NS-12, no. 3, pp. 288-292, 1965. [Ren07] M. Rentzsch, H. Guldner, C. Ditmanson, “Design of an adjustable high output voltage asymmetrically switched class D converter”, Power Electronics and Drive Systems, 2007. PEDS '07. 7th International Conference on, pp. 330-336, 2007. [Ren08] M. Rentzsch, F. Gleisberg, H. Guldner, F. Benecke, C. Ditmanson, “Closed analytical model of a 20 kV output voltage, 800 W output power series-parallelresonant converter with Walton Cockroft multiplier”, Power Electronics Specialists Conference, 2008. PESC 2008. IEEE, pp. 1023-1929, 2008. [Res99] T.A. Resnick, “Arc limiting device using the skin effect in ferro-magnetic materials”, US patent, patent Nr. 5978446, filed on Nov. 2, 1999. [Reu12] D. Reusch, F.C. Lee, Y. Su, “Optimization of a high density gallium nitride based non-isolated point of load module”, Energy Conversion Congress and Exposition (ECCE), 2012 IEEE, pp. 2914-2920, 2012. 196 [Sch08] References M.N.O. Sadiku, “Numerical techniques in electromagnetics”, ISBN: 0-84931395-3, 2001. [Sch08] P. Schavemaker, L. van der Sluis, “Electrical power system essentials”, ISBN: 978-0-470-51027-8, 2008. [Ste85] R.L. Steigerwald, “Analysis of a resonant transistor DC-DC converter with capacitive output filter”, Power Electronics, IEEE Transaction on, vol. IE-32, no. 4, pp. 439-444, 1985. [Ste88] R.L. Steigerwald, “A comparison of half-bridge resonant converter topologies”, Power Electronics, IEEE Transaction on, vol. 55, no. 2, pp. 722-730, 1988. [Sob02] W.T.Sobol, “High frequency X-ray generator basics”, Medical Physics, vol. 29, issue 2, pp.132-144, 2002. [Sul01] C.R. Sullivan, A.M. Kern, “Capacitors with fast current switching require distributed models”, Power Electronics Specialists Conference, 2001. PESC., pp. 1497-1503, 2001. [Sun00] J. Sun, H. Konishi, Y. Ogino and M. Nakaoka, “Series Resonant High-Voltage ZCS-PFM DC-DC Converter for Medical Power Electronics”, IEEE PESC 2000, vol.3, pp.1247-1252. [Swa03] D.G. Swanson, Jr. W. J.R. Hoefer, “Microwave circuit modeling using electromagnetic field simulation”, ISBN: 1-58053-308-6, 2003. [Tay32] L.S.Taylor and K.L.Tucker, “The comparison of high voltage X-ray generators”, Bureau of Standards Journal of Research, Vol. 9, No. 3, pp. 333. Research Paper 475, 1932. [Tip87] Paul A. Tipler, “College Physics”, ISBN: 0879012684, 1987. [Ver82] C.A. Vergers, “Network synthesis”, ISBN: 0-8306-1402-8, 1982. [Vla96] V. Vlatkovic, M.J. Schutten and R.L. Steigerwald, “Auxiliary Series Resonant Converter: a New Converter for High-Voltage, High-Power Applications”, Applied Power Electronics Conference and Exposition, vol. 1, pp. 493-499, 1996. 197 [Wan12] J.Wang, P. Luerkens, S.W.H. de Haan, F.A.Ferreira, “Analytical analysis of the equivalent parasitic capacitance of the high-voltage cascade multiplier in medical application of X-ray power generator”, IEEE IPEMC 2012, vol.1, pp.463-470, 2012. [Wan14] W. Wang, F. Pansier, S.W.H. de Haan, “Losses Comparison of Gallium Nitride and Silicon Transistors in a High Frequency Boost Converter”, 8th International Conference on Integrated Power Electronics Systems, 2014. [Wei69] M.M. Weiner, “Analysis of Cockcroft-Walton voltage multipliers with an arbitrary number of stages”, Review of Scientific Instruments, vol. 2, issue 2, pp. 330-333, 1969. [Wu99] T.F. Wu, J.C. Hung, “A PDM controlled series resonant multi-level converter applied for X-ray generators”, Power Electronics Specialists Conference, 1999, vol. 2, pp. 1177-1182, 1999. [Wyk13] J.D. van Wyk, F.C. Lee, “On a future for power electronics”, Emerging and Selected Topics in Power Electronics, IEEE Journal of, vol.1, issue 2, pp. 59-72, 2013. [Zha94] H. Zhang, A. Takaoka, K. Ura, “A numerical analysis approach to CockcroftWalton circuit in electron microscope”, Journal of Electron Microscopy, vol. 43, pp. 25-31, 1994. [Zha95] H. Zhang, A. Takaoka, K. Ura, “Transient analysis of Cockcroft-Walton cascade rectifier circuit after load short-circuit”, International Journal of Electronics, vol. 78, issue 5, pp. 995-1005, 1995. [Zha00] L. Zhao, D. Peng, J.D. van Wyk, “Analysis and Design of an LCLC resonant converter suitable for X-ray generator power supply”, Proceeding of the 2000 VPEC/CPES Seminar, pp. 360-365, 2000. 198 References Summary It is an inevitable trend that the power conversion module will have higher switching frequency and smaller volume in the future. Bandgap devices, such as SiC and GaN devices, accelerate the process. With this process, the parasitic elements in the module will probably have stronger influence on circuit operations than before. In this thesis, modeling of parasitic elements in the HV multiplier module of the HV generator in medical X-ray machines is addressed. The modeling is studied in two cases, the steady and transient operation of the circuit. The study results in a thorough understanding of the parasitic elements at a modular level and their influences on the circuit operation. In addition, the approaches to the modeling of the parasitics contained in this thesis can also be applied in other power electronic modules those have high power density by utilizing new devices in the future. Parasitic capacitances in the multiplier module in the steady state: The HV multiplier module in a CT scanner, which is typically a symmetrical C.W. multiplier module, can have an output as high as 160kV. This results in large number of diodes and capacitors in a compact module. By utilizing SiC diodes, the volume of the module will become much smaller than before, and the switching frequency of the circuit will become higher. The structural parasitic capacitances in such a module can be significant to the steady circuit operation. However, they were never studied before. In this thesis, the parasitic capacitances in the multiplier are thoroughly studied at a modular level. The study follows a systematic approach, including definition of the role of the capacitances, extraction of the capacitances by 3D FE simulation, construction of the analytical model, analysis and validation of the model and minimization of the parasitic capacitances. With the complete analysis, the structural parasitic capacitances in the HV module are well known and minimized. The obtained knowledge can also be applied to different HV multiplier modules. Electric field in the multiplier module in the steady state: 200 Summary Apart from the influence of the parasitic capacitances, the HV multiplier module has another important issue --- insulation. The strong electric field induced by the high voltage should be well contained to avoid breakdown of the insulation oil. In this thesis, a simple shielding technique is introduced for use in the field reduction. The distribution of the electric field strength is analyzed based on the results obtained through 3D FE field simulation. The distribution can be expressed as a function containing parasitic capacitances. Then, a shielding technique is proposed to reduce the field based on the expression. Simulation results show that the shielding technique can well contain the strong electric field. Parasitics in the multiplier module in the fast transient period: Over time, X-ray tubes have a tendency to arc-over. This results in short-circuiting of the load of the HV generator and in turn fast transient current pulses in the circuit. The bandwidths of such pulses can enter upper MHz range. In such a system, high-order circuit model of the parasitic elements are required for accurate circuit analysis. In this thesis, a theoretical development is presented on the circuit modeling of an electrical component or system in the beginning of the intermediate frequency range, which is just above the quasi-static range. The power series approach is utilized to obtain the LME model of the parasitics. With this approach, the underlying reason why the kth-order circuit model is valid for a structure with given electrical size is well understood. The calculation of EM fields and the derivation of the LME model is mathematically simpler than that by the full wave approach. Besides, the extension of the power series approach to the continuous spectrum systems provides an extension from sinusoildally single frequency systems towards real cases involving pulsed quantities. The theory can be developed in the future and applied to various applications in which high-order circuit model is necessary. Samenvatting Gelet op de huidige trend is het onvermijdelijk dat omvormer modules in de toekomst hogere schakelfrequenties en kleinere volumes zullen hebben. Bandgap componenten, zoals SiC en GaN, dragen bij aan een versnelling van dit proces. Als gevolg van deze trend, zullen parasitaire elementen in de module een veel grotere invloed hebben op werking van het circuit dan voorheen. In dit proefschrift wordt het modelleren van de parasitaire elementen, in de HV multiplier module van een HV generator in medische röntgen apparaten, behandeld. Het modelleren is bestudeerd voor twee casussen, namelijk in de stabiele en transiënte toestand van het circuit. Dit onderzoek resulteerde in een grondig inzicht van de parasitaire elementen op module niveau en hun invloed op de werking van het circuit. Daarnaast kunnen de methoden voor het modelleren van de parasitaire elementen, behandeld in dit proefschrift, ook toegepast worden in andere vermogenselektronische modules die in de toekomst gebruik maken van deze nieuwe componenten. Parasitaire condensators in de multiplier module bij stabiele toestand: De uitgansspanning van de HV multiplier module in een CT scanner, die meestal een C.W. multiplier module is, kan oplopen tot 160kV. Hierdoor zijn er een groot aantal diodes en condensators in een compacte module aanwezig. Door gebruik te maken van SiC diodes, wordt de volume van de module kleiner dan voorheen, en de schakelfrequentie van het circuit wordt hoger. De parasitaire condensators in het structuur van een module kunnen significant zijn voor werking van de module in stabiele toestand. Desondanks zijn ze nooit eerder onderzocht. In dit proefschrift zijn de parasitaire condensators uitgebreid onderzocht op module niveau. Dit onderzoek maakt gebruik van een systematische aanpak, waaronder het definiëren van de rol van de condensators, extractie van de condensators door middel van 3D FE simulatie, constructie van een analytisch model, analyse en validatie van het model en minimalisatie van de condensators. Met behulp van de volledige analyse worden de parasitaire condensators in het structuur van de HV module bekend en kunnen worden geminimaliseerd. De opgedane kennis kan ook toegepast worden bij andere HV multiplier modules. 202 Summary Elektrisch veld in de multiplier module bij stabiele toestand: Naast de invloed van de parasitaire condensators heeft de HV module een andere belangrijke issue --- isolatie. Het sterk elektrisch veld, geïnduceerd door de hoge spanning, moet goed worden beheerst om afbraak van de isolatie olie te voorkomen. In dit proefschrift wordt een eenvoudige afschermingstechniek geïntroduceerd voor veld reductie. De distributie van de elektrische veldsterkte is geanalyseerd op basis van resultaten verkregen door 3D FE veld simulatie. Deze distributie kan uitgedrukt worden als functie van de parasitaire condensators. Vervolgens is aan de hand van deze functie een afschermingstechniek voorgesteld voor de reductie van het veld. Aan de hand van simulaties is uitgewezen dat deze afschermingstechniek in staat is om het strek elektrisch veld te beheersen. Parasitaire elementen in de multiplier module in snelle transiënte perioden: Na verloop van tijd krijgen röntgen buizen de neiging om een vlamboog te creëren. Dit resulteert in kortsluiting van de belasting over de HV generator en vervolgens in snelle transiënte stroom pulsen in het circuit. De bandbreedte van zulke pulsen kunnen zich in het MHz gebied bevinden. In zulke systemen is een hoger orde model van de parasitaire elementen vereist voor een nauwkeurige circuit analyse. In dit proefschrift wordt een theoretische aanpak gepresenteerd voor het circuit modelleren van een elektrische component of systeem aan het begin van de intermediair frequentiebereik, net boven het quasi-statisch gebied. De machtreeks benadering is gebruik om het LME model van de parasitaire elementen te verkrijgen. Met deze aanpak wordt de onderliggende reden waarom het kth-orde circuit model geldig is voor een structuur van gegeven elektrische grootte duidelijk. Het berekenen van EM velden voor het afleiden van het LME model is mathematisch eenvoudiger dan de full wave aanpak. Trouwens, de uitbreiding van de machtsreeks benadering voor continue spectrum systemen biedt een uitbreiding van enkelvoudige sinusvormige frequentie systemen voor concrete gevallen met puls vormige grootheden. Deze theorie kan in de toekomst worden ontwikkeld en toegepast worden voor applicaties waarbij hoge orde circuit modellen nodig zijn. List of Publications Journal Papers: 1. J.Wang, S.W.H. de Haan, F.A.Ferreira, “Detailed derivation and minimization of the equivalent parasitic capacitance of a high voltage multiplier based on the complete model”, Accepted by IEEE Trans. on Industry Applications. 2. J.Wang, P. Luerkens, S.W.H. de Haan, F.A.Ferreira, “Complete model of parasitic capacitances in a cascade voltage multiplier in the high voltage multiplier”, submitted to IEEE Trans. on Power Electronics. Conference Papers: 3. J.Wang, P. Luerkens, S.W.H. de Haan, F.A.Ferreira, “Effect of technologies on structural parasitic capacitance of high voltage cascade rectifier”, Power Electronics and Applications (EPE 2011), Proceedings of the 2011-14th European Conference on, pp.1-10, 2011. 4. J.Wang, P. Luerkens, S.W.H. de Haan, F.A.Ferreira, “Analytical analysis of the equivalent parasitic capacitance of the high-voltage cascade multiplier in medical application of X-ray power generator”, Power Electronics and Motion Control Conference (IPEMC), 2012 7th International, vol.1, pp.463-470, 2012. 5. J.Wang, P. Luerkens, S.W.H. de Haan, F.A.Ferreira, “Complete model of parasitic capacitances in a cascade voltage multiplier in the high voltage multiplier”, ECCE Asia Downunder (ECCE Asia), 2013 IEEE, vol.1, pp.463-470, 2013. 6. J.Wang, S.W.H. de Haan, F.A.Ferreira, “Detailed derivation and minimization of the equivalent parasitic capacitance of a high voltage multiplier based on the complete model”, Energy Conversion Congress and Exposition (ECCE), 2013 IEEE, pp. 12661273, 2013. 204 List of Publications 7. J.Wang, S.W.H. de Haan, F.A.Ferreira, “Electric field reduction in a high voltage multiplier module in medical X-ray machines”, accepted by EPE 2014. Curriculum Vitae Jianing Wang was born in Anhui, China, in 1985. In 2006 and 2010, he got his bachelor and master degree respectively from Southeast University and Xi’an Jiaotong University, majored in power electronics. Since 2010, he began to work toward his Ph.D degree in the Electrical Power Processing (EPP) group, in Delft University of Technology (TUD), in the Netherlands. The title of his Ph.D project is “Smart Power Management”. It is a big joint project attended by 17 famous companies and universities in the European Union. The aim of the project is to develop the next generation of power semiconductors, SiC and GaN devices, and their applications in power converters. The focus of TUD’s research is on the modeling of parasitic elements at a modular level in the high voltage multiplier in medical X-ray machine. His research interests include the integration of power electronics converters, analysis of the EM field, wide bandgap power devices and renewable energy.