Transcript
5
4
3
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LA14 Block Diagram CLK GEN.
D
Mobile CPU
ICS 9LPRS365BKLFT (71.09365.A03) SILEGO SLG8SP513VTR(71.08513.003) 3
Project code: 91.4BW01.001 PCB P/N : 48.4BW01.01M 落 REVISION : SA PCB STACKUP
THERMAL EMC2102
Penryn 479
32
TOP VCC
4, 5
HOST BUS
DDR2 DIMM1 667/800 MHz
S
667/800/
[email protected]
SYSTEM DC/DC S
667/800MHz
Cantiga
16
INPUTS
CRT
OUTPUTS
BOTTOM
19
DDR Memory I/F
667/800MHz
5V_S5
INTEGRATED GRAHPICS
DCBATOUT
LCD
LVDS, CRT I/F
3D3V_S5
18
17
6,7,8,9,10,11
X4 DMI 400MHz
C
SYSTEM DC/DC
C-Link0
AZALIA
CX20561
1D05V_S0
6 PCIe ports
PCIex1
PCI/PCI BRIDGE
26
4 SATA
DCBATOUT
LAN Atheros AR8114 AR8132
ACPI 2.0
MIC In
TXFM 25
24
1D8V_S3
RJ45 25
RT9026
43 DDR_VREF_S0
1D8V_S3 DDR_VREF_S3
12 USB 2.0/1.1 ports
28
ETHERNET (10/100/1000MbE)
PCIex1
High Definition Audio
B
OUTPUTS
ICH9M
Codec
Matrix Storage Technology(DO)
ISL6266A
28
BIOS
KBC
Line Out (NO SPDIF)
1D5V_S0
CPU DC/DC
LPC BUS
Active Managemnet Technology(DO)
INT.SPKR
43
1D8V_S3
31
Serial Peripheral I/F
G1454 27
RT9018A
Mini Card Kedron a/b/g/n
LPC I/F
OP AMP
Winbond W25X16 16M Bits
KBC773L 33
12,13,14,15
INPUTS
LPC 34
HDD SATA
ODD SATA
A
USB 18
VCC_CORE_S0 0.35~1.5V
CHARGER Touch Pad 35
INT. KB 33
INPUTS
46 OUTPUTS BT+
SATA DCBATOUT
20 USB 4 Port
SATA 21
USB 23
CardReader Realtek RTS5159 30
DCBATOUT
MS/MS Pro/xD 30 /MMC/SD
A
5 in 1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Power Board
Title
36
Size A3
BLOCK DIAGRAM Document Number
Date: Thursday, May 07, 2009 5
B
OUTPUTS
DCBATOUT
DEBUG CONN.34
41
BQ24745 Camera (USB)
C
44
TPS51124 INPUTS
28
42
TPS51125
GND
AGTL+ CPU I/F
DDR2 DIMM2 667/800 MHz
D
4
3
2
Rev
SB
LA14 Sheet 1
1
of
52
A
B
C
ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5
4
D
ICH9M Integrated Pull-up and Pull-down Resistors
page 92
Signal
Usage/When Sampled
HDA_SDOUT
XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h). This signal has weak internal pull-down
CL_CLK[1:0]
PULL-UP 20K
CL_DATA[1:0]
PULL-UP 20K
HDA_SYNC
PCIE config1 bit0, Rising Edge of PWROK.
This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0#
PULL-UP 20K
GNT2#/ GPIO53
PCIE config2 bit2, Rising Edge of PWROK.
DPRSLPVR/GPIO16
PULL-DOWN 20K
ENERGY_DETECT
PULL-UP 20K
GPIO20
Reserved
This signal has a weak internal pull-up. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high.
HDA_BIT_CLK
PULL-DOWN 20K
GNT1#/ GPIO51
ESI Strap (Server Only) Rising Edge of PWROK
HDA_DOCK_EN#/GPIO33
PULL-UP 20K
HDA_RST#
PULL-DOWN 20K
HDA_SDIN[3:0]
PULL-DOWN 20K
HDA_SDOUT
PULL-DOWN 20K
GNT3#/ GPIO55
GNT0#: SPI_CS1#/ GPIO58
SPI_MOSI
3 GPIO49
SATALED# SPKR
TP3
GPIO33/ HDA_DOCK _EN#
Top-Block Swap Override. Rising Edge of PWROK.
Comment
ICH9 EDS 642879
SIGNAL
ESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile. Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space). Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.
CFG[4:3] CFG8 CFG[15:14] CFG[18:17]
Strap Description FSB Frequency Select
Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved
4
Reserved
CFG5
DMI x2 Select
CFG6
iTPM Host Interface
0 = DMI x2 1 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) 0 = Transport Layer Security (TLS) cipher suite with no confidentiality 1 = TLS cipher suite with confidentiality (default)
The pull-up or pull-down active when configured for nativeCFG9 GLAN_DOCK# functionality and determined by LAN controller
PCIE Graphics Lane
0 = Reverse Lanes,15->0,14->1 ect.. 1= Normal operation(Default):Lane Numbered in order
PCIE Loopback enable
0 = Enable (Note 3) 1= Disabled (default)
GNT[3:0]#/GPIO[55,53,51]
PULL-UP 20K
GPIO[20]
PULL-DOWN 20K
Integrated TPM Enable, Rising Edge of CLPWROK
Sample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.
GPIO[49]
PULL-UP 20K
LDA[3:0]#/FHW[3:0]#
PULL-UP 20K
LAN_RXD[2:0]
PULL-UP 20K
LDRQ[0]
PULL-UP 20K
LDRQ[1]/GPIO23
PULL-UP 20K
PME#
PULL-UP 20K
PWRBTN#
PULL-UP 20K
PCI Express Lane Reversal. Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)
SATALED#
PULL-UP 15K
No Reboot. Rising Edge of PWROK.
If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.
SPI_CS1#/GPIO58/CLGPIO6
PULL-UP 20K
SPI_MOSI
PULL-DOWN 20K
SPI_MISO
PULL-UP 20K
This signal should not be pull low unless using XOR Chain testing.
SPKR
PULL-DOWN 20K
TACH_[3:0]
PULL-UP 20K
TP[3]
PULL-UP 20K
USB[11:0][P,N]
PULL-DOWN 15K
Sampled low:the Flash Descriptor Security will be overridden. If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister.
CFG[2:0]
Intel Management engine Crypto strap
Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Flash Descriptor Security Override Strap Rising Edge of PWROK
Pin Name
0.5
CFG7
Boot BIOS Destination Selection 0:1. Rising Edge of PWROK.
XOR Chain Entrance. Rising Edge of PWROK.
page 218
PULL-DOWN 20K
GLAN_DOCK#
落
Montevina Platform Design guide 22339
Rev.1.5
Resistor Type/Value
HDA_SYNC
DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK. applications and required to be high for mobile applications.
E
Cantiga chipset and ICH9M I/O controller Hub strapping configuration
CFG10 CFG[13:12]
CFG16
CFG19
00 10 01 11
XOR/ALL
= = = =
Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default)
FSB Dynamic ODT
0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default)
DMI Lane Reversal
0 = Normal operation(Default): Lane Numbered in Order
3
1 = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
CFG20
Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe
0 = Only Digital Display Port or PCIE is operational (Default) 1 =Digital display Port and PCIe are operting simulataneously via the PEG port 0 =No SDVO Card Present (Default)
SDVO_CTRLDATA
SDVO Present 1 = SDVO Card Present 0 = LFP Disabled (Default)
L_DDC_DATA
Local Flat Panel (LFP) Present
1= LFP Card Present; PCIE disabled
NOTE: 1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal. 2. iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware. This 'Soft-Strap' is activated only after enabling iTPM via CFG6. Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
2
2
SMBus EMC2102
Thermal
USB Table USB
PCIE Routing
1
LANE1
LAN Atheros AR8114A
LANE2
MiniCard WLAN
LANE3
NC
LANE4
NC
LANE5
NC
LANE6
NC
Pair
KBC BAT_SCL
Device
0
USB1
1
NC
2
NC
3
MINIC1
4
WEBCAM
BATTERY
5
NC
6
NC
7
Bluetooth
Wistron Corporation
8
NC
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
9
USB2(High speed)
10
NC
11
CardReader
1
ICH9M
Title
SMBC_ICH
9LPRS365BKLFT DDR
Reference Size A3
Document Number
Date: Thursday, May 07, 2009
Rev
SB
LA14 Sheet
2
of
52
C
D
1
1
1
1
1
3D3V_CLKGEN_S0
0915 add EC34 for EMI demand
C205
DY 2
2
2
DY
2
1
C152
SCD1U16V2ZY-2GP
2
R87 2 1 0R0402-PAD C155 SCD1U16V2ZY-2GP
2
1
1
C224 SCD1U16V2ZY-2GP
2
1
C226 SCD1U16V2ZY-2GP
DY
3D3V_CLKGEN_S0 C179 SCD1U16V2ZY-2GP
DY
SC4D7U10V5ZY-3GP
2
1
C173
C204
2
DY
SCD1U16V2ZY-2GP
2
1
C196
DY
3D3V_S0
1015 modify component size of R87
1015 modify component size of R80
1 R80 2 0R2J-2-GP SCD1U16V2ZY-2GP
2
C156
SCD1U16V2ZY-2GP
4 3 2 1
C176
SCD1U16V2ZY-2GP
SRN10KJ-6-GP RN61
C149
SCD1U16V2ZY-2GP
DY
C165
SC4D7U10V5ZY-3GP
2
1 1231modify R80
3D3V_CLKPLL_S0 SCD1U16V2ZY-2GP
4
SC1U16V3ZY-GP
SC4D7U6D3V3KX-GP
DY
3D3V_S0 C227
5 6 7 8
C221
1
3D3V_48MPWR_S0
2
0R2J-2-GP
2
1 R95
R302 1 2 0R2J-2-GP
SB 1124 add R302
2
1015 modify component size of R95 1
3D3V_S0
E
3D3V_S0
2
1D05V_S0
1
B
1
A
1
落 4
1222 modify R87
RN62
R91 2 1 0R0402-PAD
GEN_XTAL_OUT
3 2
CPUT0 CPUC0
61 60
CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4
CPU
CPUT1_F CPUC1_F
58 57
CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6
1
2
RN20
NB
CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8
54 53
CLK_PCIE_LAN 24 CLK_PCIE_LAN# 24
GEN_XTAL_OUT_R
30 13
C230 SC33P50V2JN-3GP
1 2
CLK48_5159 CLK48_ICH
4,7
CPU_SEL0
R88
3
2
4 3
CLK48 17
LAN
DY
45 44
CPU_SEL2
8 7 6 5
3D3V_S0
15,16,17 SMBC_ICH 15,16,17 SMBD_ICH
7 6
2 R89
1 2 3 4
RN28 SRN10KJ-6-GP
DY
63
13 CLK_PWRGD 1 10KR2J-3-GP PCLKCLK0 PCLKCLK1 PCLKCLK2
RN23 PCLKCLK2 CPU_SEL2_R PCLKCLK4 PCLKCLK5
13
1 2 3 4
CLK_ICH14
33 13
PCLK_KBC PCLK_ICH
4,7
CPU_SEL1
8 7 6 5
CPU_SEL2_R PCLKCLK3 PCLKCLK4 PCLKCLK5
SRCT6 SRCC6
48 47
SRCT10 SRCC10
41 42
SRCT11/CR#_H SRCC11/CR#_G
40 39
SRCT9 SRCC9
37 38
CLK_PCIE_MINI1 31 CLK_PCIE_MINI1# 31
SRCT4 SRCC4
34 35
CLK_MCH_3GPLL 7 CLK_MCH_3GPLL# 7
SRCT3/CR#_C SRCC3/CR#_D
31 32
SRCT2/SATAT SRCC2/SATAC
28 29
CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12
27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2
24 25
DREFSSCLK 7 DREFSSCLK# 7
SRCT0/DOTT_96 SRCC0/DOTC_96
20 21
DREFCLK 7 DREFCLK# 7
CK_PWRGD/PD#
PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN
64 5
FSLB/TEST_MODE REF0/FSLC/TEST_SEL
1014 add ER5 for EMI deamnd ICS9LPRS365BKLFT-GP-U
ICS9LPRS365BKLFT setting table PIN NAME DESCRIPTION
71.09365.A03 2nd = 71.08513.003
PCI0/CR#_A
Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair
PCI1/CR#_B
Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair
PCI2/TME
0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed
PCI3
3.3V PCI clock output
PCI4/27M_SEL
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96# 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#
PCI_F5/ITP_EN
0 =SRC8/SRC8# 1 = ITP/ITP#
SRCT3/CR#_C
Byte 5, bit 3 0 = SRC3 enabled (default) 1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit 2 0 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair
DY
3
SB 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#)
PCIE_REQ_MINI#_R
SB 1126 add the net(PCIE_REQ_MINI#)
MINI1 NB CLK SB 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#)
SB SATA NB CLK NB CLK (96 MHz)
2
SEL2 SEL1 SEL0 FSC FSB FSA PIN NAME
DESCRIPTION
SRCC3/CR#_D
Byte 5, bit 1 0 = SRC3 enabled (default) 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair
SRCC7/CR#_E
Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_F controls SRC6
SRCT7/CR#_F
Byte 6, bit 6 0 = SRC7 enabled (default) 1= CR#_F controls SRC8
SRCC11/CR#_G
Byte 6, bit 5 0 = SRC11# enabled (default) 1= CR#_G controls SRC9
SRCT11/CR#_H
Byte 6, bit 4 0 = SRC11 enabled (default) 1= CR#_H controls SRC10
1 0 0 0 0
0 0 1 1 0
1 1 1 0 0
CPU
FSB
100M 133M 166M 200M 266M
X 533M 667M 800M 1066M
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Clock Generator Document Number
Date: Thursday, May 07, 2009 B
EC25
SB DMI
CLK_PCIE_ICH 13 CLK_PCIE_ICH# 13
Rev
LA14 A
1
PCLK_FWH
65
NC#55
DY
2
1
55
GND GNDSRC GNDSRC GNDSRC GNDCPU GND
1 PCLKCLK3 33R2J-2-GP
2
22 30 36 49 59 26
ER5
GND48 GNDPCI GNDREF
PCLK_FWH
18 15 1
34
GND
SRN33J-7-GP CPU_SEL2_R
DY
SB 1126 add the net(PCIE_REQ_LAN#)
51 50
SCLK SDATA
8 10 11 12 13 14
PCIE_REQ_LAN#_R
SRCT7/CR#_F SRCC7/CR#_E PCI_STOP# CPU_STOP#
3D3V_S0 4,7
EC34
2
EC33
USB_48MHZ/FSLA
SRN22-3-GP 1 2K2R2J-2-GP
13 PM_STPPCI# 13 PM_STPCPU#
1
1
DY
2
1 EC66
2
1
2
2
DY
2
19 27 43 52 33 56 VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO
X1 X2
EC62
2
82.30005.891
4 16 9 46 62 23 VDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3
1 1224 modify R91
X4 X-14D31818M-35GP
1
U14
1126 modify RN61 and RN62
DY
SC22P50V2JN-4GP
C229 SB SC33P50V2JN-3GP GEN_XTAL_IN 1 2
EC31
CLK48_5159 SC5P50V2CN-2GP
SB 1120 modify RN61 and RN62
CL=20pF±0.2pF
CLK48_ICH SC5P50V2CN-2GP
RN61 and RN62
PCLK_ICH SC5P50V2CN-2GP
SB 1120 add RN61 and RN62
3D3V_CLKPLL_S0
SC5P50V2CN-2GP
SB 1127 swap the nets of
SRN470J-3-GP
PCLK_KBC
1
CLK_ICH14 3D3V_48MPWR_S0
SC5P50V2CN-2GP
8 PCIE_REQ_LAN#_R 7 PCLKCLK0 6 PCIE_REQ_MINI#_R 5 PCLKCLK1
1 2 3 4
24 PCIE_REQ_LAN# 13 SATACLKREQ# 31 PCIE_REQ_MINI# 7 CLK_MCH_OE#
C
D
SB Sheet E
3
of
52
A
6
B
C
D
E
H_DINV#[3..0] U33A 1 OF 4
TPAD14-GP
TP20
RSVD_CPU_11
1
B1
H_D#[63..0]
G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
BCLK0 BCLK1
H_DSTBN#0 H_DSTBP#0 H_DINV#0
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# DSTBN0# DSTBP0# DINV0#
H_DSTBN#1 H_DSTBP#1 H_DINV#1
H_D#16 N22 H_D#17 K25 H_D#18 P26 H_D#19 R23 H_D#20 L23 H_D#21 M24 H_D#22 L22 H_D#23 M23 H_D#24 P25 H_D#25 P23 H_D#26 P22 H_D#27 T24 H_D#28 R24 H_D#29 L25 H_D#30 T25 H_D#31 N25 L26 M26 N24
D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#
H_TRDY# 6 H_HIT# H_HITM#
H_THERMDA
6 6
DY H_THERMDC XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#
C438 SC2200P50V2KX-2GP
1D05V_S0 6 6 6
R63 68R2-GP
D21 CPU_PROCHOT# A24 B25
H_THERMDA 32 H_THERMDC 32
C7
PM_THRMTRIP-A# 7,12,39
A22 A21
1 R62
DY
2
CPU_PROCHOT#_R
41
0R2J-2-GP
CLK_CPU_BCLK 3 CLK_CPU_BCLK# 3
1D05V_S0
PM_THRMTRIP# should connect to ICH9 and MCH without T-ing ( No stub)
2
THERMTRIP#
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
6 6 6
R179 1KR2F-3-GP Layout Note: "CPU_GTLREF0" 0.5" max length.
CPU_GTLREF0
1
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#
U33B 2 OF 4 6
R181 2KR2F-3-GP
DY C352 TPAD14-GP
62.10079.001 2nd = 62.10053.401
TPAD14-GP TPAD14-GP 3,7 3,7 3,7
1D05V_S0
TP18 TP44 TP60
CPU_SEL0 CPU_SEL1 CPU_SEL2
AD26 TEST1 C23 TEST2 D25 RSVD_CPU_12 C24 1 TEST4 AF26 1RSVD_CPU_13 AF1 RSVD_CPU_14 A26 1 B22 B23 C21
GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
DATA GRP2
HIT# HITM#
H_RS#0 H_RS#1 H_RS#2
KEY_NC
MISC
BSEL0 BSEL1 BSEL2
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# DSTBN2# DSTBP2# DINV2#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP0 COMP1 COMP2 COMP3
R26 U26 AA1 Y1
COMP0 COMP1 COMP2 COMP3
DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI#
E5 B5 D24 D6 D7 AE6
3
H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6
H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 R53 R51 R45 R44
1
2 54D9R2F-L1-GP
XDP_TDI
R48
1
2 54D9R2F-L1-GP
XDP_BPM#5
R43
1
2 54D9R2F-L1-GP
H_CPURST#
R213 1
XDP_TCK
R41
XDP_TRST#
R42
1 1
DY
1 R65
DY
2 51R2F-2-GP
1 R215
DY
2
2 54D9R2F-L1-GP
2 C343
2 2 2 2
27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP
2
BGA479-SKT6-GPU7
62.10079.001 2nd = 62.10053.401
2 TEST1 1KR2J-1-GP
1 1 1 1
H_DPRSTP# 7,12,41 H_DPSLP# 12 H_DPWR# 6 H_PWRGD 12,39,48 H_CPUSLP# 6 PSI# 41
Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" .
Follow Demo Circuit 1
4
6
12
DATA GRP3
C1 F3 F4 G3 G2
H_INIT#
H_LOCK# 6 H_CPURST# 6,48 H_RS#[2..0]
1
RESET# RS0# RS1# RS2# TRDY#
H_BREQ#0 6
BGA479-SKT6-GPU7
R50
6
H_IERR#
2
H4
HCLK
XDP_TMS
6
H_DSTBP#[3..0]
1 LOCK#
PROCHOT# THRMDA THRMDC
RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
H_DSTBN#[3..0]
2
CONTROL
F1 D20 B3
2
2
BR0# IERR# INIT#
SC1KP50V2KX-1GP
M4 N5 T2 V3 B2 C3 D2 D22 D3 F6
6
Place testpoint on H_IERR# with a GND 0.1" away
R64 56R2J-4-GP
1
STPCLK# LINT0 LINT1 SMI#
DEFER# DRDY# DBSY#
2
12 12 12 12
H_D#[63..0]
1
H_STPCLK# H_INTR H_NMI H_SMI#
D5 C6 B4 A3
H_DEFER# 6 H_DRDY# 6 H_DBSY# 6
H_DSTBP#[3..0]
1D05V_S0
1
A20M# FERR# IGNNE#
H5 F21 E1
6 6 6
THERMAL
ICH
12 12 12
H_ADS# H_BNR# H_BPRI#
2
H_A20M# H_FERR# H_IGNNE#
A6 A5 C4
Side Band Non GTL
A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#
TP11 TPAD14-GP
H1 E2 G5
DATA GRP1
H_ADSTB#1
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
3
6
REQ0# REQ1# REQ2# REQ3# REQ4#
ADDR GROUP 1
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_DINV#[3..0]
H_DSTBN#[3..0]
DATA GRP0
H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L1
ADS# BNR# BPRI#
XDP/ITP SIGNALS
H_ADSTB#0 H_REQ#[4..0]
1
A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0#
RESERVED
4
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
ADDR GROUP 0
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 6 6
落
H_A#[35..3]
H_A#[35..3]
Net "TEST4" as short as possible, make sure "TEST4" routing is reference to GND and away other noisy signals
TEST2 1KR2J-1-GP
TEST4 1 SCD1U10V2KX-4GP
DY
2 54D9R2F-L1-GP
3D3V_S0
1
All place within 2" to CPU XDP_DBRESET# R60
1
DY
Wistron Corporation
2 1KR2J-1-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
1D05V_S0 Title XDP_TDO
R47
1
DY
2 54D9R2F-L1-GP
CPU (1 of 2) Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 A
B
C
D
Sheet E
4
of
52
A
B
C
D
E
U33D
VCC_CORE
1 4
1
1
1
1
DY
TPAD14-GP
ST900U2D5VM-1-GP
TP46
2 3
DY 2
DY 2
DY 2
2
1 2
1 2
1 2
1
C52 SCD1U10V2KX-4GP
DY
SCD1U10V2KX-4GP
2
C96
TC6
1 2
1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
DY
C79 SC10U6D3V5MX-3GP
DY
C71 SC10U6D3V5MX-3GP
DY
C49 SC10U6D3V5MX-3GP
DY
C80 SC10U6D3V5MX-3GP
DY
C62 SC10U6D3V5MX-3GP
DY
C48 SC10U6D3V5MX-3GP
DY
C381 SC10U6D3V5MX-3GP
CAP
C384 SC10U6D3V5MX-3GP
CAP
C382 SC10U6D3V5MX-3GP
CAP
C383 SC10U6D3V5MX-3GP
CAP
C61 SC10U6D3V5MX-3GP
CAP
C90 SC10U6D3V5MX-3GP
2
C70 SC10U6D3V5MX-3GP
CAP
1
C92
2
1
VCC_CORE
DY
1D05V_S0
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
VCCA VCCA
B26 C26
VID0 VID1 VID2 VID3 VID4 VID5 VID6
AD6 AF5 AE5 AF4 AE3 AF3 AE2
VCCSENSE
AF7
VCC_SENSE 41
VSSSENSE
AE7
VSS_SENSE 41
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1 1 2
1 2
1
C446
DY
PBY160808T-121Y-GP
C429
68.00206.021
2nd = 68.00230.041
2
VCCSENSE and VSSSENSE lines should be of equal length.
Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line.
SC4D7U6D3V3KX-GP
2
C66 SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
1
C65
Layout Note: R39 100R2F-L1-GP-U
62.10079.001
DY
C63 SCD1U10V2KX-4GP
R38 100R2F-L1-GP-U
C83 SCD1U10V2KX-4GP
DY
2
C82 SCD1U10V2KX-4GP
VCC_CORE
C420
SC10U6D3V5MX-3GP
41
SCD01U16V2KX-3GP
H_VID[6..0]
C81 SCD1U10V2KX-4GP
L10
1
C69 SCD1U10V2KX-4GP
1D5V_S0 1D5V_VCCA_S0
H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6
C78 SCD1U10V2KX-4GP
layout note: "1D5V_VCCA_S0" as short as possible
1
C68
2
1
DY
2
1
1D05V_S0 C84
BGA479-SKT6-GPU7
2nd = 62.10053.401
C93 SCD1U10V2KX-4GP
DY
C59 SCD1U10V2KX-4GP
DY
C53 SCD1U10V2KX-4GP
DY
C91 SCD1U10V2KX-4GP
DY
C97 SCD1U10V2KX-4GP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
C54
SCD1U10V2KX-4GP
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
SC10U6D3V5MX-3GP
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
SCD1U10V2KX-4GP
2
VCC_CORE
VCC_CORE U33C 3 OF 4
SCD1U10V2KX-4GP
3
VCC_CORE
2
4
VCC_CORE
One phase--> ADD TC6 are 77.E9071.011
1
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3
落
4 OF 4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
4
3
2
1
TPAD14-GP
TP45
1 1
TPAD14-GP TPAD14-GP
TP48 TP21
1 1
TPAD14-GP TPAD14-GP
TP61 TP43
BGA479-SKT6-GPU7
62.10079.001 2nd = 62.10053.401
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (2 of 2) Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 A
B
C
D
Sheet E
5
of
52
5
4
3
2
1
H_A#[35..3]
1D05V_S0
H_SWING routing Trace width and Spacing use 10 / 20 mil
R239 221R2F-2-GP
2
H_SWING Resistors and Capacitors close MCH 500 mil ( MAX )
R238 100R2F-L1-GP-U
2
2
C478 SCD1U10V2KX-4GP
1
1
H_SWING
C
H_RCOMP routing Trace width and Spacing use 10 / 20 mil 1 R226
2 24D9R2F-L-GP
H_RCOMP
Place them near to the chip ( < 0.5")
B
F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
HOST
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
1
D
H_D#[63..0]
H_D#[63..0]
2
4,48 H_CPURST# 4 H_CPUSLP#
H_AVREF
A11 B11 1
R240 2KR2F-3-GP
C12 E11
C479 SCD1U16V2ZY-2GP
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY#
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
J8 L3 Y13 Y1
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
L10 M7 AA5 AE6
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
L9 M8 AA6 AE5
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
B15 K13 F13 B13 B14
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_SWING H_RCOMP H_CPURST# H_CPUSLP#
H_RS#_0 H_RS#_1 H_RS#_2
B6 F12 C8
H_RS#0 H_RS#1 H_RS#2
H_AVREF H_DVREF
4
D
H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_DEFER# 4 H_DBSY# 4 CLK_MCH_BCLK 3 CLK_MCH_BCLK# 3 H_DPWR# 4 H_DRDY# 4 H_HIT# 4 H_HITM# 4 H_LOCK# 4 H_TRDY# 4
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_REQ#[4..0]
H_RS#[2..0]
C
H_DINV#[3..0]
4
H_DSTBN#[3..0]
4
H_DSTBP#[3..0]
4
H_REQ#[4..0]
H_RS#[2..0]
B
4
4
CANTIGA-GM-GP-U-NF
2
1
1
R241 1KR2F-3-GP
C5 E3
H_A#[35..3]
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_DINV#[3..0]
1D05V_S0 H_SWING H_RCOMP
落
1 OF 10
U35A 4
2
71.CNTIG.00U
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Cantiga (1 of 6)_HOST
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
6
of
52
5
4
3
2
1
2 OF 10
U35B
1
BA17 AY16 AV16 AR13
M_CS0# M_CS1# M_CS2# M_CS3#
17 17 16 16
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
BD17 AY17 BF15 AY13
M_ODT0 M_ODT1 M_ODT2 M_ODT3
17 17 16 16
SM_RCOMP SM_RCOMP#
BG22 BH21
M_RCOMPP M_RCOMPN
SM_RCOMP_VOH SM_RCOMP_VOL
BF28 BH28
SM_RCOMP_VOH SM_RCOMP_VOL
SM_VREF SM_PWROK SM_REXT SM_DRAMRST#
AV42 AR36 BF17 BC36
SM_REXT 1R243 TP_SM_DRAMRST#
DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
B38 A38 E41 F41
DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#
PEG_CLK PEG_CLK#
F43 E43
M_RCOMPP
DY
1 R211
2 100R2J-2-GP
DY
2
C147 SC100P50V2JN-3GP
B
RN29 PM_EXTTS#0 PM_EXTTS#1
4 3
1 2 SRN10KJ-5-GP
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
AE40 AE38 AE48 AH40
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
AE35 AE43 AE46 AH42
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
AD35 AE44 AF46 AH43
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
C34
2 499R2F-2-GP TP36TPAD30
DREFCLK 3 DREFCLK# 3 DREFSSCLK 3 DREFSSCLK# 3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
18 GMCH_TXAOUT0+ 18 GMCH_TXAOUT1+ 18 GMCH_TXAOUT2+
H48 D45 F40 B40
LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3
A41 H38 G37 J37
LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3
B42 G38 F37 K37
LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3
F25 H25 K25
TVA_DAC TVB_DAC TVC_DAC
H24
TV_RTN
C31 E32
TV_DCONSEL_0 TV_DCONSEL_1
GMCH_BLUE
E28
CRT_BLUE
GMCH_GREEN
G28
CRT_GREEN
TVA_DAC TVB_DAC TVC_DAC
13 13 13 13
DMI_TXP0 13 DMI_TXP1 13 DMI_TXP2 13 DMI_TXP3 13 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
19
13 13 13 13
GMCH_BLUE
19 GMCH_GREEN 19
DMI_RXP0 13 DMI_RXP1 13 DMI_RXP2 13 DMI_RXP3 13
GMCH_RED
19 GMCH_DDCCLK 19 GMCH_DDCDATA 19 GMCH_HSYNC 19 GMCH_VSYNC
GMCH_RED
GMCH_DDCCLK
2 1
3 4
GMCH_DDCDATA GMCH_HS GMCH_VS
J28
CRT_RED
G29
CRT_IRTN
H32 J32 J29 E29 L29
CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC
RN21 SRN33J-5-GP-U 1 2 CRT_IREF R253 1K02R2F-1-GP
H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46
PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46
落
1 49D9R2F-GP
Close to GMCH as 500 mils.
D
C
CANTIGA-GM-GP-U-NF
71.CNTIG.00U FOR Cantiga: 1.02k_1% ohm Teenah: 1.3k ohm
0912 add these parts for EMI demand 1017 delete these parts(EC208~EC210)
CRT_IREF routing Trace width use 20 mil
1D05V_S0
CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF
AH37 AH36 AN36 AJ35 AH34
CLPWROK_MCH 2 R111 1 0R0402-PAD MCH_CLVREF
CL_CLK0 13 CL_DATA0 13 PWROK 13,39 CL_RST#0 13
C231
NC
3D3V_S0
NC#BG48 NC#BF48 NC#BD48 NC#BC48 NC#BH47 NC#BG47 NC#BE47 NC#BH46 NC#BF46 NC#BG45 NC#BH44 NC#BH43 NC#BH6 NC#BH5 NC#BG4 NC#BH3 NC#BF3 NC#BH2 NC#BG2 NC#BE2 NC#BG1 NC#BF1 NC#BD1 NC#BC1 NC#F1 NC#A47
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
GFX_VR_EN
LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3
0912 delete GMCH_TXB*
C250
DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC#
N28 M28 G36 E36 K36 H36
TSATN#
B12
HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC
B28 B30 B29 C29 A28
SCD1U10V2KX-4GP
4,12,39 PM_THRMTRIP-A# 13,41 PM_DPRSLPVR
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47
AE41 AE37 AE47 AH39
B33 B32 G33 F33 E33
H47 E46 G40 A40
DDR_VREF_S3
CLK_MCH_3GPLL 3 CLK_MCH_3GPLL# 3
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
18 GMCH_TXAOUT018 GMCH_TXAOUT118 GMCH_TXAOUT2-
18 GMCH_TXACLK18 GMCH_TXACLK+
R93 1KR2F-3-GP
1014 swap these nets RN14
1
PLT_RST1#
1 0R0402-PAD
ME
13,24,30,31,33,34
2 R110
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
1
13,39 PWROK
R29 B7 N33 P32 AT40 AT11 T20 R32
PM
PM_SYNC# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PWROK_GD RSTIN# PM_THRMTRIP-A# PM_DPRSLPVR
13 PM_SYNC# 4,12,41 H_DPRSTP#
MISC
1
L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK
TPAD14-GP
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_CMP 2
2
R98
GRAPHICS VID
DY
M29 C44 B43 E37 E38 C41 C40 B37 A37
TP73
PEG_COMPI PEG_COMPO
VGA
R306 1
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
CFG
1 1224 add
3D3V_S0
T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R306 R20 M20 2 4K02R2F-GP CFG16 L21 H21 P29 R28 2 4K02R2F-GP CFG20 T28
CPU_SEL0 CPU_SEL1 CPU_SEL2
1 TPAD14-GP
TP34 CLK_MCH_OE# 3 MCH_ICH_SYNC# 13
R242 MCH_TSATN# 2
1
GMCH_BLUE R92 511R2F-2-GP
GMCH_GREEN GMCH_RED
1 2 3 4
8 7 6 5 B
SRN150F-1-GP
FOR Cantiga:500 ohm Teenah: 392 ohm
1D05V_S0 RN15
56R2J-4-GP
HDA
2
C
3,4 3,4 3,4
DMI
1 R246 80D6R2F-L-GP
GMCH_LCDVDD_ON LIBG 1 L_LVBG
18 GMCH_LCDVDD_ON
TV
M_RCOMPN
L_CTRL_DATA L_DDC_CLK L_DDC_DATA
GRAPHICS
SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1
CLK
2
R247 80D6R2F-L-GP
17 17 16 16
M33 K33 J33
SCD1U10V2KX-4GP
1D8V_S3
M_CKE0 M_CKE1 M_CKE2 M_CKE3
LCTLB_DATA CLK_DDC_EDID DAT_DDC_EDID
R99
T37 T36
PCI-EXPRESS
layout take note
BC28 AY28 AY36 BB36
L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK
18 CLK_DDC_EDID 18 DAT_DDC_EDID
1
RESERVED#BG23 RESERVED#BF23 RESERVED#BH18 RESERVED#BF18
SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1
17 17 16 16
2
1
2
BG23 BF23 BH18 BF18
M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3
L32 G32 M32
1
2
RESERVED#AY21
2
1
1
AY21
C483 C484 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
AR24 AR21 AU24 AV20
L_BKLTCTL GMCH_BL_ON LCTLA_CLK
18 L_BKLTCTL 33 GMCH_BL_ON
LVDS
SM_RCOMP_VOL R248 1KR2F-3-GP
SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1
M_CLK_DDR0 17 M_CLK_DDR1 17 M_CLK_DDR2 16 M_CLK_DDR3 16
1
RESERVED#B31 RESERVED#B2 RESERVED#M1
AP24 AT21 AV24 AU20
2
2
B31 B2 M1
SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1
2
1
1
C487 SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP
2
R250 3K01R2F-3-GP
C489
RSVD
D
2
1
SM_RCOMP_VOH
DDR CLK/ CONTROL/COMPENSATION
1 2
R251 1KR2F-3-GP
RESERVED#M36 RESERVED#N36 RESERVED#R33 RESERVED#T33 RESERVED#AH9 RESERVED#AH10 RESERVED#AH12 RESERVED#AH13 RESERVED#K12 RESERVED#AL34 RESERVED#AK34 RESERVED#AN35 RESERVED#AM35 RESERVED#T24
1D05V_S0
3 OF 10
U35C
M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24
1D8V_S3
TVA_DAC TVB_DAC TVC_DAC
1 2 3 4
8 7 6 5
SRN75J-1-GP
CANTIGA-GM-GP-U-NF
3D3V_S0
71.CNTIG.00U RN32 LCTLB_DATA LCTLA_CLK CLK_MCH_OE#
5 6 7 8
4 3 2 1 SRN10KJ-6-GP
RN22
Pin Name
Strap Description
GMCH_LCDVDD_ON GMCH_BL_ON
Configuration
A
CFG20
Digital DisplayPort (SDVO/DP/HDMI) Concurrent with PCIE
LIBG
Low = Only digital DisplayPort (SDVO/DP/HDMI) or PCIE is operational (default)
1 2 3 4
8 7 6 5 A
SRN100KJ-8-GP-U R103 1 2 2K37R2F-GP
Wistron Corporation
High = Digital DisplayPort (SDVO/DP/HDMI) and PCIE are operating simultaneously via the PEG port
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cantiga (2 of 6)_DMI/PM/CFG Size
Document Number
Date:
Thursday, May 07, 2009
Rev
LA14 5
4
3
2
SB Sheet
1
7
of
52
4
B
SA_RAS# SA_CAS# SA_WE#
BB20 BD20 AY20
M_A_RAS# 17 M_A_CAS# 17 M_A_WE# 17
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]
M_A_DM[7..0] 17
M_A_DQS[7..0] 17
M_A_DQS#[7..0] 17
M_A_A[14..0] 17
M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3
5 OF 10
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
落
SB_BS_0 SB_BS_1 SB_BS_2
BC16 BB17 BB33
M_B_BS#0 16 M_B_BS#1 16 M_B_BS#2 16
SB_RAS# SB_CAS# SB_WE#
AU17 BG16 BF14
M_B_RAS# 16 M_B_CAS# 16 M_B_WE# 16 D
M_B_DM[7..0]
B
M_A_BS#0 17 M_A_BS#1 17 M_A_BS#2 17
MEMORY
BD21 BG18 AT25
SYSTEM
A
1
U35E 16 M_B_DQ[63..0]
SA_BS_0 SA_BS_1 SA_BS_2
M_A_DM[7..0]
MEMORY
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
SYSTEM
C
AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12
DDR
D
M_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
2
4 OF 10
U35D 17 M_A_DQ[63..0]
3
DDR
5
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14
M_B_DM[7..0] 16
M_B_DQS[7..0]
M_B_DQS[7..0] 16
M_B_DQS#[7..0]
M_B_DQS#[7..0] 16
M_B_A[14..0]
C
M_B_A[14..0] 16
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Cantiga (3 of 6)_DDR
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
8
of
52
5
4
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
T32
VCC
G9
1
2
VCC_GMCH_35
VCC CORE
2
2 1
C450
DY
2
1 2
C456
SCD1U10V2KX-4GP
Coupling CAP
AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23
D
POWER
1
1
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1
1 2
2
2
1
1 2
GAP-CLOSE-PWR
Place CAP where LVDS and DDR2 taps
1
1
C211
2
2
2
1
1 2
2
2
2
C210
DY
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
C
CANTIGA-GM-GP-U-NF
SB
1118 delete TC27
1
1
C235
2
C246
C253
2
1
C172
2
1
C136
2
2
C140
SC1U10V3KX-3GP
2
C153
SCD22U10V2KX-1GP 2 1
1
1
71.CNTIG.00U
SC1U10V3KX-3GP
VCC SM LF
VCC GFX
C208
SC10U6D3V5MX-3GP
C202
DY
SC10U6D3V5MX-3GP
C225
Place on the Edge
AV44 SM_LF1_GMCH BA37 SM_LF2_GMCH AM40 SM_LF3_GMCH AV21 SM_LF4_GMCH AY5 SM_LF5_GMCH AM10 SM_LF6_GMCH BB13 SM_LF7_GMCH SCD47U16V3ZY-3GP
CANTIGA-GM-GP-U-NF
C203
SC10U6D3V5MX-3GP
C207
DY
1
1
1
1D8V_S3
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
1D05V_S0
VCC NCTF
POWER
Coupling CAP 370 mils from the Edge
SC10U6D3V5MX-3GP
VCC GFX NCTF
C177 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U10V3ZY-6GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
VCC SM
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
C193
SC10U6D3V5MX-3GP
C175
DY
C145
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
FOR VCC SM
VCC_AXG_SENSE VSS_AXG_SENSE
71.CNTIG.00U
C194
C144
Coupling CAP
SCD22U10V2KX-1GP
AJ14 AH14
C164
DY
DY
C111
DY
SCD1U10V2KX-4GP
1 1
C183
Place on the Edge
SCD1U10V2KX-4GP
TPAD14-GP TPAD14-GP
C162
SC10U6D3V5MX-3GP
C
C163
DY
SCD1U10V2KX-4GP
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
DY
TC21 ST220U2VBM-3GP
SC10U6D3V5MX-3GP
Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14
1D05V_S0
DY
1D05V_S0
C112
AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33
落
6 OF 10
U35F
C455
SCD1U10V2KX-4GP
VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC VCC_SM/NC
1D05V_S0
SC10U6D3V5MX-3GP
BA36 BB24 BD16 BB21 AW16 AW13 AT13
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
SCD1U10V2KX-4GP
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
SC10U6D3V5MX-3GP
AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29
SC10U6D3V5MX-3GP
D
TP33 TP32
1
U35G
667MTS 2400mA 800MTS 3000mA
B
2
1D05V_S0
7 OF 10 1D8V_S3
3
B
place near Cantiga
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Cantiga (4 of 6)_POWER
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
9
of
52
5
4
1120 modify EC78
1 2
1 2
1
1 2
2
1
1
2
2
1 2
BF21 BH20 BG20 BF20
2
1D8V_SUS_SM_CK_RC
1D8V_TXLVDS_S3
1D8V_S3
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
V48 U48 V47 U47 U46
VCC_DMI VCC_DMI VCC_DMI VCC_DMI
AH48 AF48 AH47 AG47
R104 1 2 0R0603-PAD
1
1
3D3V_HV_S0
106mA
C262 SC1KP50V2KX-1GP
2
VCC_HV VCC_HV VCC_HV
C35 B35 A35
2
K47
B
C254 SC1U10V3KX-3GP
VCCD_LVDS VCCD_LVDS
A8 L1 AB2
1
2
2
C139 1
C244 SC10U6D3V5MX-3GP
2
1 2
1 2
1
C133 1
C198
C460 SC10U6D3V5MX-3GP
DY 1D05V_S0
1
C218
DY
DY
VTTLF1 VTTLF2 VTTLF3
C467 SCD47U6D3V2KX-GP
2
1 2
VTTLF VTTLF VTTLF
456mA
C457
C462 SC10U6D3V5MX-3GP
2
VCCD_PEG_PLL
C222
1
VCCD_HPLL
C466
DY
1
VCCD_QDAC
1782mA
2
SCD1U10V2KX-4GP
4
2
C159 SC10U6D3V5MX-3GP
119mA
VCC_TX_LVDS
1
1R2F-GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Cantiga (5 of 6)_POWER Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009
5
1
VTT AXF SM CK
HDA
VCCD_TVDAC
71.CNTIG.00U
1
R82 1 C166 SCD1U10V2KX-4GP
1D05V_S0
60.3mA 1
2
CRT A PEG
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
1D8V_S3 R81 1 2 0R0603-PAD
124mA
B22 B21 A21
CANTIGA-GM-GP-U-NF
1D8V_S3
2
C
2
M38 L37
C497
DY
2
1
C261 SCD1U10V2KX-4GP
VCC_AXF VCC_AXF VCC_AXF
HV
L28
1D05V_RUN_PEGPLL AA47
2
1 2
M25
2 1 0R0402-PAD
C480 SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
1
C481
A SM
VCC_HDA
AF1
C239
2
R255 10R2F-L-GP
BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81
SCD47U6D3V2KX-GP
2
3
SCD47U6D3V2KX-GP
2nd = 68.00214.051
A32
3D3V_HV_S0 R254
SC22U6D3V5MX-2GP
35mA
2 1 SCD1U10V2KX-4GP 1D5VRUN_QDAC
C201 SCD1U10V2KX-4GP
3D3V_S0 1D05V_HV_S0 1
2
SCD1U10V2KX-4GP
1D5VRUN_QDAC
D
D18
SC22U6D3V5MX-2GP
L4
DY
1
SC4D7U6D3V3KX-GP
C134 SCD1U10V2KX-4GP
1D5V_S0
A
VCCA_TV_DAC VCCA_TV_DAC
1D5V_S0
157.2mA
180ohm 100MHz
B24 A24
落
C138 SCD1U10V2KX-4GP
DY
1D05V_S0
POWER
50mA
C260 SCD1U10V2KX-4GP
1D05V_S0
68.00206.041
VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF VCCA_SM_CK_NCTF
2
1 1
1 C482 SCD01U16V2KX-3GP
C181
2 PBY160808T-181Y-GP
AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23
C135
2
1D05V_S0
D TV/CRT
79mA
50mA
2
2nd = 68.00217.521 220ohm 100MHz
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
1
C214
322mA
TV
2
C468 SCD1U10V2KX-4GP
DY
3D3V_S0_DAC
1
68.00119.111
AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16
C213
1D8V_SUS_SM_CK
1D05V_RUN_PEGPLL
SBK160808T-221Y-N-GP
VCCA_PEG_PLL
C220
C180
2
1
1
1 2 1
M_VCCA_MPLL
2
VCCA_PEG_BG
LVDS
L5
C184
2
1D05V_S0
DY
139.2mA
2
1 2 1 2
2nd = 68.00217.161 120ohm 100MHz
SC10U6D3V5MX-3GP
68.00119.101 DY C463
C178
DY
SCD1U10V2KX-4GP
2
1
VSSA_LVDS
26mA SC2D2U6D3V3MX-1-GP
L13
C469 SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
C464
C160
1
1
1 2
2
C157
SC1U10V3KX-3GP
1D05V_S0
DY
SC1U10V3KX-3GP
1
C161
2
1 2
1D05V_RUN_PEGPLL AA48
M_VCCA_HPLL
68.00119.101
1
VCCA_LVDS
C209
SC1U10V3KX-3GP
C169
2nd = 68.00217.161
B
J48
C256 SCD1U10V2KX-4GP
720mA
2
1
1D05V_S0
DY
24mA
SBK160808T-121Y-N-GP
VCCA_MPLL
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
PEG
1 2
1 2
2
C265 SCD1U10V2KX-4GP
2
1
AE1
AD48
M_VCCA_DPLLB
L12 SBK160808T-121Y-N-GP
M_VCCA_MPLL
13.2mA J47
120ohm 100MHz 1
VCCA_HPLL
1D8V_TXLVDS_S3
SC4D7U6D3V3KX-GP
1D05V_S0
AD1
DY
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
C
VCCA_DPLLB
M_VCCA_HPLL
1D5V_S0
1
C267
VCCA_DPLLA
L48
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
R116 1 2 0R0603-PAD
C258 SCD1U10V2KX-4GP
65mA
2
C263
1
1
1D8V_TXLVDS_S3
M_VCCA_DPLLA
1 2 0R0603-PAD
F47
M_VCCA_DPLLB
VTTLF
2nd = 68.00084.A01
M_VCCA_DPLLA
DMI
65mA
R108
C490 SCD1U10V2KX-4GP
VCCA_DAC_BG VSSA_DAC_BG
PLL
68.00331.011
M_VCCA_DAC_BG A25 B25
VCCA_CRT_DAC VCCA_CRT_DAC
A LVDS
HFB1608VF-102-GP
1D05V_S0
B27 A26
A CK
2
2
5mA
2
C494 SCD1U10V2KX-4GP
1
1 1229 modify U44
3D3V_S0_DAC R249 1
2
SB 1113 modify 2nd of U44
2
1
SC4D7U10V3KX-GP
1
1 2
SC1U16V3ZY-GP
DY
C492
SCD47U6D3V2KX-GP
EC77
RT9198-33GBR-GP
74.09198.Q7F 2nd = 74.09091.J3F
EC78
D
1 1222 modify R252 C485 SC22U16V0KX-1GP
SC4D7U6D3V3KX-GP
4
SC2D2U6D3V3MX-1-GP
5
NC#4
852mA
8 OF 10
U35H
SC4D7U6D3V3KX-GP
VOUT
3D3V_CRTDAC_S0
SC4D7U6D3V3KX-GP
VIN GND EN
1
1D05V_S0
73mA
R252 2 1 0R0402-PAD
SCD01U16V2KX-3GP
1 2 3
2
3D3V_S0_DAC
3D3V_S0_DAC
U44
2
Imax = 300 mA
5V_S0
3
1015 modify component size of R252
2
SB
3
2
Sheet 1
10
of
52
5
4
3
2
10 OF 10
U35J
B
A
VSS
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6
BA16
VSS
AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
VSS VSS VSS VSS
U24 U28 U25 U29
VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF
AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
NCTF_VSS_SCB#BH48 NCTF_VSS_SCB#BH1 NCTF_VSS_SCB#A48 NCTF_VSS_SCB#C1 NCTF_VSS_SCB#A3
BH48 BH1 A48 C1 A3
VSS NCTF
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NC
D
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NCTF TEST PIN: A3,C1,A48,BH1,BH48
AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36
BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17
VSS SCB
9 OF 10
U35I
1
NC#E1 NC#D2 NC#C3 NC#B4 NC#A5 NC#A6 NC#A43 NC#A44 NC#B45 NC#C46 NC#D47 NC#B47 NC#A46 NC#F48 NC#E48 NC#C48 NC#B48
落 D
C
B
1 1 1 1 1
TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
TP71 TP67 TP74 TP65 TP66
E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CANTIGA-GM-GP-U-NF
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
71.CNTIG.00U
Cantiga (6 of 6) Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
11
of
52
5
4
3
C76
1
1
1 1229 modify C76,C77 from 12pF to 15pF
RTC_X1
2
2
落
2 1MR2J-1-GP C396 SC1U16V3ZY-GP
1
1
2
1
C392 SC1U16V3ZY-GP
2
R193
1
62.70001.011
1119 add G84 and C540
RTCX1 RTCX2
RTC_RST# SRTC_RST# INTRUDER#
A25 F20 C22
RTCRST# SRTCRST# INTRUDER#
INTVRMEN LAN100_SLP
B22 A22
INTVRMEN LAN100_SLP
E25
GLAN_CLK
TPAD30 TP50
LAN_RSTYNCC13
G84
near DIMM door 2
1124 delete C540 GLAN_COMP place within 500 mil of ICH9M
RTC_X2
C23 C24
F14 G13 D14
GAP-OPEN
C
1R207
B10
GLAN_DOCK#/GPIO56
B28 B27
GLAN_COMPI GLAN_COMPO
ACZ_BIT_CLK_R ACZ_SYNC_R
AF6 AH4
HDA_BIT_CLK HDA_SYNC
ACZ_RST#_R
AE7
HDA_RST#
2 GLAN_COMP 24D9R2F-L-GP
26 ACZ_SDATAIN0
3D3V_S0 ACZ_SDATAOUT_R TP62 TPAD14-GP
1
1 R228
HDA_DOCK_RST#
DY
HDA_DOCK_EN# 2 8K2R2J-3-GP
33,38 HDD_LED#
B
20 20 20 20
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
ODD
21 21 21 21
SATA_RXN1 SATA_RXP1 SATA_TXN1 SATA_TXP1
C285 C286 C289 C288
1 1 1 1 1 1 1 1
LDRQ0# LDRQ1#/GPIO23
J3 J1
A20GATE A20M#
AF4 AG4 AH3 AE5
HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3
AG5
HDA_SDOUT
AG7 AE8
HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34
AG8
SATALED#
2 2 2 2
SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP
SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C
AJ16 AH16 AF17 AG17
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
2 2 2 2
SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP
SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C
AH13 AJ13 AG14 AF14
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
RTC_AUX_S5
K3
H_DPSLP#
LPC_LFRAME# 33,34 LDRQ0# 3D3V_LDRQ1_S0
N7 AJ27
1 1
TPAD14-GP TPAD14-GP
TP58 TP12
KA20GATE 33 H_A20M# 4
DPRSTP# DPSLP#
AJ25 AE23
H_DPRSTP#
FERR#
AJ26
H_FERR#_R
1 1224 modify RN54
H_DPRSTP# 4,7,41 H_DPSLP# 4
1D05V_S0 RN54
CPUPWRGD
AD22
H_PWRGD 4,39,48
IGNNE#
AF25
H_IGNNE# 4
INIT# INTR RCIN#
AE22 AG25 L3
H_INIT# 4 H_INTR 4 KBRCIN# 33
NMI SMI#
AF23 AF24
H_NMI 4 H_SMI# 4
STPCLK#
AH27
THRMTRIP#
AG26
H_THERMTRIP_R
PECI
AG27
ICH_TP8
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
AH11 AJ11 AG12 AF12
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
AH9 AJ9 AE10 AF10
SATA_CLKN SATA_CLKP
AH18 AJ18
SATARBIAS# SATARBIAS
AJ7 AH7
PM_THRMTRIP-A# H_THERMTRIP_R
4
C
1
1
High=Enable
PM_THRMTRIP-A# 4,7,39
54D9R2F-L1-GP
Layout note: R373 needs to placed within 2" of ICH9, R379 must be placed within 2" of R373 w/o stub
SATARBIAS
2 1 R227 24D9R2F-L-GP
B
1D05V_S0
Place within 500 mils of ICH9 ball
3D3V_S0
DY RN55 SRN10KJ-5-GP
0915 add EC73 for EMI demand H_INIT#_G
SB
integrated VccLan1_05VccCL1_05
LAN100_SLP
2
DY R229
TP25 TPAD14-GP
Low=Disable
1126 delete R230,R233,R235,R236 and RN63
B
R198 0R2J-2-GP
DY
1D05V_S0
CLK_PCIE_SATA# 3 CLK_PCIE_SATA 3
RN63 ACZ_RST#_R ACZ_SDATAOUT_R ACZ_SYNC_R ACZ_BIT_CLK_R
DY Q24 C
E
FWH_INIT# 1
TP70 TPAD14-GP
MMBT3904-3-GP
1
1 2 3 4
EC73 SC10P50V2JN-4GP
EC65 SC10P50V2JN-4GP
DY
DY
SRN47J-4-GP
2
8 7 6 5
1
26 ACZ_RST#_AUDIO 26 ACZ_SDATAOUT_AUDIO 26 ACZ_SYNC_AUDIO 26 ACZ_BITCLK_AUDIO
H_INIT#
2
R197 0R2J-2-GP
R222 200R2F-L-GP 1 DY 2
H_PWRGD
3 4
1117 delete MDC function(R231,R237,R232,R234)
Low=Disable
1
2
SB
High=Enable
2
2
DY
integrated VccSus1_05,VccSus1_5,VccCL1_5
H_FERR#_R
H_STPCLK# 4
ICH9M-GP-NF
INTVRMEN
8 7 6 5 SRN56J-5-GP
R199 330KR2F-L-GP LAN100_SLP
1 2 3 4
H_FERR#
1
1 2 1
INTVRMEN
R223 56R2J-4-GP
DY
71.ICH9M.00U R200 330KR2F-L-GP
33,34
1
LPC_LAD[0..3]
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
2 1
RTC_AUX_S5
HDD
C55 C56 C58 C57
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
GLAN_DOCK#
13 GLAN_DOCK#
FWH4/LFRAME#
LAN_RSTSYNC
D13 D12 E13
1D5V_S0
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
K5 K4 L6 K2
2
SC15P50V2JN-2-GP
1
C281 SCD1U16V2ZY-2GP
LPC_LAD[0..3]
1 OF 6
U16A
2
3 4
2
BAT-CON2-1-GP-U
C77
1
RN51 SRN20KJ-GP-U
2 1
2
DY
D
1D05V_S0
RTC LPC
83.R0304.B81
R121 1 2 1KR2J-1-GP
1
RTC_BAT 1 2 NP1 NP2
C391 SC1U16V3ZY-GP
LAN / GLAN CPU
CH715FPT-GP 2nd = 83.R2004.C81
RTC1
PWR GND NP1 NP2
2
1
3 1
2
RTC_BAT_R
D
R57 10MR2J-L-GP
82.30001.861
RTC_AUX_S5
IHDA
D16
2
1016 modify X2 1
X2 X-32D768KHZ-46GP
SATA
3D3V_AUX_S5
4
3
SC15P50V2JN-2-GP
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
ICH9-M (1 of 4)_SATA/HDA/RTC
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009
5
4
3
2
Sheet
1
12
of
52
A
5
4
3
2
1
3 OF 6
U16C 2 OF 6
3D3V_S0
32,41 VGATE_PWRGD R209 2 1 0R0402-PAD
1
TPAD14-GP R225 10KR2J-3-GP
TP22 TPAD14-GP
1
1 R194
33 33
PIRQA# PIRQB# PIRQC# PIRQD#
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
H4 K6 F2 G2
INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
SB 1120 add the net(SATACLKREQ#)
3 SATACLKREQ# GAP-OPEN 1
INT_PIRQH# PCI_REQ#0 INT_PIRQC# INT_PIRQB#
PCI_REQ#3 INT_PIRQF# INT_PIRQG# PCI_SERR# 3D3V_S0
1 2 3 4 5
3D3V_S0
10 9 8 7 6
TP68
INT_PIRQD# PCI_IRDY# PCI_TRDY# ECSCI#_1
26 ACZ_SPKR 7 MCH_ICH_SYNC# TP51
SRN8K2J-2-GP-U 10 9 8 7 6
TPAD14-GP
INT_SERIRQ PCI_DEVSEL# PCI_STOP# PCI_FRAME#
PERN2 PERP2 PETN2 PETP2
J29 J28 K27 K26
PERN3 PERP3 PETN3 PETP3
B
G29 G28 H27 H26
SPI_CS#1
E29 E28 F27 F26
PERN5 PERP5 PETN5 PETP5
C29 C28 D27 D26
PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP
D23 D24 F23 D25 E23
A
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11
USB_OC#0 USB_OC#1
LA14 SA->SB 0330 ADD GPIO40
R73 2
1
PERN4 PERP4 PETN4 PETP4
N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3
USB_RBIAS_PN AG2 AG1
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
V27 V26 U29 U28
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0
7 7 7 7
DMI1RXN DMI1RXP DMI1TXN DMI1TXP
Y27 Y26 W29 W28
DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1
7 7 7 7
DMI2RXN DMI2RXP DMI2TXN DMI2TXP
AB27 AB26 AA29 AA28
DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2
7 7 7 7
DMI3RXN DMI3RXP DMI3TXN DMI3TXP
AD27 AD26 AC29 AC28
DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
7 7 7 7
DMI_CLKN DMI_CLKP
DMI_ZCOMP DMI_IRCOMP
USBP0N USBP0P USBP1N USBP1P SPI_CLK USBP2N SPI_CS0# USBP2P SPI_CS1#/GPIO58/CLGPIO6 USBP3N USBP3P SPI_MOSI USBP4N SPI_MISO USBP4P USBP5N OC0#/GPIO59 USBP5P OC1#/GPIO40 USBP6N OC2#/GPIO41 USBP6P OC3#/GPIO42 USBP7N OC4#/GPIO43 USBP7P OC5#/GPIO29 USBP8N OC6#/GPIO30 USBP8P OC7#/GPIO31 USBP9N OC8#/GPIO44 USBP9P OC9#/GPIO45 USBP10N OC10#/GPIO46 USBP10P OC11#/GPIO47 USBP11N USBP11P USBRBIAS USBRBIAS#
USB
22D6R2F-L1-GP
T26 T25
CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3
AF29 AF28
DMI_IRCOMP_R
AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
USBPN0 USBPP0 USBPN1 USBPP1 USBPN2 USBPP2 USBPN3 USBPP3 USBPN4 USBPP4
23 23 23 23 23 23 31 31 18 18
USBPN7 22 USBPP7 22 USBPN9 23 USBPP9 23 USBPN11 30 USBPP11 30
8 7 6 5
3D3V_S5
AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8
TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 ENERGY_DETECT/GPIO13 TACH0/GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5
M7 AJ24 B21 AH20 AJ20 AJ21
SPKR MCH_SYNC# TP3 PWM0 PWM1 PWM2
BATLOW#
B13
PM_BATLOW#_R PWRBTN#_ICH
PWRBTN#
R3
LAN_RST#
D20
RSMRST#
D22
1 2 3 4
R5
CLK_PWRGD 3
CLPWROK
R6
PWROK
SMB
SATA GPIO
SLP_M#
B16
CL_CLK0 CL_CLK1
F24 B19
CL_DATA0 CL_DATA1
F22 C19
CL_VREF0 CL_VREF1
C25 A19
CL_RST0# CL_RST1#
F21 D18
GPIO24/MEM_LED GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT GPIO9/WOL_EN
A16 C18 C11 C20
PM_SLP_M#
1
TP4
3D3V_S5
CL_DATA0 7
CL_RST#0
1D5V_S0
10 9 8 7 6
1 2 3 4 5
3D3V_S5 PWROK
TPAD14-GP TP3
GPIO24 1 GPIO10 GPIO14 GPIO9 1
4
C390
R55 3K24R2F-GP
TPAD14-GP TP54
10 9 8 7 6
USB_OC#5 SMB_LINK_ALERT# GPIO10 SMB_ALERT#
10 9 8 7 6
USB_OC#4 DBRESET# USB_OC#3 USB_OC#6
DY
C
R205 453R2F-1-GP
R56 453R2F-1-GP
DY
RP6
3D3V_S5
USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 3D3V_S5
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
3D3V_S5 SB_GPIO13 GPIO14 B
GLAN_DOCK# 12
SRN10KJ-L3-GP
GPIO57
SRN10KJ-L3-GP R224 24D9R2F-L-GP
Device LA14 0318 ADD USBPN1,USBPP1,USBPN2,USBPP2
0
USB1
1
USB3
2
USB3
3
MINIC1
BOOT BIOS Strap
4
WEBCAM
PCI_GNT#0
5
NC
6
NC
7
Bluetooth
8
NC
9
R195 1 2 0R2J-2-GP
DY
USB Pair
D15
0 1 1
PCI_GNT#3
NC
11
CardReader
1 0 1
BOOT BIOS Location
SPI PCI LPC(Default)
BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81
A
low = A16 swap override enable high = default
PCI_GNT#0 SPI_CS#1 PCI_GNT#3 GNT0 and SPI_CS#1 have a weak internal pull up
R196 100KR2J-1-GP
2
SPI_CS#1
A16 swap override strap
USB2(High speed)
10
RSMRST#_SB
1 3
33 RSMRST#_KBC
1 R210 1 R212 1 R208
1KR2J-1-GP 2
DY
1KR2J-1-GP 2
DY
1KR2J-1-GP 2
DY
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH9-M (2 of 4)_PCIE/USB/DMI Size
Document Number
Rev
SB
LA14
1017 modify USB signal connection
71.ICH9M.00U
3D3V_S5
7
SRN10KJ-L3-GP USB_OC#2 USB_OC#7 PM_RI# PCIE_WAKE#
RP7 1 2 3 4 5
R204 3K24R2F-GP
CL_VREF0_ICH CL_VREF1_ICH
3D3V_S5
RP2
SATA0GP SATA1GP GPIO36 GPIO37
TPAD14-GP
C75
1 2 3 4 5
3D3V_S0
7,39
CL_CLK0 7
DY
USB_OC#1 PM_BATLOW#_R ECSWI# USB_OC#0
PM_DPRSLPVR 7,41
BAS16-6-GP 3 PM_PWRBTN# 33 83.00016.K11 2 Change D17 from 83.00016.B11 to 83.00016.K11
RSMRST#_SB
CK_PWRGD
RP1
SMLINK0 SMLINK1 RSMRST#_SB
7,39
R216 1 DY 2 100KR2J-1-GP D17 1
71.ICH9M.00U
SRN10KJ-6-GP
ICH9M-GP-NF
5
SST
RN5
1
TXN2 TXP2
L29 L28 M27 M26
MINICARD1
23 23
A20
PWROK PM_DPRSLPVR
2
1 1
PERN1 PERP1 PETN1 PETP1
PCI-Express
C418 SCD1U10V2KX-5GP 2 C416 SCD1U10V2KX-5GP 2
N29 N28 P27 P26
Direct Media Interface
PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2
1 1
TXN1 TXP1
SPI
31 31 31 31
VRMPWRGD
No Reboot Strap SPKR LOW = Defaule High=No Reboot
4 OF 6
U16D
C425 SCD1U10V2KX-5GP 2 C430 SCD1U10V2KX-5GP 2
D21
G20 M2
ICH9M-GP-NF
SRN8K2J-2-GP-U
PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1
1ICH_TP3
GPIO49 should be pulled down to GND only when using Teenah. When using Cantiga, this ball should be left as No Connect.
3D3V_S0
LAN 24 24 24 24
SDATAOUT1 1GPIO49 GPIO57
TPAD14-GP
WAKE# SERIRQ THRM#
PWROK DPRSLPVR/GPIO16
SCD1U10V2KX-4GP
3D3V_S0
1 2 3 4 5
RP4
3D3V_S0
SRN8K2J-2-GP-U RP3 PCI_REQ#2 PCI_REQ#1 SDATAOUT1 PM_CLKRUN#
TP19 TP63 TP69
CLKRUN#
D
TP53 TPAD14-GP
1
10 9 8 7 6
1GPIO12 SB_GPIO13 PSW_CLR# 1GPIO18 1GPIO20 1GPIO22
S4_STATE#1
SCD1U10V2KX-4GP
3D3V_S0
1 2 3 4 5
SB_GPIO1
1
TP52
TPAD14-GP TPAD14-GP TPAD14-GP
ICH_TP7
G61
71.ICH9M.00U RP5 PCI_PERR# INT_PIRQE# PCI_LOCK# INT_PIRQA#
TP64
TPAD14-GP
Interrupt I/F
2
DY 0R2J-2-GP
EC_TMR ECSCI#_1 ECSWI#
33
2
ICH_PME#
PLT_RST1# 7,24,30,31,33,34 PCLK_ICH 3
C10
TP57 TPAD14-GP
1
C405 SC100P50V2JN-3GP
S4_STATE#/GPIO26
PM_SLP_S3# 33,39,43,44 PM_SLP_S4# 33,43,44
1
2
DY
STP_PCI# STP_CPU#
E20 M5 AJ23
24 PCIE_WAKE# 33 INT_SERIRQ 32 THRM#
1222 modify R209
SMBALERT#/GPIO11
A14 E19 L4
33 PM_CLKRUN#
1
SLPS5#
1
1
PCI_DEVSEL# PCI_PERR# PCI_LOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME#
PM_STPPCI# PM_STPCPU#
C16 E16 G17
2
3 3
TP55 TPAD14-GP
SLP_S3# SLP_S4# SLP_S5#
PMSYNC#/GPIO0
A17
1
C14 PLT_RST#_R D4 R2
PCI_IRDY# PCI_PAR
PM_SUS_CLK 32
2
PLTRST# PCICLK PME#
SMB_ALERT#
SUSCLK
2
D3 E3 R1 C6 E4 C2 J4 A4 F5 D7
M6
PM_SYNC#
CLK_ICH14 3 CLK48_ICH 3
1
IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME#
7
SUS_STAT#/LPCPD# SYS_RESET#
落
H1 AF3 P1
CLK14 CLK48
2
D8 B4 D6 A5
RI#
SATA0GP SATA1GP GPIO36 GPIO37
1
C/BE0# C/BE1# C/BE2# C/BE3#
TP59
R4 G19
AH23 AF19 AE21 AD20
2
TPAD14-GP
F19
1PM_SUS_STAT# DBRESET#
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
1
PM_RI# PCI_REQ#3 PCI_GNT#3
SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1
Clocks
PCI_REQ#2
ICH9M-GP-NF C
G16 A13 SMB_LINK_ALERT# E17 SMLINK0 C17 SMLINK1 B18
SMB_CLK SMB_DATA
SYS GPIO Power MGT
15 15
PCI_REQ#0 PCI_GNT#0 PCI_REQ#1
2
J5 E1 J6 C4
F1 G4 B6 A7 F13 F12 E6 F6
MISC GPIO Controller Link
INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD#
REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
PCI
2
D
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
2
D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3
1
U16B
Date: Thursday, May 07, 2009 3
2
Sheet 1
13
of
52
4
2 1
1
2
DY 2
C397 SC4D7U6D3V3KX-GP
3D3V_S0 C408 SCD1U10V2KX-4GP
1mA
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
A10 A11
VCCLAN1_05 VCCLAN1_05
A12 B12
VCCLAN3_3 VCCLAN3_3
A27
VCCGLANPLL
D28 D29 E26 E27
VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5 VCCGLAN1_5
A26
VCCGLAN3_3
2
1 2
1
1
1 1
1D5V_S0
2 IND-1D2UH-10-GP
68.1R220.10D
DY
C435 SC4D7U6D3V3MX-2GP
2
1 2
1
1D05V_S0
2mA
1D05V_S0
1
1
1
2
2
2
2
2
1
1 2
1 2
2
1
1
C417
DY
C419 SC4D7U6D3V3KX-GP
C
C412
11mA
1
DY
3D3V_S0
C475 SCD1U10V2KX-4GP
2
1
1
C400
11mA
1
2
2
2
2
1
2
C471 SCD1U10V2KX-4GP
C436
2
1 C465 SCD1U10V2KX-4GP
2
1
1 2
1 2
D
3D3V_S0
C403
VCCSUS1_5
AD8
VCCSUS1_5
F18
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
A18 D16 D17 E22
VCCSUS3_3
AF1
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
VCCCL1_05
G22 VccSus1_05[3]
VCCCL1_5
G23 VccSus1_5[3] 1
VCCCL3_3 VCCCL3_3
A24 B24
2
2
1
3D3V_S5
C470 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP C410 SCD1U10V2KX-4GP
1D5V_S5 3D3V_S5
C432
1 2
C401 SCD1U10V2KX-4GP
VCCSUS3_3=212mA
TP56 TPAD14-GP
B
3D3V_S5
1
1
C399
C437 SCD1U10V2KX-4GP
2
C445
2
C394
DY
1
1
2
1
1D5V_S5
DY
1
VCCUSBPLL
落
C404
DY 3D3V_S0
C411 SCD1U10V2KX-4GP
2
AJ5 AA7 AB6 AB7 AC6 AC7
2
VCCSUS1_05 VCCSUS1_05
AC8 VccSus1_05 F17
2
CORE
2 AJ4 AJ3
2
VCC1_5_A VCC1_5_A VCC1_5_A
VCCPSUS
VCC1_5_A VCC1_5_A
AC12 AC13 AC14
VCCPUSB
2 1 2 1
1
1 2
2
1 2
1 2
2
2
1 2 1 2
DY
80mA
VCC1_5_A
G10 G9
1
VCCHDA VCCSUSHDA
DY
C402
SCD1U10V2KX-4GP
1D5V_S0
C421 SC10U6D3V5MX-3GP
VCC1_5_A VCC1_5_A
AC21
23mA
C442
19mA in S0;73mA in S3/S4/S5
A
GLAN POWER
1 C385 SCD1U10V2KX-4GP 2
AC18 AC19
C406
SCD1U10V2KX-4GP
23mA
VCC1_5_A
L11
C407
DY
C448 SC4D7U6D3V3KX-GP
DY
3D3V_S0
SCD1U10V2KX-4GP
VccLan1D05 SCD1U10V2KX-4GP
AC9
C395
48mA
1 R221 2 0R0603-PAD
VCC3_3=308mA 3D3V_S0
SCD1U10V2KX-4GP
C73
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
USB CORE
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
DY
C451 SCD1U10V2KX-4GP
AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10
ATX
C473
19mA in S0;78mA in S3/S4/S5 DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
3D3V_S0
A
C472
DY
USBPLL=11mA
C454 SCD1U10V2KX-4GP
C409
SC1U16V3ZY-GP
SC1U16V3ZY-GP
SC4D7U6D3V3KX-GP
1D5V_S0
C413
VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A
DY
2
B9 F9 G3 G6 J2 J7 K7
1
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
VCCP_CORE
VCCSATAPLL
AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15
1
1
1 C440 2
C452
C458
1
AJ19
AD19 AF20 AG24 AC20
2
1.34A
ARX
C117 SCD1U16V2ZY-2GP
B
C74 SCD1U10V2KX-4GP
2
2
1
A K
1D5V_S0
2
1
V5REF_S5
D7 R72 100R2J-2-GP RB751V-40-2-GP 83.R2004.B8F 2nd = 83.R0304.A8F 3rd = 83.R3004.A8F
AC10
VCC3_3 VCC3_3 VCC3_3 VCC3_3
C474 SCD1U10V2KX-4GP
C447
SCD1U10V2KX-4GP
2mA
VCC3_3
C444
SCD1U10V2KX-4GP
5V_S5
AJ6
C423
C431 SCD01U16V2KX-3GP
SCD1U10V2KX-4GP
3D3V_S5
VCC3_3
C441
1
SCD1U10V2KX-4GP
Layout Note: Place near ICH9
PCI
1
1
2
C72 SCD1U16V2ZY-2GP
AG29
C422
1D5V_DMIPLL_ICH_S0
1
1 2 1 2
1 2
1
1
1 2
2
2
1
1 2 1
A K
C477
2
1
C476 SC10U6D3V5MX-3GP
VCC3_3
DY
SCD1U10V2KX-4GP
68.1R220.10D
AB23 AC23
C439
SCD1U10V2KX-4GP
D6 R54 100R2J-2-GP RB751V-40-2-GP 83.R2004.B8F 2nd = 83.R0304.A8F 3rd = 83.R3004.A8F
DY
W23 1D05V_DMI_ICH_S0 Y23
V_CPU_IO V_CPU_IO
1D05V_S0
SCD1U10V2KX-4GP
2 IND-1D2UH-10-GP
VCCDMI VCCDMI
C434
SC10U6D3V5MX-3GP
1D5V_APLL_S0
L14
R29
VCCA3GP
V5REF_S0 C
1
SC1U16V3ZY-GP
2mA
1D5V_S0
VCCDMIPLL
1.63A Layout Note:Place near ICH9M
SCD1U10V2KX-4GP
47mA
VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1015 modify component size of C390,C419
5V_S0
V5REF_SUS
AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05
SCD1U10V2KX-4GP
C461
*Within a given well, 5VREF needs to be up before the corresponding 3.3V rail
3D3V_S0
V5REF
SCD1U10V2KX-4GP
C453
AE1
VCCRTC
SCD1U10V2KX-4GP
C443
DY
1
SCD1U10V2KX-4GP
C415
DY
A6
SCD1U10V2KX-4GP
C459
DY
V5REF_S5
A23
SCD1U10V2KX-4GP
C414
V5REF_S0
2
6 OF 6
SCD1U10V2KX-4GP
646mA
D
C388 SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
6uA in G3
2
C389
3
U16F
RTC_AUX_S5
2
5
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH9M-GP-NF Size
71.ICH9M.00U
ICH9-M (3 of 4)_POWER
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
14
of
52
A
B
2
1
E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
NCTF_VSS#A1 NCTF_VSS#A2 NCTF_VSS#B1 NCTF_VSS#A29 NCTF_VSS#A28 NCTF_VSS#B29 NCTF_VSS#AJ1 NCTF_VSS#AJ2 NCTF_VSS#AH1 NCTF_VSS#AJ28 NCTF_VSS#AJ29 NCTF_VSS#AH29
A1 A2 B1 A29 A28 B29 AJ1 AJ2 AH1 AJ28 AJ29 AH29
落 4
3
3D3V_S5
3D3V_S0
8 7 6 5
3
D
RN50 SRN2K2J-2-GP
1 2 3 4
4
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NCTF TEST PIN: A1,A2,B1,A28,A29,B29 AH1,AJ1,AJ2,AH29,AJ28,AJ29
AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29
C
5 OF 6
U16E
5V_S0
Q7
13
13
SMB_CLK
3
4
2
5
1
6
SMBC_ICH 3,16,17 2
84.27002.E3F 2N7002DW-2-GP-U
SMB_DATA
SMBD_ICH 3,16,17
SMBUS LA14 SA->SB 0403 Change Q7 from 84.27002.D3F to 84.27002.E3F
1 1 1 1 1 1 1 1 1 1 1 1
TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
TP1 TP2 TP10 TP8 TP7 TP9 TP30 TP31 TP28 TP29 TP27 TP26
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ICH9-M (4 of 4) Size
ICH9M-GP-NF
71.ICH9M.00U
Document Number
A
Rev
SB
LA14 Date: Thursday, May 07, 2009 B
C
D
Sheet E
15
of
52
A
B
C
D
E
落 DM1
Decoupling Capacitor Put decap near power(0.9V) and pull-up resistor
DDR_VREF_S3 2
1
1
2
2
C217 SCD1U16V2ZY-2GP
2
C223
DY
SCD1U16V2ZY-2GP
2
C171 SCD1U16V2ZY-2GP
2
1
1
1
1
C206 SCD1U16V2ZY-2GP
2
C243
DY
SCD1U16V2ZY-2GP
2
C191 SCD1U16V2ZY-2GP
2
C237 SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
2
C154
SCD1U16V2ZY-2GP
DY
1
1
C190
SCD1U16V2ZY-2GP
2
C234
SCD1U16V2ZY-2GP
2
C219
1
1
1
8 M_B_DQS#[7..0]
8 M_B_DQS[7..0]
DDR_VREF_S3_1
1 2
2
DY
M_ODT2 M_ODT3
VREF VSS
202
GND
GND
201
MH1
MH1
MH2
MH2
C290 SCD1U16V2ZY-2GP
C292 SC4D7U6D3V3KX-GP
1
7 7
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
Place these Caps near DM1
1D8V_S3
C200
C174
DY
C488
DY
C195
DY
C502
C499
C503
DY
1
SRN56J-5-GP
1D8V_S3
C496
2
M_B_BS#0 M_B_CAS# M_CS3# M_ODT3
1
1 2 3 4
3
2
RN13
81 82 87 88 95 96 103 104 111 112 117 118
DY
2
1
OTD0 OTD1
1 2
SRN56J-5-GP
8 7 6 5
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
C428 SCD1U16V2ZY-2GP
C493
2
114 119
M_B_A14 M_B_A11 M_B_A7
1
1
1 2 3 4
2 R220 10KR2J-3-GP
2
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
RN27
DDRB_SA0
1
13 31 51 70 131 148 169 188
SRN56J-5-GP
8 7 6 5
3
198 200 50 69 83 120 163
3D3V_S0
2
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
M_B_RAS# M_CS2# M_ODT2 M_B_A13
SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST
SMBD_ICH 3,15,17 SMBC_ICH 3,15,17
1
1 2 3 4
199
2
8 7 6 5
195 197
1
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
RN10
SDA SCL VDDSPD
M_CLK_DDR3 7 M_CLK_DDR#3 7 M_B_DM[7..0] 8
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
SC2D2U6D3V3MX-1-GP
11 29 49 68 129 146 167 186
SRN56J-5-GP
10 26 52 67 130 147 170 185
SCD1U16V2ZY-2GP
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SRN56J-5-GP RN18 1 M_B_A1 2 M_B_A3 3 M_B_A10 4 M_B_WE#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
2
8 7 6 5
M_CLK_DDR2 7 M_CLK_DDR#2 7
164 166
SC2D2U6D3V3MX-1-GP
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
8 M_B_DQ[63..0]
30 32
CK1 CK1#
SCD1U16V2ZY-2GP
BA0 BA1
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
CK0 CK0#
4
SC2D2U6D3V3MX-1-GP
107 106
M_CKE2 7 M_CKE3 7
1
SRN56J-5-GP RN26 8 1 M_B_A6 7 2 M_B_A9 6 3 M_B_A8 5 4 M_B_A5
1
79 80
SCD1U16V2ZY-2GP
M_B_BS#0 M_B_BS#1
TPAD14-GP TP37
M_CS2# 7 M_CS3# 7
CKE0 CKE1
2
M_CKE3 M_CKE2 M_B_A12 M_B_BS#2
110 115
1
SRN56J-5-GP RN31 8 1 7 2 6 3 5 4
M_B_BS#1 M_B_A0 M_B_A2 M_B_A4
M_B_RAS# 8 M_B_WE# 8 M_B_CAS# 8
CS0# CS1#
2
1 2 3 4
108 109 113
SC2D2U6D3V3MX-1-GP
8 8
Put decap near power(0.9V) and pull-up resistor RN19
8 7 6 5
RAS# WE# CAS#
SCD1U16V2ZY-2GP
M_B_BS#2
DDR_VREF_S3
4
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
SC2D2U6D3V3MX-1-GP
8
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
2
M_B_A[14..0]
REVERSE TYPE
8
PARALLEL TERMINATION
DDR2-200P-23-GP-U1
High 9.2mm 62.10017.A71 2nd = 62.10017.B51 3rd = 62.10017.K51
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR2 Socket 0 (DM1) Size
Document Number
Date:
Thursday, May 07, 2009
Rev
SB
LA14 A
B
C
D
Sheet E
16
of
52
A
B
C
D
E
落 DM2
M_A_A[14..0]
RN12
8 7 6 5
1 2 3 4
M_A_A13 M_CS0# M_ODT0 M_A_RAS#
SRN56J-5-GP RN24
8 7 6 5
1 2 3 4
M_A_A5 M_A_A8 M_A_A9 M_A_A3
TPAD14-GP TP38
SRN56J-5-GP RN11
8 7 6 5
1 2 3 4
M_A_WE# M_A_CAS# M_CS1# M_ODT1
8
M_A_BS#2
8 8
M_A_BS#0 M_A_BS#1
1
8 M_A_DQ[63..0]
RN30
1 2 3 4
M_CKE0 M_A_BS#2 M_A_A12
SRN56J-5-GP RN25
8 7 6 5
1 2 3 4
M_A_A7 M_A_A11 M_A_A14 M_CKE1
3
SRN56J-5-GP RN17
8 7 6 5
1 2 3 4
M_A_A2 M_A_A0 M_A_A6 M_A_A4
SRN56J-5-GP RN16
8 7 6 5
1 2 3 4
M_A_A1 M_A_BS#1 M_A_A10 M_A_BS#0
SRN56J-5-GP
Decoupling Capacitor
1
C249
2
C215
2
DY
2
2
1
1
1
1
C189
SCD1U16V2ZY-2GP
2
C170
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
2
C187
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
DY
SCD1U16V2ZY-2GP
2
C236
SCD1U16V2ZY-2GP
DY
1
C233
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
1
C232
2
C216
SCD1U16V2ZY-2GP
2
1
1
C167
SCD1U16V2ZY-2GP
2
C188
2
Put decap near power(0.9V) and pull-up resistor 1
1
DDR_VREF_S3
8 M_A_DQS#[7..0]
8 M_A_DQS[7..0]
Place these Caps near DM2
1 2
2
BA0 BA1
5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
11 29 49 68 129 146 167 186
/DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
13 31 51 70 131 148 169 188
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
114 119
ODT0 ODT1
1 2
M_ODT0 M_ODT1
1
1
1 2 1 2
2 1 2
2 1
107 106
C291
202
/RAS /WE /CAS
108 109 113
M_A_RAS# 8 M_A_WE# 8 M_A_CAS# 8
/CS0 /CS1
110 115
M_CS0# 7 M_CS1# 7
CKE0 CKE1
79 80
M_CKE0 7 M_CKE1 7
CK0 /CK0
30 32
M_CLK_DDR0 7 M_CLK_DDR#0 7
CK1 /CK1
164 166
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
10 26 52 67 130 147 170 185
SDA SCL
195 197
VDDSPD
199
SA0 SA1
198 200
NC#50 NC#69 NC#83 NC#120 NC#163/TEST
50 69 83 120 163
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
81 82 87 88 95 96 103 104 111 112 117 118
VREF VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
GND
GND
201
4
M_CLK_DDR1 7 M_CLK_DDR#1 7 M_A_DM[7..0] 8
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
SMBD_ICH 3,15,16 3D3V_S0 SMBC_ICH 3,15,16
C433 SCD1U16V2ZY-2GP
DY
3
1D8V_S3
2
SKT-SODIMM20022U2GP
62.10017.691 2nd = 62.10017.891 3rd = 62.10017.K41
High 5.2mm
SCD1U16V2ZY-2GP
2
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
SCD1U16V2ZY-2GP
1
DY
C293 SC4D7U6D3V3KX-GP
C238
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
7 7
C168 SC2D2U6D3V3MX-1-GP
C491
DY
DY
SC2D2U6D3V3MX-1-GP
C212
SCD1U16V2ZY-2GP
1
C498
SC2D2U6D3V3MX-1-GP
C495
DY
C486
SC2D2U6D3V3MX-1-GP
2
C500
SC2D2U6D3V3MX-1-GP
DY
1
1
1
DDR_VREF_S3_1 C241
2
1D8V_S3
102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
SRN56J-5-GP
8 7 6 5
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
1
8
Put decap near power(0.9V) and pull-up resistor
2
DDR_VREF_S3
REVERSE TYPE
PARALLEL TERMINATION 4
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DDR2 Socket 1 (DM2) Size
Document Number
Date:
Thursday, May 07, 2009
Rev
LA14 A
B
C
D
SB Sheet
E
17
of
52
1015 modify F1
CCD Pin
1015 modify LCD1 pin define
Pin
1016 modify LCD1 pin define
1
CCD_PWR
1017 modify USB signal connection
2
USB-
SB
1121 add EC87 for EMI demand
3
USB+
SB
1128 modify LCD1
4
GND
5
GND
1
CLK_DDC_EDID DAT_DDC_EDID
R124 2
7 7
BLON_OUT 1 33R2J-2-GP BRIGHTNESS_CN DCBATOUT
13 13
USBPP4_R
DY
1 2
3D3V_S0
EC1
FUSE-1D1A6V-4GP-U
2
C1
SCD1U16V2ZY-2GP
BLON_OUT_1
2
CLK_DDC_EDID DAT_DDC_EDID
1
1 3D3V_S0 C2
DY
69.50007.691 2ND = 69.50007.771
EC2
DY
F2
EC87
20.F1296.040
1
POLYSW-1D1A24V-GP
69.50007.A31EC3 2nd = 69.50007.A41 SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
ACES-CONN40C-4-GP
2
1
PWR_INVERTER
2
7 GMCH_TXAOUT0+ 7 GMCH_TXAOUT0-
USBPN4 USBPP4 F1
1
7 GMCH_TXAOUT1+ 7 GMCH_TXAOUT1-
2 0R0402-PAD 2 0R0402-PAD
CCD_PWR
2
7 GMCH_TXAOUT2+ 7 GMCH_TXAOUT2-
USBPN4_R R2 1 R1 1
1
GMCH_TXACLK+ GMCH_TXACLK-
USBPN4_R USBPP4_R
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SCD1U50V3ZY-GP
39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 42
SC4D7U10V5ZY-3GP 2 1
41 40
落 1
LCD1
2
2
C305
SCD1U25V3ZY-1GP
1
1 2
SCD1U25V3ZY-1GP
2
DY
Symbol
SCD1U50V3ZY-GP
C3 SC10U25V5KX-GP
SB 1201 modify C3
R126
2
1 0R2J-2-GP R125
BRIGHTNESS_CN
2
L_BKLTCTL 7
DY 1 0R2J-2-GP
BRIGHTNESS 33
BLON_OUT
2
1
C308 SC100P50V2JN-3GP
SC100P50V2JN-3GP
DY
2
1
BLON_OUT 33 C309
DY
SB
1106 modify R125,R126
SB
1125 modify R125,R126
3D3V_S0
2 1
1014 swap the part RN34
3 4
SRN2K2J-1-GP
CLK_DDC_EDID DAT_DDC_EDID
Layout 40 mil LCDVDD
3D3V_S0 U30
1015 modify component size of C303,C307 VIN#5
5
VIN#4
4
C303
1 C307
1
SB
EN GND VOUT
1229 modify U30
RT9724GB-GP SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
DY
74.09724.09F 2nd = 74.05285.07F
Wistron Corporation
2
C306 SCD1U16V2ZY-2GP
DY
1 2 3 1
1
GMCH_LCDVDD_ON
2
7 GMCH_LCDVDD_ON
2
7 7
C304
SC10U10V5ZY-1GP
C302
1
LCDVDD
2
LCD/CCD CONN
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
LCD CONN Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009
Sheet
18
of
52
A
B
Layout Note: Place these resistors close to the CRT-out connector
D
Ferrite bead impedance: 10 ohm@100MHz GMCH_RED
E
Hsync & Vsync level shift
L3 1 2 PBY160808T-170Y-N-GP
CRT_R
L2 1 2 PBY160808T-170Y-N-GP
CRT_G
落
1016 modify U8
5V_S0
U8B TSAHCT125PW-GP
7
1
1 2
C27 SC18P50V2JN-1-GP
1 0105 modify L1,L2 and L3
C21
73.74125.L13 2nd = 73.74125.L12 CRT_VSYNC1
6
DY
SC18P50V2JN-1-GP
1016 modify L1,L2 and L3
DY
CRT_HSYNC1
3 U8A TSAHCT125PW-GP
7
4
14 5
7 GMCH_VSYNC
2
1 2
1 2
2
1 2
1 2
2
2
7 GMCH_HSYNC
C38 SC6D8P50V2DN-GP
1 2 3 4
C42 SC6D8P50V2DN-GP
DY
CRT_B C46 SC6D8P50V2DN-GP
DY
EC18 SC3P50V2CN-1-GP
8 7 6 5
EC19 SC3P50V2CN-1-GP
DY
SC3P50V2CN-1-GP
RN39 SRN150F-1-GP
EC20
1
L1 1 2 PBY160808T-170Y-N-GP
GMCH_BLUE
1
7
C44 SCD1U16V2ZY-2GP 4
14
7 GMCH_GREEN
1
4
2
1
7
C
73.74125.L13 2nd = 73.74125.L12
Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
3
DDC_CLK & DATA level shift
CRT I/F & CONNECTOR 5V_CRT_S0
CRT_G CRT_B
CRT_IN#_R C39
7 2 8 3 9 4 10 5
DAT_DDC1_5
13
CRT_HSYNC1
14
CRT_VSYNC1
15
CLK_DDC1_5
16
SCD01U16V2KX-3GP
VIDEO-15-75-GP-U
5V_CRT_S0
F3
1
5V_CRT_DDC
2
FUSE-1D1A6V-4GP-U
RN38 SRN2K2J-1-GP
1016 modify D4 RN37 SRN10KJ-6-GP
69.50007.691 2nd = 69.50007.771 Q5
4
3
5
2
6
1
CRT_IN#_R CLK_DDC1_5
1014 swap these nets
20.20715.015 CRT_VSYNC1 CRT_HSYNC1 CLK_DDC1_5 DAT_DDC1_5
2
CH551H-30PT-GP D4
2
11 12
3D3V_S0
6 1 7 2 8 3 9 4 10 5
3D3V_S0
83.R5003.C8F
2nd = 83.R5003.H8H 3rd = 83.5R003.08F
1 2 3 4
CRT_R
1127 modify CRT1
3 4
SB
17 6 1
2 1
2
1
5V_S0
CRT1
8 7 6 5
3
1014 swap these nets
2nd = 20.20728.015 7 GMCH_DDCCLK
3rd = 20.20799.015
2N7002DW-2-GP-U 84.27002.E3F
7 GMCH_DDCDATA
DAT_DDC1_5
1 2
C26 SC100P50V2JN-3GP
D3
DY
CRT_IN#_R
CRT_IN#_R
1
36
C40
3
1
LA14 SA->SB 0403 Change Q5 from 84.27002.D3F to 84.27002.E3F
2
Wistron Corporation
DY
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
BAV99PT-GP-U 1 Title
2
1
C20 SC100P50V2JN-3GP
DY
2
1
C23 SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
2
C30
1
5V_S0
2
1
SC100P50V2JN-3GP Size
CRT Connector
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 A
B
C
D
Sheet E
19
of
52
5
4
3
2
1
落 D
D
SATA Connector 0912 add these parts for EMI demand 1001 delete these parts for EMI demand 1021 modify SATA1 SATA1
23 NP1 1 C
C
1021 modify TC5 1 1222 modify TC5 5V_S0
1016 modify D5 K
1
1
1 1224 modify D5 D5 SR24-GP
A
C50
2
TC5
SCD1U16V2ZY-2GP
SKT-SATA22P-47-GP-U B
SATA_RXN0 12 SATA_RXP0 12
SC10U10V5ZY-1GP
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NP2 24
SATA_TXP0 12 SATA_TXN0 12
2
2 3 4 5 6 7
DY
83.2R004.J8M 2nd = 83.2R004.H8M B
62.10065.741 2nd = 62.10065.781
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Document Number
HDD
Rev
LA14 Date: Thursday, May 07, 2009 5
4
3
2
SB Sheet 1
20
of
52
5
4
3
2
1
落
SATA ODD Connector D
D
0912 add these parts for EMI demand 1001 delete these parts for EMI demand
5V_S0
1 1230 modify ODD1 1
1
1 1231 modify ODD1
P2 P3
+5V +5V
SATA_TXP1 SATA_TXN1 SATA_RXP1 SATA_RXN1
S2 S3 S6 S5
A+ AB+ B-
2
2
12 12 12 12
C
1 0113 modify ODD1
TC7 SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
C273
ODD1
NP1 NP2
NP1 NP2
DP MD
P1 P4
GND GND GND GND GND GND GND
S1 S4 S7 P5 P6 8 9
ODD_DP ODD_MD
1 1
TP40 TPAD14-GP TP39 TPAD14-GP
C
SKT-SATA7P+6P-73-GP
62.10065.881
B
B
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ODD Size
Document Number
Rev
LA14 Date: Thursday, May 07, 2009 5
4
3
2
SB Sheet 1
21
of
52
A
5
4
3
2
1
落
BLUETOOTH MODULE 1.5A / High Active Voltage 2V D
D
3D3V_BT_S0
DY
U48 VOUT GND FLG#
3D3V_S0 VIN
5
EN
4
BLUETOOTH_EN 33
DY
RT9715CGBG-GP
74.09715.A7F 2nd = 74.05240.A7F
SB 1113 modify U48
DY BLUE1 R123 0R0402-PAD 2 1 2 1
6
1
3D3V_BT_S0
EC92
20.F0984.004 2nd = 20.D0197.104
DY
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
5 ETY-CON4-21-GP-U
EC93
C
USBPN7 USBPP7
13 13
R122 0R0402-PAD
1
USB_7USB_7+
2
4 3 2
1
C
EC21 put near BLUE1 / all USB put one choke near connector by EMI request
C530 SC4D7U10V5ZY-3GP 2
1
2
EC85 SCD1U16V2ZY-2GP
1 2 3
2
DY
1
3D3V_BT_S0
DY 48 48 48
USB_7USB_7+ 3D3V_BT_S0
USB_7USB_7+ 3D3V_BT_S0
1017 modify USB signal connection SB
1125 add EC92 and EC93
0930 modify BLUE1 1017 modify BLUE1
B
B
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Bluetooth
Document Number
Rev
LA14 Date: Thursday, May 07, 2009 5
4
3
2
SB Sheet 1
22
of
52
A
5
4
3
2
1
落
1017 modify USB signal connection 1021 modify and swap these parts(USB1 and USB2) D
D
5V_USB1_S0
2 3 4 7 5
C245 SC4D7U10V3KX-GP
33 USB_PWR_EN#
GND VIN VIN EN#
8 7 6 5
VOUT VOUT VOUT FLG#
USB_OC#1 13
1
USB_9USB_9+
R219 12R2F-1-GP
1
USBPN9 USBPP9
5V_USB2_S0
U49
1 2 3 4
RT9715DGF-GP
2
13 13
5V_S5
USB2
6 8 1
R218 12R2F-1-GP 2 1 2 1
74.09715.079
SKT-USB-177-GP
EC44 SCD1U16V2ZY-2GP
DY 2
USB2
2nd = 74.00547.A79
Modify 04/27 Change R218,R219,R244,R245 from 0ohm to 12ohm
22.10218.U11 2nd = 22.10321.151
5V_USB2_S0
100 mil
13 13
USBPN0 USBPP0
USB_0USB_0+
2
2
80.15715.12L 2nd = 77.C1571.09L
2 3 4 7 5
R245 12R2F-1-GP
2
1
EC71
DY
EC96
1
TC23 ST150U6D3VBM-2-GP
SKT-USB-177-GP
SC1000P50V3JN-GP-U
R244 12R2F-1-GP 2 1 2 1
C
DY
USB1
6 8 1
SCD1U16V2ZY-2GP
USB1
1
5V_USB1_S0
DY
LA14 SA->SB 0330 Modify 5V_USB2_S0,ADD U49 C245,TC23
C
22.10218.U11 2nd = 22.10321.151
5V_USB2_S0
USB3 USB3
9
USBPN2 USBPP2
B
C142 SC4D7U10V3KX-GP
5V_USB1_S0
U12
1 2 3 4
33 USB_PWR_EN#
GND VIN VIN EN#
VOUT VOUT VOUT FLG#
8 7 6 5
USB_OC#0 13
1
13 13
2 3 4 5 6 7 8
RT9715DGF-GP
SCD1U16V2ZY-2GP
DY
10
74.09715.079
ACES-CON8-15-GP 20.K0315.008
B
EC32
2
USBPN1 USBPP1
2
13 13
1
5V_S5
1
2nd = 74.00547.A79
LA14 SA->SB 0330 ADD USB3 1021 delete TC23
5V_USB1_S0
1M 0204 modify the symbol of EC74 (page23)
1
1
1
1
2
2
2
2
EC75 SC12P50V2JN-1-N3
DY
EC76 SC12P50V2JN-1-N3
DY
EC70 SC12P50V2JN-1-N3
DY
EC72 SC12P50V2JN-1-N3
DY
2 EC74
1
2
2
EC69
SC1000P50V3JN-GP-U
80.15715.12L 2nd = 77.C1571.09L
USB_0USB_0+ USB_9USB_9+ A
DY
SCD1U16V2ZY-2GP
TC22 ST150U6D3VBM-2-GP
0912 add these parts for EMI demand
1
1
100 mil
DY
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
USB Size
Document Number
Rev
LA14
SB
Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
23
of
52
5
4
3
2
1
1015 modify component size of R69 3D3V_LAN_S5
25 10M/100M_LED#
C130 LAN_RXN1
49 48 47 46 45 44 43 42 41 40 39 38 37
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
1
1 C128 SCD1U10V2KX-4GP
PCIE_RXP1 13 PCIE_RXN1 13
1D2V_LAN_S5 LANX1 LANX2
2 R59 2K37R2F-GP
SC1KP50V2KX-1GP
1
2
1
SCD1U10V2KX-4GP
C104
1D2V_LAN_S5_D
1 2 3 4
1126 add R303,R304 DY
0R2J-2-GP
82.30020.791 2nd = 82.30020.851 1113 X3 LANX2 1 2 LANX1
LA14 SA->SB
0401 DY R303
1 MDI0+ MDI0-
2
1D2V_LAN_S5
25 25
7,13,30,31,33,34
R68 2 1 0R0402-PAD
PLT_RST1#
1016 modify Q8
SB
2
1
1 1 2
2
1
C132 SC10U6D3V5KX-1GP
DY
1 2
DY
SB
1 C101 1 C125 1 C108 1 C99 1 C131
Close to AR8114 Pin16
VDD18O
Close to AR8114 Pin36
SB
1
AR8132
2
2
2
SCD1U10V2KX-4GP
AR8132
SC10U6D3V5KX-1GP
C115
R295 1
C538 SCD1U10V2KX-4GP
1D2V_LAN_S5
84.00069.B1B 2nd = 84.DCP69.01B 3rd = 84.00069.A1B AR8114
1128 Add L19
AR8114
C537
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
1D2V_LAN_S5
Close to AR8114 Pin8
Close to AR8114 Pin22
BCP69-GP Q8
1
SB
Close to AR8114 Pin46
0R2J-2-GP
3 2
CTRL12_R
Close to AR8114 Pin45
SB
AR8132 2
DY 1 C113 1 C107 1 C124DY 1 C123
Close to AR8114 Pin32
2
2
DY
1D8V_LAN_S5
C146 SC4D7U6D3V3KX-GP SCD1U10V2KX-4GP
1
1
R66 4K7R2J-2-GP
-1 1222 modify R79
1D2V_LAN_S5_D
C114 SC220P50V2JN-3GP
L19 1 2 IND-4D7UH-39-GP C143
C106 SC18P50V2JN-1-GP
Close to AR8114 Pin28
AR8114 use 0ohm resister AR8132 Atheros suggest to change 4.7uH choke 1 1229 modify L19
3D3V_LAN_S5_2
1
R79 2 1 0R0402-PAD
C103 and C106
LAN_RST
2 MDI1+ MDI1-
1015 modify component size of R79 3D3V_LAN_S5
XTAL-25MHZ-96GP C103 SC15P50V2JN-2-GP
modify
1 1222 modify R68
DY 25 25
C
SB
1
SRN49D9F-1-GP
1D2V_LAN_S5 MDI1+ MDI1-
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
VPD_CLK VPD_DATA
2nd = 72.24C08.J01
AR8114
13 14 15 16 17 18 19 20 21 22 23 24
MDI0+ MDI0-
8MDIS1_LAN 1 C95 7 6MDIS0_LAN 1 5
1 2 3 4
8 7 6 5
VCC WC# SCL SDA
72.24C08.I01
R304 0R2J-2-GP
AVDDH C94
NC#1 NC#2 E2 VSS
M24C08-WMN6TP-GP
PCIE_REQ_LAN# 3
1014 swap these nets RN9
RN53 SRN4K7J-8-GP
U10
R303 1
2
AR8132-AL1E-R-GP
1001 modify RN9
SB
TPAD14-GP R61 1 TP23 DY 4K7R2J-2-GP
VPD_DATA VPD_CLK 1D2V_LAN_S5_D
TRXP0 TRXN0 VDDHO AVVDL TRXP1 TRXN1 AVDDH NC#20 NC#21 AVDDL NC#23 NC#24
1
C102
3D3V_LAN_S5 TP24 TPAD14-GP 1
4 3
CTRL12 AVDDHO
Close to U13 Pin8
1D2V_LAN_S5
36 35 34 33 32 31 30 29 28 27 26 25
2
PCIE_WAKE#
DY
2
SC1KP50V2KX-1GP
1
13 C109
SCD1U10V2KX-4GP
AVDDL NO_CONN TESTMODE SMDATA DVDDL SMCLK TWSI_DATA TWSI_CLK DVDDL CLKREQ# NC#26 AVDDH
1
LAN_RST
3D3V_LAN_S5
2
2
0401 DY C109
LX VDD3V PERST# WAKE# VDD25V VDD17 SEL_25MHZ VDD11_REG XTLO XTLI AVDD_REG RBIAS
1
1 2 3 4 5 6 7 8 9 10 11 12
C449
1
1
2
VDD18O
1016 modify RN53 and U10
2
1
1
Modify 0504 SB->SC Change U11 P/N to 71.08132.M01
GND LED_10_100# LED_ACT# DVDD_REG DVDD_REG RX_N RX_P AVDDL REFCLKP REFCLKN AVDDL TX_P TX_N
U11
LA14 SA->SB
2
2
D
LAN_RXP1
FOR AR8114A LAN_ACT_LED is high enable pin 3D3V_LAN_S5
B
1 1224 modify R71
LAN_ACT_LED
R70 10KR2J-3-GP
MDI1MDI1+ MDI0MDI0+
落
R71 0R0402-PAD
AR8114A Atheros suggestion change to Bead 60 ohms/100Mhz 500mA (68.60090.0D1) AVDDL_REG
C129
C
CLK_PCIE_LAN 3 CLK_PCIE_LAN# 3
1
25 LAN_ACT_LED
2 2SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
AR8132 use 0 ohm resiter
CLK_PCIE_LAN_1 1 CLK_PCIE_LAN#_1 C127 1 C126
PCIE_TXP1 PCIE_TXN1
1D2V_LAN_S5
13 13
AVDDL_REG
2
DY
1D2V_LAN_S5 C116
DY
1D2V_LAN_S5_D 1D2V_LAN_S5_D
C119
1
1
SCD1U10V2KX-4GP
2
1 1222 modify R69
Close to AR8114 Pin2
SC10U6D3V5KX-2GP
SC10U6D3V5KX-2GP
SCD1U10V2KX-4GP
D
R69 2 1 0R0402-PAD 1 C122 SB
2
C118
2
1
3D3V_S5
Close to AR8114 Pin39 C121 SC1U6D3V2KX-GP
SB
2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
B
DY
DY AVDDH
Close to AR8114 Pin6
Close to AR8114 Pin1
1 C110 1 C105 1 C98 1 C100
Close to AR8114 Pin15 Close to AR8114 Pin19 Close to AR8114 Pin25
SB
2 SC1U6D3V2KX-GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP 2 SCD1U10V2KX-4GP
DY 1D2V_LAN_S5_D AVDDH
2
0R2J-2-GP
1 1224 modify R67
AR8132 R308 1
2
1
AR8114
1224 add R307 and R308
AVDDHO
2
AVDDH
AR8114
R67 2 1 0R0402-PAD
AR8114
Atheros suggestion change to Bead 60 ohms/100Mhz 500mA (68.60090.0D1)
R297 1
A
0R2J-2-GP
AR8132
CTRL12_R
0R2J-2-GP
R296 1 0R2J-2-GP
2
R307 1
2
1D8V_LAN_S5
1
CTRL12 A
1D2V_LAN_S5
Wistron Corporation
1D8V_LAN_S5
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
C539 SC1U6D3V2KX-GP
DY
AR8114
1
2 SCD1U10V2KX-4GP
Title
1 C120
2 SC1KP50V2KX-1GP
Size A3
C89
SB Close to AR8114 Pin6
Atheros AR8114/8132 Document Number
Rev
Date: Thursday, May 07, 2009 5
4
3
2
SB
LA14 Sheet 1
24
of
52
A
B
C
D
E
LAN Connector
3D3V_LAN_S5
R214 1 2 510R2F-L-GP
10M/100M_LED#
EC67 1
DY SC1KP50V2KX-1GP
CONN_PWR_2
EC68 1
DY SC1KP50V2KX-1GP
ACT_LED_B2
EC61 1
DY SC1KP50V2KX-1GP
ACT_LED_B1
EC64 1
DY SC1KP50V2KX-1GP
2 2
RJ1
2
24 10M/100M_LED#
4
CONN_PWR_2 RJ45_1 RJ45_2 RJ45_3
R298 1
LAN_ACT_LED
2 0R2J-2-GP ACT_LED_B1
SB LA14 SA->SB R301 1 2 510R2F-L-GP
ACT_LED_B2
A2(+) A1(-)::GREEN
9 A1 A2 A3 1
A2(+) A3(-):ORANGE
4
2 3 4 5 6 7 8 B1
RJ45_45 RJ45_6
SB 24
落
2
RJ45_78 ACT_LED_B1 ACT_LED_B2
B1(+) B2(-):YELLOW
B2 10
0313 Del R299,R300
RJ45-125-GP-U1
22.10277.021
10/100 Lan Transformer
1D8V_LAN_S5
2nd = 22.10277.231 SB 1204 modify second source of RJ1
XF1
1222 modify R58 24
MDI1-
1
12
RJ45_6
3
10
MCT2
MCT1 MCT2 RJ45_45 RJ45_78
MDI1+
2
11
RJ45_3
24
MDI0-
5
8
RJ45_2
4
9
MCT1
6
7
RJ45_1
24
MDI0+
3
4 3 2 1
1
1 2
DY
C87
24
RN6 SRN75J-1-GP
5 6 7 8
DY
C88
SCD01U16V2KX-3GP
2
SB
SCD1U10V2KX-4GP
2
C86 SCD01U16V2KX-3GP
DY
C85 SCD1U10V2KX-4GP
2
1
SB
1
3
XFORM-271-GP
C64 LAN_TERMINAL 1
68.HD081.301 2nd = 68.68160.30B
2 SC1KP2KV8KX-GP
1016 modify XF1
2
2
1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. 7.Must not cross ground moat,except RJ-45 moat.
RJ11 signal must leave the other signal or power plane 100mil.
DOC_TIP,DOC_RING,TIP,RING: W/S : 10/100 @ Surface layers 10/20 @ Inner layers 1
10/100 LAN Transformer
RJ45 PIN
1
TD+ --> TX+
RJ45-1
Wistron Corporation
TD- --> TX-
RJ45-2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
RD+ --> RX+
RJ45-3
RD- --> RX-
RJ45-6
Title Size A3
LAN Connector
Document Number
Date: Thursday, May 07, 2009 A
B
C
D
Rev
SB
LA14 Sheet E
25
of
52
5
4
3
3D3V_S0
3VA_S0
2
BIT_CLK SYNC SDATA_IN SDATA_OUT
C501 1 2
AUDIP_PC_BEEP
48
S/PDIF
45 46 47
GPIO2 GPIO1 EAPD#/GPIO0
MICBIASB MIC_L MIC_R
19 20 21
MICBIASC PORTC_L 20K PORTC_R
18 16 17
PORTD_L PORTD_R
27 28
PORTB_L 10K PORTB_R
14 15
MONO STEREO_L STEREO_R
29 30 31
1 2
1 2
AUD_MICIN_L AUD_MICIN_R
4 3
1 SC2D2U10V3KX-1GP 1 SC2D2U10V3KX-1GP
AUD_MICIN_L AUD_MICIN_R
C
28 28
CX_SENSE
VREF
24
FLY_P FLY_N
39 37
AUD_AVREF C271 FLY_P 1 2SC1U10V3KX-3GP FLY_N
VREF_LO VREF_HI RESERVED#32 RESERVED#33
VREF_LO VREF_HI
22 23 32 33
C505
C504
1
1230 dummy C507
DY
2
AVSS AVSS
DVSS DVSS
13
25 38
7 41
CX20561-15Z-GP
1 SENSEA
C507 C506
B
0911 add net name(FLY_P,FLY_N,VREF_LO,VREF_HI)
EC35
2
3VA_S0
R257 5K1R2F-2-GP
1
1
AUD_GPIO2
2 1
DY
2
AUD_GPIO1
2
DY
SOUNDL 27 SOUNDR 27
SC1U10V3KX-3GP
1
C280 SC10U10V5ZY-1GP
SRN2K2J-1-GP
R256 1 5K1R2F-2-GP 2
LINEOUT_JD# 28
1 R258
MIC_JD# 28
R106 CX_SENSE
Populate
0dB
74.09091.J3F 2nd = 74.09198.G7F
1014 modify these nets
1 2
MIC1-L_PORT-C C251 2 MIC1-R_PORT-C C255 2
SCD1U25V2ZY-1GP
10K GPIO RESISTORS
SB
RN33 MICBIASC
ACZ_BITCLK_AUDIO
DY
R105
FRONTL 28 FRONTR 28
SC1U10V3KX-3GP
Default gain is -6dB without populating the 10K-ohms pull-down resistors going to GPIO1 and GPIO2. 0912 add the part for EMI demand
49
PC BEEP GAIN CONTROL
DMIC_CLOCK DMIC_1/2
GND
1 2
GAIN
1
34 35
CX20561
R106 10KR2J-3-GP
NC#4
G9091-330T11U-GP
SCD1U10V2KX-4GP
EAPD#
R105 10KR2J-3-GP
5 4
1014 swap these nets
PORTA_L 5.11K PORTA_R
39.2K
PC_BEEP
DY
VOUT
1113 modify 2nd of U19
1
AUD_GPIO2 AUD_GPIO1
B
DY
VIN GND EN
SC1U10V3KX-3GP
SRN1KJ-7-GP
27
DIB_P DIB_N
12
1118 delete R107 and add L18
2
4 3
AUDIO_BEEP
1113 modify 2nd of U19
SC10U10V5ZY-1GP 2
1 2
KBC_BEEP ACZ_SPKR
1 R310 2 100KR2J-1-GP
0121 add R310 RN56
43 42
C274 SC1U10V3KX-3GP
SB
AVDD AVDD AVEE
1126 add C541 and modify R101 1M
33 13
6 10 8 5
U19
1 2 3
SB
1
1 2
C541
SC27P50V2JN-2-GP
C
RESET#
2
1001 Add R107
2
SB
ACZ_SDATAOUT_AUDIO
R101 1 2 ACZ_SDATAIN0_R ACZ_SDATAOUT_AUDIO 47R2J-2-GP
11
C277 C276
1
12 ACZ_BITCLK_AUDIO 12 ACZ_SYNC_AUDIO 12 ACZ_SDATAIN0 12 ACZ_SDATAOUT_AUDIO
26 40 36
9 4 3 44 VDD_IO DVDD_1_8 DVDD_3_3 DVDD
0911 add net name(ACZ_SDATAIN0_R)
3VA_S0
68.00119.081 2nd = 68.00230.021 SCD1U10V2KX-4GP
2
1 2 SCD1U10V2KX-4GP
12 ACZ_RST#_AUDIO
5V_S0
D
DY
U18
1
AUD_AVEE
C247
0911 add net name(DVDD_1_8)
3D3V_S0
L18
SBK160808T-100Y-N-GP
1
3D3V_S0
3VA_S0 C264 SCD1U10V2KX-4GP
SC10U10V5ZY-1GP 2
1118 delete C245 and C270
SCD1U10V2KX-4GP DVDD_1_8
2
SC10U10V5ZY-1GP 2
2 SCD1U10V2KX-4GP
1
C242 C248
1 C259
落
1
1
DY
SB
1
VDD_20561
1 R102 2 0R0603-PAD
D
2
Populate
2
20KR2F-L-GP -6dB
Omit
Omit
-12dB
Populate
Omit
-18dB
Omit
Populate
1014 modify R258 from 10k to 20k ohm
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3
Azalia codec CX20561 Document Number
Date: Thursday, May 07, 2009 5
4
3
2
Rev
SB
LA14 Sheet 1
26
of
52
A
B
C
D
E
AUDIO OP AMPLIFIER 5V_S0
落
5VA_OP_S0 G2
2
1 1224 dummy C6
1
1 GAP-CLOSE-PWR
C6 SC4D7U10V5ZY-3GP
2
4
4
DY AGND
1009 modify net name for GND to AGND 26
C15 1
SOUNDL
RN2 L_LINE_IN_1 LIN+RC
2
1 2
SCD47U16V3ZY-3GP
L_LINE_IN LIN+
4 3
SRN20KJ-GP-U
26
C13 1
SOUNDR
RN3 R_LINE_IN_1 RIN+RC
2
1 2
SCD47U16V3ZY-3GP
R_LINE_IN RIN+
4 3
3D3V_S0
1
SRN20KJ-GP-U
R309
1 5VA_OP_S0
1230 modify U1
1009 modify net name for GND to AGND
1
C8 C14
2
SC4D7U10V5ZY-3GP 2 1
AGND
SC1U16V3ZY-GP
C7
C16
1 1
2 RIN+RC SCD47U16V3ZY-3GP 2 LIN+RC SCD47U16V3ZY-3GP
AGND AGND
1009 modify net name for GND to AGND
R_LINE_IN RIN+ L_LINE_IN LIN+
2 11
VCC VCC
BYPASS SHUTDOWN#
5 14
BYPASS
7 8 15 16
RINRIN+ LINLIN+
LVO1 LVO2 RVO1 RVO2
1 4 12 9
SPKR_LSPKR_L+ SPKR_RSPKR_R+
VSS VSS
3 10
GND
17
6 13
NC#6 NC#13
1 0R2J-2-GP
AMP_SHUTDOWN# 33
3
SC4D7U6D3V3KX-GP
2
SPKR_LSPKR_L+ SPKR_RSPKR_R+
AGND
EAPD#_R
1 R135 2 0R0402-PAD
EAPD#
26
1 1222 modify R135
28,48 28,48 28,48 28,48
1 1230 delete Q1
G1454LR41U-GP
AGND
1009 modify net name for GND to AGND
74.01454.A13
2
C9 1
DY
R134
2
2
U1
3
1 1230 delete RN35 and add R309
10KR2J-3-GP
2
AC decopling 1014 swap these nets
1 1222 modify R5
RN36 R5 1 2 0R0402-PAD R4
L_LINE_IN LIN+ R_LINE_IN RIN+
1 0R2J-2-GP
2
1 2 3 4
8 7 6 5
SPKR_LSPKR_L+ SPKR_RSPKR_R+
SRN47KJ-1-GP
DY AGND
SB 1204 modify RN36
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Document Number
AUDIO AMP
Rev
SB
LA14 Date: Thursday, May 07, 2009 A
B
C
D
Sheet E
27
of
52
5
4
3
2
1
落
MIC IN 0930 add 2nd for MIC1
MIC1
1015 modify RN57 26
AUD_MIC_L
10KR2J-3-GP 10KR2J-3-GP
EU3
EU4
EC79
SB
MLVS0603M04-1-GP 2
MLVS0603M04-1-GP 2
D
PHONE-JK233-GP-U3
2
SC1KP50V2KX-1GP
LINE OUT
SC1KP50V2KX-1GP 2
EC97 SC1KP50V2KX-1GP
2 2
1
EC80
DY DY
1
1
SRN100J-3-GP
2
R260 R259
1 1
AUD_MIC_R
4 3
1
1 2
26 AUD_MICIN_R 26 AUD_MICIN_L
NP2 NP1 5 4 3 6 2 1
MIC_JD#
1
RN57
SHIELDING
D
22.10133.B01 2nd = 22.10251.491 3rd = 22.10133.H41
0930 modify
LOUT1
1126 modify EU1,EU2 and add EU3,EU4 LOUT1
C
Modify 0506 SB->SC Add EC97 and EC98, Change EC81,EC82 P/N to 78.10224.2FL
1 1222 modify RN58 from 68 to 56 ohm 26 LINEOUT_JD# 26 26
RN58
1 2
FRONTR FRONTL
LOUT_R+1
4 3
LOUT_L+1
1
EC81
2
22.10133.B21
SC1KP50V2KX-1GP
MLVS0603M04-1-GP
2
MLVS0603M04-1-GP
2nd = 22.10251.511 2
1
1
SC1KP50V2KX-1GP
4 3
PHONE-JK235-GP-U2 EC98
EC82
DY
SC1KP50V2KX-1GP
SRN1KJ-7-GP
1014 swap the part
2
2
1
EU2
1 2
EU1
SHIELDING
1
SRN56J-4-GP
ERN1
C
NP2 NP1 5 4 3 6 2 1
3rd = 22.10133.H31
B
B
Internal Speaker
0930 add 2nd for SPK1
1 1222 modify ER1~ER4
SB
1119 modify SPK1 SPK1
6 27,48 27,48 27,48
SPKR_LSPKR_L+ SPKR_R-
27,48
SPKR_R+
DY
4 3 2
R311 1 2 DY 0R2J-2-GP R312 1 2 0R2J-2-GP
1
1 2
1 2
DY
EC6
MLVG0402220NV05BP-GP-U
2
EC7
MLVG0402220NV05BP-GP-U
LA14 SA->SB 0331 Del EC7,EC8
DY
EC8
MLVG0402220NV05BP-GP-U
1201 modify EC6~9
MLVG0402220NV05BP-GP-U
SB
A
1
EC9
0912 add these parts for EMI demand
2
1
5 ACES-CON4-7-GP-U
A
20.F0772.004 2nd = 20.F1035.004
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
AUDIO JACK Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
28
of
52
5
4
3
2
1
落 D
D
MDC 1.5 CONN
0912 add the part for EMI demand 1002 modify MDC1 C
C
SB 1112 delete MDC function
B
B
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
MDC Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
29
of
52
A
5
3
2
1
3D3V_D_S0
SD_WP SD_CD# XD_D4/SD_DAT1 XD_D5/MS_BS XD_D3/MS_D1 SD_DAT0/XD_D6/MS_D0 SD_DAT7/XD_D2/MS_D2 MS_INS# SD_DAT6/XD_D7/MS_D3 SD_CLK/XD_D1/MS_CLK
R84 0R0603-PAD 1 2
1
CARD_3D3V_S0 D
C186 SCD1U10V2KX-1
2
DY
落
SD_DAT3/XD_WE# SD_DAT2/XD_RE#
3D3V_S0
4
D
U15
1 1230 modify the name of net
R97 2 0R2J-2-GP
13
USBPP11
13
USBPN11
1
1226 delete R96 1226 modify R100 and C240
MODE_SEL SD_CMD GPIO0 RREF RST#
MODE_SEL 3
1 1
DY C228 SC47P50V2JN-3GP
R94 0R2J-2-GP
DY
DY
C
71.05159.00G
Modify 04/27
Add R459 and R460
CLK48_5159
1017 modify USB signal connection
2
C240 SC1U10V3KX-3GP
6 12 32 46
2
2 2
1
RST#_CHIP
GND GND GND GND
1 R459 2USBPP11P 10R2F-L-GP 1 R460 2USBPP11N 10R2F-L-GP
3D3V_D_S0 R100 100KR2J-1-GP
30 7 3
1015 modify component size of R97 1
3D3V_D_S0
45 36 14 2 44
RST#_CHIP
NC#30 NC#7 NC#3
RTS5159-GR-GP
D3V3 D3V3
5 4
1
PLT_RST1#
24 22
U15
33 11
1 1222 modify R97
MS_D5 MS_D4
EEDO EEDI
6K19R2F-GP
1009 add R96 C
7,13,24,31,33,34
2RREF
3V3_IN
15 18
MODE_SEL SD_CMD
R86 1
VREG
8
EESK EECS
C192 SCD1U16V2ZY-2GP
10
17 16
DY
2
C252 SCD1U16V2ZY-2GP
DY
1
2
2
3D3V_D_S0
C197 SCD1U16V2ZY-2GP
1
2
C182 SC4D7U6D3V3KX-GP
1
1
3V_VBUS_S0
AV_PLL
XTLO XTLI
VREG
CARD_3V3
1
XTAL_CTR
R83 0R0603-PAD 1 2
3D3V_S0
9
47 48
1
AV_PLL
13
1015 modify component size of C182
C199 SCD1U16V2ZY-2GP
DP DM
2
2
R85 0R0603-PAD 1 2
1
C185 SC1U10V3KX-3GP
SP1 SP2 SP3 SP4 SP5 SP6 SP7 SP8 SP9 SP10 SP11 SP12 SP13 SP14 SP15 SP16 SP17 SP18 SP19
19 20 21 23 25 26 27 28 29 31 34 35 37 38 39 40 41 42 43
0910 update footprint of
3 IN1 CARD-READER (SD/MMC/MS) B
B
CARD1
NP1 NP2
NP1 NP2
SD-GND SD-GND
4 12
MS-GND MS-GND
5 19
DY
DY
DY DY
DY
DY
2
EC36
1
EC41
1
1
EC43
2
2
2 1
2 1
2
EC39
1
SD-CMD SD-CLK
DY
EC38
DY
EC37 SCD1U50V3ZY-GP
15 7
22 23
EC40
SCD1U50V3ZY-GP
SD_CMD SD_CLK/XD_D1/MS_CLK
GND GND
EC42
SD_CLK/XD_D1/MS_CLK
SCD1U50V3ZY-GP
SD-CD-SW SD-WP-SW
16
SD_CLK/XD_D1/MS_CLK SD_CMD SD_CD# SD_WP
SCD1U50V3ZY-GP
21 1
MS-SCLK
SD_DAT0/XD_D6/MS_D0 XD_D4/SD_DAT1 SD_DAT2/XD_RE# SD_DAT3/XD_WE#
SCD1U50V3ZY-GP
SD_CD# SD_WP
9 8 11 14
SCD1U50V3ZY-GP
SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3
MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3
XD_D5/MS_BS MS_INS# SD_DAT0/XD_D6/MS_D0 XD_D3/MS_D1 SD_DAT7/XD_D2/MS_D2 SD_DAT6/XD_D7/MS_D3
SCD1U50V3ZY-GP
3 2 20 18
6 13
SCD1U50V3ZY-GP
SD_DAT0/XD_D6/MS_D0 XD_D4/SD_DAT1 SD_DAT2/XD_RE# SD_DAT3/XD_WE#
MS-BS MS-INS
2
MS-VCC
1
SD-VCC
17
2
10
1
CARD_3D3V_S0
CARD_3D3V_S0
Wistron Corporation
MEMCARD-21P-2-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
2
1009 modify this net 1013 modify card1
1 2
C275 SC4D7U10V5ZY-3GP
1
A
C279 SCD1U16V2ZY-2GP
DY
CARD READER- RTS5159 Size
Document Number
Rev
LA14
1 1222 modify card1 from 20.I0043.001 to 20.I0043.011
Date: Thursday, May 07, 2009
SB 30
Sheet
1 1229 modify card1 LA14 SA 5
0217 modify card1 from 20.I0043.011 to 20.I0033.021 4
3
2
A
Title
1
of
52
A
B
C
D
E
落
Mini Card Connector(WLAN) 4
4
1D5V_S0
3D3V_MINI
3D3V_MINI
MINIC1
3 PCIE_REQ_MINI# 3 CLK_PCIE_MINI1# 3 CLK_PCIE_MINI1 33 33
E51_RxD E51_TxD
13 PCIE_RXN2 13 PCIE_RXP2 3
13 PCIE_TXN2 13 PCIE_TXP2 3D3V_MINI
5V_S5
2
3 5 7 9 11 13 15
4 6 8 10 12 14 16
17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 NP2 54
18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
PLT_RST1#_WLAN
2 R37 300R2F-GP R168 1DY 2 10KR2J-3-GP
SC100P50V2JN-3GP C47
DY
WIRELESS_EN 33 PLT_RST1# 7,13,24,30,33,34
1
1
1MINI_WAKE#
2
TPAD14-GP TP49
53 NP1 1
3
1017 modify USB signal connection USBPN3 13 USBPP3 13 LED_WWAN#
1
TP42 TPAD14-GP
LED_WPAN#
1
WLAN_LED#_MC 33,38 TP41 TPAD14-GP
1015 modify component size of R158,R159 1 1222 modify R159
SKT-MINI52P-20-GP
20.F1117.052 2nd = 62.10043.391
3D3V_S0
R159 2 1 0R0402-PAD
3D3V_S5
1 R158 2 0R2J-2-GP
3D3V_MINI
DY
1021 modify TC16
Place near MINIC1
2
3D3V_MINI
2
1D5V_S0
1
SB
2
C356
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
C330 SC1U6D3V2KX-GP
C333
DY
79.33719.L01 2nd = 77.C3371.051
1
1
SB
2
1
C326 SCD1U16V2ZY-2GP
SC1U6D3V2KX-GP
DY
2
1
C334
2
1
C360 SCD1U16V2ZY-2GP
2
1
C332 SC1U6D3V2KX-GP
2
TC16 SE330U2VDM-L-GP
DY
2
1
SB
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
MINI CARD Size
Document Number
Rev
LA14 Date: Thursday, May 07, 2009 A
B
C
D
SB Sheet E
31
of
52
EMC2102_FAN_TACH 48 EMC2102_FAN_DRIVE
48
FAN1
K
RN64
2
5V_S0
1
SRN10KJ-5-GP
R188
SMBC_Therm 33 SMBD_Therm 33
2
H_THERMDA
3
23
22
SMCLK
SMDATA
25
ALERT#
1 R177
EMC2102_DN2
4
DN2
CLK_IN
18
CLK_32K
0R2J-2-GP
EMC2102_DP2
5
EMC2102_DN3
6
DP2
CLK_SEL
17
EMC2102_CLK_SEL
DN3
RESET#
16
EMC2102_DP3
7
DP3
NC#15
15
1
DY
POWER_OK#
THERMTRIP#
EC60 SCD1U50V3ZY-GP
3D3V_S0
PURE_HW_SHUTDOWN# V_DEGREE
C355
2
C51 must be near Q8 C373 must be near EMC2102
SB 1125 modify RN40 and delete RN42
RUN_POWER_ON
1 2
R178 10KR2F-2-GP
TRIP_SET Pin Voltage V_DEGREE =(((Degree-75)/21) T8 90 degree
1
2
C349 VGATE_PWRGD
R180 3KR2F-GP
2
1
14
13
SYS_SHDN# 12
EMC2102_PWROK 39
1
Layout notice : Both EMC2102_DN3 and EMC2102_DP3 routing 10 mil trace width and 10 mil spacing
THRM# 13
SCD1U16V2ZY-2GP
PIN10 GND = Fan is OFF OPEN = Fan is at 60% full-scale +3.3V = Fan is at 75% full-scale
3.HW T8 sensor
TRIP_SET
NC#8 8
74.02102.A73
2nd = 74.07922.0B3
C
1
2
E
C51 SC470P50V3JN-2GP
PIN9 GND = Channel 1 OPEN = Channel 3 C373 SC470P50V2JN-GP +3.3V = Disabled
2
2
EMC2102
DY
SCD1U16V2ZY-2GP
84.T3904.C11 2nd = 84.03904.L06
24
19
EMC2102-DZK-GP
DY
VDD_5Vb
20
ALERT#
2.System Sensor, Put between CPU and NB.
B
26
GND
DP1
Layout notice : Both EMC2102_DN2 and EMC2102_DP2 routing 10 mil trace width and 10 mil spacing
MMBT3904-4-GP Q6
FANb
DN1
FAN_MODE
2
H_THERMDC
11
1
DY
C377 SC470P50V2JN-GP
21
C
84.T3904.C11 2nd = 84.03904.L06
B
GND = Internal Oscillator Selected +3.3V = External 32.768kHz Clock Selected
NC#21
EMC2102_fan_mode 10
E MMBT3904-4-GP Q14
C272 SC470P50V2JN-GP
1
2
CC272 must be near Q7 C377 must be near EMC2102
VDD_3V
SHDN_SEL
1.For CPU Sensor
1
9
H_THERMDA
SB
FANa
28
GND
TACH
1
2
C376 SC470P50V2JN-GP
1 1222 modify U42
1
H_THERMDC
VDD_5Va
U42
SCD1U16V2KX-3GP
27
C370
Layout notice : Both H_THERMDA and THERMDC routing 10 mil trace width and 10 mil spacing
4
C357 SCD1U16V2ZY-2GP
EMC2102_VDD_3D3
2
49D9R2F-GP
4
LA14 SA->SB 0403 Change D11 from 83.1R004.080 to 83.1R004.M8M
DY
2
1
20.F0714.003 2nd = 20.D0246.103
2
C361 SC4D7U10V5ZY-3GP
29
3D3V_S0
ACES-CON3-GP-U1
83.1R004.M8M
A
3 4
4
D11 SS14-3-GP
C346 SC22U6D3V5MX-2GP
0930 modify FAN1 1017 modify FAN1 1 1224 modify FAN1
1
*Layout* 15 mil
1
3D3V_S0 EMC2102_FAN_TACH 2 EMC2102_fan_mode 1
3 2
EMC2102_FAN_DRIVE
1 1224 delete R165 and add RN64
落
5
EMC2102_FAN_TACH
3D3V_S0 RN40
D
S
CLK_32K_R
PURE_HW_SHUTDOWN# EMC2102_CLK_SEL THRM# CLK_32K
1
PM_SUS_CLK
4 3 2 1
2N7002-12-GP 84.27002.Y31
R170 240KR3-GP
SRN10KJ-6-GP
1 1223 modify the net(EMC2102_CLK_SEL)
2
32K suspend clock output
3
3D3V_AUX_S5
DY
Q21
D
RSMRST#
Wistron Corporation
RSMRST# 33,39
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
(dummy, KBC already delay) 2N7002-12-GP 84.27002.Y31
1
S
D10 BAT54-5-GP 83.BAT54.D81 2nd = 83.BAT54.X81 3rd = 83.00054.Z81
C335 DY SCD1U16V2ZY-2GP
Title
2
PURE_HW_SHUTDOWN#
2
13,41 VGATE_PWRGD
1
LA14 SA->SB 0403 Change Q21,Q22 from 84.27002.W31 to 84.27002.Y31
G
13
5 6 7 8
G
Q22
Size
Thermal/Fan Controllor
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009
Sheet
32
of
52
A
3D3V_AUX_S5 AVCC
81
NUM_LED
22 BLUETOOTH_EN
84 83 82 91
SHBM
31 WIRELESS_EN 38 WLAN_TEST_LED
31 31
E51_TxD E51_RxD
38
DC_BATFULL
E51_TxD E51_RxD
1 R192
SP
GPIO66/G_PWM
GPIO77 GPIO76/SHBM GPIO75 GPIO81
SPI
S5_ENABLE_KBC
114 14 15
GPIO16 GPIO34 GPIO36
VCORF
44
GPIO
SER/IR
GPI94 GPI95 GPI96 GPI97
101 105 106 107
GPIO01/TB2 GPIO03 GPIO06 GPIO07 GPIO23 GPIO24 GPIO30 GPIO31 GPIO32/D_PWM GPIO33/H_PWM GPIO40/F_PWM GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO45/E_PWM GPIO46/TRST# GPIO47 GPIO50/TDO GPIO51 GPIO52/RDY# GPIO53 GPIO70 GPIO71 GPIO72 GPO82/TRIS#
64 95 93 94 119 6 109 120 65 66 16 17 20 21 22 23 24 25 26 27 28 73 74 75 110
1
1
2 20MR3-GP
KBC_XI
77
32KX1/32KCLKIN
KBC_XO 79 30
32KX2 GPIO55/CLKOUT
PM_PWRBTN# CHG_ON# KBC_BEEP EC_TMR BRIGHTNESS
PM_SLP_S3# 13,39,43,44 KBC_PWRBTN# 36 AC_IN# 46 LID_CLOSE# 37
KBC_PWRBTN# PLATFORM_ID
35 35
Pin 120: MODEL_ID_0
TPDATA TPCLK
TPDATA TPCLK
63 117 31 32 118 62
GPIO14/TB1 GPIO20/TA2 GPIO56/TA1 GPIO15/A_PWM GPIO21/B_PWM GPIO13/C_PWM
13 12 11 10 71 72
GPIO12/PSDAT3 GPIO25/PSCLK3 GPIO27/PSDAT2 GPIO26/PSCLK2 GPIO35/PSDAT1 GPIO37/PSCLK1
86 87 90 92
F_SDI F_SDO F_CS0# F_SCK
KBSOUT0/JENK# KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KBSOUT4/JEN0# KBSOUT5/TDO KBSOUT6/RDY# KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12/GPIO64 KBSOUT13/GPIO63 KBSOUT14/GPIO62 KBSOUT15/GPIO61/XOR_OUT GPIO60/KBSOUT16 GPIO57/KBSOUT17
53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33
KCOL0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7
54 55 56 57 58 59 60 61
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
VCC_POR#
85
ECRST#
KBC
PS/2
PWRLED 38 34 34 34
CAP_LED 36 AD_OFF 45 RSMRST#_KBC 13 PM_SLP_S4# 13,43,44 CHARGE_LED 38
AD_OFF RSMRST#_KBC
34
SPIDI SPIDO SPICS# SPICLK
FIU
Pin 24: MODEL_ID_1
BLON_OUT Pin 28:UMA=NC; DIS=PL
SPI_WP# 34 BLUETOOTH_LED 38 BLON_OUT 18
0916 move net(SPI_WP#) from U9 pin120 to pin25
WPCE773LA0DG-GP 3
RN46
LA14_SA 0205 add signal Bluetooth_LED USB_PWR_EN#
5 6 7 8
3D3V_AUX_S5
23
VCORF
KA20GATE KBRCIN# E51_TxD SHBM
1
103
4
2 OF 2
U9B
R49
13 46 26 13 18
CRT_DEC# 36
3D3V_S0
8 7 6 5
4 3 2 1
ECRST# KBC_THERMALTRIP# RSMRST# LID_CLOSE#
SRN10KJ-6-GP
1 2 3 4
32,39
Q23 B
RSMRST#
MMBT3906-3-GP
84.03906.R11 2ND = 84.03906.F11 3RD = 84.03906.P11
1 1223 modify the net(RSMRST#)
WPCE773LA0DG-GP
SRN10KJ-6-GP
SB
FOR KBC DEBUG
3D3V_AUX_S5
0912 add the part for EMI demand 3D3V_S5
KCOL2
2
8 7 6 5
1
0R2J-2-GP
1
KCOL3
2 0R2J-2-GP
BAT_SCL BAT_SDA
DY:
EC63 1
1 1224 modify RN48 RN48
2 SCD1U50V3ZY-GP
8 7 6 5
DY AD_OFF
1 2 3 4
DY
SPIDI RN49 SRN4K7J-12-GP
R203
SMBC_Therm SMBD_Therm
R191 1 2 1KR2J-1-GP
PCLK_KBC
1 1230 modify D14
C369 DY 1 2
RSMRST#_KBC AD_OFF S5_ENABLE_KBC BLON_OUT
SRN10KJ-6-GP RN44 3D3V_S0
SC4D7P50V2CN-1GP
1 2 3 4
8 7 6 5
PLATFORM_ID WIRELESS_BTN# HDD_LED# 12,38 WLAN_LED#_MC 31,38
SRN10KJ-6-GP
D14 ECSCI#_1
1 2 3 4
DY
ISP Mode disable
13
C378
1106 modify net connection of RN46 and RN44
3D3V_S0
R202
DY
1 10KR2J-3-GP
SC1U10V3KX-3GP
2
R46
KBC_THERMALTRIP# 39
2 R201
X1
27 AMP_SHUTDOWN# KBC_THERMALTRIP# PCB_VER0 PCB_VER1
RN45
C387 SCD1U16V2ZY-2GP
1
2
1KBC_XO_R2 AD_IA 46 NOVO_BTN# 36 WIRELESS_BTN# 36
2
4
DY
2
19 46 76 88 115 VCC VCC VCC VCC VCC
AVCC
SMB
GPO83/SOUT_CR/BADDR1 GPIO87/SIN_CR GPO84/BADDR0
LA14 SA->SB 0401 ADD GPIO16
102
80
GPIO74/SDA2 GPIO73/SCL2 GPIO22/SDA1 GPIO17/SCL1
111 113 112
3
S5_ENABLE 2 2K2R2J-2-GP
D/A
97 98 99 100 108 96
3
1
36
LPC
GPI90/AD0 GPI91/AD1 GPI92/AD2 GPI93/AD3 GPIO05 GPIO04
C67
E
BATTERY----->
A/D
104
82.30001.861 X-32D768KHZ-46GP
2
THERMAL----->
VDD
GPIO41 68 67 69 70
7
U9A
VREF
落
1016 modify X1
1
1 2
C362
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP 2 1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP 2 1
SCD1U16V2ZY-2GP 2 1
1 2
SCD1U16V2ZY-2GP 2 1
2
1
1 2
32 SMBD_Therm 32 SMBC_Therm 45,46 BAT_SDA 45,46 BAT_SCL
KBRCIN# KA20GATE
DY
39,42,48 S5_ENABLE
C359
C
2PCLK_KBC_RC
1
C380
GND GND GND GND GND GND
1
12 12
GPIO10/LPCPD# LRESET# LCLK LFRAME# LAD0 LAD1 LAD2 LAD3 SERIRQ GPIO11/CLKRUN# KBRST# GA20 ECSCI#/GPIO54 GPIO65/SMI# GPIO67/PWUREQ#
5 18 45 78 89 116
2 R187 0R2J-2-GP
DY
C386
33KR2J-3-GP
GMCH_BL_ON
124 PLT_RST1#_1 7 2 3 126 127 128 1 125 8 122 121 ECSCI#_KBC 29 9 ECSWI#_KBC 123
12,34 LPC_LFRAME# 12,34 LPC_LAD0 12,34 LPC_LAD1 12,34 LPC_LAD2 12,34 LPC_LAD3 13 INT_SERIRQ 13 PM_CLKRUN#
C371
C354
C60
1 OF 2
PCLK_KBC
SC4D7P50V2CN-1GP
C353
DY
BAT_IN#
BAT_IN#
4
45
AGND
1 2
DY 4
3
3D3V_S0
SB
C359,C362 colse to Pin VDD SC27P50V2JN-2-GP
C368
SC10U10V5ZY-1GP 2 1
R189 2 1 0R0402-PAD
PLT_RST1#
C374
SC15P50V2JN-2-GP
7,13,24,30,31,34
DY
3D3V_S0
SC15P50V2JN-2-GP
SC1U16V3ZY-GP
1 1222 modify R189
SCD1U16V2ZY-2GP
SB C366 C363
3D3V_AUX_S5
2 R184 1 0R0603-PAD
6
1
5
2
ECSCI#_KBC
1 1224 modify R191and this net AD_OFF
LA14 SA->SB
66.10336.08L
2
2
0330 ADD WLAN_LED#_MC
4
ECSWI#
3
ECSWI#_KBC
0930 modify net name for BIOS demand 3D3V_AUX_S5
83.R2002.B8E
2nd = 83.R3004.A8E
48 48 48 48
KCOL8 KCOL7 KCOL6 KCOL5
28
KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 KCOL17
KROW0 KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1
27
KCOL0
LA14 SA modify
KB1
1
Internal KeyBoard CONN 1
26
KCOL8 KCOL7 KCOL6 KCOL5
DY
2
2
KCOL16 KCOL15 KCOL14 KCOL13
1
1
KCOL16 KCOL15 KCOL14 KCOL13
1
48 48 48 48
PCB_VER0 PCB_VER1
R176
R173
LA14_SA
PlanarID (0,0) SA: 0,0
10KR2J-3-GP
KCOL0
KCOL0
10KR2J-3-GP
48
DY
KCOL17
2
20.K0382.026
KCOL17
1 2 3 4
R175 10KR2J-3-GP
KB1 PTWO-CON26-4-GP
48
10KR2J-3-GP
Internal KeyBoard Connector
RN47
3D3V_AUX_S5 R174
1
RB731U-2-GP
2
13
SRN100KJ-8-GP-U 66.1043A.08L
LA14 SA->SB 0330 Change RN47 from 66.10436.04L to 66.1043A.08L
0207 Dummy R174,ADD R173 -1 1222 modify PCB Ver. from SB to -1
48 48 48 48
KCOL4 KCOL3 KCOL2 KCOL1
48 48 48 48
KROW0 KROW7 KROW6 KROW5
48 48 48 48
KROW4 KROW3 KROW2 KROW1
48 48 48 48
KCOL12 KCOL11 KCOL10 KCOL9
KCOL4 KCOL3 KCOL2 KCOL1
KROW0 KROW7 KROW6 KROW5
1
KROW4 KROW3 KROW2 KROW1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
........
CHECK KB SPEC. AND PIN DEFINE
BAT_IN# NOVO_BTN# KBC_PWRBTN#
8 7 6 5
KCOL12 KCOL11 KCOL10 KCOL9
Title
KBC WPCE773L
Size Document Number Custom
Rev
SB
LA14
Date: Thursday, May 07, 2009 A
Sheet
33
of
52
A
B
C
D
E
落 3D3V_AUX_S5 4
5 6 7 8
4
RN41
0330 Modify NOVO_BTN#
2
4 3 2 1 SPI_HOLD#
ER6 0R0603-PAD
1 2 3 4
SPICS#
VCC HOLD# CLK DIO
8 7 6 5
3D3V_AUX_S5_SPI_ROM SPI_HOLD# SPICLK SPIDO
33 33
GOLDEN FINGER FOR DEBUG BOARD
2
72.25X16.A01 2nd = 72.25165.A01
3
1013 modify U40 from 72.25X16.001 to
1
1 2
SC4D7P50V2CN-1GP
EC59 SC4D7P50V2CN-1GP
2
DY EC57
W25X16AVSSIG-GP
SPIDI
1
33
2
DY EC55 SC4D7P50V2CN-1GP
SPI_WP#
CS# DO WP# GND
1
33
SPI_WP#
1
U40 33
1 1224 modify ERN2
3D3V_AUX_S5
16M Bits SPI FLASH ROM
SRN10KJ-6-GP
DY EC58 SC4D7P50V2CN-1GP
3
3D3V_S0
SB
72.25X16.A01
GF1
1 2 3 4 5 6 7 8 9 10 11 12
0912 add the part for EMI demand
SPI_HOLD#EC56 1
2 SCD1U50V3ZY-GP
DY
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PLT_RST1# PCLK_FWH
LPC_LAD[0..3]
LPC_LAD[0..3]
PCLK_FWH 3 PCLK_FWH
2
MLX-CON10-7-GP
DY
12,33
LPC_LFRAME# 12,33 PLT_RST1# 7,13,24,30,31,33
1
LA14 SA->SB
EC26 SC5P50V2CN-2GP
DY
20.D0183.110
2
2
1
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
BIOS/GOLDEN FINGER Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 A
B
C
D
Sheet E
34
of
52
5
4
3
2
1
落 D
5V_S0
TOUCH PAD
D
2
SCD1U10V2KX-4GP
2
EC27
DY
37,48 37,48
SCD1U10V2KX-4GP
EC28
6
T/P
1
1
1
DY
0930 modify
TPAD1
1013 modify
TPAD1
1015 modify
TPAD1
1124 modify
TPAD1
TPAD1
7 1 TP_CLK TP_DATA
2 3 4 5 6
TP_LEFT TP_RIGHT
8
PTWO-CON6-12-GP
5V_S0
1 2
20.K0382.006 2nd = 20.K0356.006
RN7
C
C
4 3
SRN10KJ-5-GP
RN8 33 33
TPDATA TPCLK
1 2
4 3
TP_DATA TP_CLK
TP_DATA 48 TP_CLK 48
2
DY
SC220P50V2JN-3GP
SC220P50V2JN-3GP
DY
0910 delete RIGHT1 and LEFT1
EC30
1
EC29
1
2
SRN33J-5-GP-U
B
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Touch pad Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
35
of
52
5
4
3
2
1
落 R129
Q16 D
33
1
NUM_LED
R1
NUM_LED#
3
1
2
NUM_LED#_R
D
100R2J-2-GP
2
R2 DTC143ZUB-GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
R128
Q15 CAP_LED#
3
1
2
CAP_LED#_R POWERCN1 7
100R2J-2-GP
2 R2 DTC143ZUB-GP
1
1 WIRELESS_BTN#_1
NP1
CRT_DEC#
1 2
DY
C
0205 modify POWERCN1 from 20.K0384.016 to 20.K0204.006
3
33
C4
DY
PTWO-CON6-12-GP
LA14_SA
2
RN1 48 KBC_PWRBTN#_1 48 WIRELESS_BTN#_1 48 NOVO_BT#
EC4
DY
SC1U16V3ZY-GP
EC5
0205 ADD signal NOVO_BT# SW1
C
8 1
LA14_SA
0205 remove signals(TP_LOCK_LED,TP_LOCK_LED#,TP_LOCK_LED#_R)and R132,Q17
2 3 4 5 6
5V_S0
2
LA14_SA
KBC_PWRBTN#_1 CAP_LED#_R NUM_LED#_R NOVO_BT#
1
48 KBC_PWRBTN#_1 48 CAP_LED#_R 48 NUM_LED#_R 48 NOVO_BT#
SCD1U16V2ZY-2GP
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
2
CAP_LED
R1
SCD1U16V2ZY-2GP
33
1
NP2
1 2 3 4
8 7 6 5 CRT_IN#_R
KBC_PWRBTN# 33 WIRELESS_BTN# 33 NOVO_BTN# 33 CRT_IN#_R 19
0223 modify POWERCN1 from 20.K0204.006 to 20.K0382.006 SW-SLIDE57-GP-U
22.40048.741
SRN470J-3-GP
NUM_LED#_R CAP_LED#_R
2
KBC_PWRBTN#_1
1
1
2
2
DY
B
LA14_SA EC45
DY
SCD1U50V3ZY-GP
GAP-OPEN
EC46 SCD1U50V3ZY-GP
1
G1
0205 remove EC49
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Power Board Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
36
of
52
5
4
3
2
1
落
TP_LEFT 1017 modify RN60 TP_L1
RN60 TP_LEFT#_1
2
SW-TACT-5P-1-GP
TP_LEFT 35,48 TP_RIGHT 35,48
Cover Up Switch
EC84 SC1KP50V2KX-1GP
D
3D3V_AUX_S5 SRN470J-4-GP-U
DY
62.40009.A61
TP_RIGHT
2
VDD
1
LID_CLOSE#
2
OUT
LID_CLOSE# 33
GND EC22 SCD1U16V2ZY-2GP
DY 1
3
R40 10KR2J-3-GP
DY
U4
2
4 2
3
4 3
1
5
D
1 2
1
1
ME268-002-GP TP_RIGHT#_1
74.00268.07B
EC21 SCD1U16V2ZY-2GP
1
2
3
4
2
SW-TACT-5P-1-GP
EC83 SC1KP50V2KX-1GP
1
5
2
TP_R1
1
DY
1016 modify U4 62.40009.A61
1017 modify U4
C
C
1 1226 modify TP_L1 and TP_R1
1017 add U61,R52,EC24 and EC23 1020 delete U61,R52,EC24 and EC23
B
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
SWITCHS Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
37
of
52
5
4
3
2
33
PWRLED
PWRLED#
3
R1
1
D
LED11
1
PWRLED#_R
2
K
330R2F-GP
2 R2 DTC143ZUB-GP
落
5V_S5
White R291
Q27
1
A LED-W-12-GP-U
D
83.00191.D70
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
LA14_SA 0205 modify LED11 from 83.00195.G70 to 83.00190.L70
R293
Q29 33
1
DC_BATFULL
3
R1
LA14 SA->SB
1
2
0401 Change from 83.00190.L70 to 83.19223.D70 330R2F-GP 64.33005.6DL
2 R2 DTC143ZUB-GP
0401 ADD R293,Q29
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
5V_AUX_S5 LED13
orange
4
C
33
1
CHARGE_LED
1
R294
Q30 CHARGE_LED#
3
R1
1
CHARGE_LED#_R
2
C
white
LA14_SA 0205 modify LED13 from 83.00195.G70 to 83.00190.L70 White
R3 12,33 HDD_LED#
2 LED-OW-1-GP-U 83.19223.D70
84.00143.G1K 2nd = 84.00143.D1K 3rd = 84.00143.E1K
1
3
330R2F-GP
2 R2 DTC143ZUB-GP
5V_S0
LED14 HDD_LED#_R
2
K
330R2F-GP
A LED-W-12-GP-U 83.00191.D70
LA14_SA 0205 add LE14,R294
2
WLAN_LED#
1 D
3
DTA143ZUB-GP
B
2
WLAN_LED#_R
S
EC47 84.27002.Y31
DY
LA14 SA->SB modify Q19
SCD1U50V3ZY-GP
1016 modify Q18
R2
0205 add LE12
2
Bluetooth_LED#
1
2
K
A
DY
330R2F-GP
3
5V_S0
LED15
LED-W-12-GP-U
1
1
R1
33 BLUETOOTH_LED
R305
DY
B
LA14_SA
White Q31
WLAN_LED#_R 48
83.00191.D70
G
33 WLAN_TEST_LED
A LED-W-12-GP-U
Q19 2N7002-12-GP
84.00143.F1K
K
330R2F-GP
1
R1
1
48
LED12
2
R2 31,33 WLAN_LED#_MC
HDD_LED#_R
5V_S0
White R130
Q18
DTA143ZUB-GP
83.00191.D70 EC48
2
DY
SCD1U50V3ZY-GP
84.00143.F1K
DY
A
A
Wistron Corporation
LA14_SA
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
0209 Change R305,R291,R294,R130,R3 from 29L2589AA to 64.33005.6DL Title
LA14 SA->SB
0331 Change LED11,LED12,LED14,LED15 from
83.19213.H70 to 83.00191.D70
LED Size
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
38
of
52
Aux Power
3D3V_AUX_S5
落
Run Power I min = 300 mA 5V_AUX_S5 U43
3D3V_AUX_S5
DY
C269 1
SCD1U25V3KX-GP
R117 100KR2J-1-GP
K
C278
R120
D9 PDZ9D1B-GP
3D3V_S0
3D3V_S5
1 2 3 4
A
2
Z_12V_D4
2
3D3V_runpwr 2
83.9R103.C3F 2nd = 83.9R103.F3F
U21 S S S G
D D D D
8 7 6 5
AO4468-GP
1016 modify D9
84.04468.037
Q12 Z_12V_D3
D
DY
AO4468-GP
1
1 R115
2Z_12V_G3
330KR2J-L1-GP
DY DY
8 7 6 5
D
2
R118 1
D D D D
84.04468.037 S
10KR2J-3-GP
R109 100R5J-3-GP
1113 modify 2nd of U43
2
C372 SCD1U10V2KX-4GP
2
1 2 3 4
2
U20 S S S G
RUN_POWER_ON
1
3D3V_S0
SB
1
2
DY
Z_12V
330KR2J-L1-GP
R190 0R0402-PAD 2 1
R119 1
SCD22U25V3KX-GP
5V_AUX_S5
Q13 NDS0610-NL-GP
DCBATOUT C379
10KR2J-3-GP
3D3V_AUX_S5_EN
74.09091.J3F 2nd = 74.09198.Q7F DY
2
G9091-330T11U-GP C375
G
4
1
NC#4
5V_S5
5V_S0
1
5
1
VOUT
2
VIN GND EN
SC1U16V3ZY-GP
Q11 2N7002-11-GP
Z_12V_D3
3
5
2
6
1
S
G
4
2N7002DW-2-GP-U 84.27002.E3F
PM_SLP_S3# 13,33,43,44
LA14 SA->SB 0403 Change Q12 from 84.27002.D3F to 84.27002.E3F
3D3V_S5 SCD1U16V2KX-3GP C257 1
U17
1
B
2
A
3
GND
VCC
5
Y
4
2
DY PWROK 7,13
74LVC1G08GW-1-GP 1D05V_S0
1
73.01G08.L04 2nd = 73.7SZ08.AAH 3rd = 73.01G08.L03
R112 2K2R2J-2-GP
DY 2
1 1224 remove R113
C266 1
PM_THRMTRIP-A# 4,7,12
DY
B R114 1KR2J-1-GP 4,12,48 H_PWRGD
1
2
DY E
E H_PWRGD#
B
C268 SC2D2U16V3KX-GP
C
13,33,43,44 PM_SLP_S3#
EMC2102_PWROK
1
32 EMC2102_PWROK
C
2 SCD1U16V2ZY-2GP
KBC_THERMALTRIP# 33
Q9
Q10 MMBT2222A-3-GP
MMBT3904-3-GP
84.02222.V11 2nd = 84.02222.R11
2
SC1U16V3ZY-GP
DY
1
1 2 3
D8 33,42,48 S5_ENABLE
1 BAS16-6-GP 283.00016.K11
3
RSMRST# 32,33 UMA Two Phase
Wistron Corporation
LA14 SA->SB 0403 Change D8 from 83.00016.B11 to 83.00016.K11
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
RUN POWER and 3D3V_AUX_S5 Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009
Sheet
39
of
52
5
4
3
CPU_CORE ISL6266A VID0 D
VID1 VID2 VID3 VID4 VID5 VID6
VID Setting
Output Signal
VID0(I / 3.3V)
2
PGOOD
Input Power VGATE_PWRGD
DCBATOUT_51125
1D5V_S0
Output Power 5V(O)
VIN
1D8V_S3
5V_S5 (6A)
VIN
落
1D5V_S0 (2.5A)
1D5V(O)
D
VID1(I / 3.3V) S5_ENABLE
VID2(I / 3.3V) VID3(I / 3.3V)
Output Power
VID4(I / 3.3V)
VCC_CORE_PWR(O)
VCC_CORE(Imax=38A) ALW_PWRGD_3V_5V
Input Signal
3D3V(O)
EN0
5V(O)
Output Signal
3D3V_S5 (6A)
PM_SLP_S3#
EN
RT9026
PGOOD
3D3V(O)
VID5(I / 3.3V)
CPUCORE_ON
PGOOD
5V_AUX_S5 5V_S5
3D3V_AUX_S5
0D9V_S0
VIN
1D8V_S3 PM_SLP_S4#
EN (I / 3.3V)
0D9V_S3 (1A)
VTT
VLDOIN
VID6(I / 3.3V) Input Signal
CPUCORE_ON
1
RT9018A
TPS51125 5V/3D3V
S3
0D9V_S3_1
VTTREF
S5
C
C
Voltage Sense VCC_SENSE VSS_SENSE
VSEN(I / Vcore) RGND(I / Vcore)
Input Power DCBATOUT_6266A 5V_S0 3D3V_S0
VCC(I)
Charger BQ24745
VCC(I)
Input Signal CHG_ON#
VCC(I)
B
24750_CELLS
TPS51124 1D8V/1D05V 5V_S5 DCBATOUT_51124
PM_SLP_S4# PM_SLP_S3# A
Input Power
VCC Input Signal
1D8V (O)
1D05V(O)
1D8V_S3 (10A)
AD+
Input Signal
EN1 AD_OFF
EN2
ACN
Output Power BT+
VOUT (O) VOUT (O)
Output Signal (O)
(I)
B
AD_IA
SRSET
CELLS
Adapter
1D05V_S0 (15A)
AC_IN#
ACGOOD#
Input Power
Output Power
VDD
CHGEN#
Output Signal
AD_IN#
DCBATOUT
Wistron Corporation CPUCORE_ON
Output Signal
Input Power
PGOOD1
AD_JK
PGOOD2
5V_AUX_S5
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Output Power
VCC(I)
VCC(O)
Title
AD+
Power Sequence Logic Size B
VCC(I)
Document Number
Date: Thursday, May 07, 2009 5
4
3
2
Rev
LA14
SB
Sheet 1
40
of
52
A
PHASE2
28
UGATE2
27
6266A_UGATE2
BOOT2
26
NC#25
25
one phase
1
2
1 2
1 2
2
2
2 1
1
1
5 6 7 8
2
FDMS7672-GP
1 R35
2 1R2F-GP
1 R34
2 10KR2F-2-GP
6266A_ISEN2_P1_VCORE DCBATOUT_6266A
one phase
R156 6266A_BOOT2 1 26266A_BOOT2_R 2D2R2J-GP
-1
2009/01/13 2
C310
5 6 7 8
DY
1 26266A_VO SCD22U10V2KX-1GP
84.08692.037 2nd = 84.01426.037
C33
1 2 SCD22U10V2KX-1GP
6266A_UGATE2
1230 modify C33,C34
6266A_PHASE2
one phase
U34 FDMS8692-GP
One phase--> C33,C34 are 63.R0034.1DL
C34 6266A_ISEN1
-1
1
one phase
C312
C11
DY
DY
C316 SCD1U50V3KX-GP
Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A
VCC_CORE
B
G59 GAP-CLOSE
1
1
TC1
CAP 2
2
2
2 G60 GAP-CLOSE
1
1
5 6 7 8
one phase
FDMS7672-GP
84.07672.037 2nd = 84.01712.037
68.R3610.20ACAP 2nd = 68.R3610.20C
4 3 2 1
del R20
TC3
L-D36UH-1-GP
2
1
LA14_SA
U36
one phase
0212
2 10R2F-L-GP C31 SC1U25V3KX-1-GP
5 6 7 8
U6 FDMS7672-GP
2
5V_S0 R25 1
2
one phase
5V_S0
1229 modify R20
DY
4 3 2 1
1
1 2 0R2J-2-GP
1
79.33719.L01 79.33719.L01 2nd = 77.C3371.051 2nd = 77.C3371.051
6266A_LGATE2 R31 1
2 0R0402-PAD
C36 SCD01U25V2KX-3GP
6266A_VSUM 6266A_ISEN2
6266A_ISEN1
Single Phase R47=1.2K, R63=5.6K,R460=0R C33=47p, C49=0.033u, C52=0.1u
R27 1 R26 1 R29 1 R28 1
one phase 2 3K65R2F-1-GP
84.07672.037 2nd = 84.01712.037 6266A_ISEN2_P2_VCORE
2 10KR2F-2-GP
one phase 2 1R2F-GP 2 10KR2F-2-GP
one phase
6266A_ISEN1_P2_VCORE
A
one phase
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
ISL6266A_CPU_CORE
DY=U7,U28,U29,L9,R62,R56,R42, R45,R37,R39,R48,C20 4
4 3 2 1
1
6266A_ISEN2 C329 SCD22U25V3KX-GP
Size A3
1013 modify R162 5
2
2 4 3 2 1
2 10KR2F-2-GP
one phase
1 2 1 2
5 6 7 8
1 R36
6266A_VO 6266A_PHASE2
1 1
FDMS7672-GP
6266A_ISEN1
SC2D2U16V3KX-GP
2
29
2
1
PGND2
1
1
6266A_LGATE2
6266A_ISEN1_P1_VCORE
2
5V_S0
R162 NTC-10K-26-GP
2
2
6266A_VSUM_R_VO
4 3 2 1
37
31 30
ISEN1
ISEN2
23 6266A_ISEN2 24
VDD
GND
22 6266A_VDD
21
VSUM
VIN 6266A_VIN 20
VO
DFB
18 1 6266A_VO 6266A_VSUM 19
6266A_DFB 17
2 3K65R2F-1-GP
4 3 2 1
VID1
38
39 VID2
VID3
40
41 VID4
42 VID5
VID0 PVCC LGATE2
R30 2K61R2F-1-GP
R32 11KR2F-L-GP
1
1 1 2
5 6 7 8
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 2 0R0402-PAD 44
43
VR_ON
VID6
45
46 DPRSTP#
DPRSLPVR
1 2
2 1 2
1 R33
6266A_VO
2
1
1 2
1 2
6266A_VO
C43 SCD033U25V3KX-GP
C45 SCD22U50V3ZY-1GP
TC2
CAP
SE330U2VDM-L-GP
6266A_VSUM
G58 GAP-CLOSE
TC20
C
6266A_VSUM C327
20081121
A
G57 GAP-CLOSE
SE330U2VDM-L-GP
SB
TC4
CAP
84.07672.037 2nd = 84.01712.037
S S S G
2 R22 1 0R0402-PAD
68.R3610.20A 2nd = 68.R3610.20C
D D D D
VSS_SENSE
6266A_ LGATE1
C29
SCD33U10V3KX-3GP
C28 SC330P50V2KX-3GP 5
33 32
R20
10R3F-GP
C41
2 R21 1 0R0402-PAD
PGND1 LGATE1
L-D36UH-1-GP
79.33719.L01 79.33719.L01 2nd = 77.C3371.051 2nd = 77.C3371.051
6266A_ LGATE1 C321 SCD22U25V3KX-GP
2
S S S G
1222 modify R21,R22
VCC_CORE
L9
R24
SCD01U25V2KX-3GP
1 VCC_SENSE
6266A_PHASE1
DCBATOUT_6266A
C37 SC180P50V2JN-1GP
C35 SC330P50V2KX-3GP
PHASE1
34
D D D D
1
DY
5
DROOP
VDIFF 6266A_VDIFF 13 POWER SB
SB 20081121
2
2 R16 1KR2J-1-GP
R18
1
2
6266A_SOFT
2 1KR2F-3-GP
2K87R2F-1-GP
R15 1
R23 1KR2F-3-GP
B
36 35
U37
SC10U25V6KX-1GP
6266A_VDIFF
RTN
FB2
6266A_RTN 15
6266A_FB2 12
16 16266A_DROOP
FB
R14 1KR2F-3-GP one phase
C32 2 6266A_FB2_R 1 2 100R2F-L1-GP-U SC2200P50V2KX-2GP
48
49 GND COMP
6266A_FB 11
D
2
SC10U25V6KX-1GP
2 SC270P50V2KX-1GP
BOOT1 UGATE1
R151 6266A_BOOT1 1 2 6266A_BOOT1_R 2D2R2J-GP 1 6266A_UGATE1
S S S G
R19 1
VW
6266A_COMP 10
84.07672.037 2nd = 84.01712.037
POWER SB
D D D D
2 6266A_COMP_R 97K6R2F-GP
C24 1
OCSET
1 U7
Id=19.5A Qg=21.5~33nC, Rdson=5.5~6.7mohm
74.06266.073
SOFT
Vcc_core Iomax=38A
L8 6266A_PHASE1
SC10U25V6KX-1GP
R17 1
2 10K5R2F-GP
ISL6266AHRZ-GP
NTC
1
1 R13 2 SC100P50V2JN-3GP
VR_TT#
2
C25 1
6266A_VR_ON 1 R144 6266A_D6 1 R143 6266A_D5 1 R139 6266A_D4 1 R138 6266A_D3 1 R146 6266A_D2 1 R142 6266A_D1 1 R137 6266A_D0 1 R136
1 2 1 2 POWER SA
RBIAS
C317 SCD1U50V3KX-GP
SE330U2VDM-L-GP
6266A_NTC 6 1 R161 26266A_NTC_R1 R155 2 NTC-470K-8-GP 4K02R2F-GP C328 C325 6266A_SOFT 7 1 2 SCD015U50V3KX-GP 1 2 SCD01U25V2KX-3GP 6266A_VO 1 8 26266A_OCSET R157 12KR3F-GP 1013 modify R161 C22 1 6266A_VW 9 2 SC1000P50V3JN-GP-U
PMON
落
DY
SE330U2VDM-L-GP
4 CPU_PROCHOT#_R
PSI#
DY
C313
SE330U2VDM-L-GP
C
PGOOD
C311
Cyntec 10*10*4 DCR=1.05+-5%mohm, Irating=30A Isat=60A
6266A_UGATE1
S S S G
2 R149 16266A_PSI# 2 C320 0R0402-PAD 3 1 2 6266A_PMON_R 1 2 6266A_PMON R150 4K99R2F-L-GP SCD1U25V3KX-GP 1 26266A_RBIAS4 R152 147KR2F-GP 5 PSI#
DY
S S S G
1
13,32 VGATE_PWRGD
C12
D D D D
R148 1K91R2F-1-GP
4
84.08692.037 2nd = 84.01426.037
U5
20080930 R154 68R2-GP
U38 FDMS8692-GP
D D D D
6266A_3V3
3D3V_S0
20081117
6266A_DPRSTP# 1 2 R140 0R0402-PAD 6266A_DPRSLPVR2 R145 1 499R2F-2-GP
1 2
R147 R147 2
2
DY
SCD1U10V2KX-4GP
1D05V_S0
1 0R2J-2-GP
1 C314
79.10712.L02 GAP-CLOSE-PWR 2nd = 79.10112.3JL
47
2 1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR G47 1 2
TC18 SE100U25VM-L1-GP
GAP-CLOSE-PWR G51 1 2
5
SC10U25V6KX-1GP
GAP-CLOSE-PWR G49 1 2
H_VID[6..0]
SC10U25V6KX-1GP
R141 10R3F-GP
SC10U25V6KX-1GP
GAP-CLOSE-PWR G54 1 2
GAP-CLOSE-PWR G50 1 2
S S S G
D
DY
TC17 ST15U25VDM-1-GP
2009/01/13
43,44
D D D D
GAP-CLOSE-PWR G52 1 2
2
3V3
1
CPUCORE_ON
CLK_EN#
2
1 1222 modify R136~140,R142~R144,R146
3D3V_S0
G48
1
1
PM_DPRSLPVR 7,13
VSEN
G53
4,7,12 H_DPRSTP#
1
DCBATOUT_6266A
1
DCBATOUT_6266A
6266A_VSEN 14
DCBATOUT
2
1
DCBATOUT_6266A
3
2
DCBATOUT
4
2
5
Document Number
Rev
3
2
SB
LA14
Date: Thursday, May 07, 2009
Sheet 1
41
of
52
5
4
3
2
1
POWER SA
GAP-CLOSE-PWR G12 1 2
GAP-CLOSE-PWR G44 1 2
GAP-CLOSE-PWR G38 1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
3 4 6
6
1
DY
GAP-CLOSE-PWR G83 1 2
S5_ENABLE 33,39,48
C521
R268 110KR3F-GP
84.27002.E3F 2N7002DW-2-GP-U
C519
R275 120KR3F-GP
LA14 SA->SB 0403 Change Q25,Q26 from 84.27002.D3F to 84.27002.E3F
1121 modify R275
SB
GAP-CLOSE-PWR G34 1 2
DY
GAP-CLOSE-PWR G31 1 2 GAP-CLOSE-PWR G32 1 2 GAP-CLOSE-PWR
1020 delete C537 for Power demand 1
DRVH1
21
51125_DRVH1
LL1
20
51125_LL1
DRVL1
19
51125_DRVL1
DRVL2
VFB2
VFB1
2
51125_FB1
TONSEL
GND
25
SKIPSEL
VCLK
18
1 DY 0R2J-2-GP C524 SC10U10V5KX-2GP
2
2
1 DY 0R2J-2-GP
5 6 7 8
1 2
1 2
S
VREG5
R273 0R2J-2-GP
DY
2
GAP-CLOSE-PWR-3-GP
R458 100KR2F-L1-GP
1013 modify TC11 and add TC12
SB 1118 delete TC12
1
1
DY
DY
1
G80
1
B
79.22710.6AL 2nd = 77.92271.021
51125_FB1_R
2
1 2 C518 SC18P50V2JN-1-GP
3D3V_S5 5V_AUX_S5
DY
C283
R270 30KR2F-GP
TPAD28
R276 100KR2J-1-GP
R266 20KR2F-L-GP
DY
2
Close to VFB Pin (pin2)
2
GAP-CLOSE-PWR-3-GP
84.04812.A37 2nd = 84.06690.E37
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
51125_VCLK
17
VREG3 2
15V_AUX_S5_51125
G79
1
G
TC11 G39
20090204
C534 SC10U10V5KX-2GP
S5_ENABLE
2
2 1
4 14
74.51125.073
R283 51125_VREF
51125_ENTIP1
GND
R261
A
51125_PGOOD
1
VREF
TPS51125RGER-GP
R264 0R0402-PAD 2 1
2
23
15
51125_SKIPSEL
3D3V_AUX_S5
51125_VREF
PGOOD ENTRIP1
2
1
51125_TONSEL
ENTRIP2
3D3V_AUX_S5_5_51125 8
51125_FB2_R C516 DYSC18P50V2JN-1-GP
C517
EN0
1
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
1 2
R262 0R2J-2-GP
2 51125_EN 13 820KR2F-GP 51125_ENTIP2 6
D D D D D D D D
5
2
1 1 2
51125_FB2
3
3D3V_AUX_S5
Close to VFB Pin (pin5)
24
2
1 2 3 4
1 2
51125_VREF SCD22U6D3V2KX-1GP
R269 10KR2F-2-GP
VO1
SCD1U10V2KX-4GP
1 R280
G
77.C2271.00L 2nd = 77.22271.27L
R265 6K65R2F-GP
VO2
68.3R310.20A 2nd = 68.3R31A.10E
D
GAP-CLOSE-PWR-3-GP
S
DY
7
SI4812BDY-T1-E3-GP
84.04812.A37 2nd = 84.06690.E37
51125_VO1
SE220U6D3VM-7GP
2
U29 51125_VO2
G S S S
SI4812BDY-T1-E3-GP
GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-15GP
SCD1U10V2KX-4GP
G42
G S S S
IND-3D3UH-57GP
D D D D
TC8
1
12
5V_PWR
2
1
LL2
51125_DRVL2 U23
Iomax=5A
L6
1
2
11
1
51125_LL2
Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A
SI4800BDY-T1
S
2
DRVH2
G
1
VBST1
10
2
DY
1
VBST2
51125_DRVH2
1
C
2
8 7 6 5
1
D
51125_VBST1
5 6 7 8
SCD1U25V3KX-GP
22
9
4 3 2 1
VIN
C529 SCD1U25V3KX-GP
DY
C294
G S S S
1 2 3 4
G
51125_VBST2
D
U28
84.04800.D37 2nd = 84.08884.037
G S S S C528 2 1
1 2
Id=7A Qg=8.7~13nC Rdson=23~30mohm
C299
4 3 2 1
2
U47
1 2 IND-3D3UH-57GP 1
16
20090204
84.04800.D37 2nd = 84.08884.037
L15
DY
1
2 8 7 6 5
2
1 2
2
1
U22 SI4800BDY-T1
C301
0113 modify U29 for Power demand
SCD01U50V2KX-1GP
51125_EN
SC10U25V6KX-1GP
D
68.3R310.20AS 2nd = 68.3R31A.10E
3D3V_PWR
Id=7A Qg=8.7~13nC Rdson=23~30mohm
DY
D D D D
SC10U25V6KX-1GP
DY
C295
DCBATOUT_51125
C533 SC10U25V6KX-1GP
1
DY
C508 SC10U25V6KX-1GP
Iomax=5A
SCD01U50V2KX-1GP
Cyntec 7*7*3 DCR=30mohm, Irating=6A Isat=13.5A
DCBATOUT_51125 R457 249KR2F-GP
0113 modify U23 for Power demand
SCD01U50V2KX-1GP
C298
D
GAP-CLOSE-PWR G36 1 2
51125_ENTIP1 84.27002.E3F 2N7002DW-2-GP-U
DCBATOUT_51125
C
2
1
51125_ENTIP1
51125_ENTIP2
20081117 DCBATOUT_51125
B
2
1
GAP-CLOSE-PWR G43 1 2
5
2
GAP-CLOSE-PWR G10 1 2
3
5
1
GAP-CLOSE-PWR G75 1 2
4
2
2
GAP-CLOSE-PWR G41 1 2
4 2 1
GAP-CLOSE-PWR G74 1 2
33,39,48 S5_ENABLE
3
2
GAP-CLOSE-PWR G35 1 2
Q26 RN59 SRN100KJ-6-GP
51125_ENTIP2
1
GAP-CLOSE-PWR G11 1 2
Q25
2
GAP-CLOSE-PWR G46 1 2
DY
落
5V_S5 G37
1
TC13 ST15U25VDM-1-GP
C287
5V_PWR
5V_AUX_S5
2
GAP-CLOSE-PWR G40 1 2
2
1
1
GAP-CLOSE-PWR G45 1 2
SC18P50V2JN-1-GP
2
3D3V_S5 G30
SC18P50V2JN-1-GP
79.68612.30L 2nd = 79.68612.L01
3D3V_PWR
1
TC30 SE68U25VM-3-GP
2
1
D
DCBATOUT_51125 G73 1 2
2
DCBATOUT
A
1 1222 modify R281 3D3V_AUX_S5
Wistron Corporation
R281 2 1 0R0402-PAD
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
R282
2
DY
Title
1 0R2J-2-GP
DCDC 5V/3D3V (TPS51125) Size A3
Document Number
Rev
5
4
3
2
SB
LA14
Date: Thursday, May 07, 2009
Sheet 1
42
of
52
5
4
3
2
DY 1 2
20081001 1
G6
1
C158 SC1U16V3KX-2GP
2
1
R76 2
PM_SLP_S3#
13,33,39,44 PM_SLP_S3#
SC10U10V5KX-2GP
SC10U10V5KX-LGP
D
5V_S5 C150
2
C151
落
1D5V_S0 Iomax=2.5A
1D8V_S3
D
1
15912_EN_U111 0R0402-PAD
1
1
GAP-CLOSE-PWR G7 2
1
GAP-CLOSE-PWR G5 2
Vo(cal.)=1.5024V
3D3V_S0
5912_POK_U111
5912_FB_U111
1
U13 RT9018A-25PSP-GP
R75 20K5R2F-GP
2
74.09018.A3D
1
C141
GAP-CLOSE-PWR
DY C148
2
1
C137
2
1 2
2
2 1 0R0402-PAD
R74 18KR2J-GP
1D5V_S0
SC10U10V5KX-LGP
R77 2
5 6 7 8
NC#5 VOUT ADJ GND
SC10U10V5KX-2GP
41,44 CPUCORE_ON
C
VDD VIN EN PGOOD
SC100P50V2JN-3GP
4 3 2 1
1
R78 2K2R2J-2-GP
GND
1
9
1D5V_LDO
2 GAP-CLOSE-PWR G8 2
C
Vo=0.8*(1+(R1/R2))
B
B
20081001
G78
1
2
1016 modify U45
1
74.09026.079
GAP-CLOSE-PWR C509 SC10U10V5KX-2GP
2
RT9026PFP-GP
11
2
C513 SC1U10V2KX-1GP
GAP-CLOSE-PWR G76 1 2
1 2 3 4 5 1
VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS GND
9026_S3
2
10 9 8 7 6
9026_S5
1
DDR_VREF_S3_1
R267 2 1 0R0402-PAD R263 2 1 0R0402-PAD
2
GAP-CLOSE-PWR G77 1 2
U45
13,33,44 PM_SLP_S4#
DDR_VREF_S3
DDR_VREF_PWR
C523 SCD1U10V2KX-4GP
1
2
1
C522 SC10U10V5KX-2GP
2
C520 SC1U10V3KX-3GP
Iomax=1A OCP>2A
1D8V_S3
1
5V_S5
C512 SC10U10V5KX-2GP
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3
Document Number
Date: Thursday, May 07, 2009 5
4
3
2
1D5V & 0D9V
Rev
SB
LA14 Sheet 1
43
of
52
5
4
3
2
1
1D8V_S3 1D8V_PWR
1
DY DCBATOUT_51124
TC29 SE68U25VM-3-GP
1 6
2
84.01712.037 2nd = 84.07672.037
2
R289 30KR2F-GP
2 1 2
1
2 1
DY
GAP-CLOSE-PWR G16 1 2 GAP-CLOSE-PWR G13 1 2
2 1
1128 add TC25 DY
Vout=0.758V*(R1+R2)/R2 --> PWM mode Vout=0.764V*(R1+R2)/R2 --> Skip Mode
1017 add TC25
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
TPS51124_1D8V_1D05V Size A3
Document Number
Rev
2
SB
LA14
Date: Thursday, May 07, 2009 3
GAP-CLOSE-PWR G66 1 2 GAP-CLOSE-PWR
TC25
79.3971V.6AL 2nd = 79.3971V.E0L
GAP-CLOSE-PWR G14 1 2 GAP-CLOSE-PWR G15 1 2
20081117 SE390U2D5VM-2GP
SB
4
TC9
1D05V Iomax=14A OCP>24A
360k/CH1 420k/CH2
B
GAP-CLOSE-PWR G17 1 2
V5FILT
A
5
GAP-CLOSE-PWR G64 1 2
77.23371.13L 2nd = 77.C3371.10L
1127 modify U27
2
300k/CH1 360k/CH2
1
C284
1D05V_S0
240k/CH1 300k/CH2
GAP-CLOSE-PWR G63 1 2
2
C536
1
1
51124_VFB2
4 3 2 1
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
2
U27 AOL1712-GP
DY 2
5 6 7 8 R287 0R2J-2-GP
SB OPEN
R286 11K8R2F-GP
2
GAP-CLOSE-PWR G62 1 2
1121 modify L16,R2861D05V_PWR 1
SB
1
1
10KR2J-3-GP
51124_VBST2
DY
1D05V_S0
1
2 1
L16
2
DY R288
1
2
51124_VBST1
51124_V5FILT
TONSEL
1
2 2 1
4 3 2 1
2
1
24 7 PGOOD1 PGOOD2
TONSEL
5 6 7 8
Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A 1 2 IND-D88UH-GP
SCD1U16V2KX-3GP
GND
GAP-CLOSE-PWR
1
ST330U2D5VDM-9GP
C526 1
84.01426.037 2nd = 84.08692.037
Id=7A Qg=8.7~13nC Rdson=23~30mohm
S S S G
2
GAP-CLOSE-PWR G23 1 2
C296
SC10U25V6KX-1GPDY
DY
2nd = 68.R8810.10B
SCD1U16V2KX-3GP 51124_LL2
TPS51124RGER-GPU1
C514 SC10U25V6KX-1GP
SCD1U10V2KX-4GP
2
C510
D D D D
51124_LL1
C527 1
C
G65
SC18P50V2JN-1-GP
Modify 0429 R271 change to 64.95315.55L
2
9K53R3F-2-GP
1121 modify R271,R272
U26 AOL1426-GP
4 3 2 1
17 14 1
1
R272 10KR2F-2-GP
2
SB
51124_DRVH2 51124_LL2 51124_DRVL2
10 11 12
51124_TONSEL
R271
GAP-CLOSE-PWR G24 1 2
20081117
74.51124.073
51124_TRIP1 51124_TRIP2
B
79.33719.20D 2nd = 77.C3371.10L
1013 modify TC10 and add TC26
S S S G
BC1 SCD47U6D3V2KX-GP
2
GAP-CLOSE-PWR G27 1 2
1D8V Iomax=10A OCP>15A
Id=7.7A Qg=8.5~13nC Rdson=16.5~21mohm
51124_DRVH1 51124_LL1 51124_DRVL1
21 20 19
GAP-CLOSE-PWR G29 1 2
1D05V_PWR
DRVH2 LL2 DRVL2
4
GND GND PGND2 PGND1
DRVH1 LL1 DRVL1
DY
GAP-CLOSE-PWR G26 1 2
TC10
DCBATOUT_51124
VBST1 VBST2
EN1 EN2
3 25 13 18
SC1000P50V3JN-GP-U
D D D D
DY1
VO1 VO2
VFB1 VFB2 23 8
TRIP1 TRIP2
51124_EN1 51124_EN2
22 9
V5FILT V5IN
2 R277 1 0R0402-PAD
1222 modify R277,R278
2 5
1 2
15 16
C532
R290 21K5R3F-GP
GAP-CLOSE-PWR G18 1 2
SCD1U50V3KX-GP
51124_V5FILT
5 6 7 8
1 51124RGER_PG1 51124RGER_PG2
1 1 2
2
C300 SC1U10V3KX-3GPU46
51124_VFB1
84.04168.037 2nd = 84.08672.A37
1
R284 0R0402-PAD
GAP-CLOSE-PWR G20 1 2
ST330U2VDM-3GP
BC2 SCD47U6D3V2KX-GP
2
2
DY
C282 SCD1U10V2KX-4GP
2 R278 1 0R0402-PAD
1D05V_PWR 1D8V_PWR 51124_VFB2 51124_VFB1
S S S G
C
U25 SI4168DY-T1-GE3-GP
SC18P50V2JN-1-GP
R274 3D3R3J-L-GP
R285 30KR2F-GP
D D D D
C525 SC4D7U10V5KX-1GP
DY
C535
2
2
1 2 IND-1D5UH-34-GP
1
41,43
C531 SC1000P50V3JN-GP-U
GAP-CLOSE-PWR G19 1 2
1D8V_PWR
68.1R510.10J 2nd = 68.1R51A.10A
L17
1
G S S S
Id=7A Qg=8.7~13nC Rdson=23~30mohm
CPUCORE_ON
5V_S5
1
GAP-CLOSE-PWR G22 1 2
C297
DY
Cyntec 10*10*4 DCR=4.2mohm, Irating=16A Isat=33A
2
2008/06/16 R279 0R0402-PAD 2 1
GAP-CLOSE-PWR
13,33,39,43 PM_SLP_S3#
D
DY
84.04800.D37 2nd = 84.08884.037
0204 modify these symbol of C531and C532
落
GAP-CLOSE-PWR G21 1 2
C515 SC10U25V6KX-1GP
1M
20081117
GAP-CLOSE-PWR G72 1 2
DY1
C511 SC10U25V6KX-1GP
1
1
5 6 7 8
2
GAP-CLOSE-PWR G70 1 2
U24 SI4800BDY-T1
D D D D
79.68612.30L 2nd = 79.68612.L01
2
GAP-CLOSE-PWR G25 1 2
SCD1U50V3KX-GP
GAP-CLOSE-PWR G67 1 2
13,33,43 PM_SLP_S4#
1
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
GAP-CLOSE-PWR G68 1 2
4 3 2 1
2
TC28 ST15U25VDM-3-GP
79.3971V.6AL 2nd = 79.3971V.E0L
1
2
DY
D
1
GAP-CLOSE-PWR G69 1 2
2
Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))
2
TC26 SE390U2D5VM-2GP
SB 1128 add TC26
G71
1
1D8V_S3 G28
DCBATOUT_51124
2
DCBATOUT
Sheet 1
44
of
52
A
B
C
D
E
Adaptor in to generate DCBATOUT
DC1
AD+
SB 1121 add the part(EC88) for EMI demand
GND
5 6 4 1 2 3 NP1
1
R1
1
AD_OFF
1
84.04433.A37 2nd = 84.04407.F37
1013 modify U2 3 R6 100KR2J-1-GP 2
2 R2 DTC124EUB-GP
4
2
1
C10 SC1U50V5ZY-1-GP
84.00124.T1K 2nd = 84.00124.N1K 3rd = 84.00124.K1K
3
8 7 6 5
2
DTA124EUB-GP
Q4
D D D D
1
AD_OFF#_JK
SB 1125 add the part(EC91) for EMI demand
33
R7 200KR2F-L-GP
Q3
U2 S S S G AO4433-GP
2
1
K
1 2 3 4
AD+_2
A
2
DY
C5 D1 SCD1U50V3ZY-GP P6SMBJ20A-GP 83.P6SMB.AAG 2nd = 83.P6SBM.AAG
2
1
1 2
2 1
DY
SCD1U25V2ZY-1GP
1022 modify DC1
EC91
SCD1U25V2ZY-1GP
22.10037.H31
EC88
R1
EC11 SCD1U50V3KX-GP
DC-JACK163-GP
R2
4
落
AD_JK
1016 modify Q3
1016 modify Q4 3
3
84.00124.S1K 2nd = 84.00124.M1K 3rd = 84.00124.H1K
LA_SA 0216 Change DC1 from 22.10037.F11 to 22.10037.H31
BATA_SDA_1 48 BATA_SCL_1 48 BAT_IN#_1 48
BATTERY CONNECTOR SB 1127 modify BAT1 BAT1
1M
Modify 0506 SB->SC Add EC50,EC51 and EC52.
2
0204 modify these symbol of EC52 and EC53
2
9 8 7 6 5 4 3 2 1
RN4 1 2 3 4
33,46 BAT_SDA 33,46 BAT_SCL 33 BAT_IN#
8 7 6 5
BATA_SDA_1 BATA_SCL_1 BAT_IN#_1
1
1
2
EC50 EC51
2
1 2
1 2
2
1
1
2
2
2
1
1 2
K A
DY
SC1000P50V3JN-GP-U
DY
EL2
SC1000P50V3JN-GP-U
DY
EL1
MLVS0402M04-GP
EC52 SC1000P50V3JN-GP-U
MMPZ5232BPT-GP-U
1
EC53 SC1000P50V3JN-GP-U
DY
EC14
EL3
MLVS0402M04-GP
EC13 SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
D2
SB
MLVS0402M04-GP
SB
1
SRN33J-7-GP
BT+
GND GND GND GND DAT CLK BAT_IN BT+2 BT+1
SYN-CON7-40-GP
20.81171.007 2nd = 20.81179.007
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
46 BATT_SENSE
R8 1 2 0R0402-PAD
Title
AD/BATT CONN
Size
1119 modify EC52 and EL3
Document Number
Date: Thursday, May 07, 2009 A
B
Rev
SB
LA14 C
D
Sheet
45
of E
52
1
5
4
3
2
1
1013 modify U3 DCBATOUT
R11 100KR2J-1-GP
1 2
2
2
1
G S S S
2
VICM
1
SI4800BDY-T1
SCD1U50V3KX-GP
16
VFB
15
BQ24745RHDR-GP
BATT_SENSE
BATT_SENSE 45
1 2
1
1
MAX8731A_CSIN
Q20
A
SRN100KJ-8-GP-U
BQ24745_CHG_ON
3
4
AC_OK
2
5
1
6 84.27002.E3F 2N7002DW-2-GP-U
1 2
1 2
1 2
C398
1 1230 Add C393,C398
CHG_ON#
CHG_ON#
AC_IN#
1
2
C345 SCD1U10V2KX-4GP
1
DY
LA14 SA->SB 0403 Change Q20 from 84.27002.D3F to 84.27002.E3F
AC_IN#
C339 SC1U10V3KX-3GP
A
33 33
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
AC_IN# to KBC Title
2
3D3V_AUX_S5
AC_OK CHG_ON# AC_IN# BQ24745_CHG_ON
BQ24745 Charger Size A3
Document Number
Date: Thursday, May 07, 2009 5
4
3
B
SC10U25V6KX-1GP
CHG_AGND RN43
C393 SC10U25V6KX-1GP
CHG_AGND BQ24745_VREF
8 7 6 5
C318
20081230 R163 1 2 0R0402-PAD
CHG_AGND
1 2 3 4
C18
C364 SCD1U25V2ZY-1GP
2
74.24745.073
C19
MAX8731A_CSIP
1
NC#16
1
C338 SC1U10V3KX-3GP
FBO EAI EAO VREF CE GND
GND
6 BQ24745_EAI 5 BQ24745_EAO 4 BQ24745_VREF 3 BQ24745_CHG_ON 7 12
29
1 2 C341 SC56P50V2JN-2GP
1
C337 R167 SC2200P50V2KX-2GP 7K5R2F-1-GP 2 1BQ24745_EAO_RC2 1
2
C348 SC220P50V2KX-3GP
8
R166 1 2BQ24745_FBO 4K7R2J-2-GP
2
1
2 BQ24745_FBO_RC R171 1 2 200KR2F-L-GP
C322
2
SC150P50V2JN-3GP
84.04800.D37 2nd = 84.08884.037
C365
C323
1
17
G55
2
18
G56
4 3 2 1
CHG_AGND BQ24745_IINP
68.5R610.10I 2nd = 68.5R610.201
SCD1U50V3KX-GP
CSOP CSON
U39
SC10U25V6KX-1GP
CHG_AGND
NC#14
SC10U25V6KX-1GP
14
2
D01R2512F-4-GP
SC10U25V6KX-1GP
19
24745_LOW_G
BT+_R
2 IND-5D6UH-32-GP
SC10U25V6KX-1GP
PGND
1
R160 1
GAP-CLOSE-PWR
20
BQ24745_LX1
GAP-CLOSE-PWR
LGATE
BT+ L7
1 2 C351 SCD1U50V3KX-GP
D D D D
CHG_AGND
SI4800BDY-T1
1
23
C
DY
2
SCL PHASE
DY
83.R0203.08F 2nd = 83.R2003.A8M 24745_HIGH_G
ACOK
SDA
2
CH520S-30PT-GP SC1U10V3KX-3GP
2
24
2
UGATE
BQ24745_BST BQ24745_VDDP
C367 1
A
2
1 5 6 7 8
25 21
D12
K
D D D D
BOOT VDDP
BQ24745_CSSN TP47
G S S S
27 26
DY
4 3 2 1
VDDSMB
U32
C319 SCD1U25V2ZY-1GP
1
9
CSSN ICOUT
ACIN
84.04800.D37 2nd = 84.08884.037
C17
2
33,45 BAT_SDA
28
C331
2
10
CSSP
C315
1
1
C350 SC1U10V3KX-3GP 33,45 BAT_SCL
SCD1U25V3KX-GP CHG_AGND
2
AC_OK
2
R183 1 2BQ24745_ACOK 13 0R0402-PAD
DCIN
C344 SCD1U50V3KX-GP
5 6 7 8
2 11
1
DCBATOUT
2
1
1
BQ24745_ACIN
22
1
SC10U25V6KX-1GP
U41
1
2
K 1
SCD1U50V3KX-GP CHG_AGND
2
SC10U25V6KX-1GP
2
2
2
1
3 4
5
6
GAP-CLOSE-PWR
C347 C340 2 1 BQ24745_CSSP
3D3V_AUX_S5
C336 1
D
POWER SB
BQ24745_DCIN
AD_IA
8 7 6 5
84.04433.A37 2nd = 84.04407.F37
SC10U25V6KX-1GP
SC1U25V5KX-1GP
AC_OK C
33
D D D D
R153 470KR2J-2-GP
C358
R164 309KR3F-GP
2
GAP-CLOSE-PWR
83.00400.C1F 2nd = 83.1S400.A2F
G4
AD+
Q2
1
G3
1
2
A
1016 modify D13
2
1
C324 SCD1U25V2ZY-1GP
D13 1SS400GPT-GP
2N7002DW-2-GP-U 84.27002.E3F
B
BT+
AO4433-GP AD+
C342 SCD01U50V2KX-1GP
U31 S S S G
1
1 2
AD+
20080605
DC_IN_D
R172 1 2 0R0402-PAD
1 2 3 4
LA14 SA->SB 0403 Change Q2 from 84.27002.D3F to 84.27002.E3F
R12 49K9R2F-L-GP
1
2
D01R2512F-4-GP AD+_G_2
AD+_G_1
R169 49K9R2F-L-GP
R9 1
AD+_TO_SYS
2
84.04433.A37 2nd = 84.04407.F37
R10 10KR2F-2-GP
1013 modify U31
DCBATOUT
AO4433-GP
D
落
EC54 SCD1U50V3KX-GP
1 1 2 3 4
ICREF
U3 S S S G
D D D D
1
8 7 6 5
2
NEAR
AD+
2
Rev
SB
LA14 Sheet 1
46
of
52
5
4
5V_S0
3
2
5V_S0
1
1020 delete TC14,TC15
13
9
8
12
11
7
7
TSAHCT125PW-GP
2
U8D TSAHCT125PW-GP
D
73.74125.L13 2nd = 73.74125.L12
73.74125.L13 2nd = 73.74125.L12
TC24
1117 delete TC19
SE100U25VM-L1-GP
U8C
落
SB 1
14
10
14
DCBATOUT
D
79.10712.L02 2nd = 79.10112.3JL
1016 modify U32 1017 add these parts(EC10,EC12,EC15~EC17,EC86) for EMI demand SB
1020 add the part(EC86) for EMI demand
1125 add the part(EC90) for EMI demand
1121 add the part(EC89) for EMI demand
1128 add EC94,EC95 for EMI demand 1D8V_S3
2
2
2
1
1
2
1
1
1
1 2
2
DY
SCD1U25V2ZY-1GP
DY
EC86
EC95
SCD1U25V2ZY-1GP
2
EC94
SCD1U25V2ZY-1GP
DY
EC90
SCD1U25V2ZY-1GP
2
EC89
SCD1U25V2ZY-1GP
DY
EC16
SCD1U25V2ZY-1GP
2
EC17
SCD1U25V2ZY-1GP
2
EC10
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY
C
EC12
SCD1U25V2ZY-1GP
EC15
1
1
1
1
DCBATOUT
DY
C
Modify 0506 SB->SC Add EC89 and EC90 for EMI demand 1016 add GND1 and GND2 for EMI demand 1017 add GND3 and modify GND2 for EMI demand
LA14 SA->SB 0401 DY GND9 0402 Del GND4,GND7,GND8,GND9
CPU
ZZ.00PAD.D11
GND2 SPRING-51-GP
34.4F822.002
GND3 SPRING-9-GP
34.49U23.001
GND9 SPRING-9-GP
34.49U23.001
1
1
1
1 ZZ.00PAD.D11
B
34.4B312.002
1
GND1 SPRING-58-GP
1
TOP
H38 HOLE256R115-GP
1
H37 HOLE256R115-GP
1
H35 H36 HOLE256R115-GP HOLE256R115-GP
ZZ.00PAD.D11
ZZ.00PAD.D11
B
LA14 SB 0402 modify H35~H36 1016 modify H31 and H32
1016 modify H35~H38 1016 delete H9~H12
Modify 0506 SB->SC Add GND9 for EMI demand
SB 1128 Add GND4,GND7,GND8
SB 1120 remove H31and H32
1 1230 Add GND9
H29
ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX ZZ.0HOLE.XXX
ZZ.00PAD.571
ZZ.00PAD.571
H17
ZZ.0HOLE.XXX
H43
A
Wistron Corporation
1
ZZ.00PAD.571
ZZ.0HOLE.XXX
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
LA14 SA->SB 0401 DY H8 0402 Del H8
1
H8
1
1
1
1
1
1
1
1
ZZ.00PAD.571
H7
HOLE512X512R111-S-GP
ZZ.00PAD.571
H6
HOLE355X355R111-S1-GP
ZZ.00PAD.571
H5
HOLE355X355R111-S1-GP
ZZ.00PAD.571
H4
HOLE355X355R111-S1-GP
ZZ.00PAD.571
H3
HOLE355X355R111-S1-GP
H2
HOLE355X355R111-S1-GP
ZZ.00PAD.571
HOLE355X355R111-S1-GP
H1
HOLE355X355R111-S1-GP
HOLE355X355R111-S1-GP
A
H30
1
H28
1
1
H27
1
H26
1
H24
1
H23
1
H22
1
H21
1
H20
1
H19
1
H18
1
LA_SA 0218 Change H35~H38 from ZZ.00PAD.571 to ZZ.00PAD.801
Title
SB 1128 Add H43
Size
EMI/Spring/Boss
Document Number
Date: Thursday, May 07, 2009 5
4
Rev
SB
LA14 3
2
Sheet 1
47
of
52
5
4
3
1 1 1 1
SPKR_R+ SPKR_RSPKR_L+ SPKR_L-
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
5V_S0
TP244 TP243 TP245 TP246
38
3D3V_S0
Touch pad 35 35 35,37 35,37
TP_DATA TP_CLK TP_RIGHT TP_LEFT
WLAN_LED#_R
36 NOVO_BT# 36 WIRELESS_BTN#_1 36 CAP_LED#_R 36 NUM_LED#_R 38 HDD_LED#_R
D
5V_S0
1
LED
Speaker 27,28 27,28 27,28 27,28
2
1 1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP109 TP105 TP110 TP114 TP113
36 KBC_PWRBTN#_1
1
AFTE14P-GP
TP88
1
AFTE14P-GP
TP229
1 1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP230 TP231 TP91 TP90 TP234
1
AFTE14P-GP
TP253
1
AFTE14P-GP
TP254
Battery
KCOL16 KCOL15 KCOL14 KCOL13
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP127 TP139 TP148 TP146
33 33 33 33
KCOL8 KCOL7 KCOL6 KCOL5
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP98 TP99 TP101 TP100
KCOL4 KCOL3 KCOL2 KCOL1
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP118 TP138 TP122 TP123
D
SB 1112 remove the signal( STDBY_LED#_R)
45 45 45
Keyboard 33 33 33 33
落
BATA_SDA_1 BATA_SCL_1 BAT_IN#_1 BT+ BT+ AD_JK
1 1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP16 TP17 TP15 TP14 TP13
1 1
AFTE14P-GP AFTE14P-GP
TP6 TP5
C
C
Check test point 1
AFTE14P-GP
TP237
1
AFTE14P-GP
TP240
3D3V_S5
1
AFTE14P-GP
TP236
5V_S5
1
AFTE14P-GP
TP238
4,12,39 H_PWRGD
1
AFTE14P-GP
TP241
33,39,42 S5_ENABLE
1
AFTE14P-GP
TP242
1
AFTE14P-GP
TP239
3D3V_S0 33 33 33 33
33 33 33 33
KROW0 KROW7 KROW6 KROW5
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
3D3V_AUX_S5
TP152 TP154 TP153 TP151
4,6 B
33 33 33 33
KROW4 KROW3 KROW2 KROW1
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP94 TP95 TP92 TP97
33 33 33 33
KCOL12 KCOL11 KCOL10 KCOL9
1 1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
TP260 TP116 TP117 TP102
33 33
KCOL17 KCOL0
1 1
AFTE14P-GP AFTE14P-GP
TP72 TP87
H_CPURST#
B
Test Point放在Dimm Door打開可量測處
FAN
Bluetooth A
22 22 22
USB_7USB_7+ 3D3V_BT_S0
1 1 1
AFTE14P-GP AFTE14P-GP AFTE14P-GP
32 EMC2102_FAN_TACH
1
AFTE14P-GP
TP187
32 EMC2102_FAN_DRIVE
1
AFTE14P-GP
TP188
TP134 TP136 TP133
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1017 modify USB signal connection
Size
AFTE test point
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet
48
of 1
52
A
5
4
3
2
1
落
0910 delete F4(Page 18) 0910 update footprint of U15(Page 30) 0910 delete RIGHT1 and LEFT1(Page 33) 0910 modify net names of TP_LEFT and TP_RIGHT(Page 36) 0910 modify
test points of AFTE and TPAD
D
D
0911 modify net name from LPC_RST to PLT_RST1#(Page 24) 0911 add net name(RBIAS,LED_DUPLEX#,SMDATA,SMCLK)(Page 24) 0911 add net name(DVDD_1_8,ACZ_SDATAIN0_R,FLY_P,FLY_N,VREF_LO,VREF_HI)(Page 26) 0911 add net name(EAPD#_R)(Page 27) 0912 modify the schematic of Page 33 0912 delete GMCH_TXB*(Page 7& 18) 0912 add these parts for EMI demand(page 7,18,20,21,23,26,28,29,30,32,33,34,35) 0915 modify
net name from 10M/100M/1G_LED# to 10M/100M_LED#(page24,25)
0915 delete these parts for EMI demand(page 30) 0915 add EC34 for EMI demand(page3) 0915 add EC73 for EMI demand(page 12) 0915 modify LEDs port 0916 move net(SPI_WP#) from U9 pin120 to pin25(page33) 0930 modify BLUE1(page22) C
0930 add 2nd for SPK1, MIC1 and modify LOUT1 (page28) 0930 modify
FAN1(page32)
0930 modify
TPAD1(page35)
0930 modify
KB1(page33)
C
0930 modify net name for BIOS demand(page33) 1001 delete these parts for EMI demand(ED1~8) 1009 modify net name for GND to AGND(page27) 1009 add R4,R5 for AC decopling(page27) 1009 add R96(page30) 1013 modify
TPAD1(page35)
1013 modify U40 from 72.25X16.001 to 72.25X16.A01(page 34) 1013 modify TC11 and add TC12(page42) 1013 modify TC10 and add TC26(page44) 1013 modify U2(page45) B
1013 modify U3 and U31(page 46)
B
1013 modify R161 and R162(page41) 1013 modify card1(page 30) 1014 modify these LEDs(LED11,LED12)(page38) 1014 modify these nets(page 26) 1014 modify R258 from 10k to 20k ohm(page26) 1014 add ER5 for EMI deamnd(page3) 1015 modify LCD1 pin define(page 18) 1015 modify the power from 3D3V_S5 to 5V_S5(page38) 1015 modify TPAD1(page35) 1015 modify RN57(page28) 1015 modify F1(page18)
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Change List
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
49
of
52
5
4
3
2
1
1016 modify L1,L2 and L3(page 19) 1016 modify XF1(page 25)
落
1016 modify RN53 and U10(page 24) 1016 modify U8(page19,47) 1016 modify U4(page 37) 1016 modify U23(page 43) D
1016 modify X2(page12)
D
1016 modify X1(page 33) 1016 modify X3(page 3) 1016 modify D13(page 46) 1016 modify D23(page 20) 1016 modify D9(page 39) 1016 modify D4(page 19) 1016 modify Q3 and Q4(page45) 1016 modify Q18(page 36) 1016 modify Q15~Q17(page 36) 1016 modify Q27~Q30(page38) 1016 modify Q6 and Q14(page 32) 1016 modify Q8(PAGE 24) 1016 add GND1 nad GND2 for EMI demand(page 47) C
1016 modify LCD1 pin define(page 18)
C
1016 delete H9~H12 and modify H35~H38,H31,H32(page 47) 1017 add these parts for EMI demand(page 47) 1017 delete these parts(EC208~EC210)(page 7) 1017 modify BLUE1(page 22) 1017 modify FAN1(page 32) 1017 modify R291 and R293(page 38) 1017 add U61,R52,EC23 and EC24(page 37) 1017 modify RN60(page37) 1017 add TC25(page 44) 1017 add GND3 and modify GND2 for EMI demand(page 47) 1017 modify USB signal connection(page13,18,22,23,30,31,48) 1020 delete C537 for Power demand(page42) 1020 add the part(EC86) for EMI demand(page 47) 1020 delete U61,R52,EC24 and EC23(page 37) B
B
1020 delete TC14,TC15(page 47) 1021 modify TC16(page 31) 1021 delete TC23(page 23) 1021 modify TC5(page 20) 1021 modify and swap these parts(USB1 and USB2)(page 23) 1021 modify SATA1(page 20) 1022 modify DC1(page 45)
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
Change List
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
50
of
52
5
4
3
2
1
SA to SB 1127 modify C377(page32) for
thermal function
1106 modify net connection of RN46 and RN44(page33) for layout demand
1128 Add H43,GND4,GND7,GND8(page47) for EMI demand
1106 modify LED11 and LED12(page38) for fixing issue
1128 modify LCD1(page18) for cost down
1106 modify LED power from 5V_S5 to 5V_AUX_S5(page38) for customer demand
1128 Add L19(page24) for vender demand
1112 remove the signal(STDBY_LED#_FR)page38 for customer demand
1128 add EC94,EC95 for EMI demand(page47)
1112 remove these signals( STDBY_LED#_FR and STDBY_LED#_R) and R131(page36) for customer demand
1201 modify C3 (page18)
1112 remove the signal( STDBY_LED#_R)page36 for customer demand
1201 modify EC6~9(page28)
1112 remove the signal( STDBY_LED#_R)and TP253(page48) for customer demand
1204 modify RN36
1113 modify
1204 modify second source of RJ1
落
D
D
C103 and C106(page24) for crystal issue
1113 modify 2nd of U19(page26) 1113 modify 2nd of U43(page39) 1113 modify 2nd of U44(page10) 1113 modify U48(page22) 1117 delete MDC function(R231,R237,R232,R234)(page12) 1117 delete TC19(page 47) for ME deamnd 1118 modify PCB Ver. from SA to SB(page33) 1118 delete TC12(page42) for layout demand 1118 delete TC27(page9) for layout demand 1118 delete R107 and add L18 for cost down 1119 modify R130 and R133(page 36) for LED brightness C
1119 modify EC52 and EL3(page45) for EMI demand
C
1119 modify SPK1(page 28) for ME deamnd 1119 add G84
for RTC reset demand
1120 modify EC78for EMI demand((page10) 1120 modify PowerCN1 pin3 and remove EC44(page36) fro LED function 1120 remove H31 and H32(page47)for ME demand 1120 add RN61 and RN62(page3) for layout demand 1120 swap these nets(CLK_MCH_3GPLL,CLK_MCH_3GPLL#, CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 add the net( SATACLKREQ#)(page3,13)for CLK REQ demand 1120 move these nets (CLK_PCIE_MINI1,CLK_PCIE_MINI1#)(page3)for CLK REQ demand 1120 modify RN61 and RN62(page3)for CLK REQ demand 1121 add EC87 for EMI demand(page18) 1121 add the part(EC89) for EMI demand(page47) 1121 add the part(EC88) for EMI demand(page45) B
1121 modify R18,C43(page41) for Power demand
B
1121 modify R275(page42)for Power demand 1121 modify R271,R272,R286 and L16(page44) for Power demand 1124 modify U42 and delete R182,R185 (page32) for thermal function 1124 modify these names of these nets(G7922_SGND2,G7922_SGND3...) (page32) for thermal function 1124 add R302(page3) for clock gen function 1125 add the part(EC90) for EMI demand(page47) 1125 add the part(EC91) for EMI demand(page45) 1125 modify R125,R126(page18) for LCD brightness control 1125 modify RN40 and delete RN42(page32) for layout demand 1125 add EC92 and EC93 for EMI demand(page 22) 1126 add these nets (PCIE_REQ_LAN#,PCIE_REQ_MINI#)(page3)for CLK REQ demand 1126 delete R230,R233,R235,R236 and RN63(page12) for removing MDC function 1126 add C541 and modify R101(page26) for codec function 1126 modify RN61 and RN62(page3) for layout demand A
A
1126 modify EU1,EU2 and add EU3,EU4 for EMI demand(page28) 1127 modify CRT1(page19) for customer demand
Wistron Corporation
1127 swap the nets of
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
RN61 and RN62 for layout demand(page3) Title
1127 modify BAT1(page45) for ME demand 1127 modify U27(page44) for power demand
Size
Change List
Document Number
Rev
SB
LA14 Date: Thursday, May 07, 2009 5
4
3
2
Sheet 1
51
of
52
5
4
SB to 1
D
3
2
1
0 ohm to short pad
1222 modify U42 for customer demand(page32)
1222 modify R277,R278(page44)
1222 modify these names of nets (BMC2102_DN2,DP2,DN3,DP3,PWROK,FAN_TACH,FAN_DRIVE)(page32)
1222 modify R135,R5(page27)
1222 modify RN58 from 68 to 56 ohm for customer demand(page28)
1222 modify R58(page25)
1222 modify PCB Ver. from SB to -1(page33)
1222 modify R136~140,R142~R144,R146,R149(page41)
1222 modify TC5 for HDD side(page20)
1222 modify R21,R22(page41)
1222 modify card1 from 20.I0043.001 to 20.I0043.011for CE demand(PAGE30)
1222 modify R80,R87(page3)
1223 modify the net(EMC2102_CLK_SEL) for reducing component (page32)
1222 modify R252(page10)
1223 modify the net(RSMRST#) for reducing component(page33)
1222 modify R209(page13)
1224 dummy C6(page27)
1222 modify R68,R69,R79(page24)
1224 add R306 for FSB Dynamic ODT(dummy)(page7)
1222 modify R97(page30)
1224 add R307 and R308 for LAN co-layout demand(page24)
1222 modify R159(page31)
1224 modify FAN1for CE demand(page32)
1222 modify R189(page33)
1224 remove R113 for reducing component (page39)
1222 modify R281(page42)
1224 modify RN54 for reducing component (page12)
1222 modify ER1~ER4(page28)
1224 modify R191,RN48 and this net AD_OFF for reducing component (page33)
1224 modify R91(page3)
1224 modify D5(dummy)(page20)
1224 modify R67,R71(page24)
1224 delete R165 and add RN64 for reducing component (page32)
1224 modify ERN2(page34)
落 D
1226 modify TP_L1 and TP_R1 for ME demand(page37) 1226 modify R100 and C240(dummy)(page30) C
1226 delete R96 for reducing component (page30)
C
1229 modify C76,C77 from 12pF to 15pF for vender demand(page12) 1229 modify L19 for vender demand(page24) 1229 modify U30 for cost down(page18) 1229 modify U44 for cost down(page10) 1229 modify R20 for power team demand(page41) 1230 modify the name of net(RST#_CHIP)(beacuse R97 was removed)(page30) 1230 modify ODD1 for CE demand(page21) 1230 modify C33,C34 for power team demand (page41) 1230 modify D14 for CE demand(page33) 1230 Add C393,C398 for power team demand(page46) 1230 Add GND9 for EMI demand(page47) 1230 dummy C507(page26) 1230 delete Q1 and modify U1 for new AMP IC(page27) 1230 delete RN35 and add R309(page27) B
B
1231 modify R80 for clock gen voltage(3.3V to 1.05V) (page3) 1231 modify ODD1 for ME demand(page21) 0105 modify R3,R128,R129,R130,R132 and R133 for LED brightness conrtol(page36) 0105 modify R291,R292,R293 and R294 for LED brightness conrtol (page38) 0105 modify L1,L2 and L3 for EMI demand(page19) 0112 modify TC10(page44) 0113 modify ODD1 for ME demand(page21) 0113 modify U34,U38,U6,U7,U36 and U37 for power demand(page41) 0113 modify U23 and U29 for power demand(page42) 0113 modify U25,U27,TC10 and L16 for power demand(page44) 1 to 1M
0121 modify PCB Ver. from 1 to 1M(page33) 0121 add R310(page26) A
0204 add R457,R458 for power demand(co-layout)(page42)
A
0204 modify R130,R132 and R133 for LED brightness conrtol(page36)
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
0204 modify KB1 for CE demand(add mylar)(page33) 0204 modify the symbol of C22 (page41)
Title
0204 modify these symbol of C531and C532 (page44) Size
0204 modify these symbol of EC52 and EC53 (page45)
Rev
SB
LA14
0204 modify the symbol of EC74 (page23) 5
Change List
Document Number
Date: Thursday, May 07, 2009 4
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2
Sheet 1
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