Lab 2: Getting Started With Magic

Transcript

Lab 2: Getting Started with Magic Developed by: Basawaraj Last Modified Apr., 2011 Requirements: Before starting this lab please read the following documents from the tutorial section of Magic: http://opencircuitdesign.com/magic/archive/papers/tut1.pdf http://opencircuitdesign.com/magic/archive/papers/tut2.pdf These pages provide a short introduction to the options available and also the mouse usage guidelines. The complete documentation for Magic is available at: http://opencircuitdesign.com/magic/magic_docs.html INTRODUCTION: This lab will illustrate the process of layout design. In this lab we will draw the layout of a simple 2 input NAND gate, that you can use as a cell in your later designs. This lab will cover: 1. Starting Magic 2. Draw PMOS in NWELL 3. Draw NMOS 4. Interconnects and Labeling 5. Circuit extraction and IRSIM simulation Starting Magic: 1. To launch Magic, run the following command in the terminal window. magic nand This launches magic. Two windows pop up. The cell “nand” is opened for editing in the layout window, Figure 1a, and a console window (tkcon) for entering text commands, Figure 1b. Figure 1a Figure 1b 2. To see the toolbar enter, Options-> Toolbar, on the layout window. 3. To zoom in click the small square on the bottom left corner of the layout window with the left mouse button and to zoom out click on this with the right mouse button. 4. To see the grid lines on the layout window run the following command in the console window. grid Draw PMOS in NWELL: For this class we assume that the circuits are designed using an NWELL process, that is the substrate is p-type. MOS transistors have to be fabricated in a well of the opposite type, i.e. PMOS in an n-substrate and NMOS in p-substrate. Hence to create the required PMOS transistors we first create a NWELL on a part of the p-substrate and fabricate the PMOS transistors within this region. 5. To start create a NWELL of the required size. Draw a box (24λ, 18λ), i.e., height = 24λ (y-axis) and width = 18λ (x-axis). Run the following command in the console window to make this area into NWELL. paint nwell To draw any layer / material in Magic we first draw a box of the required size, using the mouse, and then enter commands into the console window to specify the type of material that we have drawn. Figure 3a: NWELL 6. Next we paint p-diffusion (active region) of (12 λ, 12 λ). Draw a box of the required size inside the NWELL created in the previous step, but 3λ from its sides. Run the following command in the console window to make this into the p-diffusion region. paint pdiff Figure 3b: p-diffusion inside the NWELL 7. Now let us make a metal1 to p-diffusion contact inside the p-diffusion region. Remember that a transistor is formed by the overlap of a poly on an active region. But to make contacts we need metal layers, and to have contacts between active / poly we need contacts. Now draw a box (12λ, 4λ) on the p-diffusion layer drawn above, and run the command below in the console window. In future whenever this document refers to running the command, unless mentioned otherwise, it is to be assumed that the command is run inside the console window. paint pdc Figure 3c: Metal 1 to p-diffusion contact 8. To create the transistor now draw a poly (polysilicon) layer of the required size. Draw a box of (16λ, 2λ) at least 1λ away from the pdc layer that you drew in the step above and extending 2λ on either side of the p-diffusion layer, and run the command paint poly Figure 3d: PMOS transistor 9. We have a PMOS with W/L = 12/2. Add another layer of the metal 1 to p-diffusion (pdc), and we would be done with a PMOS and its source and drain contact points. But remember, from the circuit in Lab 1, that we need 2 PMOS devices in the pull-up part of the NAND gate. Though we can have two independent PMOS devices, doing so would require more area and their interconnections would require more effort and time. Instead we can extend the NWELL and the p-diffusion so that we can have two PMOS transistors. 10. For this we extend (increase the length of) NWELL and the p-diffusion layers to accommodate another transistor. To accommodate this additional transistor extend these layers by 8λ. Draw a box enclosing the right-side of the p-diffusion and the NWELL, Figure 4a. Figure 4a: Box enclosing right-side of NWELL and p-diffusion 11. Now select this area by running the following command in the console window. select area Figure 4b: NWELL and p-diffusion selected 12. Stretch the NWELL and p-diffusion layers by the required amount in the proper direction. Since we want to have the 2nd PMOS device to the right, we extend these layers right by 8λ, by running the following command in the console window. stretch right 8 Figure 4c: Stretching the NWELL and p-diffusion layers Now unselect the layers by executing the following command, select clear 13. It is now time to draw the remaining Metal 1 to p-diffusion contact layers and the poly layer of the second PMOS transistors. Remember from previous steps that the poly is (16λ, 2λ) and Metal 1 to p-diffusion contact is (10λ, 4λ). Figure below shows the two PMOS devices inside the NWELL. Figure 4d: PMOS devices in NWELL 14. We have made the PMOS devices in the NWELL, but have we followed all the design rules? No. The rules say that the Drain/source active region to well edge distance has to be 5λ, which is not the case here. Hence we now stretch the NWELL along the necessary sides to make this distance 5λ lambda, as shown in the figure below. Figure 4e: NWELL extended to account for the design rules Draw NMOS: It is now time to draw the two NMOS transistors. Remember that we do not need a p-well as the substrate itself is p -type. The NMOS is drawn in a manner similar to the PMOS, except that the size of the device is smaller. This is because of the fact that the NMOS devices are faster than the PMOS devices, and they have to be properly sized if you want the pull-up time (0 – 1 transition) to be the same as the pull-down time (1 – 0 transition). This will be dealt with in detail in the class. 15. To start, draw the n-diffusion layer of size (4λ, 20λ) below the PMOS created earlier. For this lab we can keep it about 20λ below, as we would like to show the input and output ports in between the transistors. Once we get experienced on the tool and understand all the design rules we can calculate the exact dimensions and make a optimized design. To draw the n-diffusion layer, draw a box of the required size and execute the following command in the console window to make it into n-diffusion layer. paint ndiff Figure 5a: n-diffusion layer of the NMOS 16. It is now time to make the Metal 1 to n-diffusion contacts. For this make a box (4λ, 4λ) at one of the edge of the n-diffusion layer and run the following command in the console window into make the required contact at that point. paint ndc Figure 5b: Metal 1 to n-diffusion contact 17. It is now time to make the additional metal to diffusion contact of the NMOS devices. This can be done by either drawing another contact as done in the previous step or by copying the existing one to the new location. To copy: select the metal 1 to n-diffusion contact that you drew in the previous step (draw a box enclosing only the contact that you just drew), run commands “select area” and “copy right 16” to draw the new contact layer. Figure 5c: New Metal 1 to n-diffusion contact drawn Since the NMOS transistors in the pull down circuit of the NAND gate are in series and we do not need any contacts in between them. We need only two metal to active layer contacts in case of the NMOS. The n-diffusion layer itself acts as a contact / conductor between the two NMOS transistors that are in series. 18. From our knowledge of CMOS circuits we know that for every input to a PMOS device we have a corresponding NMOS device with the same input. Due to this fact, and based on our circuit from lab 1, we understand that there are two different methods to draw the polysilicon (poly) layers for the PMOS transistors. We can either extend the poly from the PMOS devices into the n-diffusion region to create the NMOS transistors or draw the poly layers of the NMOS transistors which are then connected to the PMOS poly layers (gate). Here we use the first method, extending the poly layers. This is done in the following sequence of steps: a. Change to wiring tool by typing "spacebar" key, mouse pointer should switch to arrow type. b. Click left mouse button (LMB) at the bottom of poly at PMOS, c. Put cursor at the end point of the poly, 2λ (2 grid below) of NMOS, and d. Click LMB followed by right mouse button (RMB). e. If NWELL is selected instead of poly when you click LMB on bottom of poly, click again. f. Do this for both the NMOS transistors. When done switch back to box tool (type "spacebar" key 3 times). Figure 5d: PMOS Transistors Interconnects & Labeling: 19. It is now time to draw the Vdd and Gnd lines. Before drawing the Vdd line, stretch up (extend up) the NWELL by 2λ (by running the command “extend up 2” in the console window) as we need the Vdd and Gnd lines to be at least 8λ high. This is because we want to keep the NWELL and PWELL contacts at least 2λ from the edges of the Vdd and Gnd lines. 20. It is now time to draw the actual Vdd and Gnd lines. For this draw a box 8λ high and as wide as the NWELL, and make it into Metal 1 by running the following command in the console window. paint m1 Next draw metal 1 lines that overlap the metal 1 to diffusion contact on either ends of the PMOS transistors. This is because we have the PMOS transistors in parallel. Figure 6a: PMOS transistors in parallel 21. It is now time to draw the NWELL contacts. For this draw boxes (4λ, 4λ) and convert them to NWELL contact using the command “paint nwc”. Similarly draw the Gnd line, but this overlaps only the metal 1 to diffusion contact on the left side of the NMOS devices. Now draw the PWELL contacts (4λ, 4λ) using the command “paint pwc”. Figure 6b: Layout with power lines and well contacts nwc (NWELL contact) is a contact between Vdd and NWELL, and pwc (PWELL contact) is a contact between Gnd and p-substrate. 22. Now we have to draw the poly contact, contact between poly and metal 1, and metal 1. To do this first make an extension of 4λ x4λ to the poly layers as shown in the figure below. Figure 6c: Extensions to the poly layers Now you can add the poly 2 metal contacts. For this switch to wiring tool and do the following:a. Click LMB followed by RMB on the middle of poly extension that you created in the step above. b. Put cursor on any of metal 1 layer and click the MMB (middle mouse button) to make a poly contact. Clicking middle mouse button makes a contact between selected layer (poly, in this case) and layer below the cursor automatically. c. Return to the box. Can this be done with the box tool? Yes. For this make a box of the required size and run the command “paint pc”. This method can be used to make a via contact between metal 1 and metal 2. Click metal1 (or metal2), put cursor on metal2 (or metal1) and click MMB. Figure 6d: Poly contacts 23. Now we can add metal contacts that can be used as ports/ connections. Draw metal 1 layers such that they completely overlap the contacts created and also protrude further to one side, giving us the input ports. Again make sure that the metal 1 layer overlaps the poly contact created above. Figure 7a: Input ports 24. For the output we can use metal 1 to connect the middle pdc with the rightmost ndc. To help us practice drawing using metal2 and the via contacts, we use metal 2 in this lab. Draw via and metal1. To draw the via, use the command “paint via”. Via is a contact between metal 1 and metal 2. Make sure that the metal 1 layer you drew overlaps the metal 1 to diffusion contacts, and that the via lies over metal1. Figure 7b: Via and Metal 1 25. Draw metal2, using the command “paint m2”, again making sure that the metal 2 layer overlaps the both the via's. Figure 7c: Metal 2 connecting the via 26. Now add via and draw a metal 1 layer that will be the output port, again making sure that the metal 1 overlaps the via. Figure 7d: Output Port 27. Save the layout. Run the “save” command in the console window or “File -> save” in the layout window. 28. It is now time to label the ports: - put cursor on metal 1 of one of the inputs and click the left and right mouse buttons at the same time. This will put a small cross/point on the metal 1 layer. Figure 8a: Cross/point on Metal 1 of input port Run “label a”, in the console window. Figure 8b: Port “a” labeled Similarly add labels to input b and the output 29. Now add labels to Vdd and Gnd planes, There are two kinds of node names, local and global. Any label that ends in “!” is treated as a global node name; it will be assumed that all nodes by this name, anywhere in any cell in a layout, are electrically connected. Hence it is useful to make them global. Put cursor on metal1 of Vdd, click LMB and RMB at the same point, and run the command “label Vdd! n m1" in the console window. When two layers are overlapped like Vdd (metal1 and NWELL), it is always good practice to specify direction and layer explicitly. For Gnd layer, run the command “label GND!” in the console window. Note that we do not need an explicit p-layer in case of the Gnd. Note that the ground layer is all caps, it is just the convention followed in Magic. Figure 8c: Completed labeling 30. After all labeling have been done, figure 8c, save your layout. Circuit extraction and IRSIM simulation: 31. To extract the netlist, run the following command in the console window: extract all This extracts an .ext file (nand.ext in this particular example), which has to be converted to either a .sim (for IRSIM simulation) or .spice (for spice simulation). To generate the .sim file run “ext2sim nand” in the console window. This generates nand.sim file that you can use for simulation using IRSIM. (For .spice file run “ext2spice nand” which generates nand.spice.) 32. Use this file, nand.sim, to run simulation using IRSIM as in lab 1. 33. Make sure that the output matches with the truth table of the NAND gate. 34. Observe the nand.sim file, what do you see? It shows that in addition to the actual PMOS and NMOS transistors we have parasitic elements. 35. Will they affect the performance of your design? How?