Transcript
Lab 2 preview Hung-Wei Tseng
Announcement •
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Lab 1 due tomorrow!
• • • • •
Mail it to h1tseng @ cs.ucsd.edu, not to the TAs! name your pdf as cse141L-lab1-LastName-FirstName.pdf! name your e-mail title as
[CSE141LSU14] cse141L-lab1-LastName-FirstName! Your report will not be graded if any of the above goes wrong! No late reports, no group work!
Form your group from now!!
• •
We need 2 or 3 persons
to make a processor! 4 or 5 are too more,
we are not making burgers 2
In Lab 2... • •
You will be implementing the datapath elements for a single cycle processor!
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We provide ALU, data memory, instruction! You need to implement the rest!
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What are the elements required for a single cycle processor! How to test each component! How to connect them together
Design the schematic of your processor first!
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Lab 2: single-cycle datapath Add 4
RegWrite
PC
JumpOut BranchOut
inst[25:21] Read Reg 1
Instruc(on Memory
Read Address
RE
inst[31:0]
Register Read inst[20:16] Read Reg 2 Data 1
!
0
m
u
1x
File
Write Reg
inst[15:11] RegDst Write Data 16
Read Data 2 sign-
extend
WE
Data Memory
ALUSrc ALU 0
m
u
x
1
ALUop
Address Write Data
Read Data
1
m
u
x
0
32
4
You have to implement the processor reset
clock
serial_in[7:0]
serial_ready_in
serial_valid_in
Add 4
RegWrite
PC
JumpOut BranchOut
inst[25:21] Read Reg 1
Instruc(on Memory
Read Address
RE
inst[31:0]
Register Read inst[20:16] Read Reg 2 Data 1
!
0
m
u
1x
File
Write Reg
inst[15:11] RegDst Write Data 16
serial_wden_out
Read Data 2 sign-
extend
WE
Data Memory
ALUSrc ALU 0
m
u
x
1
ALUop
Address Write Data
Read Data
1
m
u
x
0
32
serial_rden_out
You have to implement the black parts!
serial_out[7:0] 5
Interface of instruction memory clock addr_in[31:0] reset
data_out[31:0]
Instruc(on Memory
module inst_rom(! ! input clock,! ! input reset,!
!
! input [31:0] addr_in, //Connect to PC_next! ! output [31:0] data_out //Fetched instruction! );! parameter INIT_PROGRAM=”c:/myfiles/blank.memh”;! endmodule
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Interface of ALU A_in[31:0]
Jump_out Branch_out
32
ALU
B_in[31:0]
32
O_out[31:0]
module alu(! ! input [5:0] Func_in,! ! input [31:0] A_in,! ! input [31:0] B_in,! ! output [31:0] O_out,! ! output Branch_out,! ! output Jump_out! );!
6 Func_in[5:0]
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Interface of data memory addr_in[31:0] writedata_in[31:0]
32 32
clock reset re_in we_in size_in[1:0] serial_in[7:0] serial_ready_in serial_valid_in
readdata_out[31:0]
Data Memory
module data_memory(! ! input clock,! ! input reset,! ! input [31:0] addr_in,! //Read/Write address! ! input [31:0] writedata_in, //Data to write to memory! ! input re_in, //Read Enable - set high when reading from memory! ! input we_in, //Write Enable - set high when writing to memory! ! output [31:0] readdata_out, //Data output for reads from memory! ! input [1:0] size_in, //Not used yet - hardwire to 2'b11! ! input [7:0] serial_in,! ! input serial_ready_in,! ! input serial_valid_in,! ! output [7:0] serial_out,! ! output serial_rden_out,! ! output serial_wren_out! );! parameter INIT_PROGRAM0=”c:/myfiles/blank.memh”; ! parameter INIT_PROGRAM1=”c:/myfiles/blank.memh”;! parameter INIT_PROGRAM2=”c:/myfiles/blank.memh”;! parameter INIT_PROGRAM3=”c:/myfiles/blank.memh”;
serial_out[7:0] serial_rden_out serial_wden_out
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Your register file inst[25:21] Read Reg 1
Register Read
inst[31:0]
32
inst[20:16] Read Reg 2 Data 1 ! 0
m
u
1x
inst[15:11]
File
Write Reg Write Data
Read Data 2
32
• Should contain at least the above inputs/outputs! • Does every instruction write back data?! • Is it clocked?! • Support reset! • Deal with $zero 9
When you interview with us • Show us your processor.v! • Show us your register_file.v! • Demonstrate it works: you need to design a testbench for it.! • Show us your schematic! •
You may output it through the RTL viewer under analysis tool in Quartus II
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Q&A
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