Transcript
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Compal Confidential NIWE2 2
Schematics Document Arrandale with Intel IBEX PEAK-M core logic
2
3
3
REV:0.3
4
4
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
Security Classification 2008/03/25
Deciphered Date
2008/04/
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
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Cover Sheet Size Document Number Custom
Rev 0.3
LA-5752P
Date: Thursday, October 29, 2009
Sheet E
1
of
51
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Compal confidential
POWER BD: LS-5754P POWER BT NOVO BT POWER MANAGE BT
File Name : Z ZZ
intel Arrandale (UMA/DIS)
VRAM 64*16 DDR3*4
15.6W_PCB_LA5752P 1
page20
PCI-E X16
Clock Generator
E
CAP SENSOR BD:LS-5752P VOLUME UP VOLUME DOWN MUTE AUDIO ENHANCE BUTTON & LED
CARD READER BD: LS-5753P RTS5138 HP JACK MIC JACK 1
ICS9LRS3199AKLFT page12
Socket-rPGA989 37.5mm*37.5mm
NVidia N11M-GE1 page19~23
level shift IC ASM1442
HDMI CONN
DDR3-SO-DIMM X2 BANK 0, 1, 2, 3
page5~9
100MHz 2.7GT/s
page25
page24
FDI *8
Dual Channel DDR3-800(1.5V) DDR3-1067(1.5V)
DMI *4
page 10,11
UP TO 8G 2Channel Speaker
page33
CRT Connector
Intel Ibex Peak M
page26 2
LVDS Connector
2
Audio Codec AZALIA
page27
Conexant CX20671
FCBGA 951
PCI Express Mini card Slot 1
Analog MIC_Int
page33
page33
25mm*25mm
6*PCI-E BUS
CMOS Camera
14*USB2.0
page28
page27
PCI Express Mini card Slot 2
BlueTooth CONN
6*SATA serial
page 13~18
page37
page28
USB CONN X1(Right)
SPI ROM BIOS page13 3
page37
LPC BUS
USB PORT X1(Left)
SIM Card page28
3
page37
USB(WWAN)
EC
RTL8111DL-VB-GR 10/100/1G LAN
New Card X1
ENE KB926D
page29
Card Reader/Audio Jack SB CONN
page28
page34
WWAN
Realtek 5138 MS/MS pro/SD/SD pro/mmc/XD
page28
Int.KBD
RJ45 CONN
page30
page35
Touch Pad page35
SPI ROM page36
HP X 1+ MIC_Ext X1 page38
ESATA HDD AND USB CONN page37
SATA HDD CONN page32
SATA ODD CONN 4
4
page32
Compal Secret Data
Security Classification 2008/03/24
Issued Date
2008/04/
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
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Title
Compal Electronics, Inc. MB Block Diagram
Size Document Number Custom
R ev 0.3
LA-5752P
Date:
Thursday, October 29, 2009
Sheet E
2
of
51
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E
DDR3 Voltage Rails SMBUS Control Table SOURCE
+5VS power plane 1
+5VALW
+1.5V
+B +3VALW State
+3VS
SMB_EC_CK1
+1.5VS
SMB_EC_DA1
+VCCP
SMB_EC_CK2
+CPU_CORE
SMB_EC_DA2
+VGA_CORE
SMBCLK
+1.8VS
SMBDATA
+0.75VS
SML0CLK
+1.05VS
SML0DATA SML1CLK SML1DATA
2
S0
O
O
O
O
S3
O
O
O
X
S5 S4/AC
O
O
X
X
X
X
X
X
X
X
S5 S4/ Battery only
O
S5 S4/AC & Battery don't exist
X
@ FUNCTION
3
45@ 100@ GIGA@ UMA_HDMI@ HDMI@ 3G@ X76@ ESATA@ CMOS@ BT@ 10M@ 11M@ UMA@ DIS@ VGA@ HYBRID@ HU@ HD@
EVT (45 BOM) 10/100 LAN GIGA LAN FOR UMA HDMI components FOR HDMI components 3G(WWAN) function (X76 BOM) ESATA function Camera function Blue Tooth FOR 10M CHIP FOR 11M CHIP UMA only (Arranddale) DIS only (Arranddale) FOR NVIDIA PART FOR SWITCHABLE
KB926 +3VALW KB926 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW
RAM M2
N10x Thermal Sensor
N10x
Cap sensor board
X
X
X
X
X
X
X
X
X
X
X
WLAN CLK CHIP WWAN
BATT
KE926
SODIMM
V
X
X
X
X
X
X
X
V
X
X
X
X
X
X
X
+3VALW
+3VALW
+3VS
+3VS
V
X
X
X
X
X
X
X
X
X
X
V
X
X
X
V
X
+3VALW
V
Arrandale(dGPU)
DEVICE
HEX
ADDRESS
DDR SO-DIMM 0
A0
10100000
DDR SO-DIMM 1
A4
10100100
CLOCK GENERATOR (EXT.)
D2
11010010
X V
V
X
X
X
X
V
X
X
+3VS
+3VS
1
+3VALW
2
NON-USE
PCIE PORT LIST PORT 1 2 3 4 5 6 7 8
USB PORT LIST
DEVICE
PORT 0 1 2 3 4 5 6 7 8 9 10 11 12 13
WLAN LAN 3G NEW CARD
SWITCHABLE or UMA only SWITCHABLE or DIS only
DIS@ / 100@
PCH
I2C / SMBUS ADDRESSING
SKU 4
+3VS
NEW CARD
DEVICE
3
RIGHT SIDE LEFT SIDE CMOS LEFT SIDE RIGHT SIDE CARD READER WIRELESS NEW CARD BT 3G
for EVT 4
DIS only
Arrandale(iGPU)
UMA@ / 100@
for EVT
UMA only
Arrandale(iGPU+dGPU) VGA@+HD@+HU@+HYBRID@
Compal Secret Data
Security Classification
SWITCHABLE
2008/03/24
Issued Date
2008/04/
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. MB Notes List
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet E
3
of
51
A
B
VGA and DDR3 Voltage Rails
C
(N10x GPIO)
GPIO
I/O
ACTIVE
GPIO0
N/A
N/A
GPIO1
IN
-
Hot plug detect for IFP link C
GPIO2
OUT
H
Panel Back-Light brightness(PWM capable)
GPIO3
OUT
H
Panel Power Enable
GPIO4
OUT
H
Panel Back-Light On/Off (PWM)
GPIO5
OUT
-
GPU VID0
GPIO6
OUT
-
GPU VID1
GPIO7
OUT
-
GPU VID2
GPIO8
I/O
L
Thermal Catastrophic Overtemp
GPIO9
OUT
L
Thermal Alert
GPIO10
OUT
D
E
Performance Mode P0 TDP at Tj = 102 C* (DDR3) GPU (4)
Mem (1,5)
NVCLK /MCLK
Products
(W)
(W)
(MHz)
(V)
N10P-GS 128bit 1024MB DDR3
21.07
6.67
TBD
N10P-GE 128bit 1024MB DDR3
20.97
6.73
N10P-LP 128bit 1024MB DDR3
15.48
6.44
Function Description
FBVDD (1.5V)
NVVDD (A)
(W)
FBVDDQ (GPU+Mem) (1.5V)
PCI Express I/O and (1.05V) PLLVDD (6) (1.8V)
I/O and PLLVDD (1.05V)
Other (3.3V)
(A)
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
TBD 18.25 17.34
2.06
3.09
4.09
6.14
850
0.89
75
0.14
63
0.07
55
0.18
TBD
TBD 19.17 17.25
2.03
3.05
4.09
6.14
840
0.88
75
0.14
63
0.07
55
0.18
TBD
TBD 13.95 11.86
1.90
2.85
3.99
5.99
810
0.85
75
0.14
63
0.07
55
0.18
1
2
1
Performance Mode P0 TDP at Tj = 102 C* (DDR3)
Memory VREF switch
GPIO11
I/O
L
SLI raster sync
GPIO12
IN
-
AC power detect pin
GPIO13
OUT
-
MEM_VID orPower supply control
GPIO14
OUT
-
Power supply control
GPIO15
IN
-
Hot plug detect for IFP Link E
GPIO16
OUT
-
Programmable Fan Control
GPIO17
IN
-
GPIO18
IN
-
GPIO19
IN
-
GPIO20
IN
-
GPIO21
IN
-
Hot plug detect for IFP link F
GPIO22
IN
-
SLI swap ready signal
GPIO23
I/O
GPU (4)
Mem (1,5)
NVCLK /MCLK
Products
(W)
(W)
(MHz)
(V)
N10M-GE 64bit 512MB DDR3
13.36
2.93
TBD
N10M-GS 64bit 512MB DDR3
14.29
3.10
N10M-LP 64bit 512MB DDR3
8.28
2.91
FBVDD (1.5V)
NVVDD (A)
(W)
FBVDDQ (GPU+Mem) (1.5V)
PCI Express I/O and (1.05V) PLLVDD (6) (1.8V)
I/O and PLLVDD (1.05V)
Other (3.3V)
(A)
(W)
(A)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
(mA)
(W)
TBD 11.89 10.70
0.66
0.99
2.16
3.24
792
0.83
75
0.14
63
0.07
100
0.33
TBD
TBD 11.53 11.53
0.70
1.05
2.28
3.42
817
0.86
75
0.14
63
0.07
100
0.33
TBD
TBD
0.62
0.93
2.20
3.3
782
0.82
75
0.14
63
0.07
100
0.33
6.60 5.61
2
The ramp time for any rail must be more than 40us
Power Sequence Hot plug detect for IFP Link D
(+3VS) VDD33 PEX_VDD can ramp up any time
(1.05VS)PEX_VDD tNVVDD
3
3
(+VGA_CORE) NVVDD GPIO6
GPIO5
N10M-GS N10P-GS
GPU_VID1
GPU_VID0
VGA_CORE
0
0
0.8V
0
1
0.85V
12
1
0
0.9V
0,10
1
1
tNV-IFPAB_IOVDD P-State
(1.8VS)IFPAB_IOVDD
12 tNV-FBVDDQ
(1.5VS) FBVDDQ 1.0V (N10M-GS) 0.925V (N10P-GS)
4
4
Compal Secret Data
Security Classification 2009/03/16
Issued Date
2010/03/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. VGA Notes List
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet E
4
of
51
5
4
3
2
1
DDR3 Compensation Signals
SM_RCOMP0
1 R5 67 1 R5 66 1 R5 65
SM_RCOMP1 SM_RCOMP2
：
D
2 2 2
100_0402_1% 24.9_0402_1% 130_0402_1%
Layout Note:Please these resistors near Processor
Layout rule 10mil width trace length < 0.5", spacing 20mil
D
J C PU1B COMP3
2COMP2 AT24
COMP2
49.9_0402_1% 1 R5 48
2COMP1
G16
COMP1
49.9_0402_1% 1 R5 57
2COMP0 AT26
COMP0
TP_SKTOCC#
<16>
49.9_0402_1%
H_ PECI
2
H _CATERR#
1 R 163
R 564 0_0402_5% 1 2 H_PECI_ISO 2 R5 69
+ VCCP
AK14
AT15
SKTOCC# CATERR#
THERMAL
+ VCCP
AH24
PECI
1 68_0402_5% H _PROCHOT#
<34,48> H _PROCHOT#
H_THERMTRIP#
<16> H_THERMTRIP#
AN26
AK15
PROCHOT#
THERMTRIP#
A16 B16
C LK_CPU_BCLK CLK_CPU_BCLK#
BCLK_ITP BCLK_ITP#
AR30 AT30
CLK_CPU_ITP CLK_CPU_ITP#
PEG_CLK PEG_CLK#
E16 D16
CLK_EXP CLK_EXP#
DPLL_REF_SSCLK DPLL_REF_SSCLK#
A18 A17
BCLK BCLK#
CLOCKS
2COMP3 AT23
1 R5 58
2
1 H_ CPURST#_R R1 35
AP26
RESET_OBS#
2 H_P M_SYNC_R 0_0402_5%
AL15
PM_SYNC
1 R1 87
1 R1 90 2 V CC PWRGOOD_1 AN14 0_0402_5% <16> H_CP UP W RGD <15> PM_DRAM_PWRGD
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2
PM_EXT_TS#[0] PM_EXT_TS#[1]
AN15 AP15
PM_EXTTS#0 PM_EXTTS#1
PRDY# PREQ#
AT28 AP27
XDP_PRDY# XDP _PREQ#
TCK TMS TRST#
AN28 AP28 AT27
X DP_TCK XDP_TMS XDP_TRST#
TDI TDO TDI_M TDO_M
AT29 AR27 AR29 AP29
XDP_TDI X DP_TDO R 555 2
DBR#
AN25
XDP _DBRESET#
SM_DRAMPWROK
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7
VTT_POK
AM15
1
R 183 560_0402_5% <16,19,28,29> BUF_PLT_RST#
VTTPWRGOOD
AM26
TAPPWRGOOD
AL14
RSTIN#
R1 85 1
PLT_RST#_R
2
1.5K_0402_5%
3
1 R5 63
2 0_0402_5%
T19
PM_EXTTS#1_R <10,11>
2 2
10K_0402_5%
XDP _PREQ# R 136 1
@
2 51_0402_1%
XDP_TMS
R 138 1
@
2 51_0402_1%
XDP_TDI
R 556 1
@
2 51_0402_1%
X DP_TDO
R 134 1
X DP_TCK
R57
1
2 51_0402_5% @
XDP_TRST# R 133 1
P AD
10K_0402_5%
XDP _DBRESET#
2 51_0402_1% 2 51_0402_5%
R1 37 @ 1
2 1K_0402_5%
C
+3VS
CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3 1 0_0402_5%
1
FROM POWER VTT POWER GOOD SIGNAL
VCCPWRGOOD_0
1 R1 91 2 V DDP W RGOOD_R AK13 0_0402_5%
2
2 1 R 184 1K_0402_1%
<46> VCCP_POK
VCCPWRGOOD_1
1 R1 39 2 V CC PWRGOOD_0 AN27 0_0402_5%
JTAG & BPM
68_0402_5%
PWR MANAGEMENT
+ VCCP
<15> H_ PM_SYNC
1 R5 61 1 R5 62
PM_EXTTS#1
pins unused by Clarksfield on the rPGA989 Package
AL1 AM1 AN1
C
+ VCCP PM_EXTTS#0
P AD P AD CLK_EXP <14> CLK_EXP# <14>
SM_DRAMRST#
SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]
C LK_CPU_BCLK <16> CLK_CPU_BCLK# <16> T17 T18
F6
SM_DRAMRST#
DDR3 MISC
1 R5 60
20_0402_1%
MISC
20_0402_1%
I C,AUB_CFD_rPGA,R1P0 ME@
2
R 186 750_0402_1% B
B
+1.5V
G 3
1
@
DRA M_PWRGD 1
D
1
PCH GPIO CONTROL <16> DRAMRST_CNTRL_PCH <34> DRAMRST_CNTRL_EC
2
2
2 R 300
1
SM_DRAMRST#
3
Q27 2N7002_SOT23
R 192 3K_0402_1% @
750_0402_1% +5VALW
DRAMRST#
<10,11> DRAMRST# V DDP W RGOOD_R
2
1.5K_0402_1% MC74VHC1G08DFT2G SC70 5P R 194
1 0_0402_5%
DDR3 CONNECTER
2
R1 95 4
Y
1
A
U8
P
B
1
R 193 1.1K_0402_1% @
2 R2 83
2 G
5
+3VALW
2
R3 01 1K_0402_1%
S
+1.5V
<46> VCCP_POK
3
2
For Intel S3 Power Reduction.
1
5
For Intel S3 Power Reduction.
1 R2 81
2 DRAMRST_CNTRL_R 0_0402_5%
1 R2 82 @
2 0_0402_5%
EC GPIO CONTROL
1
1 100K_0402_5%
0.01U_0402_16V7K
1
C 338
A
R6 10 10K_0402_5%
2
A
2
6
1
S3_0.75V_EN
S3_0.75V_EN <44>
VCCP_P OK
5
Issued Date 3
2 G Q42 2N7002_SOT23
Compal Secret Data
Security Classification
D
S
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
Compal Electronics, Inc. Arrandale(1/5)-Thermal/XDP
Size D ocument Number Cus tom Dat e:
Rev 0.3
LA-5752P
Thursday, October 29, 2009 1
Sheet
5
of
51
5
：
4
3
2
1
Layout rule trace length < 0.5" J C PU1A
DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]
<15> <15> <15> <15>
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
B24 D23 B23 A22
DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]
<15> <15> <15> <15>
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
D24 G24 F23 H23
DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]
<15> <15> <15> <15>
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
D25 F24 E23 G23
DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]
<15> <15> <15> <15> <15> C <15> <15> <15>
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
E22 D21 D19 D18 G21 E19 F21 G18
FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7]
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
D22 C21 D20 C18 G22 E20 F20 G19
FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7]
<15> FDI_FS Y NC0 <15> FDI_FS Y NC1
FDI_FS Y N C0 FDI_FS Y N C1
F17 E17
FDI_FSYNC[0] FDI_FSYNC[1]
<15> FDI_ INT
FDI _INT
C17
FDI_INT
<15> FDI_LS Y NC0 <15> FDI_LS Y NC1
FDI_LS Y NC0 FDI_LS Y NC1
F18 D17
Intel(R) FDI
<15> <15> <15> <15> <15> <15> <15> <15>
J C PU1E
FDI_LSYNC[0] FDI_LSYNC[1]
E XP_ICOMPI
1 R 544
2 49.9_0402_1%
E XP_RBIAS
1 R 545
2 750_0402_1% PCIE_CRX_GTX_N[0..15] <19>
PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS
B26 A26 B27 A25
PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]
K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31
PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]
J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30
PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0
PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]
L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26
PCIE_CTX _GRX_C_N15 PCIE_CTX _GRX_C_N14 PCIE_CTX _GRX_C_N13 PCIE_CTX _GRX_C_N12 PCIE_CTX _GRX_C_N11 PCIE_CTX _GRX_C_N10 PCIE_CTX _GRX_C_N9 PCIE_CTX _GRX_C_N8 PCIE_CTX _GRX_C_N7 PCIE_CTX _GRX_C_N6 PCIE_CTX _GRX_C_N5 PCIE_CTX _GRX_C_N4 PCIE_CTX _GRX_C_N3 PCIE_CTX _GRX_C_N2 PCIE_CTX _GRX_C_N1 PCIE_CTX _GRX_C_N0
C5 27 C5 40 C5 29 C5 42 C5 31 C5 44 C5 33 C5 46 C5 35 C5 62 C5 64 C5 55 C5 57 C5 61 C5 48 C5 59
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0
PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]
L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0
C5 28 C5 41 C5 30 C5 43 C5 32 C5 45 C5 34 C5 47 C5 36 C5 63 C5 65 C5 56 C5 58 C5 60 C5 49 C5 50
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0
AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30
PCIE_CRX_GTX_P[0..15] <19>
CFG0
R5 36 1
DI S@ 2 1K_0402_5%
FDI _INT
R5 34 1
DI S@ 2 1K_0402_5%
FDI_LS Y NC0
R5 33 1
DI S@ 2 1K_0402_5%
FDI_LS Y NC1
R5 35 1
DI S@ 2 1K_0402_5%
CFG7
FOR ES1 SAMPLE ONLY
R5 47 0_0402_5% @ 1 2 @ 1 2
H_R SVD17_R H_R SVD18_R
R5 46 0_0402_5%
PCIE_CTX_GRX_P[0..15] <19>
AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16
CFG Straps for PROCESSOR 1 R58
@ 2 3.01K_0402_1%
PCI-Express Configuration Select 1: Single PEG CFG0 0: Bifurcation enabled Not applicable for Clarksfield Processor
CFG3
RSVD15 RSVD16
A20 B20
RSVD17 RSVD18
U9 T9
RSVD19 RSVD20
AC9 AB9
RSVD21 RSVD22
RSVD32 RSVD33
AJ13 AJ12
RSVD34 RSVD35
AH25 AK26
RSVD36 RSVD_NCTF_37
AL26 AR2
RSVD38 RSVD39
AJ26 AJ27
RSVD_NCTF_40 RSVD_NCTF_41
AP1 AT2
RSVD_NCTF_42 RSVD_NCTF_43
AT3 AR1
RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32
RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65
E15 F15 A2 D15 C15 AJ15 AH15
RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3
RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85
V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9
RSVD_NCTF_23 RSVD_NCTF_24
J29 J28
RSVD26 RSVD27
A34 A33
RSVD_NCTF_28 RSVD_NCTF_29
C35 B35
RSVD_NCTF_30 RSVD_NCTF_31
VSS
11=1*16 PEG 10=2*8 PEG
1 R61
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86
B19 A19
C1 A3
CFG[1:0]
FDI_FS Y N C1
1 2 3.01K_0402_1%
PCIE_CTX_GRX_N[0..15] <19>
I C,AUB_CFD_rPGA,R1P0 ME@
DI S@ 2 1K_0402_5%
@ R 59
VGA@
CFG0
R5 32 1
CFG3 CFG4
PCIE Lane Numbers Reversed CFG3-PCI Express Static Lane Reversal
B
FDI_FS Y N C0
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14
RESERVED
A24 C23 B22 A21
PCI EXPRESS -- GRAPHICS
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI
D
<15> <15> <15> <15>
D
C
R 189 0_0402_5% RS VD64_R 2 @ RS VD65_R 2 @ R 188 0_0402_5%
1 1
B
AP34
I C,AUB_CFD_rPGA,R1P0 ME@
2 3.01K_0402_1%
CFG3-PCI Express Static Lane Reversal 1: Normal Operation CFG3 0: Lane Numbers Reversed 15 -> 0, 14 ->1, ..... @ CFG4
1 R60
2 3.01K_0402_1%
CFG4-Display Port Presence 1: Disabled; No Physical Display Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port A
A
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Arrandale(2/5)-DMI/PEG/FDI
Size D ocument Number Cus tom Dat e:
Rev 0.3
LA-5752P
Thursday, October 29, 2009 1
Sheet
6
of
51
5
4
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2
1
J CP U1D J CP U1C
DDR_A _D0 DDR_A _D1 DDR_A _D2 DDR_A _D3 DDR_A _D4 DDR_A _D5 DDR_A _D6 DDR_A _D7 DDR_A _D8 DDR_A _D9 DDR_ A_D10 DDR_ A_D11 DDR_ A_D12 DDR_ A_D13 DDR_ A_D14 DDR_ A_D15 DDR_ A_D16 DDR_ A_D17 DDR_ A_D18 DDR_ A_D19 DDR_ A_D20 DDR_ A_D21 DDR_ A_D22 DDR_ A_D23 DDR_ A_D24 DDR_ A_D25 DDR_ A_D26 DDR_ A_D27 DDR_ A_D28 DDR_ A_D29 DDR_ A_D30 DDR_ A_D31 DDR_ A_D32 DDR_ A_D33 DDR_ A_D34 DDR_ A_D35 DDR_ A_D36 DDR_ A_D37 DDR_ A_D38 DDR_ A_D39 DDR_ A_D40 DDR_ A_D41 DDR_ A_D42 DDR_ A_D43 DDR_ A_D44 DDR_ A_D45 DDR_ A_D46 DDR_ A_D47 DDR_ A_D48 DDR_ A_D49 DDR_ A_D50 DDR_ A_D51 DDR_ A_D52 DDR_ A_D53 DDR_ A_D54 DDR_ A_D55 DDR_ A_D56 DDR_ A_D57 DDR_ A_D58 DDR_ A_D59 DDR_ A_D60 DDR_ A_D61 DDR_ A_D62 DDR_ A_D63
C
B
A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
<10> D DR_A_BS0 <10> D DR_A_BS1 <10> D DR_A_BS2
AC3 AB2 U7
SA_BS[0] SA_BS[1] SA_BS[2]
<10> DD R_A_CAS# <10> DD R_A_RAS# <10> DDR_ A_WE#
AE1 AB3 AE9
SA_CAS# SA_RAS# SA_WE#
DDR SYSTEM MEMORY A
<10> DDR_A _D[0..63]
<11> DDR_B _D[0..63]
SA_CK[0] SA_CK#[0] SA_CKE[0]
AA6 AA7 P7
M _CLK_DDR0 <10> M_CLK_DDR#0 <10> DDR_CKE0_DIMMA <10>
SA_CK[1] SA_CK#[1] SA_CKE[1]
Y6 Y5 P6
M _CLK_DDR1 <10> M_CLK_DDR#1 <10> DDR_CKE1_DIMMA <10>
SA_CS#[0] SA_CS#[1]
AE2 AE8
DDR_CS0_DIMMA# <10> DDR_CS1_DIMMA# <10>
SA_ODT[0] SA_ODT[1]
AD8 AF9
M_ODT0 <10> M_ODT1 <10>
SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]
B9 D7 H7 M7 AG6 AM7 AN10 AN13
DD R_A_DM0 DD R_A_DM1 DD R_A_DM2 DD R_A_DM3 DD R_A_DM4 DD R_A_DM5 DD R_A_DM6 DD R_A_DM7
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
C9 F8 J9 N9 AH7 AK9 AP11 AT13
DD R_A_DQS#0 DD R_A_DQS#1 DD R_A_DQS#2 DD R_A_DQS#3 DD R_A_DQS#4 DD R_A_DQS#5 DD R_A_DQS#6 DD R_A_DQS#7
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
C8 F9 H9 M9 AH8 AK10 AN11 AR13
DDR _A_DQS0 DDR _A_DQS1 DDR _A_DQS2 DDR _A_DQS3 DDR _A_DQS4 DDR _A_DQS5 DDR _A_DQS6 DDR _A_DQS7
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
DDR_A_M A0 DDR_A_M A1 DDR_A_M A2 DDR_A_M A3 DDR_A_M A4 DDR_A_M A5 DDR_A_M A6 DDR_A_M A7 DDR_A_M A8 DDR_A_M A9 DDR_A_MA 10 DDR_A_MA 11 DDR_A_MA 12 DDR_A_MA 13 DDR_A_MA 14 DDR_A_MA 15
DDR_B _D0 DDR_B _D1 DDR_B _D2 DDR_B _D3 DDR_B _D4 DDR_B _D5 DDR_B _D6 DDR_B _D7 DDR_B _D8 DDR_B _D9 DDR_ B_D10 DDR_ B_D11 DDR_ B_D12 DDR_ B_D13 DDR_ B_D14 DDR_ B_D15 DDR_ B_D16 DDR_ B_D17 DDR_ B_D18 DDR_ B_D19 DDR_ B_D20 DDR_ B_D21 DDR_ B_D22 DDR_ B_D23 DDR_ B_D24 DDR_ B_D25 DDR_ B_D26 DDR_ B_D27 DDR_ B_D28 DDR_ B_D29 DDR_ B_D30 DDR_ B_D31 DDR_ B_D32 DDR_ B_D33 DDR_ B_D34 DDR_ B_D35 DDR_ B_D36 DDR_ B_D37 DDR_ B_D38 DDR_ B_D39 DDR_ B_D40 DDR_ B_D41 DDR_ B_D42 DDR_ B_D43 DDR_ B_D44 DDR_ B_D45 DDR_ B_D46 DDR_ B_D47 DDR_ B_D48 DDR_ B_D49 DDR_ B_D50 DDR_ B_D51 DDR_ B_D52 DDR_ B_D53 DDR_ B_D54 DDR_ B_D55 DDR_ B_D56 DDR_ B_D57 DDR_ B_D58 DDR_ B_D59 DDR_ B_D60 DDR_ B_D61 DDR_ B_D62 DDR_ B_D63
DDR _A_DM[0..7] <10>
DDR _A_DQS#[0..7] <10>
DDR _A_DQS[0..7] <10>
DDR_A_MA[0..15] <10>
B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10
SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
<11> D DR_B_BS0 <11> D DR_B_BS1 <11> D DR_B_BS2
AB1 W5 R7
SB_BS[0] SB_BS[1] SB_BS[2]
<11> DD R_B_CAS# <11> DD R_B_RAS# <11> DDR _B_WE#
AC5 Y7 AC6
SB_CAS# SB_RAS# SB_WE#
SB_CK[0] SB_CK#[0] SB_CKE[0]
W8 W9 M3
M _CLK_DDR2 <11> M _CLK_DDR#2 <11> DDR_CKE2_DIMMB <11>
SB_CK[1] SB_CK#[1] SB_CKE[1]
V7 V6 M2
M _CLK_DDR3 <11> M _CLK_DDR#3 <11> DDR_CKE3_DIMMB <11>
SB_CS#[0] SB_CS#[1]
AB8 AD6
DDR_CS2_DIMMB# <11> DDR_CS3_DIMMB# <11>
SB_ODT[0] SB_ODT[1]
AC7 AD1
M_ODT2 <11> M_ODT3 <11>
SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]
D4 E1 H3 K1 AH1 AL2 AR4 AT8
D
DDR _B_DM[0..7] <11>
DD R_B_DM0 DD R_B_DM1 DD R_B_DM2 DD R_B_DM3 DD R_B_DM4 DD R_B_DM5 DD R_B_DM6 DD R_B_DM7
C
DDR SYSTEM MEMORY - B
D
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]
D5 F4 J4 L4 AH2 AL4 AR5 AR8
DD R_B_DQS#0 DD R_B_DQS#1 DD R_B_DQS#2 DD R_B_DQS#3 DD R_B_DQS#4 DD R_B_DQS#5 DD R_B_DQS#6 DD R_B_DQS#7
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
C5 E3 H4 M5 AG2 AL5 AP5 AR7
DDR _B_DQS0 DDR _B_DQS1 DDR _B_DQS2 DDR _B_DQS3 DDR _B_DQS4 DDR _B_DQS5 DDR _B_DQS6 DDR _B_DQS7
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
DDR_B_M A0 DDR_B_M A1 DDR_B_M A2 DDR_B_M A3 DDR_B_M A4 DDR_B_M A5 DDR_B_M A6 DDR_B_M A7 DDR_B_M A8 DDR_B_M A9 DDR_B_MA 10 DDR_B_MA 11 DDR_B_MA 12 DDR_B_MA 13 DDR_B_MA 14 DDR_B_MA 15
DDR _B_DQS#[0..7] <11>
DDR_ B_DQS[0..7] <11>
DDR_B_MA[0..15] <11>
B
I C,AUB_CFD_rPGA,R1P0 ME@ I C,AUB_CFD_rPGA,R1P0 ME@
A
A
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Arrandale(3/5)-DDR III
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
7
of
51
5
4
3
2
1
R1 32 GFX _IMON
1 1K_0402_5%
2 DI S@
+CP U_CORE
AS NO CONNECT
+GFX_CORE
J CP U1F
J C PU1G
2
C 189 UMA@
1
2
1
C1 59 UMA@
C5 91
1
C5 92
UMA@ 2
2
1
UMA@ 2
1 2
R 559 0_0402_5% DI S@
+ VCCP
AR25 GFX_V R_EN AT25 AM24 GFX _IMON
2 R1 41 0_0402_5%
1
1
2
2
1
2
1
1.1V
H_V I D[0..6] <48>
H_V ID0 H_V ID1 H_V ID2 H_V ID3 H_V ID4 H_V ID5 H_V ID6 PM_DPRSLP VR_R 1 R56
VCCPLL1 VCCPLL2 VCCPLL3
2
L26 L27 M26
G15 VTT_SELECT
2
IC,AUB_CFD_rPGA,R1P0 ME@
P ROC_DPRSLPVR <48>
1
+1.5V
+ 1.5V_DDR3
J3 2
2
1
Modify for cost revew. 09/16/2009
C
1
2
1
2
1
2
1
2
1
2
1
2
B
For Intel S3 Power Reduction.
1
@
VTT_SELECT <46>
2
1
+1.8VS
1
2 0_0402_5%
2
1
C 170 4.7U_0603_6.3V6K
1.8V
0.6A
1
C 169 10U_0805_10V4K
POWER
<48>
1
C 168 2.2U_0603_6.3V4Z
CPU VIDS
2
GFXVR_EN <47> GFXVR_DPRSLPVR <47> GFXVR_IMON <47>
+VCCP C 218 10U_0805_10V4K
VTT_SELECT
1
UMA@
+ VCCP
C 149 1U_0603_10V4Z
AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34
2
2 4.7K_0402_5%
1
C 257 1U_0603_10V4Z
J22 J20 J18 H21 H20 H19
2
C 167 1U_0603_10V4Z
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR
PSI#
1
VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58
PEG & DMI
AN33
2
C2 40 10U_0805_10V4K
PSI#
1
C2 72 10U_0805_10V4K
2
C2 15 10U_0805_10V4K
2 1K_0402_5%
GFX_V R_EN
C 213 10U_0805_10V4K
VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68
1 @ +
2
1
2
C2 14 10U_0805_10V4K
1 R 608 1
R 140
C2 12 10U_0805_10V4K
P10 N10 L10 K10
2
1
C 255 1U_0603_10V4Z
VTT0_59 VTT0_60 VTT0_61 VTT0_62
1
C2 73 10U_0805_10V4K
AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1
C2 58 22U_0805_6.3V6M
VTT1_45 VTT1_46 VTT1_47
3A
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18
+ VCCP K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25
<47> <47> <47> <47> <47> <47> <47>
UMA@ GFX_VR_EN GFX_DPRSLPVR GFX_IMON
C2 52 22U_0805_6.3V6M
2
D
GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6
C2 68 220U_B2_2.5VM_R35
2
1
J24 J23 H25
FDI
1
C2 11 10U_0805_10V4K
2
C2 10 10U_0805_10V4K
2
1
C2 09 10U_0805_10V4K
1
C2 08 10U_0805_10V4K
AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15
AM22 AP22 AN22 AP23 AM23 AP24 AN24
DESIGN GUIDE REV1.1
+ 1.5V_DDR3
+ VCCP VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44
GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]
(~15MW) MAYBE WASTED
C 253 1U_0603_10V4Z
2
VAXG_SENSE VSSAXG_SENSE
C 256 1U_0603_10V4Z
2
1
15A
VCC_AXG_SENSE <47> VSS_AXG_SENSE <47>
C 254 1U_0603_10V4Z
1
SENSE LINES
1
GRAPHICS VIDs
2
C 190 @
C2 07 10U_0805_10V4K
2
2
1
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_6.3V6M
C2 74 10U_0805_10V4K
1
C2 17 10U_0805_10V4K
2
C2 19 10U_0805_10V4K
1
2
C1 91 @
- 1.5V RAILS
2
1
1
AR22 AT22
DDR3
2
1
+ 2
C1 60 @
VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36
GRAPHICS
@
2
1
2
C5 54 C2 00 330U_D2_2.5VY_R9M 10U_0805_10V4K
2
1
1
1
C1 82 10U_0805_10V4K
@
2
C1 81 10U_0805_10V4K
1
1
C2 16 10U_0805_10V4K
2
2
C2 70 10U_0805_10V4K
1
1
C1 98 10U_0805_10V4K
2
C1 99 10U_0805_10V4K
1
C2 71 10U_0805_10V4K
IMVP_IMON <48>
V CCSENSE <48> VSSSENSE <48>
SI4800BDY-T1-E3_SO8 R2 68 20K_0402_5%
VTT_SENSE <46> @ P AD T15 1
1.5V_DDR3_GATE
VCCSENSE VSS SENSE
1 R 552 1 R 551
Q23 2N7002_SOT23 1
S
2
2
1
2
1
2
2
SUSP
1 R2 33 220_0402_5% D
S
Q19 BSS138_NL_SOT23-3
2 G
R2 67 0_0402_5% @
2
A
C 325 0.1U_0603_25V7K
For Intel S3 Power Reduction.
+C PU_CORE
Compal Secret Data
Security Classification
2 100_0402_1% 2 100_0402_1%
Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
I C,AUB_CFD_rPGA,R1P0 ME@
5
+ 1.5V_DDR3
1
1
D
2 G 3
<39,44,45> SUSP
Close to CPU
1
C2 86 0.1U_0402_10V6K
0_0402_5% VCCSENSE VSS SENSE 0_0402_5%
@
1 2 3 4
C2 87 0.1U_0402_10V6K
2 2
S S S G
C2 88 0.1U_0402_10V6K
VTT_SENSE VSS_SENSE_VTT
B15 A15
1 R 554 1 R 553
D D D D
C2 89 0.1U_0402_10V6K
VCC_SENSE VSS_SENSE
AJ34 VCC_SENSE AJ35 VSS _SENSE
1
U11 8 7 6 5
+5VALW
2
AN35
C2 69 0.1U_0402_10V6K
ISENSE
JUMP_43X118
+1 .5V_DDR3
2
+1.5V
@
H_VTTVID1 = High, 1.05V FOR Auburndale
12
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
3
JUMP_43X118 J2 2 2 1 1
CPU
A
VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32
C1 61 @
AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16
+ VCCP
CPU CORE SUPPLY
B
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100
AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11
C2 01 10U_0805_10V4K
C
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26
SENSE LINES
D
+ VCCP
18A
1.1V RAIL POWER
48A
BUT A SMALL AMOUNT OF POWER
10U_0805_6.3V6M
POWER
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
4
3
2
Title
Compal Electronics, Inc. Arrandale(4/5)-PWR
Size D ocument Number Cus tom Dat e:
Rev 0.3
LA-5752P
Thursday, October 29, 2009 1
Sheet
8
of
51
5
4
3
2
CPU CORE
+C PU_CORE
J CP U 1H
2
1
2
1
2
C5 71 22U_0805_6.3V6M
2
1
C5 72 22U_0805_6.3V6M
2
1
C5 77 22U_0805_6.3V6M
2
1
C5 83 22U_0805_6.3V6M
2
1
C5 78 22U_0805_6.3V6M
2
1
C5 84 22U_0805_6.3V6M
2
1
C5 73 22U_0805_6.3V6M
2
1
C5 74 22U_0805_6.3V6M
2
1
C5 79 22U_0805_6.3V6M
2
1
Inside cavity
D
1
2
2 3
1 + 2 3
1 + 2 3
1
2
1
2
1
2
1
2
C1 29 22U_0805_6.3V6M
+
C 87 22U_0805_6.3V6M
2 3
1
C 90 22U_0805_6.3V6M
+
C 91 22U_0805_6.3V6M
1
between Inductor and socket
C1 64 470U_D2T_2VM
2
2
C 92 470U_D2T_2VM
1
1
C 75 470U_D2T_2VM
2
2
C 76 470U_D2T_2VM
1
1
C 194 10U_0805_6.3V6M
2
2
C 165 10U_0805_6.3V6M
1
1
C1 97 10U_0805_6.3V6M
2
2
C 148 10U_0805_6.3V6M
1
1
C 89 10U_0805_6.3V6M
2
2
C 166 10U_0805_6.3V6M
1
1
C1 80 10U_0805_6.3V6M
2
2
C 193 10U_0805_6.3V6M
1
1
C1 96 10U_0805_6.3V6M
2
2
C 88 10U_0805_6.3V6M
1
1
C 179 10U_0805_6.3V6M
2
C 162 10U_0805_6.3V6M
1
C1 92 10U_0805_6.3V6M
IC,AUB_CFD_rPGA,R1P0 ME@
Under cavity
VSS
470uF 4.5mohm C
NCTF
VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233
C5 80 22U_0805_6.3V6M
1 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9
C 163 10U_0805_6.3V6M
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
C5 85 22U_0805_6.3V6M
VSS
VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160
C1 95 10U_0805_6.3V6M
B
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80
C 147 10U_0805_6.3V6M
C
J CP U 1I C5 68 22U_0805_6.3V6M
D
AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35
1
VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7
AT35 AT1 AR34 B34 B2 B1 A35
VSS_NCTF1_R VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R
B
I C,AUB_CFD_rPGA,R1P0 ME@
A
A
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. Arrandale(5/5)-GND/Bypass
Size D ocument Number Cus tom Dat e:
Rev 0.3
LA-5752P
Thursday, October 29, 2009 1
Sheet
9
of
51
5
4
+1.5V
3
3A@ 1.5V
DDR_A _D2 DDR_A _D3 DDR_A _D8 DDR_A _D9 DD R_A_DQS#1 DDR _A_DQS1 DDR_ A_D10 DDR_ A_D11 DDR_ A_D16 DDR_ A_D17 DD R_A_DQS#2 DDR _A_DQS2 DDR_ A_D18 DDR_ A_D19 DDR_ A_D24 DDR_ A_D25 DD R_A_DM3 DDR_ A_D26 DDR_ A_D27
C
<7> DDR_CKE0_DIMMA
DDR_CKE0_DIM MA
<7> DDR_A_BS2
D DR_A_BS2 DDR_A_MA 12 DDR_A_M A9 DDR_A_MA8 DDR_A_M A5 DDR_A_M A3 DDR_A_M A1
<7> M _CLK_DDR0 <7> M_CLK_DDR#0
M _CLK_DDR0 M _CLK_DDR#0
<7> DDR_A_BS0
DDR_A_MA 10 D DR_A_BS0
<7> DDR _A_WE# <7> DD R_A_CAS#
DDR _A_WE# DD R_A_CAS#
<7> DDR_CS1_DIMMA#
DDR_A_MA 13 DDR_CS1_DIMM A#
B
DDR_ A_D34 DDR_ A_D35
1 DDR_CKE1_DIMMA <7>
C
DDR_A_MA 15 DDR_A_MA 14 DDR_A_MA11 DDR_A_M A7 DDR_A_MA6 DDR_A_M A4 DDR_A_M A2 DDR_A_M A0 M _CLK_DDR1 M _CLK_DDR#1 D DR_A_BS1 DD R_A_RAS# DDR_CS0_DIMM A# M _ODT0 M _ODT1
M _CLK_DDR1 <7> M_CLK_DDR#1 <7> DDR_A_BS1 <7> DD R_A_RAS# <7> DDR_CS0_DIMMA# <7> M_ODT0 <7> M_ODT1 <7>
DDR_ A_D36 DDR_ A_D37
1
DD R_A_DM4 2
DDR_ A_D38 DDR_ A_D39
+VREF_DQ_DIMMA
1
2
Layout Note: Place near DIMM
B
+1.5V
2
2
2
6*0603 10uf (PER CONNECTOR)
DD R_A_DM6
2
1
2
1
2
1
2
1 +
C5 69 220U_B2_2.5VM_R35
2
VTT(0.75V) =
DDR_ A_D54 DDR_ A_D55
3*0805 10uf 4*0402 1uf VREF =
DDR_ A_D60 DDR_ A_D61
1*0402 0.1uf
DD R_A_DQS#7 DDR _A_DQS7
2
1
2
1
2
1
2
1U_0603_10V4Z
2
1
C3 01
PM_EXTTS#1_R <5,11> SMB_DATA_S3 <11,12,14,28> SMB_CLK_S3 <11,12,14,28>
1
1U_0603_10V4Z
PM_EXTTS#1_R S MB_DATA_S3 SMB _CLK_S3
1*0402 2.2uf
1U_0603_10V4Z
1*0402 0.1uf
DDR_ A_D62 DDR_ A_D63
+0.75VS
1*0402 2.2uf
VDDSPD (3.3V)=
A
+0.75VS
0.
[email protected]
FOX_AS0A626-U4SN-7F ME@
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
1
C 316 0.1U_0402_10V6K
2
1
C 317 0.1U_0402_10V6K
2
1
C 315 0.1U_0402_10V6K
2
1
C 314 0.1U_0402_10V6K
2
1
C 308
@
1
10U_0603_6.3V6M
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
DDR_ A_D52 DDR_ A_D53
2
1
10U_0603_6.3V6M
@
1
C 570
VDDQ(1.5V) =
DDR_ A_D46 DDR_ A_D47
1
C 309
DD R_A_DQS#5 DDR _A_DQS5
10U_0603_6.3V6M
DDR_ A_D44 DDR_ A_D45
C3 00
1
DDR_CKE1_DIM MA
10U_0603_6.3V6M
2
DDR_ A_D30 DDR_ A_D31
C6 06
206
DD R_A_DQS#3 DDR _A_DQS3
C 310
G2
DDR_ A_D28 DDR_ A_D29
1U_0603_10V4Z
G1
DDR_ A_D22 DDR_ A_D23
C6 07
205
DD R_A_DM2
1U_0603_10V4Z
2
R5 71 10K_0402_5%
2
1
C 617 0.1U_0402_10V6K
1
C 608 2.2U_0603_6.3V4Z
+3VS A
For Arranale only +VREF_DQ_DIMMA supply from a external 1.5V voltage divide circuit. 07/17/2009
DDR_ A_D20 DDR_ A_D21
C6 05
DDR_ A_D58 DDR_ A_D59 1 R5 70 2 10K_0402_5%
DRAMRST# <5,11>
DDR_ A_D14 DDR_ A_D15
10U_0603_6.3V6M
DD R_A_DM7
DD R_A_DM1 DRAMRST#
C 581
DDR_ A_D56 DDR_ A_D57
D
C 586
DDR_ A_D50 DDR_ A_D51
+VREF_DQ_DIMMA
R3 05 1K_0402_1%
DDR_ A_D12 DDR_ A_D13
10U_0603_6.3V6M
DD R_A_DQS#6 DDR _A_DQS6
DDR_A _D6 DDR_A _D7
C 588
DDR_ A_D48 DDR_ A_D49
DD R_A_DQS#0 DDR _A_DQS0
10U_0603_6.3V6M
DDR_ A_D42 DDR_ A_D43
<7> DDR_A_MA[0..15]
C 589
DD R_A_DM5
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
R 297 1K_0402_1%
<7> DDR _A_DQS#[0..7]
10U_0603_6.3V6M
DDR_ A_D40 DDR_ A_D41
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
<7> DDR_ A_DQS[0..7] DDR_A _D4 DDR_A _D5
C 355 2.2U_0603_6.3V4Z
DD R_A_DQS#4 DDR _A_DQS4
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
C 346 0.1U_0402_10V6K
DDR_ A_D32 DDR_ A_D33
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
1
2
DD R_A_DM0
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
2
1
C 347 2.2U_0603_6.3V4Z
2 D
C 303 0.1U_0402_10V6K
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
+1.5V
<7> DDR _A_DM[0..7]
JDIMM1 DDR_A _D0 DDR_A _D1
1
<7> DDR_A _D[0..63]
DDR3 SO-DIMM A +VREF_DQ_DIMMA
2
+1.5V
2
+VREF_DQ_DIMMA
4
3
2
Title
Compal Electronics, Inc. DDRIII-SODIMM SLOT1
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
10
of
51
5
4
+1.5V 3 A @ 1 . 5 V
+VREF_DQ_DIMMB
3
+1.5V
2
1
<7> DDR _B_DQS#[0..7] <7> DDR_B _D[0..63]
2
DDR_B _D2 DDR_B _D3 DDR_B _D8 DDR_B _D9 DD R_B_DQS#1 DDR _B_DQS1 DDR_ B_D10 DDR_ B_D11 DDR_ B_D16 DDR_ B_D17 DD R_B_DQS#2 DDR _B_DQS2 DDR_ B_D18 DDR_ B_D19 DDR_ B_D24 DDR_ B_D25 DD R_B_DM3 DDR_ B_D26 DDR_ B_D27
<7> DDR_CKE2_DIMMB
DDR_CKE2_DIM MB
<7> D DR_B_BS2
D DR_B_BS2
C
DDR_B_MA 12 DDR_B_M A9 DDR_B_MA8 DDR_B_M A5 DDR_B_M A3 DDR_B_M A1 <7> M _CLK_DDR2 <7> M _CLK_DDR#2
M _CLK_DDR2 M _CLK_DDR#2
<7> D DR_B_BS0
DDR_B_MA 10 D DR_B_BS0
<7> DDR_ B_WE# <7> DD R_B_CAS#
DDR _B_WE# DD R_B_CAS#
<7> DDR_CS3_DIMMB#
DDR_B_MA 13 DDR_CS3_DIMM B#
DDR_CKE3_DIM MB
1
DDR_CKE3_DIMMB <7> C
DDR_B_MA 15 DDR_B_MA 14 DDR_B_MA11 DDR_B_M A7 DDR_B_MA6 DDR_B_M A4 DDR_B_M A2 DDR_B_M A0 M _CLK_DDR3 M _CLK_DDR#3 D DR_B_BS1 DD R_B_RAS# DDR_CS2_DIMM B# M _ODT2 M _ODT3
M _ CLK_DDR3 <7> M _CLK_DDR#3 <7> D DR_B_BS1 <7> DDR _B_RAS# <7>
M_ODT3 <7>
DDR_ B_D36 DDR_ B_D37
DD R_B_DM6 DDR_ B_D54 DDR_ B_D55 DDR_ B_D60 DDR_ B_D61 DD R_B_DQS#7 DDR _B_DQS7
0.
[email protected]
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
B
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs) 6*0603 10uf (PER CONNECTOR) Layout Note: Place near DIMM
VTT(0.75V) = 3*0805 10uf 4*0402 1uf 1*0402 0.1uf
+0.75VS
1*0402 2.2uf
VDDSPD (3.3V)= 1*0402 0.1uf
1*0402 2.2uf 1
PM_EXTTS#1_R <5,10> SMB_DATA_S3 <10,12,14,28> SMB_CLK_S3 <10,12,14,28> +0.75VS
2
1
2
1
2
1
2
A
TYCO_2-2013297-2~D ME@
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
1
VDDQ(1.5V) =
DDR_ B_D62 DDR_ B_D63 PM_EXTTS#1_R S MB_DATA_S3 SMB _CLK_S3
2
1
C3 06 0.1U_0402_10V6K
DDR_ B_D52 DDR_ B_D53
2
1
C3 05 0.1U_0402_10V6K
DDR_ B_D46 DDR_ B_D47
1
C3 04 0.1U_0402_10V6K
DD R_B_DQS#5 DDR _B_DQS5
2
@
C3 07 0.1U_0402_10V6K
DDR_ B_D44 DDR_ B_D45
1
C3 12
@
C5 75
2
+1.5V 10U_0603_6.3V6M
1
C5 90
2
+VREF_DQ_DIMMB
10U_0603_6.3V6M
1
DD R_B_DM4 DDR_ B_D38 DDR_ B_D39
Layout Note: Place near DIMM
DDR_CS2_DIMMB# <7> M_ODT2 <7>
10U_0603_6.3V6M
206
DDR_ B_D30 DDR_ B_D31
C5 98 1U_0603_10V4Z
GND1
DD R_B_DQS#3 DDR _B_DQS3
C3 13
GND1
DDR_ B_D28 DDR_ B_D29
C2 99 1U_0603_10V4Z
2
205
DDR_ B_D22 DDR_ B_D23
C5 95 1U_0603_10V4Z
2
1
C 616 0.1U_0402_10V6K
1
C 618 2.2U_0603_6.3V4Z
+3VS A
1 R5 72 2 10K_0402_5% 1 2 R5 73 10K_0402_5%
For Arranale only +VREF_DQ_DIMMB supply from a external 1.5V voltage divide circuit. 07/17/2009
DD R_B_DM2
C5 96 10U_0603_6.3V6M
DDR_ B_D58 DDR_ B_D59
DDR_ B_D20 DDR_ B_D21
10U_0603_6.3V6M
DD R_B_DM7
DRAMRST# <5,10>
10U_0603_6.3V6M
DDR_ B_D56 DDR_ B_D57
D
DDR_ B_D14 DDR_ B_D15
C3 11
DDR_ B_D50 DDR_ B_D51
DD R_B_DM1 DRAMRST#
C5 76
DD R_B_DQS#6 DDR _B_DQS6
+VREF_DQ_DIMMB
R3 40 1K_0402_1%
10U_0603_6.3V6M
DDR_ B_D48 DDR_ B_D49
DDR_ B_D12 DDR_ B_D13
C5 87
DDR_ B_D42 DDR_ B_D43
DDR_B _D6 DDR_B _D7
10U_0603_6.3V6M
DD R_B_DM5
R 341 1K_0402_1%
<7> DDR_B_MA[0..15]
DD R_B_DQS#0 DDR _B_DQS0
C5 82
DDR_ B_D40 DDR_ B_D41
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
DDR_B _D4 DDR_B _D5
10U_0603_6.3V6M
DDR_ B_D34 DDR_ B_D35
CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT
<7> DDR _B_DQS[0..7]
C3 83 2.2U_0603_6.3V4Z
DD R_B_DQS#4 DDR _B_DQS4 B
CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
C3 85 0.1U_0402_10V6K
DDR_ B_D32 DDR_ B_D33
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS
2
DD R_B_DM0
VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS
1
DDR_B _D0 DDR_B _D1
1 C3 84
C3 82
2
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
D
1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
2
+VREF_DQ_DIMMB
+1.5V
<7> DDR _B_DM[0..7]
JDIMM2
4
3
2
Title
Compal Electronics, Inc. DDRIII-SODIMM SLOT2
Size
D ocument Number
Rev 0.3
LA-5752P Dat e:
Thursday, October 29, 2009 1
Sheet
11
of
51
5
4
3
2
1
Reserve for Low Power CLK GEN. RTM890N-632 SLG8LV597VTR +3VS_CK505
VDD_3V3_1V5
1 0_0603_5%
2 R2 78
@
+1.5VS
1 PCS CAP(0.1u) BY 1 INPUT PIN
D
1 0_0603_5%
1. 27M_CLK_SS
+3VS_CK505
VDD_3V3_1V5
5. CLK_14M_PCH
R3 18 CLK_BUF_DOT96 1 CLK_BUF_DOT96# 1 R3 19
<14> CLK_BUF_DOT96 <14> CLK_BUF_DOT96#
0_0402_5% 2 2
L_CLK_BUF_DOT96 L_CLK_BUF_DOT96# 0_0402_5% CLK_48M_CR_R
CLOSE U27 CL K_BUF_CKSSCD R 324 CL K_BUF_CKSSCD# R 308
<14> CLK _BUF_CKSSCD <14> CL K_BUF_CKSSCD#
C
CLK_DMI CLK_DMI#
<14> CLK_DMI <14> CLK_DMI#
+3VS_CK505
CLK _BUF_CKSSCD_R 2 0_0402_5% CL K_BUF_CKSSCD#_R 2 0_0402_5% 2 0_0402_5% L_CLK_DMI L_CLK_DMI# 2 0_0402_5% CPU_S TOP# 2 10K_0402_5%
1 1
R 307 R 306
1 1
R 299
1
2
+1.05VS_CK505 U14
3. CLK_BUF_CKSSCD 4. CLK_BUF_DOT96
1
1
2
C3 30 0.1U_0402_10V6K
1. 27M_CLK
2. CLK_BUF_BCLK
2
C3 34 0.1U_0402_10V6K
CLK GEN TO VGA
1. CLK_DMI
1
C3 66 0.1U_0402_10V6K
2
C3 36 10U_0805_10V4K
1
CLK GEN TO PCH
+3VS_CK505
1 2 3 4 5 6 7 8
VDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_48
9 10 11 12 13 14 15 16
VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP#
33
TGND
D
VDD_3V3_1V5
2 R2 69
+1.05VS_CK505
SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD#
32 31 30 29 28 27 26 25
SMB _CLK_S3 S MB_DATA_S3 R EF_0/CPU_SEL
VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRC
24 23 22 21 20 19 18 17
VDD_3V3_1V5 R2 75 R _CLK_BUF_BCLK 1 R_CLK_BUF_BCLK# 1 R2 76
2
1 R 315 CLK_14M_PCH 33_0402_1%
SMB_CLK_S3 <10,11,14,28> SMB_DATA_S3 <10,11,14,28> CLK_14M_PCH <14>
CLK _XTAL_IN CLK_XTAL_OUT CK _P WRGD 0_0402_5% 2 CLK_BUF_BCLK 2 CLK_BUF_BCLK# 0_0402_5%
CLK_BUF_BCLK <14> CLK_BUF_BCLK# <14>
C
VDD_3V3_1V5
SLG8SP587VTR_QFN32_5X5 CK _P WRGD
2
1
2
1
2
C 335 0.1U_0402_10V6K
1
C 343 0.1U_0402_10V6K
2
C 332 0.1U_0402_10V6K
1
C 331 10U_0805_10V4K
C 333 10U_0805_10V4K
2
+3VS_CK505
1
D
RTM890N-631-GRT QFN 32P CLK GEN (SA00003HQ00) ICS9LVS3199AKLFT MLF 32P CLK GEN (SA00003HR00)
2 R 277 1
2 10K_0402_5%
1 PCS CAP(0.1u) BY 1 INPUT PIN 1 0_0603_5%
R2 98 1
+1.05VS_CK505
CLK_48M_CR
1 33_0402_1%
2
CLK_48M_CR_R 2 R 322 0_0402_5%
2 G
CLK_EN# <48>
Q25 S 2N7002_SOT23-3
3
+1.05VS
1 R3 23
@
@
unstuff 09.09.08
PIN8 IS GND FOR ICS3197 PIN8 IS 48MHz FOR ICS3199
B
B
+3VS_CK505 C3 64 2
1 PCS CAP(0.1u) BY 1 INPUT PIN 1 0_0603_5%
1
CLK_14M_PCH 22P_0402_50V8J 14.31818MHZ_16PF_DSX840GA
+3VS
2 R 279
2
1
2
C 367 0.1U_0402_10V6K
2
1
C 350 0.1U_0402_10V6K
1
C 342 0.1U_0402_10V6K
2
C 344 10U_0805_10V4K
1
C 365
2 @
1
R EF_0/CPU_SEL 10P_0402_50V8J
EMI Capacitor
C3 48 22P_0402_50V8J
CLK_XTAL_OUT CLK _XTAL_IN
Y1 2
1
2
2
1
1
C 349 22P_0402_50V8J
+1.05VS
CPU_0
CPU_1
0 (Default)
PIN 30
133MHz
133MHz
1
100MHz
100MHz
1 R 317
2 @ 10K_0402_5%
1 R 316
2 10K_0402_5%
R EF_0/CPU_SEL
A
A
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. CLOCK GENERATOR
Size
D ocument Number
Rev 0 .3
LA-5752P Dat e:
Thursday, October 29, 2009 1
Sheet
12
of
51
5
4
3
2
1
PCH_RTCX1
OSC NC
4
OSC NC
D
C1 83 15P_0402_50V8J
2
A16
INTRUDER#
PCH_INTVRMEN
A14
INTVRMEN
R 168 1
2 33_0402_5%
R 167 1
2 33_0402_5%
R 169 1
<33> HD A_RST_CODEC#
2 33_0402_5%
<33> HDA _ SDIN1
BITCLK
A30
R 166 1
<33> HDA _SDOUT_CODEC
2 33_0402_5% R4 09 1 R4 25 1
GPIO33 = GPO , internal pull-up,should not be pulled low <34> ME_FLASH R 424 1
+3VALW
@
D29
P CH_SPKR
P1
HDA_RST#
C30
HDA_RST#
HDA _ SDIN0
G30
HDA_SDIN0
HDA _ SDIN1
F30
HDA_SDIN1
E32
HDA_SDIN2
F32
HDA_SDIN3
B29
HDA_SDO
H32
HDA_DOCK_EN# / GPIO33
A34 F34
GPIO23
SERIRQ
AB9
S E RIRQ
LPC
LPC_FRAME# <28,34> T7
P AD
GPIO23 = NATIVE,3.3V,CORE +3VS S E RIRQ <34>
GPIO13
PCH_JTA G_TCK
M3
JTAG_TCK
PCH_JTAG_TMS
K3
JTAG_TMS
PCH_JTAG_TDI
K1
JTAG_TDI
PCH_JTAG_TDO
J2
JTAG_TDO
PCH_JTA G_RST#
J4
TRST#
1
R 479
SATA0RXN SATA0RXP SATA0TXN SATA0TXP
AK7 AK6 AK11 AK9
SATA_ITX_C_DRX_N0 S ATA_ITX_C_DRX_P0
0.01U_0402_16V7K 2 0.01U_0402_16V7K 2
1 C 140 1 C 141
SATA_DTX_C_IRX_N0 S ATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0
SATA_DTX_C_IRX_N0 <32> SATA_DTX_C_IRX_P0 <32> SATA_ITX_DRX_N0 <32> SATA_ITX_DRX_P0 <32>
HDD
SATA1RXN SATA1RXP SATA1TXN SATA1TXP
AH6 AH5 AH9 AH8
SATA_ITX_C_DRX_N1 S ATA_ITX_C_DRX_P1
0.01U_0402_16V7K 2 0.01U_0402_16V7K 2
1 C 427 1 C 428
SATA_DTX_C_IRX_N1 S ATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1
SATA_DTX_C_IRX_N1 <32> SATA_DTX_C_IRX_P1 <32> SATA_ITX_DRX_N1 <32> SATA_ITX_DRX_P1 <32>
ODD
SATA2RXN SATA2RXP SATA2TXN SATA2TXP
AF11 AF9 AF7 AF6
SATA3RXN SATA3RXP SATA3TXN SATA3TXP
AH3 AH1 AF3 AF1
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
AD9 AD8 AD6 AD5
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
AD3 AD1 AB3 AB1
SATAICOMPO
AF16
SATAICOMPI
AF15
C
SATA_DTX_C_IRX_N4 S ATA_DTX_C_IRX_P4 SATA_ITX_C_DRX_N4 S ATA_ITX_C_DRX_P4
0.01U_0402_16V7K 2 0.01U_0402_16V7K 2
R 500 S ATAICOMP 1 2 37.4_0402_1%
SATA_DTX_C_IRX_N4 <37> SATA_DTX_C_IRX_P4 <37> SATA_ITX_DRX_N4_CONN <37> SATA_ITX_DRX_P4_CONN <37>
1 ESATA@ C1 42SATA_ITX _DRX_N4_CONN 1 ESATA@ C1 43SATA_ITX_DRX_P4_CONN
E-SATA
+3VS
+1.05VS
R99 SPI_CLK_PCH
1
2 0_0402_5%
S PI_CLK_PCH_R BA2 SPI_SB _CS0#
1 R 453
2 10K_0402_5%
R 447 10K_0402_5%
AV3
SPI_CS0#
AY3
SPI_CS1#
SATALED#
T3
SPI_SI
AY1
SPI_MOSI
SATA0GP / GPIO21
Y9
GPIO21
GPIO21
SPI_SO_R
AV1
SATA1GP / GPIO19
V1
GPIO19
GPIO19
PCH_JTA G_RST# @ R1 18 10K_0402_5%
SPI_CLK +3VS
R4 82 10K_0402_5%
HDD_ LED# <36>
GPIO21 = GPI,3.3V,CORE SPI_MISO
2
2
@ R75 20K_0402_5%
1K_0402_5% 0_0402_5%
SPKR
2
@ R1 16 100_0402_1%
1
PCH_JTAG_TDI
1
1
@ R1 15 100_0402_1%
@ R73 200_0402_5%
2
PCH_JTAG_TMS
1
1 2
@ R72 200_0402_5%
2 2
HDA_SYNC
J30 GPIO13 = GPI,3.3V,SUS HDA_DOCK_RST# / GPIO13
+3VALW
2
@ R1 17 100_0402_1%
1
PCH_JTAG_TDO
+3VALW
2
1 2 1
@ R74 200_0402_5%
2
B
+3VALW
H DA_SDOUT
2 10K_0402_5%
@
(2009,07,07) +3VALW
C34
LDRQ0# LDRQ1# / GPIO23
HDA_BCLK
HDA _S Y NC
C
flash ME core of strap pin pull down
RTC
2
CL RP2 SHORT PADS
FWH4 / LFRAME#
2 10K_0402_5%
<33> HDA _S Y NC_ CODEC 1 2 @ <33> P CH_SPKR 12P_0402_50V8J C 648
P CH_SPKR 2 1K_0402_5%
SRTCRST#
S M_INTRUDER#
<28,34> <28,34> <28,34> <28,34>
1
@
RTCRST#
D17
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
2
1 R4 52
+3VS
C14
PCH_SRTCRS T#
D33 B33 C32 A32
1
0.1U_0402_16V4Z
： Integr ated VRM enable ：Integra ted VRM disable
PCH_RTCRST#
LAD0 LAD1 LAD2 LAD3
FWH0 / FWH1 / FWH2 / FWH3 /
IHDA
H L
2
RTCX1 RTCX2
SATA
*
12P_0402_50V8J C 647 @ 1 2 <33> H DA_BITCLK_CODEC
1
B13 D13
JTAG
2
C4 41
CLR P1 SHORT PADS
C2 02 1U_0603_10V4Z
2
PCH_RTCX1 PCH_RTCX2
CL RP3 SHORT PADS
SPI
100_0603_1%
S M_INTRUDER# 2 1M_0402_5% PCH_INTVRMEN 2 330K_0402_5%
R4 20 1
1
2
1
1
+R TCVCC
1
3
U 7A
C1 84 1U_0603_10V4Z 1 2 R 419 20K_0402_1% 1 2 R 422 20K_0402_1%
R4 21 1
+RTCBATT
R1 44
1
2
+R TCVCC
1 2
X1 32.768KHZ_12.5PF_9H03200413 1
C1 71
2
+R TCVCC
1
2
15P_0402_50V8J
D
PCH_RTCX2
2 10M_0402_5%
1
1 R1 54
B
GPIO19 = GPI,3.3V,CORE
IBEXPEAK-M_FCBGA1071
1
SPI_CLK_PCH
PCH Pin
RefDes
ES1
PCH_JTAG_TDO
*
No Install 200ohm
No Install
R590
No Install 100ohm
No Install
200ohm
200ohm
PCH_JTA G_TCK
R1 14 1
2 51_0402_5%
(2009,05,04)
MP
R591
R584 PCH_JTAG_TMS
ES2
PCH JTAG Production
R 62
100ohm
100ohm
No Install
R587
200ohm
200ohm
No Install
R586
100ohm
100ohm
No Install
2 SPI_W P# 3.3K_0402_5%
R1 02 1
2 SPI_HOLD# 3.3K_0402_5%
U3
1 SPI_SO_L R1 01 SPI_W P# 15_0402_5%
A
PCH_JTAG_TDI
PCH_JTAG_TCK
PCH_JTAG_RST#
R580
51ohm
R595
20Kohm
20Kohm
No Install
R594
10Kohm
10Kohm
No Install
5
51ohm
1 2 3 4
CS# SO WP# GND
VCC HOLD# SCLK SI
8 7 6 5
C1 38 22P_0402_50V8J @
C 460
+3VS 1
R 103 15_0402_5% SPI_SB _CS0# 1 2 SPI_SO_R 2
No Install
R583
1
FOR INTEL DPDG REV1.6 (MAY 2009)
4M SPI ROM FOR HM55 (ME code & BIOS code) SA00003K800
2
+3VS
PCH JTAG Pre-Production
R1 00 33_0402_5% @
2 0.1U_0402_16V4Z
SPI_HOLD# SPI_CLK_PCH SPI_SI A
S IC FL 16M EN25F16-100HIP SOP 8P
51ohm
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
Compal Electronics, Inc. IBEX-M(1/6)-HDA/JTAG/SATA
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
13
of
51
5
4
3
2
SMB _CLK_S3
PCIE PORT LIST PORT
S MB_DATA_S3
1
1 R1 21 1 R4 06
2 10K_0402_5% 2 10K_0402_5%
SM BCLK
+3VS
1 R1 23 1 R 78 1 R1 48 1 R1 47 1 R4 04 1 R4 03 1 R3 99 1 R1 45 1 R4 00
SMBDATA SML0CLK
DEVICE
S ML0DATA SML1CLK S ML1DATA GPIO74
GPIO60
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
PCIE _PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE _PTX_DRX_N3 PCIE_PTX_DRX_P3
<28> <28> <28> <28>
PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
PCIE _PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE _PTX_DRX_N5 PCIE_PTX_DRX_P5
BF33 BH33 BG32 BJ32
PERN5 PERP5 PETN5 PETP5
BA34 AW34 BC34 BD34
PERN6 PERP6 PETN6 PETP6
AT34 AU34 AU36 AV36 BG34 BJ34 BG36 BJ36 AK48 AK47
WLAN
<28> CLK_PCIE_WLAN1# <28> C LK_PCIE_WLAN1 <28> WLAN_CLKREQ1# +3VS
B
LAN
<29> CLK_PCIE_LAN# <29> CLK_PCIE_LAN <29> CLKREQ_LAN# +3VS
3G
<28> CLK _PCIE_CARD_PCH# <28> CLK _ PCIE_CARD_PCH
3G@ 3G@
<28> PCIECLKREQ3# +3VALW
EXP
<28> CLK_PCIE_EXP_PCH# <28> CLK_PCIE_EXP_PCH
R 431 1
2 10K_0402_5%
R 196 1 R 197 1
2 0_0402_5% C LK_PCIE_WLAN1#_R 2 0_0402_5% C LK_PCIE_WLAN1_R
R 454 1
2 10K_0402_5%
R 220 1 R 221 1
2 0_0402_5% 2 0_0402_5%
R 113 1
2 10K_0402_5%
R 223 1 R 222 1
2 0_0402_5% CLK _ PCIE_CARD_PCH#_R 2 0_0402_5% CLK _P CIE_CARD_PCH_R
GPIO73 = NATIVE,3.3V,SUS
AM43 AM45 U4
+3VALW
NEW CARD
CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18
CLK_PCIE_LAN#_R CLK_PCIE_LAN_R
AM47 AM48 N4
CLKOUT_PCIE2N CLKOUT_PCIE2P
2 Q8B 2N7002DW-T/R7_SOT363-6 3 4
GPIO60
SML0CLK
C6
SML0CLK
SML0DATA
G8
S ML0DATA
SML1ALERT# / GPIO74
M14
GPIO74
SML1CLK / GPIO58
E10
SML1CLK
R79
0_0402_5%
EC_SM B_CK2
EC_SMB_CK2 <34>
SML1DATA / GPIO75
G12
S ML1DATA
R80
0_0402_5%
EC_SM B_DA2
EC_SMB_DA2 <34>
S MB_DATA_S3
SM BCLK
1
SMBDATA
1
R 122 0_0402_5% @ 2
SMB _CLK_S3
@ 2
S MB_DATA_S3
0_0402_5% R 119
SMB_DATA_S3 <10,11,12,28>
EC_THERMAL
DTS , read from EC CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
PEG_A_CLKRQ# / GPIO47
H1
C
PEG_CLKREQ# <19> 10K_0402_5% R4 12 PEG_CLK REQ# 1 2
GPIO47 = 10Kohm PULL DOWN
PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8
J14
DDR3*2 AND CLK GEN
+3VS
SMBDATA
GPIO74 = NATIVE,3.3V,SUS
MINI1
GPIO18 = NATIVE,3.3V,CORE
AD43 AD45
CLK_PCIE_VGA#_R CLK_PCIE_VGA_R
R 524 1 R 525 1
2 0_0402_5% 2 0_0402_5%
CLKOUT_DMI_N CLKOUT_DMI_P
AN4 AN2
CLK _EXP#_R CLK _EXP_R
R 105 1 R 106 1
2 0_0402_5% 2 0_0402_5%
CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P
AT1 AT3
CLKOUT_DP_N CLKOUT_DP_P
CLKOUT_PEG_A_N CLKOUT_PEG_A_P
CLK_PCIE_VGA# <19> CLK_PCIE_VGA <19>
CLK_EXP# <5> CLK_EXP <5> +3VS +3VS +3VS
AW24 BA24
CLK_DMI# <12> C LK_DMI <12>
CLKIN_BCLK_N CLKIN_BCLK_P
AP3 AP1
CLK_BUF_BCLK# <12> CLK_BUF_BCLK <12>
CLKIN_DOT_96N CLKIN_DOT_96P
F18 E18
CLK_BUF_DOT96# <12> CLK_BUF_DOT96 <12>
AH13 AH12
CL K_BUF_CKSSCD# <12> CLK _BUF_CKSSCD <12>
CLKIN_DMI_N CLKIN_DMI_P
R1 24 2.2K_0402_5% Q7A 6
EC_SM B_DA2
CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P
PCIECLKRQ2# / GPIO20
CLK_PCIE_VGA# CLK_PCIE _VGA
R82 2.2K_0402_5%
Q7B EC_SM B_CK2 3
SMB_EC_DA2_R
1
SMB_EC_DA2_R <19,31>
2N7002DW-T/R7_SOT363-6
Nvidia thermal SMB_EC_CK2_R sensor
SMB_EC_CK2_R
4
2N7002DW-T/R7_SOT363-6
<19,31>
B
GPIO20 = NATIVE,3.3V,CORE
R 120 1
2 10K_0402_5%
R 224 1 R 225 1
2 0_0402_5% 2 0_0402_5%
R 435 1
2 10K_0402_5%
AH42 AH41 A8
CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25
REFCLK14IN
P41
CLK_14M_PCH
CLKIN_PCILOOPBACK
J42
C LK_PCI_FB
XTAL25_IN XTAL25_OUT
AH51 AH53
X TAL25_IN XTAL25_OUT
XCLK_RCOMP
AF38
R 491
CLK_14M_PCH <12>
CLK_PCIE_EXP _PCH#_R AM51 CLK_PCIE_EXP _PCH_R AM53 M9
CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26
1
EC_SM B_DA2
R 81 0_0402_5% @ 2 1
EC_SM B_CK2
R 83 0_0402_5% @ 2 1
C LK_PCI_FB <16>
GPIO25 = NATIVE,3.3V,SUS
CLK REQ_EXP#
<28> CLKREQ_EXP#
P9
SML0ALERT# / GPIO60
SMB_CLK_S3 <10,11,12,28>
2 90.9_0402_1%
SMB_EC_DA2_R
SMB_EC_CK2_R
25MHz crystal not used, XTAL25_IN need to GND. (checklist Rev1.6)
+1.05VS
GPIO26 = NATIVE,3.3V,SUS AJ50 AJ52
R 434 1
2 10K_0402_5%
+3VALW
R 457 1
2 10K_0402_5%
H6
GPIO44 = NATIVE,3.3V,SUS
AK53 AK51 P13
CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56
T45
CLKOUTFLEX1 / GPIO65
P43
CLKOUTFLEX2 / GPIO66
T42
CLKOUTFLEX3 / GPIO67
N50
CL K_PCI_DB_R
R1 98 1 @
X TAL25_IN
EMI REQUEST 0303 2 22_0402_5%
C LK_PCI_DB <28>
C LK_PCI_FB
XTAL25_OUT
1 @ R5 98
CLK_14M_PCH
2 1M_0402_5% @ Y4
1 R2 09 33_0402_5% @
IBEXPEAK-M_FCBGA1071
C2 63 22P_0402_50V8J @
A
R 413 33_0402_5% @
2
25MHZ_20P_1BG25000CK1A
C 439 22P_0402_50V8J @
0_0402_5%
GPIO56 = NATIVE,3.3V,SUS
PCIECLKRQ5# / GPIO44
CLKOUTFLEX0 / GPIO64
18P_0402_50V8J
+3VALW
CLKOUT_PCIE5N CLKOUT_PCIE5P
2
+3VALW
LAN
PERN4 PERP4 PETN4 PETP4
SMBDATA
SMB _CLK_S3
SMBCLK
1
C2 20 1 C2 21 1
PERN3 PERP3 PETN3 PETP3
BA32 BB32 BD32 BE32
C8
GPIO11 = NATIVE,3.3V,SUS
2
PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE_PTX_C_DRX_N5 PCIE_PTX_C_DRX_P5
WLAN
PCIE _PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE _PTX_DRX_N4 PCIE_PTX_DRX_P4
SM BCLK
1
EXP C
3G@ C2 31 1 3G@ C2 32 1
AU30 AT30 AU32 AV32
H14
Q8A 2N7002DW-T/R7_SOT363-6 6 1
2
C2 23 1 C2 22 1
LID_OUT#
5
PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_C_DRX_N3 PCIE_PTX_C_DRX_P3
<28> <28> <28> <28>
D
5
<29> <29> <29> <29>
B9
GPIO60 = NATIVE,3.3V,SUS
PERN2 PERP2 PETN2 PETP2
SMBus
2 0.1U_0402_10V6K 2 0.1U_0402_10V6K
SMBDATA
Link
C2 30 1 C2 29 1
PCIE _PRX_DTX_N2 AW30 PCIE_PRX_DTX_P2 BA30 PCIE _PTX_DRX_N2 BC30 PCIE_PTX_DRX_P2 BD30
SMBCLK
Controller
PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2
SMBALERT# / GPIO11
PEG
3G
<28> <28> <28> <28>
PERN1 PERP1 PETN1 PETP1
PCI-E*
LAN
+3VALW
R 407 0_0402_5% U7B BG30 BJ30 BF29 BH29
WLAN
LID_OUT#
EC_LID_OUT# <34>
From CLK BUFFER
D
X WLAN LAN 3G NEW CARD X X X
Clock Flex
1 2 3 4 5 6 7 8
2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%
1 C 630 @ 2
1 C 631
2 A
C631 Resistor Pull down Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. IBEX-M(2/6)-PCI-E/SMBUS/CLK
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
14
of
51
5
4
3
2
1
D
D
<6> <6> <6> <6>
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3
BE22 BF21 BD20 BE18
DMI0TXN DMI1TXN DMI2TXN DMI3TXN
<6> <6> <6> <6>
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3
BD22 BH21 BC20 BD18
DMI0TXP DMI1TXP DMI2TXP DMI3TXP
DMI_IRCOMP 2 49.9_0402_1%
1 R5 20
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
FDI
DMI
+1.05VS
4mil width and place within 500mil of the PCH
：
FDI_INT
BJ14
FDI _INT
FDI_FSYNC0
BF13
FDI_FS Y N C0
FDI_FSYNC1
BH13
FDI_FS Y N C1
FDI_LSYNC0
BJ12
FDI_LS Y NC0
FDI_LSYNC1
BG14
FDI_LS Y NC1
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
<6> <6> <6> <6> <6> <6> <6> <6>
E DI D_CLK EDID_DATA
AB46 V48
L_CTRL_CLK L_CTRL_DATA
AP39 AP41
LVD_IBG LVD_VBG
AT43 AT42
LVD_VREFH LVD_VREFL
<27> LVDS_ACLK# <27> LVDS_ACLK
AV53 AV51
LVDSA_CLK# LVDSA_CLK
<27> LVDS_A0# <27> LVDS_A1# <27> LVDS_A2#
BB47 BA52 AY48 AV47
LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3
<27> LVDS_A0 <27> LVDS_A1 <27> LVDS_A2
BB48 BA50 AY49 AV48
LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3
AP48 AP47
LVDSB_CLK# LVDSB_CLK
AY53 AT49 AU52 AT53
LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3
AY51 AT48 AU50 AT51
LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
AA52 AB53 AD53
CRT_BLUE CRT_GREEN CRT_RED
1 R4 97 1 R4 96
2 2 10K_0402_5% 10K_0402_5%
R5 02 2.37K_0402_1%
T10
P AD
FDI_FS Y NC1 <6> FDI_LS Y NC0 <6> FDI_LS Y NC1 <6>
IC H_POK
R 397 1
SYS_RS T#
S YS_PWROKM6
2 0_0402_5%
1
R4 55 0_0402_5%
R 146
B17 K5
2 10K_0402_5%A10
1
PM_DRAM_PW RGD D9
<5> PM_DRAM_PWRGD R4 01 2 1 10K_0402_5%
+3VALW
T6
2 0_0402_5%
P M_RSMRST#
C16
R4 37 1
2 10K_0402_5% S US _PWR_DN_ACK_RM1 2 0_0402_5% PBTN_OUT#P5 <34> PBTN_OUT# 1 R5 99
SYS_RESET#
WAKE#
SYS_PWROK
CLKRUN# / GPIO32
PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST#
1 R 451
2 AC_PRESENT_R 0_0402_5%
P7
ACPRESENT / GPIO31
1 R1 08
PCIE_WAKE# <28> 2 10K_0402_5%
+3VS
SUS_STAT# / GPIO61
P8
GPIO61
GPIO61 = NATIVE,3.3V,SUS
SUSCLK / GPIO62
F3
GPIO62
GPIO62 = NATIVE,3.3V,SUS
SLP_S5# / GPIO63
E4
SLP_S5# <34>
SLP_S4#
H7
SLP_S4# <34>
SLP_S3#
P12
SLP_S3# <34>
SLP_M#
K8
TP23
N2
<26> DA C _BLU <26> DA C_G RN <26> DA C_R ED
DA C _BLU DA C_G RN DA C_R ED
CRT_DDC_CLK CRT_DDC_DATA
<26> CRT_HS Y NC <26> CRT_V SYNC
Y53 Y51
CRT_HSYNC CRT_VSYNC
Can be left NC when IAMT is not support on the platfrom
R77
1
R 165
1
2
8.2K_0402_1%
GPIO72
A6
BATLOW# / GPIO72
PMSYNCH
GPIO30 = GPI,3.3V,SUS 2
10K_0402_5%
F14
BJ10
H_P M_SYNC <5>
GPIO29 = GPO,3.3V,SUS If not using integrated SLP_LAN# / GPIO29 F6 LAN,signal may be left as NC.
RI#
CRT _IREF AD48 AB51
BJ48 BG48
SDVO_INTN SDVO_INTP
BF45 BH45
DAC_IREF CRT_IRTN
T51 T53
DDPB_AUXN DDPB_AUXP DDPB_HPD
BG44 BJ44 AU38
DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P
BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38
DDPC_CTRLCLK DDPC_CTRLDATA
Y49 AB49
DDPC_AUXN DDPC_AUXP DDPC_HPD
BE44 BD44 AV40
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P
BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36
R5 10 2
10K_0402_5% 1 +3VS
UMA@ R 504 2.2K_0402_5%
UMA@ R 503 2.2K_0402_5%
HD MICLK_NB HDMIDAT_NB
HD MICLK_NB <25> HDMIDAT_NB <25> C
TMDS_B_HPD# <25> TMDS_B_DATA2#_PCH TMDS_B_DATA2_PCH TMDS_B_DATA1#_PCH TMDS_B_DATA1_PCH TMDS_B_DATA0#_PCH TMDS_B_DATA0_PCH TMDS_B_CLK#_PCH TMDS_B_CLK_PCH
C 638 C 639 C 640 C 641 C 642 C 643 C 644 C 645
1 1 1 1 1 1 1 1
UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2 UMA_HDMI@ 0.1U_0402_10V6K 2
HDMI
U50 U52
DDPD_AUXN DDPD_AUXP DDPD_HPD
BC46 BD46 AT38
DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
TMDS_B_DATA2# <25> TMDS_B_DATA2 <25> TMDS_B_DATA1# <25> TMDS_B_DATA1 <25> TMDS_B_DATA0# <25> TMDS_B_DATA0 <25> TMDS_B_CLK# <25> TMDS_B_CLK <25>
IBEXPEAK-M_FCBGA1071
update R492 tolerance for DAC_CRT from 0.5% to 5% (checklist 2.0)
2
+3VALW
SDVO_STALLN SDVO_STALLP
DDPD_CTRLCLK DDPD_CTRLDATA
V51 V53
GPIO31 = GPI,3.3V,SUS B
SDVO_TVCLKINN SDVO_TVCLKINP
SDVO_CTRLCLK SDVO_CTRLDATA
<26> CRT_D DC_CLK <26> C RT_DDC_DATA
R 492 1K_0402_5%
10K_0402_5% 1 2 <34> AC_PRESENT
PWRBTN#
R4 50
Y1
GPIO32 = GPO,3.3V,CORE
SUS_PWR_DN_ACK / GPIO30
@
PCIE_WA KE#
J12
1
<34>
@
System Power Management
R 398 1
+3VALW
R 436
2
VGATE
10K_0402_5% 2
L_BKLTCTL L_DDC_CLK L_DDC_DATA
+3VS
FDI_FS Y NC0 <6>
1
L_BKLTEN L_VDD_EN
Y48 AB48 Y45
<27> E DI D_CLK <27> EDID_DATA
FDI_ INT <6>
2 100K_0402_1%
1
<48>
<34> S U S_PWR_DN_ACK +3VALW
FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7
R4 48 10K_0402_5% 1
R3 96 2
(2009,05,04)
BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12
PCH_PWM
+3VS
Checklist0.8 MEPWROK can be connect to PWROK if iAMT disable
C
FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7
<27>
1
DMI0RXP DMI1RXP DMI2RXP DMI3RXP
P CH_E NVDD
<27> P CH_E NVDD
1
BD24 BG22 BA20 BG20
<6> <6> <6> <6> <6> <6> <6> <6>
2
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
Digital Display Interface
DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7
BJ46 BG46
LVDS
<6> <6> <6> <6>
DMI0RXN DMI1RXN DMI2RXN DMI3RXN
T48 T47
CRT
DMI_CTX_PRX_N0 BC24 DMI_CTX_PRX_N1 BJ22 DMI_CTX_PRX_N2 AW20 DMI_CTX_PRX_N3 BJ20
U7D
PCH_ENBKL
<27> P CH_ENBKL
1
DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3
FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7
2
<6> <6> <6> <6>
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12
2
U7C
B
VGATE
1
A
IC H_POK
2
B
CRT OUT
MC74VHC1G08DFT2G SC70 5P @
G
3
IBEXPEAK-M_FCBGA1071
4
S YS_PWROK
5
P
Y
DA C _BLU
R4 93
1 UMA@ 2 150_0402_1%
DA C_G RN
R4 95
1 UMA@ 2 150_0402_1%
DA C_R ED
R4 94
1 UMA@ 2 150_0402_1%
U28
RSMRST circuit
+3VS
Reserved (2009,09,08)
@ R 402 0_0402_5% 2
1
E BAV99DW-7_SOT363 1 2
2
4
B
5
SLP_S4# SLP_S5#
1 2 R4 18 @ 10K_0402_5% 1 2 R4 17 @ 10K_0402_5% 1 2 R4 16 @ 10K_0402_5%
+3VS
E DI D_CLK
P M_RSMRST# 1 Q14 MMBT3906_SOT23-3 1 2 +3VALW R1 76 4.7K_0402_5%
C
3
<34> EC_RSMRST#
SLP_S3#
R4 58
UMA@
2.2K_0402_5%
EDID_DATA R4 98
UMA@
2.2K_0402_5%
D 8B
1
3
6
D8A BAV99DW-7_SOT363 R 175
A
A
2
2.2K_0402_5%
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. IBEX-M(3/6)-DMI/GPIO/LVDS
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
15
of
51
5
4
3
2
GPIO2 GPIO3 GPIO4 GPIO5
= = = =
F51 A46 B45 M53
REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54
PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3#
F48 K45 F36 H53
GNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55
B41 K53 A36 A48
PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5
K6
<28,34> PCI_RST# R4 08 2
PCIRST#
1 100K_0402_1% P C I_SERR# P C I_PERR#
E44 E50
P CI_IRD Y# PCI_DEVS EL# PCI_FRAM E#
A42 H44 F46 C46
IRDY# PAR DEVSEL# FRAME#
PCI_LOCK#
D49
PLOCK#
AU2
NV_RB#
AV7
NV_WR#0_RE# NV_WR#1_RE#
AY8 AY5
NV_WE#_CK0 NV_WE#_CK1
AV11 BF5
SERR# PERR#
GNT2 Default-Internal pull up
*
Low=Configures DMI for ESI compatible operation(for servers only.Not for mobile/desktops)
<34>
PCI_STOP# P CI_ TRDY#
PCI_PME# P LT_RST#
B
R1 99 1 1
<34> C LK_PCI_LPC <14> C LK_PCI_FB
R2 11
22_0402_5% CL K_PCI_LPC_R 2 CL K_PCI_FB_R 2
D41 C48
STOP# TRDY#
M7
PME#
D5
PLTRST#
N52 P53 P46 P51 P48
CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4
NV_A LE N V_CLE
GPIO27 Default
：
NV_RCOMP 1 R1 04 2 32.4_0402_1%
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#
B25
USBRBIAS
USBRBIAS
D25
：Do not connect(floating)
High Enable s the internal VccVRM to have a clean supply for analog rails. no need to use on board filter circuit.
@
USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3
N16 J16 F16 L16 E14 G16 F12 T15
GPIO1 = GPI,3.3V,CORE GPIO6 = GPI,3.3V,CORE GPIO7 = GPI,3.3V,CORE GPIO8 = GPO,3.3V,SUS USB20_N0 <37> GPIO12 = GPI,3.3V,SUS USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3
<37> <37> <37> <27> <27> <37> <37>
LEFT USB
6
10K_0402_5%
USB20_N5 <38> USB20_P5 <38>
LEFT USB (COMBO)
10K_0402_5% <34> PCH_TEMP_ALERT#
USB20_N8 USB20_P8
USB20_N8 <28> USB20_P8 <28>
USB20_N10 USB20_P10 USB20_N11 USB20_P11
USB20_N10 USB20_P10 USB20_N11 USB20_P11
USB20_N13 USB20_P13
<28> <28> <37> <37>
USB20_N13 <28> USB20_P13 <28> 1 R1 64
TACH3 / GPIO7 GPIO8
1 R 449
2
K9
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
T7
GPIO15
GPIO16
AA2
GPIO17
F38
GPIO22
Y7
GPIO38
R P3 P CI_PIRQG# P CI _PIRQC# PCI_PIRQA# PCI_PIRQE#
1 2 3 4
8 7 6 5
8.2K_0804_8P4R_5%
TACH0 / GPIO17 SCLOCK / GPIO22
1 2 3 4
PCI_GNT0# R 212 1
@
PCI_GNT1# R 210 1
@
8 7 6 5
GPIO24
PROCPWRGD
BE10
THRMTRIP#
BD10
SATA2GP / GPIO36
TP1
BA22
SATA3GP / GPIO37
TP2
AW22
GPIO27 GPIO28 STP_PCI# / GPIO34 SATACLKREQ# / GPIO35
TP4
AY45
TP5
AY46
GPIO46
F1
PCIECLKRQ7# / GPIO46
TP6
AV43
GPIO48
AB6
SDATAOUT1 / GPIO48
TP7
AV45
AA4
SATA5GP / GPIO49
TP8
AF13
GPIO57
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
TP13
AK42
TP14
M32
TP15
N32
TP16
M30
TP17
N30
TP18
H12
TP19
AA23
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
NC_5
T39
2 GPIO57 10K_0402_5% 2 10K_0402_5%
F8
A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31
INIT3_3V# TP24
2 1K_0402_5% 2 1K_0402_5%
8.2K_0804_8P4R_5%
Intel Anti-Theft Techonlogy
High=Enabled NV_ALE Low=Disable(floating)
*
NV_A LE
@ R 515 1
2 1K_0402_5%
1
0
PCI
DMI Termination Voltage
1
SPI
Set to Vcc when HIGH NV_CLE Set to Vss when LOW
2 0_0402_5%
Weak internal PU,Do not pull low @ R98
1
+3VS
2 1K_0402_5%
1 0.1U_0402_16V4Z C6 46
U5
1
2
G
A
1
B
2
Y
R 111 10K_0402_5%
<5> KB _RST#
KB_RST# <34> H_CP UP W RGD <5>
H_THERMTRIP#_L 1 R5 18 2 56_0402_5% 56 5%-->checklist 1.6 R 519 54.9 1%-->CRB 1.0 56_0402_5%
H_THERMTRIP# <5>
+ VCCP
2
+3VALW
1 R4 05
DRAMRST_CNTRL_PCH 10K_0402_5%
C
B
P6
INT3_3V#
C10
TP24
USB PORT LIST PORT
DEVICE
1 2 3 4
8 7 6 5 8.2K_0804_8P4R_5%
1 R4 29
2 10K_0402_5%
GPIO17
R P2
1 R4 85
2 10K_0402_5%
GPIO36
1 R4 84
PCH_TEMP_ALERT# 2 10K_0402_5%
2 R1 07
1 10K_0402_5%
GPIO16
+3VS
@ 1 R4 26
2 10K_0402_5%
E C _SCI#
+3VALW
@ 1 R4 14
2 10K_0402_5%
EC_S MI#
8 7 6 5
+3VS
8.2K_0804_8P4R_5%
NV_ALE Enable Intel Anti-Theft Technology 8.2K PU to +3VS
： Disable Intel Anti-Theft Technology ： floating(internal PD) NV_CLE
Compal Secret Data
Security Classification Issued Date
R 155 100K_0402_5%
2008/08/12
Deciphered Date
2009/08/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VS
4
USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
0 1 2 3 4 5 6 7 8 9 10 11 12 13
DMI termination voltage. weak internal PU, don't PD
P LT_RST#
5
4
<5,19,28,29> BUF_PLT_RST#
P
3
MC74VHC1G08DFT2G SC70 5P @
2 1K_0402_5%
1 2 3 4
+1.8VS
N V_CLE
A16 swap overide Strap/Top-Block Swap Override jumper
H_P ECI
R P1 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3
1
8.2K_0804_8P4R_5%
5
T1
KB _RST#
PCIECLKRQ6# / GPIO45
USB_OC#0 <37> USB_OC#1 <37>
Reserved(NAND)
1 R 149
Low=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *
RCIN#
H_ PECI
TP3
<45>
+3VS
C LK_CPU_BCLK <5>
BG10
SDATAOUT0 / GPIO39
3G CARD
1
8 7 6 5
PCI_GNT3# @ R2 00 1
PECI
SLOAD / GPIO38
Bluetooth
0
2
A
1 2 3 4
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
P3
Within 500 mils minimum spacing to other signal is 15mil
RP 4 PCI_STOP# P CI_IRD Y# P CI _PIRQD# PCI_REQ2#
CLK_CPU_BCLK# <5>
AM1
H3
EXPRESS
Boot BIOS Strap
R P6 PCI_DEVS EL# PCI_LOCK# P C I_SERR# P C I_PERR#
8 7 6 5
AM3
GPIO45
WLAN
PCI_GNT0# PCI_GNT1# Boot BIOS Location 0 0 LPC *
8.2K_0804_8P4R_5%
RP 7 1 2 3 4
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
+3VALW +3VS
8.2K_0804_8P4R_5% PCI_REQ1# PCI_FRAM E# P CI_ TRDY# P CI _PIRQH#
GATEA20 <34>
IBEXPEAK-M_FCBGA1071
RP 5 8 7 6 5
R1 10 10K_0402_5%
U2
A20GATE
GPIO39
22_0402_5% +3VS
1 2 3 4
+3VS
D
SATA4GP / GPIO16
IBEXPEAK-M_FCBGA1071
PCI_REQ0# PCI_PIRQB# P C I_PIRQF# PCI_REQ3#
AF48 AF47
BB22
2 22.6_0402_1%
USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7
CLKOUT_PCIE7N CLKOUT_PCIE7P
V3
1 2 R 480 PCH_TEMP_ALERT#
VGA_EN
AH45 AH46
1
GPIO37 AB13
@
DI S@ R 506 0_0402_5% 1 2
<28,34,39,42,44,46> SUSP#
2
1 R 415 1 R 609
+3VALW
CARD READER
J32 F10
C PUSB# 1 R 433
1 2 R 481 1 2 10K_0402_5% R 109 1 2 10K_0402_5% R 112 1 2 10K_0402_5% R76 DRAMRST_CNTRL_PCH
checklist 2.0 update 2009.0916 USB20_N5 USB20_P5
TACH2 / GPIO6
EC_S MI#
10K_0402_5%
+3VALW
RIGHT USB
D37
H10 GPIO27 if pull down to turn off 1.8V VR @ 2 1 AB12 10K_0402_5% R 507 1 2 GPIO28 V13 +3VALW 10K_0402_5% R 446 2 1 GPIO34 M11 10K_0402_5% R 432 2 1 GPIO35 V6 10K_0402_5% R 456 GPIO36 AB7
<5> DRAMRST_CNTRL_PCH
USB Camera
GPIO6
CLKOUT_PCIE6N CLKOUT_PCIE6P
2
1K_0402_5%
TACH1 / GPIO1
BMBUSY# / GPIO0
1
it have weak internal PU 20K
H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24
OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14
C PUSB#
：
H Intel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality
within 500mil
NV_RCOMP
<28> +3VALW
C38
2
BD3 AY6
*：
GPIO15 L Intel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality
EC_SMI#
Y3
GPIO1
2
NV_ALE NV_CLE
10K_0402_5% <34> E C _SCI# <34>
GPIO0
1
AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6
Check list Rev0.8 section1.23.2 If not implemented, the Braidwood interface signals can be left as No Connect (NC).
1 2 R 483 1 2 R 428 1 2 R 427 E C _SCI#
MISC
NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15
10K_0402_5%
CPU
AV9 BG8
GPIO0 = GPI,3.3V,CORE 10K_0402_5%
GPIO
PIRQA# PIRQB# PIRQC# PIRQD#
PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#
PCI_PIRQE# P C I_PIRQF# P CI_PIRQG# P CI _PIRQH#
GPI,5V,CORE GPI,5V,CORE GPI,5V,CORE GPI,5V,CORE
G38 H51 B37 A44
NV_DQS0 NV_DQS1
GPIO8 Weak internal PU, don't PD +3VS
NCTF
C
C/BE0# C/BE1# C/BE2# C/BE3#
AY9 BD1 AP15 BD8
USB
GPIO18 = NATIVE,5V,CORE GPIO52 = NATIVE,5V,CORE GPIO54 = NATIVE,5V,CORE
J50 G42 H47 G34
NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3
RSVD
PCI_PIRQA# PCI_PIRQB# P CI _PIRQC# P CI _PIRQD#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
PCI
D
H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36
1
U 7F
NVRAM
U 7E
3
2
Title
RIGHT SIDE LEFT SIDE CMOS LEFT SIDE CARD READER
WIRELESS NEW CARD BT
A
3G
Compal Electronics, Inc. IBEX-M(4/6)-PCI/USB/RSVD
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
16
of
51
5
+3VALW
0.
[email protected] 2 0.1U_0402_16V4Z C 454
1
DCPSUS
P18
VCCSUS3_3[29]
U19
VCCSUS3_3[30]
2 0.1U_0402_16V4Z C 139
VCCSUS3_3[31]
U22
VCCSUS3_3[32]
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
2
AT20
VCCIO[10]
AH19
VCCIO[11]
AD20
VCCIO[12]
AF22
VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16]
AD19 AF20 AF19 AH20
VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20]
AB19 AB20 AB22 AD22
VCCME[13] VCCME[14] VCCME[15] VCCME[16]
AA34 Y34 Y35 AA35
A12
VCCRTC
2mA
IBEXPEAK-M_FCBGA1071
AN35
VCC3_3[1]
AT22
VCCVRM[1]
0.035A
BJ18
VCCFDIPLL
6mA
AM23
VCCIO[1]
1 VCC3_3[4]
AD35
VCCVRM[2]
AT24
VCCDMI[1]
AT16
VCCDMI[2]
AU16
VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]
AM8 AM9 AP11 AP9
1
2
6mA
VCCSUSHDA
R5 28 0_0402_5% DI S@
2
1 C 456
2 0.1U_0402_16V4Z
+1.8VS
C
R 509
0.061A
0.156A
2 0_0402_5%
1 + VCCP 1 C 491
1
2
2 1U_0402_6.3V6K
R 508
1
2 0_0402_5%
+1.8VS
R 501
1
2 0_0402_5%
+3VS
@
+3VS
0.085A
1
B
10uH inductor, 120mA L26 1 2 10UH_LB2012T100MR_20%
+1.05VS +PCH_VCC1_1_20 +PCH_VCC1_1_21 +PCH_VCC1_1_22 +PCH_VCC1_1_23
L30 1
2
1 1 1 1
R4 88 R4 87 R4 89 R4 90
2 2 2 2
+5VALW +3VALW 1
C5 07 + 220U_B2_2.5VM_R35 UMA@
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
R 410
1
R 411
1
@
2 0_0402_5%
+3VALW
2
1 C4 94 1U_0402_6.3V4Z 2 @
2 0_0402_5%
+1.5V
R5 21 0_0402_5% @
R 423 10_0402_1%
D6
+5VS
+3VS
R 438 10_0402_1%
D9
CH751H-40PT_SOD323-2 +VCCADPLLB
CH751H-40PT_SOD323-2
P CH_V5REF_SUS
10uH inductor, 120mA 1 1 C5 06 + 220U_B2_2.5VM_R35 UMA@
2
1
2
C4 48 1U_0402_6.3V6K A
Compal Secret Data 2008/08/12
20 mils 1
C 447 1U_0402_6.3V6K
2
C4 93 1U_0402_6.3V4Z 2 @
Deciphered Date
2009/08/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
P CH_V 5 REF_RUN
20 mils
L25 1 2 10UH_LB2012T100MR_20%
Issued Date
4
C4 92 UMA@
2
+VCCADPLLA
Security Classification
5
C 505 UMA@
10U_0805_6.3V6M
IBEXPEAK-M_FCBGA1071
+1.05VS
2
+3VS
+PCH_VRM
+PCH_VRM +1.05VS
C 486 UMA@
2
1
LVDS
VCC3_3[3]
AB35
2
CRT
VCC CORE
2 +1.05VS
VCCIO[54] VCCIO[55]
2
>1mA
CPU
V_CPU_IO[2]
VCCVRM[4]
C 435
1
AU18
AH22
1U_0402_6.3V6K
2
C4 40
1
0.1U_0402_16V4Z
C4 42
A
0.1U_0402_16V4Z
2mA @3.3V
V_CPU_IO[1]
HDA
2
AT18
RTC
1
0.1U_0402_16V4Z
+R TCVCC
2
C4 89 0.1U_0402_16V4Z
C5 00
2
C5 01 4.7U_0603_6.3V6K
0.
[email protected]
VCCIO[9]
AN30 AN31
0.01U_0402_16V7K UMA@ AB34
2
+ VCCP
1
+3VS
C 483
0.
[email protected]
1
AK3 AK1
1U_0402_6.3V6K
U20
+3VS 1
2
1 2 C4 57 0.1U_0402_16V4Z
+PCH_VRM
1
B
VCCSATAPLL[1] VCCSATAPLL[2]
2
1
VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53]
VCC3_3[2]
2
Y22
0.032A
2
+3VS
1
VCCAPLLEXP0.042A
L 28 UMA@ 2 1 0.1UH_MLF1608DR10KT_10%_1608
+VCCTX_LVDS 0.01U_0402_16V7K 10U_0805_6.3V6M C 485 1 1 1 1
1
+V1.1A_INT_V CCSUS 2 0.1U_0402_16V4Z C 463
AD13
1
BJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27
0.1uH inductor, 200mA +1.8VS
2
DCPSST
VCC3_3[14]
3.208A
2
VCCIO[24]
1 UMA@ 2 0.022_0805_1%
1
V12
1
VCC3_3[13]
U35
C4 76 0.1U_0402_16V4Z
AK24
C4 67
VCCIO[4]
+VCCSST 2 0.1U_0402_16V4Z C 453
2
P36
R 213
0.1U_0402_16V4Z
VCCIO[3]
AF32
2
N36
VCC3_3[12]
D
+3VS
0.1U_0402_16V4Z
AH34
2
VCC3_3[11]
1
AP43 AP45 AT46 AT45
2
0_0603_5%
R2 14 0_0402_5% DI S@
C4 68
VCCIO[2]
VCC3_3[10]
M36
2
C 514
AF34
L38
2
+3VS
1
10U_0603_6.3V6M
VCCIO[21] VCCIO[22] VCCIO[23]
0.357A
VCC3_3[9]
P CH_V 5 REF_RUN
C 474
VCCADPLLB[1] VCCADPLLB[2]
AH23 AJ35 AH35
J38
1
1U_0402_6.3V6K
1
BD51 BD53
K49
C 473
1
1U_0402_6.3V6K
C4 84 1U_0402_6.3V6K
C4 72
C4 65 1U_0402_6.3V6K
1
0.073A
V5REF
VCC3_3[8]
+1.05VS
1U_0402_6.3V6K
+1.05VS
VCCADPLLA[1] VCCADPLLA[2]
>1mA
AH39
2
1
2
+VCCADPLLB
0.072A
VSSA_LVDS VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]
1
1
BB51 BB53
0.035A VCCVRM[3]
1
2
SATA
lsolate AF32,AF34,AH34 from AH35,AJ35 for Intel request 09.09.08
DCPRTC
+1.05VS P CH_V5REF_SUS
C4 62
+VCCADPLLA
F24
C4 64
AU24
+PCH_VRM
V23
1U_0402_6.3V6K
V9
PCI/GPIO/LPC
2 C
VCCIO[56] V5REF_SUS
>1mA
+3VALW
1U_0402_6.3V6K
C 452 +VCCRTCEXT 1 2 0.1U_0402_16V4Z
VCCSUS3_3[28]
AH38
2
2
VCCME[12]
0.059A
C4 55
VCCME[11]
Y42
U23
VCCALVDS
@
1
VCCME[10]
Y41
AF51
HVCMOS
VCCME[9]
Y39
VSSA_DAC[2]
1
2
+VCCA_LV DS
DMI
V42
VSSA_DAC[1]
AF53
PCI E*
VCCME[8]
AE52
NAND / SPI
VCCME[7]
V41
1.998A
2
FDI
V39
USB
VCCME[6]
Clock and Miscellaneous
AF42
PCI/GPIO/LPC
VCCME[5]
VCCADAC[2]
0.030A
+1.05VS
1
1
2
AF41
1
VCCADAC[1]
0.069A
C4 78
1
VCCME[4]
0.1U_0402_16V4Z
2
C4 75
2
1
VCCME[3]
AF43
1U_0402_6.3V6K
1
10U_0603_6.3V6M
2
C5 04 10U_0603_6.3V6M
1
C5 15 10U_0603_6.3V6M
2
C5 03 10U_0603_6.3V6M
C5 16
1
VCCME[2]
AD41
C 224
UPDATE 0210
AD39
+3VALW 0.1U_0402_16V4Z
C4 71
2
1U_0402_6.3V6K
1
VCCME[1]
2
VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4] 1.524A VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15]
+3VS 1
0.1U_0402_16V4Z
+1.05VS
DCPSUSBYP
2
1
C2 62
AD38
VCCLAN[2]
1
10U_0805_6.3V6M
2
T8 2 Y20 0.1U_0402_16V4Z
2
C4 77
P AD 1 C 461
V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26
AE50
0.01U_0402_16V7K
AF24
@ C4 69 1U_0402_6.3V4Z
VCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] 0.163AVCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]
AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31
R2 08
POWER
U7G
C5 02
1
R 486 0_0402_5%
0.344A
+1.05VS 1
10U_0603_6.3V6M
VCCLAN[1]
V24 V26 Y24 Y26
C4 70
VCCACLK[2]
AF23
1
+3VS_DAC VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]
0.052A
1U_0402_6.3V6K
D
VCCACLK[1]
AP53
C 466
@ R5 27 1 2 0_0603_5%
AP51
2
+1.05VS
POWER
U 7J
DG1.1 no M3 support and not Intel LAN, VCCLAN Source=>GND
3
1U_0402_6.3V6K
+1.05VS
4
2
Title
Compal Electronics, Inc. IBEX-M(5/6)-PWR
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
17
of
51
5
4
3
2
1
U7I AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42
D
C
B
A
VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]
VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[326] VSS[327] VSS[328] VSS[329] VSS[330] VSS[331] VSS[332] VSS[333] VSS[334] VSS[335] VSS[336] VSS[337] VSS[338] VSS[339] VSS[340] VSS[341] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352] VSS[353] VSS[354] VSS[355] VSS[356] VSS[366]
U7H
H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14
AB16
VSS[0]
AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28
VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]
VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]
AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47
D
C
B
IBEXPEAK-M_FCBGA1071
A
IBEXPEAK-M_FCBGA1071
Compal Secret Data
Security Classification Issued Date
2008/10/31
Deciphered Date
2009/10/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. IBEX-M(6/6)-GND
Size D ocument Number Cus t om Dat e:
Rev 0 .3
LA-5752P
Thursday, October 29, 2009 1
Sheet
18
of
51
4
3
2
1
U22A
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0 PCIE_CRX_C_GTX_P1 PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4 PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P8 PCIE_CRX_C_GTX_N8 PCIE_CRX_C_GTX_P9 PCIE_CRX_C_GTX_N9 PCIE_CRX_C_GTX_P10 PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P11 PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P12 PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P13 PCIE_CRX_C_GTX_N13 PCIE_CRX_C_GTX_P14 PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P15 PCIE_CRX_C_GTX_N15
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
CLK_PCIE_VGA CLK_PCIE_VGA#
<14> CLK_PCIE_VGA <14> CLK_PCIE_VGA#
AB10 AC10
AF10 1 2 AE10 R540 200_0402_5% @ 1 2 AG10 R541 2.49K_0402_1% DIS@ AD9 1
<5,16,28,29> BUF_PLT_RST# B
AE9
R46 10K_0402_5% @ 2 <14> PEG_CLKREQ#
PEG_CLKREQ#
1
1 R543 @
I2CA_SCL I2CA_SDA I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA I2CH_SCL I2CH_SDA I2CS_SCL I2CS_SDA
2 10K_0402_5% R542
Deep P12
0.85V
P8
1
1 1
GPU_VID0
GPU_VID1
0 0
0x0A7D
1
AD2 AD1
AF1 AE1
DACA_VREF DACA_RSET
VGA_CRT_R <26> VGA_CRT_B <26> VGA_CRT_G <26> DIS@ 2 C81 R48
U6 U4
A2 B1
0
0.8V
Deep P12
1 1
0.85V
P8
0.9V
P0
VGA_GPIO11 VGA_GPIO14
DIS@
124_0402_1%
R513 10K_0402_5% @
R6 V6
R2 R3
P-State D
CRT OUT
1 0.1U_0402_16V4Z
T5 R4 T4
R1 T3
P0
VGA_CORE
1
VGA_CRT_R VGA_CRT_B VGA_CRT_G
AD25
1.0V
VGA_HSYNC <26> VGA_VSYNC <26>
AE2 AD3 AE3
AF3 AG4 AE4 AF4 AG3
P-State
T4
VGA_CRT_R VGA_CRT_G VGA_CRT_B JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
1 R539 DIS@ TESTMODE 1 R24 DIS@ 1 10K_0402_5% @ R25 VGA_DDCCLK_C VGA_DDCDATA_C I2CB_SCL I2CB_SDA
R517 1 DIS@ R516 1 DIS@ VGA_LVDS_SCL_C VGA_LVDS_SDA_C
PAD PAD PAD PAD
2
T14 T13 T12 T11
R505 10K_0402_5% @
SMB_EC_CK2_R SMB_EC_DA2_R
T1 T2
1 DIS@ 1 DIS@ 1 DIS@
2 2 2
150_0402_1% 150_0402_1% 150_0402_1%
C
Pull Hi at CRT CONN side.
2
+3VS
10K_0402_5% 2
+3VS +3VS
2.2K_0402_5% 2.2K_0402_5%
2 2
R499 2.2K_0402_5% DIS@
+3VS
SMB_EC_CK2_R <14,31> SMB_EC_DA2_R <14,31>
VGA_DDCCLK_C
R443 2
@
1 4.7K_0402_5%
VGA_DDCDATA_C
R444 2
@
1 4.7K_0402_5%
+3VS
R478 2.2K_0402_5% DIS@
HDCP_SMB_CK1 HDCP_SMB_DAI
A3 A4
R537 R538 R530
10K_0402_5%
VGA_LVDS_SCL_C
R64
2 DIS@
1 2.2K_0402_5%
VGA_LVDS_SDA_C
R63
2 DIS@
1 2.2K_0402_5%
I2CS is VDD33 power plane same as EC +3.3VS.
I2CS is internal thermal sensor. XTAL_SSIN XTAL_OUTBUFF XTAL_OUT XTAL_IN
Removed external HDCP. 07/17/2009
D11 E9 E10
XTALOUT
D10
XTALIN
R42 10K_0402_5% DIS@
N11M-GE1-S-A2 _BGA533 DIS@
DIS@ +3VS
PEX_CLKREQ_N
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N TESTMODE
PEX_TSTCLK_OUT PEX_TSTCLK_OUT_N
PEX_RST_N
DACB_RED DACB_BLUE DACB_GREEN DACB_VREF DACB_RSET
PEX_REFCLK PEX_REFCLK_N
PEX_TERMP
DACB_HSYNC DACB_VSYNC
PAD
0.8V
VGA_CORE
1
PEX_TX0 PEX_TX0_N PEX_TX1 PEX_TX1_N PEX_TX2 PEX_TX2_N PEX_TX3 PEX_TX3_N PEX_TX4 PEX_TX4_N PEX_TX5 PEX_TX5_N PEX_TX6 PEX_TX6_N PEX_TX7 PEX_TX7_N PEX_TX8 PEX_TX8_N PEX_TX9 PEX_TX9_N PEX_TX10 PEX_TX10_N PEX_TX11 PEX_TX11_N PEX_TX12 PEX_TX12_N PEX_TX13 PEX_TX13_N PEX_TX14 PEX_TX14_N PEX_TX15 PEX_TX15_N
DACA
AD10 AD11 AD12 AC12 AB11 AB12 AD13 AD14 AD15 AC15 AB14 AB15 AC16 AD16 AD17 AD18 AC18 AB18 AB19 AB20 AD19 AD20 AD21 AC21 AB21 AB22 AC22 AD22 AD23 AD24 AE25 AE26
N11M-GE1/LP1 (40nm)
VGA_GPIO14
0
0x0A74
Device ID
VGA_GPIO11
GPU_VID1
0 0
2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N10M-GS (40nm)
GPIO6
GPU_VID0
1
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
GPU_VID0 <45> GPU_VID1 <45>
GPIO5
R34 10K_0402_5% DIS@
B
2
C120 C119 C118 C117 C80 C79 C78 C77 C116 C115 C114 C113 C112 C111 C109 C110 C108 C107 C105 C106 C104 C103 C102 C101 C100 C99 C98 C97 C96 C95 C94 C93
DACA_RED DACA_BLUE DACA_GREEN
Device ID
HDMI_DETECT_VGA <24> NV_INVTPWM PAD T9 VGA_ENVDD_R VGA_ENVDD_R <27> VGA_ENBKL_R VGA_ENBKL_R <27> GPU_VID0 1 2 GPU_VID1 R511 1 DIS@ 2 0_0402_5% R512 DIS@ 0_0402_5%
1
C
PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15
DACA_HSYNC DACA_VSYNC
N1 G1 C1 M2 M3 K3 K2 J2 C2 M1 D2 D1 J3 J1 K1 F3 G3 G2 F1 F2
2
DIS@
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19
DACA_VREF DACA_RSET
DACB
D
PCI EXPRESS
PCIE_CRX_GTX_P[0..15]
<6> PCIE_CRX_GTX_P[0..15]
TEST
<6> PCIE_CRX_GTX_N[0..15]
PEX_RX0 PEX_RX0_N PEX_RX1 PEX_RX1_N PEX_RX2 PEX_RX2_N PEX_RX3 PEX_RX3_N PEX_RX4 PEX_RX4_N PEX_RX5 PEX_RX5_N PEX_RX6 PEX_RX6_N PEX_RX7 PEX_RX7_N PEX_RX8 PEX_RX8_N PEX_RX9 PEX_RX9_N PEX_RX10 PEX_RX10_N PEX_RX11 PEX_RX11_N PEX_RX12 PEX_RX12_N PEX_RX13 PEX_RX13_N PEX_RX14 PEX_RX14_N PEX_RX15 PEX_RX15_N
CLK
PCIE_CRX_GTX_N[0..15]
AE12 AF12 AG12 AG13 AF13 AE13 AE15 AF15 AG15 AG16 AF16 AE16 AE18 AF18 AG18 AG19 AF19 AE19 AE21 AF21 AG21 AG22 AF22 AE22 AE24 AF24 AG24 AF25 AG25 AG26 AF27 AE27
GPIO
Part 1 of 5 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P[0..15]
<6> PCIE_CTX_GRX_P[0..15]
I2C
PCIE_CTX_GRX_N[0..15]
<6> PCIE_CTX_GRX_N[0..15]
2
5
2 0_0402_5%
Y2 4 1
1 C69 20P_0402_50V8 DIS@
GND
OUT
IN
GND
3 2
27MHZ_16PF_X7S027000BG1H-U DIS@
2
1
2
L17 C56 20P_0402_50V8 DIS@
VGA_DDCCLK_C VGA_DDCDATA_C L18 VGA_LVDS_SCL_C VGA_LVDS_SDA_C
DIS@ 1 1 DIS@ DIS@
L8 1 1 L7 DIS@
MBK1608121YZF_0603 2 2 MBK1608121YZF_0603 MBK1608121YZF_0603 2 2 MBK1608121YZF_0603
VGA_DDCCLK <26> VGA_DDCDATA <26> VGA_LVDS_SCL <27> VGA_LVDS_SDA <27>
1 1 1 1 C451 C86 C85 DIS@ DIS@ DIS@ 12P_0402_50V8J 12P_0402_50V8J 2 2 2 2 12P_0402_50V8J 12P_0402_50V8J C450 DIS@
A
Compal Secret Data
Security Classification 2007/10/15
Issued Date
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
A
Compal Electronics, Inc. N10M-GE1 PCIE,GPIO,CLK
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet 1
19
of
51
5
4
<23> FBAA[0..13]
3
2
1
FBAA[0..13] VGA_LVDS_ACLK FBBA[2..5]
<23> FBBA[2..5]
VGA_LVDS_ACLK# FBADQM[0..7]
<23> FBADQM[0..7]
FBADQS[0..7]
<23> FBADQS[0..7]
FBADQS#[0..7]
<23> FBADQS#[0..7]
C649 12P_0402_50V8J @
FBA_D[0..63]
<23> FBAD[0..63]
2
2
1
1
C650 12P_0402_50V8J @
U22B D
2
R23 10K_0402_5% DIS@
1
1
R18 10K_0402_5% DIS@
R15 10K_0402_5% DIS@
HDMI
<24> VGA_HDMI_TX2+ <24> VGA_HDMI_TX2<24> VGA_HDMI_TX1+ <24> VGA_HDMI_TX1<24> VGA_HDMI_TX0+ <24> VGA_HDMI_TX0<24> VGA_HDMI_CLK+ <24> VGA_HDMI_CLK-
+1.5VS
G4 G5 P4 N4 M5 M4 L4 K4 H4 J4
IFPC_AUX_I2CW_SCL IFPC_AUX_I2CW_SDA_N IFPC_L0 IFPC_L0_N IFPC_L1 IFPC_L1_N IFPC_L2 IFPC_L2_N IFPC_L3 IFPC_L3_N
D3 D4 F5 F4 E4 D5 C3 C4 B3 B4
IFPD_AUX_I2CX_SCL IFPD_AUX_I2CX_SDA_N IFPD_L0 IFPD_L0_N IFPD_L1 IFPD_L1_N IFPD_L2 IFPD_L2_N IFPD_L3 IFPD_L3_N
1
F7 G6 D6 C6 A6 A7 B6 B7 E6 E7
R30 1.3K_0402_1% @
1.27V~0.9V
10mil
FBACLK0 <23> FBACLK0# <23>
1
FBA_CLK1 FBA_CLK1_N
N24 N23
FBACLK1 <23> FBACLK1# <23>
2
FBA_DEBUG
R26 M22 1 10K_0402_5%DIS@
2
C7
STRAP0
B9
STRAP1
STRAP2
A9
STRAP2
BUFRST_N
N5
PAD
T1
THERMDN
D8
PAD
T2
D9
PAD
T3
STRAP0 STRAP1
C43 0.01U_0402_16V7K @
STRAP0
<22>
STRAP1
<22>
STRAP2
<22>
+3VS
THERMDP
CEC
N2
SPDIF
F9
C
R445 10K_0402_5% DIS@ +3VS
SPDIF_IN 1 DIS@ 2 R32 36K_0402_5%
ROM_CS_N
IFPE_AUX_I2CY_SCL IFPE_AUX_I2CY_SDA_N IFPE_L0 IFPE_L0_N IFPE_L1 IFPE_L1_N IFPE_L2 IFPE_L2_N IFPE_L3 IFPE_L3_N
ROM_SCLK
R468 10K_0402_5% DIS@
ROM_SI ROM_SO
IFPAB_RSET IFPC_RSET IFPD_RSET IFPE_RSET
B10 C9
ROM_SCLK
A10
ROM_SI
C10
ROM_SO
AB6
ROM_SCLK <22> ROM_SI <22> ROM_SO <22>
1 R44
R5
2 @
1 R39
M6
1K_0402_1% 2
DIS@ 1
R40 F8
1K_0402_1% 2
@
1 R477
1
F24 F23
FBA_CLK0 FBA_CLK0_N
IFPC_AUX IFPC_AUX_N
FBA_BA2 <23> FBBAODT0 <23> FBAACS0# <23> FBAAODT0 <23>
IFPB_TXC IFPB_TXC_N IFPB_TXD4 IFPB_TXD4_N IFPB_TXD5 IFPB_TXD5_N IFPB_TXD6 IFPB_TXD6_N IFPB_TXD7 IFPB_TXD7_N
1
1 2 1
1
FBAA_CKE <23>
2
FB_VREF1
FBAA0 FBAA9 FBAA6 FBAA2 FBAA8 FBAA3 FBAA1 FBAA13 FBA_BA2 FBBAODT0 FBAACS0# FBAAODT0
AB3 AB2 W1 V1 W3 W2 AA2 AA3 AB1 AA1
FBA_RST <23> R16 10K_0402_5% DIS@
T6 W6 Y6 AA6 N3
1
A16
FB_VREF
FBAA_CKE
RFU_1 RFU_2 RFU_3 RFU_4 RFU_5
C15 D15 J5
2
FBADQS0 FBADQS1 FBADQS2 FBADQS3 FBADQS4 FBADQS5 FBADQS6 FBADQS7
<23>
NC
C25 A19 E19 A24 T22 AA24 AA26 T27
LVDS
NC NC NC
RFU
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
FBACAS# <23> FBAWE# <23> FBA_BA0 <23> FBAA12
FBBA_CKE <23> R22 10K_0402_5% DIS@
IFPA_TXC IFPA_TXC_N IFPA_TXD0 IFPA_TXD0_N IFPA_TXD1 IFPA_TXD1_N IFPA_TXD2 IFPA_TXD2_N IFPA_TXD3 IFPA_TXD3_N
STRAP
FBADQS#0 FBADQS#1 FBADQS#2 FBADQS#3 FBADQS#4 FBADQS#5 FBADQS#6 FBADQS#7
FBBACS0# <23>
VGA_LVDS_ACLK AC4 VGA_LVDS_ACLK# AD4 VGA_LVDS_A0 V5 VGA_LVDS_A0# V4 VGA_LVDS_A1 AA5 VGA_LVDS_A1# AA4 VGA_LVDS_A2 W4 VGA_LVDS_A2# Y4 AB4 AB5
LVDS / TMDS
D25 A18 E18 B24 R22 Y24 AA27 R27
FBBA_CKE FBBACS0# FBAA11 FBACAS# FBAWE# FBA_BA0 FBBA5 FBAA12 FBA_RST FBAA7 FBAA10
VGA_LVDS_ACLK VGA_LVDS_ACLK# VGA_LVDS_A0 VGA_LVDS_A0# VGA_LVDS_A1 VGA_LVDS_A1# VGA_LVDS_A2 VGA_LVDS_A2#
GENERAL
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
Part 3 of 5 <27> <27> <27> <27> <27> <27> <27> <27>
FBA_BA1 <23>
SERIAL
FBADQM0 FBADQM1 FBADQM2 FBADQM3 FBADQM4 FBADQM5 FBADQM6 FBADQM7
FBARAS# <23>
2
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7
C26 B19 D19 D23 T24 AA23 AB27 T26
U22C
2
FBAA4 FBARAS# FBAA5 FBA_BA1 FBBA2 FBBA4 FBBA3
2
F26 J24 F25 M23 N27 M27 K26 J25 J27 G23 G26 J23 M25 K27 G25 L24 K23 K24 G22 K25 H22 M26 H24 F27 J26 G24 G27 M24 K22 J22 L22
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30
2
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
1K_0402_1% 2
@
1K_0402_1% B
N11M-GE1-S-A2 _BGA533 DIS@
R29 1.3K_0402_1% @
+3VS
+3VS
2
B
D22 E24 E22 D24 D26 D27 C27 B27 A21 B21 C21 C19 C18 D18 B18 C16 E21 F21 D20 F20 D17 F18 D16 E16 A22 C24 D21 B22 C22 A25 B25 A26 U24 V24 V23 R24 T23 R23 P24 P22 AC24 AB23 AB24 W24 AA22 W23 W22 V22 AA25 W27 W26 W25 AB25 AB26 AD26 AD27 V25 R25 V26 V27 R26 T25 N25 N26
MEMORY INTERFACE
C
D
Part 2 of 5 FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
+1.5VS
2
N11M-GE1-S-A2 _BGA533 DIS@
1
2
R526 4.7K_0402_5% DIS@ Q38A 1
IFPC_AUX
6 VGA_HDMI_SCL <24>
2
2N7002DW-T/R7_SOT363-6 DIS@
5
R531 4.7K_0402_5% DIS@ Q38B 4
1
IFPC_AUX_N
DIS@ 3
VGA_HDMI_SDA <24>
2N7002DW-T/R7_SOT363-6
5V PULL UP IN CONNECTER SIDE A
A
Compal Secret Data
Security Classification 2007/10/15
Issued Date
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. N10M-GE1 LVDS,Memory Bus
Size B Date:
Document Number
R ev 0.3
LA-5752P Sheet
Thursday, October 29, 2009 1
20
of
51
5
4
3
2
0.01U_0402_16V7K
1
U22D Part 4 of 5
0.047U_0402_25V7K
1 C26 DIS@
2
1 C50 DIS@
0.01U_0402_16V7K
1 C38 DIS@
2
2
J9 J10 J12 J13 L9 M9 M11 M17 N9 N11 N12 N13 N14 N15 N16 N17 N19 P11 P12 P13 P14 P15 P16 P17 R9 R11 R12 R13 R14 R15 R16 R17 T9 T11 T17 U9 U19 W9 W 10 W 12 W 13 W 18 W 19
1 C39 DIS@
2
C40 DIS@
2 0.1U_0402_10V7K
0.01U_0402_16V7K 0.047U_0402_25V7K
N10M-GS: 15.8A N11M-GE1:16.7A
1
0.01U_0402_16V7K
1 C41 DIS@
2
2
1 C37 DIS@
2
C29 DIS@
0.01U_0402_16V7K 0.047U_0402_25V7K
1
0.01U_0402_16V7K
1 C36 DIS@
2
2
1 C52 DIS@
2
C51 DIS@
0.01U_0402_16V7K
+3VS
NEAR BALL
C
1U_0402_6.3V6K
120mA
1
2
C84 DIS@
2
1 C459 DIS@
4.7U 6.3V K X5R 0603
C44 DIS@
2
1 C55 DIS@
0.1U_0402_10V7K
2
C54 DIS@
A12 B12 C12 D12 E12 F12
0.1U_0402_10V7K
+PEX_SVDD_3V3
NEAR BALL
L27 MBK1608121YZF_0603 2 DIS@ 1
300mA
1
2
NEAR BGA +1.8VS 1
0.1U_0402_10V7K
1
AG9
1 C512 DIS@
2
1 C499 DIS@
2
+IFPA_IOVDD
0.1U_0402_10V7K 1 C510 DIS@
2
C511 DIS@
PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ
VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 PEX_SVDD_3V3
V3
IFPA_IOVDD
+IFPB_IOVDD
V2
IFPB_IOVDD
+IFPC_IOVDD
J6
IFPC_IOVDD
H6
IFPDE_IOVDD
2 10K_0402_5% DIS@
0.1U_0402_10V7K
1 R41 +IFPAB_PLLVDD
AD5
+IFPC_PLLVDD 1U_0402_6.3V6K 1
B
2
0.1U_0402_10V7K 1
1
C498 DIS@
C497 DIS@
2
1 R49
2
PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD
AG7 AF7 AE7 AD8 AD7 AC9
PEX_PLLVDD
AF9
NEAR BGA
K6
SP_PLLVDD
L6
PLLVDD
K5
1U_0402_6.3V6K
285mA
2
C68 DIS@
C67 DIS@ 2
2
4.7U 6.3V K X5R 0603
2
NEAR BALL 1U_0402_6.3V6K
MBK1608121YZF_0603 1
2
1 C73 DIS@
2
4.7U 6.3V K X5R 0603
2
0.1U_0402_10V7K
1 C72 DIS@
2
1 C62 DIS@
2
1U_0402_6.3V6K
1 C46 DIS@
+IFPC_PLLVDD
2
1 C83 DIS@
2
1 C35 DIS@
2
2A
2
22U_0805_6.3V6M
1 C537 DIS@
1U_0402_6.3V6K
2
1 C538 DIS@
2
C552 DIS@
10U_0805_6.3V6M +1.05VS
NEAR BALL
NEAR BGA
0.1U_0402_10V7K
1
2
1U_0402_6.3V6K
1 C47 DIS@
2
1 C60 DIS@
0.1U_0402_10V7K
4.7U 6.3V K X5R 0603
1 C59 DIS@
2
2
1 C49 DIS@
0.1U_0402_10V7K
2
1 C48 DIS@
2
1 C551 DIS@
1U_0402_6.3V6K
2
C553 DIS@
10U_0805_6.3V6M
NEAR BGA 1U_0402_6.3V6K
2
1 C45 DIS@
2
DIS@
C57 DIS@
+PEX_PLLVDD
NEAR BALL
NEAR BGA
0.1U_0402_10V7K
12~16mil
DACA_VDD
AG2
+DACA_VDD
1U_0402_6.3V6K
DACB_VDD
W5
+DACB_VDD
1
2
1 C480 DIS@
2
1 C481 DIS@
2
C65 DIS@
0.1U_0402_10V7K
1 R45
FB_CAL_PD_VDDQ
IFPD_PLLVDD
VDD_SENSE
W 15
D7
IFPE_PLLVDD
VDD_SENSE
E15
VID_PLLVDD=45mA SP_PLLVDD=45mA PLLVDD=60mA
4.7U 6.3V K X5R 0603
+1.05VS
2 DIS@
10K_0402_5% +SP_PLLVDD
IFPC_PLLVDD
+1.05VS
MBK1608121YZF_0603 2 1 L21 1 DIS@ C482 DIS@ 2
+FB_PLLAVDD
IFPAB_PLLVDD B15
1
The power is base on VRAM type. +VGASENSE
L24 1 2 MBK1608121YZF_0603 DIS@
1U_0402_6.3V6K
+1.5VS
R465 DIS@ 40.2_0402_1%
+VGASENSE <45>
NEAR BALL 120mA
2
1 C64 DIS@
B
C488 DIS@
2 4.7U 6.3V K X5R 0603
+1.05VS
+FB_PLLAVDD
NEAR BGA 1U_0402_6.3V6K
1
C458 DIS@
2
1 2 MBK1608121YZF_0603 DIS@
1 C30 DIS@
2
L1
FB_PLLVDD=100mA FB_DLLVDD=100mA
C23 DIS@
4.7U 6.3V K X5R 0603 L29
NEAR BALL +DACA_VDD
1U_0402_6.3V6K
0.1U_0402_10V7K
1U_0402_6.3V6K
2
2
2
1 DIS@
1 C82 DIS@
+3VS
NEAR BGAMBK1608121YZF_0603
4700P_0402_25V7K
+IFPAB_PLLVDD
1
C
1 2 MBK1608121YZF_0603
1
+3VS
DIS@ 2
+1.05VS
120mA L3
1 C71 DIS@
2
4.7U 6.3V K X5R 0603
1 C523 DIS@
470P_0402_50V7K
2
1 C522 DIS@
2
1 C520 DIS@
2
0.1U_0402_10V7K
1 C513 DIS@
2
1 C521 DIS@
2
120mA
1 C519 DIS@
0.1U_0402_10V7K
2
C524 DIS@ A
4.7U 6.3V K X5R 0603
1 C63 DIS@
C61 DIS@ 2 0.1U_0402_10V7K
Compal Secret Data
Security Classification Issued Date
0.1U_0402_10V7K
2007/10/15
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
N10M-GS: 2.63A N11M-GE1:2.55A
1
C24 DIS@
4.7U 6.3V K X5R 0603
1 C58 DIS@
0.1U_0402_10V7K
+1.05VS
MBK1608121YZF_0603
C31 DIS@
2
0.047U_0402_25V7K
0.1U_0402_10V7K
220mA
220mA
1
NEAR BGA
0.1U_0402_10V7K
C32 DIS@
2
NEAR BGA
0.1U_0402_10V7K
T19
C66 DIS@
+3VS DIS@ 2
C42 DIS@
2
1
L6
0.01U_0402_16V7K
NEAR BALL
1
NEAR BGA 1
2
1
D
AC19
1 @ R47 1 DIS@ R43
L5
A
C27 DIS@
2
1
+1.05VS
FB_PLLAVDD
1 C74 DIS@
C28 DIS@
0.01U_0402_16V7K
0.1U_0402_10V7K
1
2
1
2
FB_DLLAVDD
DIS@
1
C53 DIS@
1
+1.05VS_PLL
R19
NEAR BALL
1
1
+SP_PLLVDD
FB_PLLAVDD
+PEX_SVDD_3V3
L4 MBK1608121YZF_0603
2
0.047U_0402_25V7K
4.7U 6.3V K X5R 0603
VID_PLLVDD
N11M-GE1-S-A2 _BGA533 DIS@
2 10K_0402_5% 2 10K_0402_5%
2
AG6 AF6 AE6 AD6 AC13 AC7 AB17 AB16 AB13 AB9 AB8 AB7
P6
0_0402_5% DIS@
A13 B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19 L19 L23 L26 M19 N22 U22 Y22
N6
C496 DIS@
2
0.1U_0402_10V7K
1
FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ
1U_0402_6.3V6K
2 4.7U 6.3V K X5R 0603
+1.05VS
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
POWER
4.7U 6.3V K X5R 0603
NEAR BGA
0.047U_0402_25V7K
4.7U 6.3V K X5R 0603
NEAR BALL
D
CLOSE TO GPU +1.5VS
PLACE UNDER GPU
NEAR BGA +VGA_CORE
1
1
4
3
2
Title
Compal Electronics, Inc. N10M-GE1 PWR
Size Document Number C u stom D ate:
R ev 0.3
LA-5 752P
Thursday, October 29, 2009
Sheet 1
21
of
51
5
4
3
2
1
A total of 8 signals are required for GB1 strapping this includes 2 reference signals 6 physical strapping pins 4 logical strapping bits A total of 24 logical strapping bits are available
U22E
E14
1 R467
1
2
@
2
R466 DIS@ 10K_0402_5%
20K_0402_1%
R470 X76@ 2
2K_0402_5%
1 2 1
2 1 2
R50 @ 15K_0402_1%
2
10K_0402_5%
R476 @
R469 @ 2K_0402_5%
1 R51 DIS@ 15K_0402_1%
1 2
45.3K_0402_1%
1
2 1
R473 D IS@
R471 @ 2
2
30K_0402_1%
R475 DIS@
34.8K_0402_1%
2 STRAP2 STRAP1 STRAP0 ROM_SCLK ROM_SI ROM_SO
R472
DIS@
1
<20> STRAP2 <20> STRAP1 <20> STRAP0 <20> ROM_SCLK <20> ROM_SI <20> ROM_SO
30K_0402_1%
R474 @
34.8K_0402_1%
1
1
D
C
FB_CAL_PU_GND
A15
R28
1 DIS@
2 40.2_0402_1%
FB_CAL_TERM_GND
B16
R27
1
2 60.4_0402_1%
GND_SENSE MULTI_STRAP_REF1_GND
F11
GND_SENSE MULTI_STRAP_REF0_GND
F10
STRAP1 use for 3GIO_PADCFG to set 35K pull up. (PUN-04335-001_V10 HW9 update)
DIS@
1
W16
+3VS
R463 40.2K_0402_1% DIS@
N11M-GE1-S-A2 _BGA533 DIS@ 2
Place Components Close to BGA
R464 40.2K_0402_1% DIS@
GPU
2
C
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
U2 U5 U11 U12 U13 U14 U15 U16 U17 U23 U26 V9 V19 W11 W14 W17 Y2 Y5 Y23 Y26 AC2 AC5 AC6 AC8 AC11 AC14 AC17 AC20 AC23 AC26 AF2 AF5 AF8 AF11 AF14 AF17 AF20 AF23 AF26 T16 T15 T14 F6
1
D
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Part 5 of 5
GND
B2 B5 B8 B11 B14 B17 B20 B23 B26 E2 E5 E8 E11 E17 E20 E23 E26 H2 H5 J11 J14 J17 K9 K19 L2 L5 L11 L12 L13 L14 L15 L16 L17 M12 M13 M14 M15 M16 P2 P5 P9 P19 P23 P26 T12 T13
N11M-GE1 LP1 (0x0A7D) 40nm
FB Memory (DDR3) Samsung 800MHz (defaul)
K4W1G1646E-HC12
Hynix 800MHz
H5TQ1G63BFR-12C
64Mx16
64Mx16
ROM_SO
ROM_SCLK
ROM_SI
STRAP2
STRAP1
STRAP0
PD 10K
PD 15K
PD 20K
PU 30K
PU 35K
PU 45K
PD 10K
PD 15K
PD 15K
PU 30K
PU 35K
PU 45K
X76 B
B
N11M-GE1 LP1
Memory/PKG DDR3
FBVDDQ +1.5VS
FB_CAL_PU_GND FBCAL_PD_VDDQ 40.2 ohm
Must be used 1% resister for driver calibration
40.2 ohm
FBCAL_TERM_GND 40.2/60.4 ohm
DG-04642-001-V01(May 22, 2009)
A
A
Compal Secret Data
Security Classification 2007/10/15
Issued Date
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. N10M-GE1 GND & STRAP
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet 1
22
of
51
5
4
+VRAM_VREFB
N10x 40nm DDR3 MAPPING NVIDIA COCUMENT FOR DA-3978-001
3
+VRAM_VREFC
<20> FBADQS#[0..7] D
<20> FBAD[0..63]
M9 H2
FBBA[2. .5] FBADQM[0..7] FBADQS[0. .7] FBADQS#[0. .7] FBA_D[0.. 63]
<20> <20> <20>
FBA_BA0 FBA_BA1 FBA_BA2
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
FBA_BA0 FBA_BA1 FBA_BA2
M3 N9 M4
J8 K8 FBAA_CKE K10
<20> FBACLK0 <20> FBACLK0# <20> FBAA_CKE <20> FBAAODT0 <20> FBAACS0# <20> F BARAS# <20> F BACAS# <20> F B AWE#
C
<20>
FBAA0 FBAA1 FBAA2 FBAA3 FBAA4 FBAA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBAA12 FBAA13
FBA_RST
FBAAODT0 FBAACS0# FBARAS# FBACAS# F BAWE#
K2 L3 J4 K4 L4
FBADQS1 FBADQS3
F4 C8
FBADQM1 FBADQM3
E8 D4
FBADQS#1 FBADQS#3
G4 B8
FBA_RST
T3
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
CK CK CKE/CKE0
DQSL DQSU
FBA_D9 FBA_D14 FBA_D8 FBA_D12 FBA_D10 FBA_D13 FBA_D11 FBA_D15
1
D8 C4 C9 C3 A8 A3 B9 A4
FBA_D26 FBA_D29 FBA_D24 FBA_D25 FBA_D28 FBA_D31 FBA_D27 FBA_D30
3
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DML DMU
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET
D IS@
FBAA0 FBAA1 FBAA2 FBAA3 FBAA4 FBAA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBAA12 FBAA13
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
B3 D10 G8 K3 K9 N2 N10 R2 R10
FBA_BA0 FBA_BA1 FBA_BA2
M3 N9 M4
FBACLK0 FBACLK0# FBAA_CKE
+1.5VS
J8 K8 K10
A2 A9 C2 C10 D3 E10 F2 H3 H10
FBAAODT0 FBAACS0# FBARAS# FBACAS# F BAWE#
K2 L3 J4 K4 L4
FBADQS2 FBADQS0
F4 C8
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
FBADQM2 FBADQM0
E8 D4
FBADQS#2 FBADQS#0
G4 B8
FBA_RST
T3 L9
U1
VREFCA VREFDQ
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E4 F8 F3 F9 H4 H9 G3 H8
FBA_D21 FBA_D17 FBA_D20 FBA_D16 FBA_D22 FBA_D18 FBA_D23 FBA_D19
D8 C4 C9 C3 A8 A3 B9 A4
FBA_D4 FBA_D1 FBA_D7 FBA_D0 FBA_D5 FBA_D2 FBA_D6 FBA_D3
M9 H2
2
0
VDD VDD VDD VDD VDD VDD VDD VDD VDD
CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DQSL DQSU DML DMU
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET ZQ/ZQ0
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
A1 A11 T1 T11
NC NC NC NC
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
B2 B10 D2 D9 E3 E9 F10 G2 G10
J2 L2 J10 L10
R 21 240_0402_1%
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
2
J2 L2 J10 L10
FBAA0 FBAA1 FBBA2 FBBA3 FBBA4 FBBA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBAA12 FBAA13
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
FBA_BA0 FBA_BA1 FBA_BA2
M3 N9 M4
+1.5VS
BA0 BA1 BA2
B3 D10 G8 K3 K9 N2 N10 R2 R10
FBACLK1 FBACLK1#
<20> FBACLK1 <20> FBACLK1# +1.5VS
<20> FBBA_CKE
A2 A9 C2 C10 D3 E10 F2 H3 H10
J8 K8 K10
FBBA_CKE
<20> FBBAODT0 <20> FBBACS0#
FBBAODT0 FBBACS0# FBARAS# FBACAS# F BAWE#
K2 L3 J4 K4 L4
FBADQS4 FBADQS7
F4 C8
FBADQM4 FBADQM7
E8 D4
FBADQS#4 FBADQS#7
G4 B8
FBA_RST
T3
A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
L9
1
ZQ/ZQ0
2
R 12 240_0402_1%
M9 H2
+1.5VS
BA0 BA1 BA2
ODT/ODT0 CS RAS CAS WE
E4 F8 F3 F9 H4 H9 G3 H8
1
L9
U2
U 23
VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDD VDD VDD VDD VDD VDD VDD VDD VDD
CK CK CKE/CKE0
DQSL DQSU
FBA_D37 FBA_D36 FBA_D35 FBA_D32 FBA_D39 FBA_D34 FBA_D38 FBA_D33
D8 C4 C9 C3 A8 A3 B9 A4
FBA_D61 FBA_D57 FBA_D56 FBA_D62 FBA_D58 FBA_D63 FBA_D59 FBA_D60
M9 H2
A1 A11 T1 T11
D IS@
NC NC NC NC
100-BALL SDRAM DDR3
B2 B10 D2 D9 E3 E9 F10 G2 G10
R7 240_0402_1%
D IS@
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DML DMU
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET ZQ/ZQ0
J2 L2 J10 L10
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
A1 A11 T1 T11
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
NC NC NC NC
100-BALL SDRAM DDR3
K4B1G1646D-HCF8_FBGA100 X76@
FBAA0 FBAA1 FBBA2 FBBA3 FBBA4 FBBA5 FBAA6 FBAA7 FBAA8 FBAA9 FBAA10 FBAA11 FBAA12 FBAA13
N4 P8 P4 N3 P9 P3 R9 R3 T9 R4 L8 R8 N8 T4 T8 M8
FBA_BA0 FBA_BA1 FBA_BA2
M3 N9 M4
FBACLK1 FBACLK1# FBBA_CKE
J8 K8 K10
4
7
+1.5VS
BA0 BA1 BA2
ODT/ODT0 CS RAS CAS WE
E4 F8 F3 F9 H4 H9 G3 H8
B3 D10 G8 K3 K9 N2 N10 R2 R10
+1.5VS
FBBAODT0 FBBACS0# FBARAS# FBACAS# F BAWE#
A2 A9 C2 C10 D3 E10 F2 H3 H10 A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
K2 L3 J4 K4 L4
FBADQS5 FBADQS6
F4 C8
FBADQM5 FBADQM6
E8 D4
FBADQS#5 FBADQS#6
G4 B8
FBA_RST
T3 L9
B2 B10 D2 D9 E3 E9 F10 G2 G10
R523 240_0402_1%
J2 L2 J10 L10
D IS@
A1 A11 T1 T11
100-BALL SDRAM DDR3
K4B1G1646D-HCF8_FBGA100 X76@
VREFCA VREFDQ
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E4 F8 F3 F9 H4 H9 G3 H8
FBA_D42 FBA_D46 FBA_D40 FBA_D45 FBA_D41 FBA_D47 FBA_D44 FBA_D43
D8 C4 C9 C3 A8 A3 B9 A4
FBA_D50 FBA_D52 FBA_D49 FBA_D53 FBA_D48 FBA_D54 FBA_D51 FBA_D55
5
D
6
+1.5VS
BA0 BA1 BA2
VDD VDD VDD VDD VDD VDD VDD VDD VDD
CK CK CKE/CKE0 ODT/ODT0 CS RAS CAS WE DQSL DQSU
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
DML DMU
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQSL DQSU
RESET ZQ/ZQ0
B3 D10 G8 K3 K9 N2 N10 R2 R10
+1.5VS
A2 A9 C2 C10 D3 E10 F2 H3 H10 A10 B4 E2 G9 J3 J9 M2 M10 P2 P10 T2 T10
C
1
<20> FBADQS[0..7]
FBAA[0. .13]
+VRAM_VREFC
+VRAM_VREFA
NC/ODT1 NC/CS1 NC/CE1 NCZQ1
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
2
+VRAM_VREFA
1
<20> FBADQM[0..7]
+VRAM_VREFD
2
<20> FBBA[2..5]
1
+VRAM_VREFD
U 21 <20> FBAA[0..13]
2
+VRAM_VREFB
NC NC NC NC
B2 B10 D2 D9 E3 E9 F10 G2 G10
100-BALL SDRAM DDR3
K4B1G1646D-HCF8_FBGA100 X76@
K4B1G1646D-HCF8_FBGA100 X76@
+1.5VS
1 R 20 1.33K_0402_1% D IS@
2
1
R9 1.33K_0402_1% D IS@
1 1
2
R522 1.33K_0402_1% D IS@
D IS@
2
2
12MIL
Compal Secret Data 2007/10/15
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
4
3
2
2
D IS@ A
Compal Electronics, Inc. VRAM DDR3
Size C Date:
5
1
0.1U_0402_10V6K
R8 1.33K_0402_1% D IS@
+VRAM_VREFD 2
2
12MIL
Security Classification Issued Date
R529 1.33K_0402_1% D IS@
+VRAM_VREFC
0.1U_0402_10V6K
A
+ 2
C436 220U_B2_2.5VM_R35
1
C 19
1
C 16
1
C 11
1
C 12
1
C 17
1
C 18
1
C9
1
C 10
1
C 438
C 526
1
1
1
+1.5VS
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
C8
+1.5VS
1
+1.5VS
1
+1.5VS
D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
D IS@
2
C495
1
1
C525
1
C446
1
C445
1
C437
1
C479
1
C487
1
C 20
1
C5
1
C509
C517
1
D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ D IS@ 2 2 2 2 2 2 2 2 2 2 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
R 10 1.33K_0402_1% D IS@
D IS@
1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z R 14 243_0402_1% D IS@
FBACLK1#
12MIL 1
2
2
1 1
+1.5VS
B
+VRAM_VREFB
0.1U_0402_10V6K
R 19 1.33K_0402_1% D IS@
0.1U_0402_10V6K
FBACLK1
C 22
1
12MIL
D IS@ 243_0402_1% R 442 FBACLK0#
R 11 1.33K_0402_1% D IS@
+VRAM_VREFA
C4
C444 C3 C6 C7 D IS@ D IS@ D IS@ D IS@ 2 2 2 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
2
C518 D IS@
2
FBACLK0
2
+1.5VS
2
C 21 D IS@
10U_0603_6.3V6M 1 1
2
B
10U_0603_6.3V6M 1 1
1
1
+1.5VS 10U_0603_6.3V6M 1
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009 1
Sheet
23
of
51
5
4
<20> <20> <20> <20> <20> <20> <20> <20>
D
3
C284 C283 C282 C281 C601 C600 C614 C599
VGA_HDMI_CLK+ VGA_HDMI_CLKVGA_HDMI_TX0+ VGA_HDMI_TX0VGA_HDMI_TX1+ VGA_HDMI_TX1VGA_HDMI_TX2+ VGA_HDMI_TX2-
<20> VGA_HDMI_SDA <20> VGA_HDMI_SCL
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
2
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
HDMI_CLK+_CK HD MI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK
<25> <25> <25> <25> <25> <25> <25> <25>
1
HDMI_CLK+_CK HD MI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK
HDMI_CLK+_CK HDMI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK
D
L15 1 1 L16
DIS@ DIS@
MBK1608121YZF_0603 2 2 MBK1608121YZF_0603 C295
1
DIS@ 2 12P_0402_50V8J
HD MIDAT_R HDMICLK_R
1 C302 DIS@ 2 12P_0402_50V8J
C
C
R593 HDMI_TX1-_CONN R591 HDMI_TX2+_CONN R597 HDMI_TX2-_CONN R595
1 1 1
499_0402_1% 499_0402_1%
D
499_0402_1% 499_0402_1%
S
499_0402_1%
2 +3VS G DIS@ Q41 2N7002W -T/R7_SOT323-3
R581 0_0805_5%
+5VS
HDMI@ D28 RB491D_SC59-3
@
NEAR CONNECT
2
B
1
+5VS
499_0402_1%
2
HDMI_TX1+_CONN
1
499_0402_1%
1
R587
1
+5VS_HDMI
1 C627 0.1U_0402_16V4Z HDMI@
2
R589 HDMI_TX0-_CONN
499_0402_1%
2
HDMI_TX0+_CONN
2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@ 2 DIS@
1
3
R583
1
1
R585 HDMI_ CLK-_CONN
3
HDM I_CLK+_CONN
4
1
2
HDM I_CLK+_CONN
3
3
HDMI_ CLK-_CONN
4
@ L34
2
2
HDMI_TX0+_CONN
3
3
HDMI_TX0-_CONN
HDMI_DETECT_VGA
<19> HDMI_DETECT_VGA
HDMI_TX0-_CK
4
4
@ D22 RB751V_SOD323
2
W CM-2012-900T_4P @ L35 HDMI_TX1+_CK HDMI_TX1-_CK
1
1
2
2
HDMI_TX1+_CONN
4
4
3
3
HDMI_TX1-_CONN
2
1
R579 10K_0402_1% 1 2 1 DIS@ MBK1608121YZF_0603
A
HDMI_TX2-_CK
4
1
2
2
4
3
3
R584 R582 R588 R586 R592 R590 R596 R594 5
1 1 1 1 1 1 1 1
HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@ HDMI@
+5VS
HD MIDAT_R HDMICLK_R
<25> HDMIDAT_R <25> HDMICLK_R
3
HDMI_TX2+_CONN HDMI_TX2-_CONN
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
HDMI_TX1+_CONN HDMI_TX2-_CONN
3 HD MIDAT_R
@ D24 BAT54S-7-F_SOT23-3
2
HDM I_CLK+_CONN HDMI_ CLK-_CONN HDMI_TX0+_CONN HDMI_TX0-_CONN HDMI_TX1+_CONN HDMI_TX1-_CONN HDMI_TX2+_CONN HDMI_TX2-_CONN
HDMI_TX0+_CONN HDMI_TX1-_CONN
+5VS
1
2 2 2 2 2 2 2 2
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HDMI_ CLK-_CONN
W CM-2012-900T_4P HDMI_CLK+_CK HD MI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK HDMI_TX1+_CK HDMI_TX1-_CK HDMI_TX2+_CK HDMI_TX2-_CK
JHDMI1
2
HDM I_CLK+_CONN HDMI_TX0-_CONN
@ L36
1
L30
DIS@ C603 330P_0402_50V7K
R578 100K_0402_5% DIS@
W CM-2012-900T_4P HDMI_TX2+_CK
B
2
DIS@
1
1
1
HDMI_TX0+_CK
R257 2.2K_0402_5% HDMI@
HDMI_DET_UMA
<25> HDMI_DET_UMA
W CM-2012-900T_4P
@ D23 BAT54S-7-F_SOT23-3
R249 2.2K_0402_5% HDMI@
1
HD MI_CLK-_CK
2
1
1
1
@ L33 HDMI_CLK+_CK
1 2
HDMICLK_R HDMI_TX2+_CONN
@ D25 BAT54S-7-F_SOT23-3
2008/03/25
Issued Date
Deciphered Date
3
A
Compal Electronics,Ltd. 2008/04/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
20 21 22 23
TAITW _PDVBR9-19FLBS4NN4N1 ME@
Compal Secret Data
Security Classification
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+
2
Title
HDMI CONN Size Document Number C ustom
R ev 0.3
LA-5752P
D ate: Thursday, October 29, 2009
Sheet 1
24
of
51
5
4
3
2
P/N:SA00002D700 (8101T) P/N:SA00001U900 (CH7318A)
P/N:SA00003GT00 (ASM1442) FOR asmedia
R428 STUFF RESERVE THE R668 PULL UP TO 3VS RESERVE THE R670 PULL DOWN TO GND CHANGE R483 FROM 499 TO 3.4K OHM
D
1
FOR 7318C
PIN6 PULL DOWN 1.2Kohm PIN7 PULL DOWN 7.5Kohm PIN7 PULL UP 20Kohm
D
1
+3VS
@ R231 0_0402_5%
28
HD MIDAT_R
29
VCC VCC VCC VCC VCC VCC VCC VCC
SCL_SINK
output SDA_SINK
HDMI_DET_UMA
<24> HDMI_DET_UMA
30
HPD_SINK
32 1
+3VS @ R243 0_0402_5%
DDC_EN
34 35
CFG0 CFG1 internal pull down
R256 4.7K_0402_5% @
input
1
1
R244 4.7K_0402_5% @
1
2
UMA_HDMI@ C280 0.1U_0402_16V4Z
REXT
6
HPD#
7
SDA
8
SCL
9
1
2
UMA_HDMI@ C602 0.1U_0402_16V4Z
4.7K_0402_5% R247 1 @ 2
R246 1 PC1 4 R248 1 3 PC0 internal pull down
2
2
2
C
4.7K_0402_5% R254 1 2 @ R255 1 2 @ 4.7K_0402_5%
+3VS
R245 1
2 @ 2 @
1
2
UMA_HDMI@ C604 0.1U_0402_16V4Z
1
2
UMA_HDMI@ C285 10U_0805_10V4Z
R253 20K_0402_1% @ TMDS_B_HPD#
R252 7.5K_0402_1% @
+3VS 4.7K_0402_5% 4.7K_0402_5%
C
2
HDMICLK_R
<24> HDMIDAT_R
2
R242 4.7K_0402_5% UMA_HDMI@
<24> HDMICLK_R
2
1
UMA_HDMI@ R230 0_0402_5%
2 11 15 21 26 33 40 46
1
+3VS
OE#
1
25 +3VS
1 2
2
U12
3.4K_0402_1% 2 UMA_HDMI@
TMDS_B_HPD#
TMDS_B_HPD# <15> HDMIDAT_NB <15> HDMICLK_NB <15> +3VS
R232 1
RT_EN#
10
OUT_D4+ OUT_D4-
13 14
HDMI_CLK+_CK HD MI_CLK-_CK HDMI_TX0+_CK HDMI_TX0-_CK
<15> TMDS_B_CLK <15> TMDS_B_CLK#
48 47
<15> TMDS_B_DATA0 <15> TMDS_B_DATA0#
45 44
IN_D3+ IN_D3-
OUT_D3+ OUT_D3-
16 17
<15> TMDS_B_DATA1 <15> TMDS_B_DATA1#
42 41
IN_D2+ IN_D2-
OUT_D2+ OUT_D2-
19 20
HDMI_TX1+_CK HDMI_TX1-_CK
OUT_D1+ OUT_D1-
22 23
HDMI_TX2+_CK HDMI_TX2-_CK
GND GND GND GND GND GND GND GND GND GND PAD
1 5 12 18 24 27 31 36 37 43 49
39 38
<15> TMDS_B_DATA2 <15> TMDS_B_DATA2#
IN_D4+ IN_D4-
IN_D1+ IN_D1-
@
2 4.7K_0402_5%
HDMI_CLK+_CK <24> HDMI_CLK-_CK <24> HDMI_TX0+_CK <24> HDMI_TX0-_CK <24> HDMI_TX1+_CK <24> HDMI_TX1-_CK <24> HDMI_TX2+_CK <24> HDMI_TX2-_CK <24>
B
B
ASM1442_QFN48_7X7 UMA_HDMI@
A
A
Compal Electronics,Ltd.
Compal Secret Data
Security Classification 2008/03/25
Issued Date
Deciphered Date
2008/04/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Level Shiftter_ASM1442 Size Document Number C ustom
R ev 0.3
LA-5752P
D ate: Thursday, October 29, 2009
Sheet 1
25
of
51
A
B
C
D
+5VS
+5VS
3
3
2
1
<15> DAC_RED <15> DAC_GRN <15> DAC_BLU
DAC_ RED
1
C RT_R
1
CRT_G
2 UMA@ 0_0402_5% 2 R91 UMA@ 0_0402_5% DA C_BLU 1 2 R93 UMA@ 0_0402_5% R92
DAC_ GRN
2
CRT_B CRT_G
1
1
C RT_R
1 R153 150_0402_1%
DIS only
CRT_B
R131 150_0402_1%
R90 150_0402_1%
2
CRT_G
2
<19> VGA_CRT_B
VGA_CRT_R 1 2 R66 DIS@ 0_0402_5% VGA_CRT_G 1 2 R65 DIS@ 0_0402_5% VGA_CRT_B 1 2 R67 DIS@ 0_0402_5%
2
<19> VGA_CRT_G
1
CRT_B <19> VGA_CRT_R
1 C158
2
@ D3
C146
2
2
C137 10P_0402_50V8J
10P_0402_50V8J 10P_0402_50V8J
CLOSE TO CONN
JVGA_HS
1 2
@ D27 BAT54S-7-F_SOT23-3
@ D26 BAT54S-7-F_SOT23-3
CRT Connector
+CRT_VCC D21
R ED
JVGA_VS
1 2
+5VS
FCM1608CF-121T03 0603 1 2 L11 FCM1608CF-121T03 0603 1 2 L10 FCM1608CF-121T03 0603 1 2 L9 1 1
C RT_R
UMA only
BAT54S-7-F_SOT23-3
2
3
R ED
1
@ D2 BAT54S-7-F_SOT23-3
+5VS
3
GR EEN
1
@ D1 BAT54S-7-F_SOT23-3
+5VS
3
BLUE
1
E
+5VS
1
1
2 1
RB491D_SC59-3
GR EEN
1.1A_6V_SMD1812P110TF
W=40mils
BLUE
1
C157
2
2
2
2
C136 10P_0402_50V8J JCRT1
6 11 1 7 12 2 8 13 3 9 14 4 10 15 5
R ED CRT _DDC_DAT_CONN GR EEN JVGA_HS BLUE JVGA_VS CRT_D DC_CLK_CONN
2
1
R575
1
2 1K_0402_5%
1
<19> VGA_HSYNC
P
16 17 2
TYCO_1775763-1 ME@
H S YNC_G
2
A
1
5 DIS@ R68
OE#
<15> CRT_HSYNC
G G
2
Y
G
0_0402_5% 1 2 0_0402_5% 2
CRT_HSYNC_1
4
1
L32
2 FCM1608CF-121T03 0603
U26 SN74AHCT1G125DCKR_SC70-5
3
UMA@ R94
C628
100P_0402_50V8J 2 Structure>
CRT_VSYNC
3
DIS@ R69
1
<19> VGA_VSYNC
P VSYNC_G
2
0_0402_5% 2
A
1
5
2
G
0_0402_5% 1 2
3
UMA@ R95
OE#
C620 0.1U_0402_16V4Z
1K_0402_5%
Y
CRT_ VSYNC_1
4
1
U25 SN74AHCT1G125DCKR_SC70-5
L31
2 FCM1608CF-121T03 0603 1
2
<19> VGA_DDCDATA <15> CRT_DDC_CLK <19> VGA_DDCCLK
VGA_DDCDATA CRT _DDC_CLK VG A_DDCCLK
1
1 1
@ C625 10P_0402_50V8J
2
R158 2.2K_0402_5%
2
5
R157 2.2K_0402_5%
2
CRT _DDC_CLK_R 2 UMA@ 1 R97 0_0402_5% 2 DIS@ 1 R71 0_0402_5%
3
+CRT_VCC
4 2
<15> CRT_DDC_DATA
CRT_DDC_DATA_R 2 UMA@ 1 R96 0_0402_5% 2 DIS@ 1 R70 0_0402_5%
R162 2.2K_0402_5%
2
R159 2.2K_0402_5% CRT_DDC_DATA
+3VS
1
1
+3VS
JVGA_VS
3
CRT _DDC_DAT_CONN
Q13B 2N7002DW -T/R7_SOT363-6
6 Q13A @ C178 2N7002DW -T/R7_SOT363-6 100P_0402_50V8J
1
2
CRT_D DC_CLK_CONN 1 @ C177 68P_0402_50V8K 2
4
4
Compal Secret Data
Security Classification 2007/10/15
Issued Date
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
Compal Electronics, Inc. CRT Connector
Size Document Number C ustom D ate:
R ev 0.3
LA-5752P
Thursday, October 29, 2009
Sheet E
26
of
51
5
4
3
2
1
INVPWM +LEDVDD
B+
C15 1 @
2
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
DAC_BRIG
1 @ C13 2
DISPOFF# C567 680P_0402_50V7K @
1 @ C296 JLVDS1
2 +LCDVDD_CONN
For EMI
D
LCD POWER CIRCUIT +LCDVDD
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
(60 MIL)
+3VS @ 680P_0402_50V7K C14
+5VALW
1
LCD_COLOR_1 <34> INVT_PWM
R17 1 0_0402_5% DIS@
2
INVPWM DISPOFF#
<34> DAC_BRIG 2
2
2
1
0_0402_5% LCD_ENVDD
2
1 0_0402_5%
2
1 3
R36
<19> VGA_ENVDD_R
IN
1
UMA@
GND
R35
<15> PCH_ENVDD
DIS@
2
C34
R392 2.2K_0402_5% @
2
USB20_N2 USB20_P2
CMOS
USB20_N2 <16> USB20_P2 <16>
D
CONN_LVDS_A0# CONN_LVDS_A0 CONN_LVDS_A1# CONN_LVDS_A1 CONN_LVDS_A2# CONN_LVDS_A2 CONN_LVDS_ACLK# CONN_LVDS_ACLK
31
GNDGND
ACES_87142-3041 ME@
+LCDVDD_CONN
L2 1
2
FBMA-L11-201209-221LMA30T_0805 C33 4.7U_0805_10V4Z
2
C566 4.7U_0805_25V6-K
W=60mils +LCDVDD
Q5 DTC124EKAT146_SC59-3
R395 2.2K_0402_5% @
2
CONN_LVDS_SCL CONN_LVDS_SDA
AO3413_SOT23-3 Q4
0.1U_0402_16V4Z
R37 @ 100K_0402_5%
C
32 C539 4.7U_0805_10V4Z
2 1
OUT
DTC124EK
+3VS
2
+CMOS_PW
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
1
2 0_0805_5% 2 0_0805_5%
1
1
2
2
+3VS
C25
C
0.1U_0402_16V4Z
1
220K_0402_5%
1
3
R38
2 G
3
1
1
1
D Q3 2N7002_SOT23 S
W=60mils
G
2
R31 100K_0402_5%
D
R13 150_0603_1%
S
1
+3VS
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1
1 R549 1 R550
R250 4.7K_0402_5%
BKOFF#
BKOFF#
2
D12 <34>
1
DISPOFF#
2
CH751H-40PT_SOD323-2
R261
ENBKL
<34>
UMA@ U6 Y
PCH_PWM_R
4
0_0402_5% 2
2
1
UMA@ R161 2 0_0402_5%
R259 100K_0402_1% INVPWM 1
1
5 P
R260 1
NC7SZ14P5X_NL_SC70-5
3
G
A
<15> PCH_ENBKL
NC
2
0_0402_5% 2
UMA@
+3VS
<15> PCH_PWM
DIS@ 1
<19> VGA_ENBKL_R
G
2
1
3
1
S
D
INVPWM
@ R160 2 0_0402_5% 2 R156 10K_0402_5% @
1
+3VS
B
B
2N7002_SOT23 Q12 @
For GMCH DPST
CMOS Camera 1 R390 1 R391
CONN_LVDS_SCL CONN_LVDS_SDA
VGA_LVDS_A0 VGA_LVDS_A0#
0_0402_5% 0_0402_5%
2 DIS@ 2 DIS@
1 R86 1 R85
CONN_LVDS_A0 CONN_LVDS_A0#
VGA_LVDS_A1 VGA_LVDS_A1#
0_0402_5% 0_0402_5%
2 DIS@ 2 DIS@
1 R150 1 R128
CONN_LVDS_A1 CONN_LVDS_A1#
VGA_LVDS_A2 VGA_LVDS_A2#
0_0402_5% 0_0402_5%
2 DIS@ 2 DIS@
1 R126 1 R127
CONN_LVDS_A2 CONN_LVDS_A2#
VGA_LVDS_ACLK 0_0402_5% VGA_LVDS_ACLK#0_0402_5%
2 DIS@ 2 DIS@
1 R84 1 R125
CONN_LVDS_ACLK CONN_LVDS_ACLK#
+5VS
<15> <15>
LVDS_A1 LVDS_A1#
<15> <15>
LVDS_A2 LVDS_A2#
<15> LVDS_ACLK <15> LVDS_ACLK#
5
EDID_CLK EDID_DATA
0_0402_5% 0_0402_5%
2 UMA@ 1 R393 2 UMA@ 1 R394
CONN_LVDS_SCL CONN_LVDS_SDA
LVDS_A0 LVDS_A0#
0_0402_5% 0_0402_5%
2 UMA@ 1 R383 2 UMA@ 1 R382
CONN_LVDS_A0 CONN_LVDS_A0#
LVDS_A1 LVDS_A1#
0_0402_5% 0_0402_5%
2 UMA@ 1 R389 2 UMA@ 1 R388
CONN_LVDS_A1 CONN_LVDS_A1#
LVDS_A2 LVDS_A2#
0_0402_5% 0_0402_5%
2 UMA@ 1 R386 2 UMA@ 1 R387
CONN_LVDS_A2 CONN_LVDS_A2#
LVDS_ACLK LVDS_ACLK#
0_0402_5% 0_0402_5%
2 UMA@ 1 R384 2 UMA@ 1 R385
CONN_LVDS_ACLK CONN_LVDS_ACLK#
1 IN
1 C275 0.1U_0402_16V4Z 2 CMOS@
2007/10/15
3
2
+CMOS_PW
Q21 CMOS@ DTC124EKAT146_SC59-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
2
1
2008/10/15
Deciphered Date
0.01U_0402_16V7K
R280 0_0603_5% CMOS@
CMOS@
Compal Secret Data
Security Classification Issued Date
1
2
2
C326 CMOS1
1 2
3
<34> CMOS_OFF# <15> EDID_CLK <15> EDID_DATA
R270 10K_0402_5%
2
CMOS@
OUT
<20> VGA_LVDS_ACLK <20> VGA_LVDS_ACLK#
LVDS_A0 LVDS_A0#
1
CMOS@
GND
<20> VGA_LVDS_A2 <20> VGA_LVDS_A2#
<15> <15>
AO3413_SOT23-3
3
G
<20> VGA_LVDS_A1 <20> VGA_LVDS_A1#
A
Q24
1
2 DIS@ 2 DIS@
D
<20> VGA_LVDS_A0 <20> VGA_LVDS_A0#
VGA_LVDS_SCL 0_0402_5% VGA_LVDS_SDA 0_0402_5%
S
<19> VGA_LVDS_SCL <19> VGA_LVDS_SDA
Title
2
C337 CMOS@ 10U_0805_10V4Z
A
Compal Electronics, Inc. LVDS/CAMERA
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet 1
27
of
51
A
B
C
Mini-Express Card for WLAN/WiMAX(Half) Mini-Express Card for WWAN(Full)
WLAN_CLKREQ1#
2 @ 0_0402_5%
<14> CLK_PCIE_WLAN1# <14> CLK_PCIE_WLAN1
1
PCI_RST#_R CLK_PCI_DB <14> PCIE_PRX_DTX_N2 <14> PCIE_PRX_DTX_P2 <14> PCIE_PTX_C_DRX_N2 <14> PCIE_PTX_C_DRX_P2 +3VS
<34,35> EC_TX_P80_DATA <34,35> EC_RX_P80_CLK
100_0402_1% R274 EC_TX_P80_DATA1 2 EC_RX_P80_CLK 1 2 R273 100_0402_1%
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53
1 1
@
2
<14> WLAN_CLKREQ1#
R333 1
+3VALW J4 JUMP_43X791
2
+3VS JP10 PCIE_WAKE# BT _ACTIVE
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND
E
+1.5VS
Mini-Express Card(WLAN/WiMAX) <15> PCIE_WAKE# <37> BT_ACTIVE
D
2
C 422 0.1U_0402_16V4Z
2Watt
Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.
LPC_FRAM E#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R R 377 1
2
R 376 1 R 375 1
2 @ 0_0402_5% 0_0402_5% 2
0_0402_5%
R 374 1 R 373 1
2 @ 0_0402_5% 2 @ 0_0402_5%
W L_OFF# <34> BUF_PLT_RST# <5,16,19,29> +3VALW +3VS
LPC_FRAM E#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB
R284 R285 R286 R287 R288 R290
1 1 1 1 1 1
@ @ @ @ @ @
2 2 2 2 2 2
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
LPC_FR AME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PCI_R ST#
1
LPC_FRAME# <13,34> LPC_AD3 <13,34> LPC_AD2 <13,34> LPC_AD1 <13,34> LPC_AD0 <13,34> PCI_RST# <16,34> CLK_PCI_DB <14>
SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 <10,11,12,14>
USB20_N8 <16> USB20_P8 <16> 300_0402_5% 300_0402_5%
2 @ 2
1 R372 1 R371
WLAN_LED#
WLAN_LED# <36>
54
GND
TAITW_PFPET0-AFGLBG1ZZ4N0 ME@
+3VS 2
2
+3VS
1
2
J P9 PCIE_WAKE# BT _ACTIVE
<14> PCIECLKREQ3#
PCIECLKREQ3#
R370 1
2 @ 0_0402_5%
<14> CLK_PCIE_CARD_PCH# <14> C LK_PCIE_CARD_PCH
<14> PCIE_PRX_DTX_N4 <14> PCIE_PRX_DTX_P4 <14> PCIE_PTX_C_DRX_N4 <14> PCIE_PTX_C_DRX_P4
Vcc 3.3V +/- 8% Peak Icc 2750mA with max supply droop 50mA Average Icc 1000mA
+3VS
EC_TX_P80_DATA EC_RX_P80_CLK
<34,35> EC_TX_P80_DATA <34,35> EC_RX_P80_CLK
100_0402_1% R364 1 2 3G@ 1 2 3G@ R363 100_0402_1%
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
WAKE# 3.3V NC GND NC 1.5V CLKREQ# NC GND NC REFCLKNC REFCLK+ NC GND NC NC GND NC NC GND PERST# PERn0 +3.3Vaux PERp0 GND GND +1.5V GND SMB_CLK PETn0 SMB_DATA PETp0 GND GND USB_DNC USB_D+ NC GND NC LED_WWAN# NC LED_WLAN# NC LED_WPAN# NC +1.5V NC GND NC +3.3V GND
+1.5VS
C418 10U_0805_10V4Z
2
D4 @ CM1293-04SO_SOT23-6 @ C420 10U_0805_10V4Z
1
CH1
CH4
UIM _DATA
4
1 +UIM_PWR R152
2
10K_0402_5% +3VS
2Watt
2
+UIM_PWR UIM _DATA UIM_C LK UIM _RST UIM_VPP
3
Vn
Vp
CH2
CH3
5
6
J P2 R 368 1
3G@ 2
0_0402_5%
R 367 1 R 369 1
0_0402_5% +3VALW 2 @ 2 @ 0_0402_5% +3VS
R 366 1 R 365 1
2 @ 0_0402_5% 2 @ 0_0402_5%
USB20_N13 USB20_P13
3G_OFF# <34> BUF_PLT_RST# <5,16,19,29>
4 5 6 7
UIM_VPP UIM _DATA
SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 <10,11,12,14>
USB20_N13 <16> USB20_P13 <16>
+1.5VS
GND VPP I/O DET
VCC RST CLK
+UIM_PWR UIM _RST UIM_C LK
1 2 3
@ 1
GND GND
+3VS DAN217T146_SC59-3 3 1 2
40mil
8 9
2
D5
1
2
C176 0.1U_0402_16V4Z
+UIM_PWR TAITW_PMPAT6-06GLBS7N14N0 ME@
1
54
GND
@
R151 10K_0402_5% 2 1
<15> PCIE_WAKE# <37> BT_ACTIVE
1
C188 4.7U_0805_10V4Z
Mini-Express Card(WWAN 3G)
2
1 C 417 0.1U_0402_16V4Z
2
C419 0.1U_0402_16V4Z
TAITW_PFPET0-AFGLBG1ZZ4N0 ME@
3
3
+1.5VS
2
New Card 34mm Socket (Left/TOP)
+1.5VS_CARD1
Imax = 0.75A
Express Card Power Switch
1
1
C358 0.1U_0402_16V4Z
U 15
+1.5VS 12 14
+1.5VS_CARD1
1.5Vin 1.5Vin
1.5Vout 1.5Vout
3.3Vin 3.3Vin
3.3Vout 3.3Vout
11 13
40mil
2
JEXP1
1 C360 10U_0805_10V4Z
2
C359 0.1U_0402_16V4Z
USB20_N10 USB20_P10 C PUSB#
<16> USB20_N10 <16> USB20_P10 <16> C PUSB#
+3VS_CARD1 +3VS
+3VS
2 4
+3VALW
17
1
2
C386 0.1U_0402_16V4Z
<34,39,44> SYSON +3VALW
<16,34,39,42,44,46> SUSP# +3VALW
R 334 1
1
2
C372 0.1U_0402_16V4Z
6
<5,16,19,29> BUF_PLT_RST#
<16>
CPUSB#
SYSON
20
SUSP#
1
2 @ 100K_0402_5% 10 C PUSB#
9 18
AUX_IN SYSRST#
AUX_OUT OC#
SHDN#
PERST#
STBY#
NC
CPPE#
GND
3 5
60mil
+3VS_CARD1
+3VALW_CARD1
15
40mil
Imax = 1.35A 1
19 8
PERST#
2
C388 10U_0805_10V4Z
7
<10,11,12,14> SMB_CLK_S3 <10,11,12,14> SMB_DATA_S3 +1.5VS_CARD1 <15> PCIE_WAKE# +3VALW_CARD1
+3VALW_CARD1
Imax = 0.275A 1
2
@ C356 10U_0805_10V4Z
1
2
C357 0.1U_0402_16V4Z
PERST#
+3VS_CARD1 <14> CLKREQ_EXP#
CPUSB# RCLKEN
2
C387 0.1U_0402_16V4Z
16
G577BSR91U_QFN20 4
1
C PUSB#
<14> CLK_PCIE_EXP_PCH# <14> CLK_PCIE_EXP_PCH <14> PCIE_PRX_DTX_N5 <14> PCIE_PRX_DTX_P5 <14> PCIE_PTX_C_DRX_N5 <14> PCIE_PTX_C_DRX_P5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND
4
GND GND SANTA_130801-5_LT ME@
Compal Secret Data
Security Classification Issued Date
2007/10/15
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title Size
B
C
D
Document Number
R ev 0 .3
LA-5752P Date:
A
Compal Electronics, Inc. Mini-Card/Nwe Card/SIM Thursday, October 29, 2009 E
Sheet
28
of
51
A
B
C
D
E
Close to 8111DL pins--1,29,37 1 R182
2 3.6K_0402_5%
+3V_LAN +3V_LAN
100@
0.1U_0402_16V4Z LAN_DI
2
2
C597
2
C613
C246
LAN_CS 1 1 R203
4
Place Close to Chip C594
0.1U_0402_16V7K PCIE_IRX_C_PTX_N3 21
20
15
<14> PCIE_PTX_C_DRX_P3
16
<14> PCIE_PTX_C_DRX_N3
17 18
<14> CLK_PCIE_LAN <14> CLK_PCIE_LAN#
25
<14> CLKREQ_LAN#
27
<5,16,19,28> BUF_PLT_RST# 2 2.49K_0402_1%
1
<34> LAN_WAKE# 2 R206
+3V_LAN
1 10K_0402_5%
@
HSOP
LED3/EEDO LED2/EEDI/AUX LED1/EESK EECS
HSON HSIP
LED0 HSIN
RTL8111DL
REFCLK_P REFCLK_N CLKREQB PERSTB
46
RSET
ISOLATEB
26 28
LANWAKEB ISOLATEB
LAN_XTALI LAN_XTALO
41 42
CKTAL1 CKTAL2
FB12 SROUT12 EVDD12 DVDD12 DVDD12 DVDD12 AVDD12
+3VS 1
3
2
R204 1K_0402_5% ISOLATEB
R205 15K_0402_5%
MDIP0 MDIN0 MDIP1 MDIN1 MDIP2 MDIN2 MDIP3 MDIN3
33 34 35 32
LAN_DI LAN_SK# LAN_CS
38
ACTIVITY#
2 3 5 6 8 9 11 12
MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-
LAN_SK# <30> ACTIVITY# <30> MDI0+ MDI0MDI1+ MDI1MDI2+ MDI2MDI3+ MDI3-
4
+LAN_VDD12 VCTRL12
48 19 30 36 13 10
+EVDD12 +LAN_VDD12
2 R177
AVDD12
39
23 24
GPO NC
VDDSR VDDSR
44 45
7 14 31 47
GND GND GND GND
VDD33 VDD33
29 37
22
EGND
AVDD33 AVDD33 ENSR
1 40 43
GIGA@
2
2
C612 30P_0402_50V8J
1
2
C611
GIGA@
R179 0_0402_5%
RTL8103EL-VB-GR 100@
30P_0402_50V8J
C245 2
1
2
+3V_LAN
1 R577 2 0_0603_5% 100@
+LAN_VDD12
C244 GIGA@
Close to pin.
2
1
LAN_XTALO
25MHZ_20P
1
1 R576 2 GIGA@ 0_0603_5%
R180 0_0402_5%
1
1
C242 0.1U_0402_16V4Z GIGA@
3
40 mil width
1
+3V_LAN
U24 2
C243
2 R181 1 GIGA@ 0_0402_5%
1 Y3
GIGA@ 1 0_0402_5% 2 0.1U_0402_16V4Z
+3V_LAN
RTL8111DL-VB-GR_LQFP48_7X7 GIGA@
LAN_XTALI 1
<30> <30> <30> <30> <30> <30> <30> <30>
22U_0805_6.3V6M
0.1U_0402_16V7K PCIE_IRX_C_PTX_P3
R171
4
U24
C593
0.1U_0402_16V4Z
<14> PCIE_PRX_DTX_N3
1 0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
<14> PCIE_PRX_DTX_P3
2 1K_0402_5%
1
For RTL8111DL pin43: pull hi if switching regulator is enable. pull low if external power 1.2Vis used. For RTL8103EL is NC.
@
2
2
60 mil width VCTRL12
The trace length L69 to 8111DL's pin<200mils. L69 to C934/C941<200mils.
GIGA@ L12 1 2 S INDUC_ 4.7UH +-20% SIA4012-4R7M
Close to U44 pin19 1 R173 2 GIGA@ 0_0603_5%
1U_0603_10V4Z
2 0_0603_5%
60 mil width
J1 2
@ 1 JOPEN
Layout Notice : Place as close ch ip as possible.
1 C238 2
0.1U_0402_16V4Z
1 R170 100@
22U_0805_6.3V6M
2
1 R172 2 GIGA@ 0_0603_5%
C261 4.7U_0805_10V4Z
2 1 EN_WOL# 2 G Q18 2N7002_SOT23-3
3
EN_WOL#
D
2
S
1
1
C247
2
C248
1
+LAN_VDD12 2
2
C260
C259
0.1U_0402_16V4Z 1
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1
Close to U44 pin10,13,30,36
C267 0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Secret Data
Security Classification Issued Date
2006/08/04
2006/10/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
0.1U_0402_16V4Z
S
D
1
2 G
AO3414_SOT23-3
<34>
1
2
R219 33K_0402_5% 1
1
C239
C250 1U_0603_10V4Z
2
3 Q17
1
+5VALW
+EVDD12 2
1
+3V_LAN +3VALW
C251
B
C
D
Title
RTL8103EL Size Document Number Custom Date:
R ev 0.3
LA-5752P
Thursday, October 29, 2009
Sheet E
29
of
51
5
4
3
2
1
Close to T14
D
GIGA@ C133 2 1 0.01U_0402_16V7K
GIGA@ C132 2 1 0.01U_0402_16V7K
C131 2
C130 2
T16
1 <29>
MDI3+
<29>
MDI3-
<29>
MDI2+
<29>
MDI2-
2
TD1+
M DI3-
3
TD1-
MDI1+
<29>
MDI1-
<29>
MDI0+
MCT1
24
MCT3
MX1+
23
MDO3+
MX1-
22
MDO3-
MCT2
21
MCT2
MX2+
20
MDO2+
MDO2-
TCT2
MDI2+
5
TD2+
M DI2-
6
TD2-
MX2-
19
7
TCT3
MCT3
18
MCT1
8
TD3+
MX3+
17
MDO1+
9
TD3-
MX3-
16
MDO1-
10
TCT4
MCT4
15
MCT0
MX4+
14
MDO0+
MDI1+
M DI1-
1 0.01U_0402_16V7K
C
1:1
4
1 0.01U_0402_16V7K <29>
TCT1
MDI3+
MDI0+
11
1:1
1:1
1:1
TD4+
R55
2 GIGA@ 1 75_0402_5%
R54
2 GIGA@ 1 75_0402_5%
R53
1 75_0402_5%
2
R52
D
1 75_0402_5%
2
C
C128
Place close to TCT pin
1000P_1206_2KV7K <29>
MDI0-
M DI0-
12
TD4-
MX4-
13
MDO0-
1
2
LG-2446S GIGA@
T16
RJ45 Conn. JRJ45 HH-065 100@
<29> ACTIVITY#
ACTIVITY#
R178
1 300_0402_5%
2
12
Amber LED-
11
1
2
C249 @ 68P_0402_50V8K
Amber LED+
SHLD4
16
MDO3-
8
PR4-
SHLD3
15
MDO3+
7
PR4+
MDO1-
6
PR2-
MDO2-
5
PR3-
MDO2+
4
PR3+
MDO1+
3
PR2+
MDO0-
2
PR1-
MDO0+
1
PR1+
+3V_LAN
C70
@
2
1 470P_0402_50V7K
For EMI. B
<29>
LAN_SK#
LAN_SK#
R574
2
1
2
B
1 300_0402_5%
10
Green LED-
+3V_LAN
9
Green LED+
C609 68P_0402_50V8K @
SHLD2
14
SHLD1
13
FOX_JM36113-P2221-7F ME@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2009/03/20
Issued Date
Deciphered Date
2010/03/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
LAN_Transformer Size Document Number C ustom D ate:
Thursday, October 29, 2009
R ev 0.3
LA-5752P Sheet 1
30
of
51
5
R430
4
3
2
1
1403@
1403: @C508/@C324=100p
0_0402_5%
1 3 5 7 9 11 13 15
SMB_EC_CK2_R
C443 0.1U_0402_16V4Z
SMB_EC_CK2_R FAN_PW M S HDN_SEL
DN1 DP1 VDD GPIO1 GPIO2 ALERT# SYS_SHDN# SMDATA SMCLK TACH PWM GND SHDN_SEL TRIP_SET DN2 / DP3 DP2 / DN3 GPAD
2 4 6 8 10 12 14 16 17
2
1
1
C Q39 MMST3904-7-F_SOT323-3
2 B E
3
@ C508 1000P_0402_50V7K REMOTE1-
1
1
ALERT# SMB_EC_DA2_R TACH
SMB_EC_DA2_R <14,19>
TRIP_SET REMOTE2+
REMOTE2EMC2103-2-AP-TR_QFN16_4X4
Under WWAN
REMOTE2+ @ C324 1000P_0402_50V7K
R439 1.5K_0402_1% @
1
2
C Q22 MMST3904-7-F_SOT323-3
2 B E
REMOTE2-
1
FAN_PWM & TACH Address 0101_110xb for PWM FAN C
Close to DDR
REMOTE1+ 2103@ R441 10K_0402_5%
2
2103@
2
U20
2103@ R461 10K_0402_5%
1
<14,19>
SMSC thermal sensor placed near by VRAM
+3VS
3
1
R440 10K_0402_5% @
+3VS
2
V DD
2
2103@ R462 10K_0402_5%
2
2
2
2103@ 2103@ R460 R459 10K_0402_5% 6.8K_0402_5%
+3VS
2
1
1
2103@ R430 68_0402_5%
+3VS
2
+3VS
1
+3VS
1
D
+3VS
1
D
REMOTE1,2+/-: Trace width/space:10/10 mil Trace length:<8"
internal pull up 1.2K to 1.5V R for initial thermal shutdown temp
TACH
Close U20
2103@ REMOTE1+
1403@ C449 2200P_0402_50V7K
REMOTE2+
1 REMOTE2-
2
FAN_PW M
1 2 R622 0_0402_5% 2103@ 1 2 R623 0_0402_5%
REMOTE1REMOTE1+
<34>
EC_TACH
REMOTE2+
TRIP_SET R439 (1%) 953ohm 1020ohm 1100ohm 1150ohm 1240ohm 1330ohm 1400ohm 1500ohm 1580ohm 1690ohm 1820ohm 1960ohm 2050ohm 5
2 0_0402_5%
TACH_R
2 0_0402_5%
FAN_PW M_R
1 R620
1 REMOTE2-
B
R624 10K_0402_5% @ U29
A
1 R619
1
VDD
1403@
2
2
V DD
Shutdown Temp 93 94 95 96 97 98 99 100 101 102 103 104 105
2 0_0402_5% 2 0_0402_5%
+3VS
1 B
@ 1 R617 @ 1 R618
REMOTE1<34> EC_FAN_PW M
C651 2200P_0402_50V7K
C
SMCLK
SMB_EC_CK2_R
10
REMOTE1+
2
DP1
SMDATA
9
REMOTE1-
3
DN1
ALERT#
8
REMOTE2+
4
DP2
THERM#
7
REMOTE2-
5
DN2
GND
6
FAN1 Conn
SMB_EC_DA2_R ALERT# +5VS
JP12
1 2 3 4 5 6
TACH_R FAN_PW M_R EMC1403-2-AIZL-TR_MSOP10
2
Address 1001_101xb 1
C490 10U_0805_10V4Z
1 2 3 4 G5 G6
ACES_85205-04001 ME@
A
Compal Electronics,Ltd.
Compal Secret Data
Security Classification 2008/03/25
Issued Date
Deciphered Date
2008/04/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
EMC2103/1403_Thermal sensor/FAN Size Document Number C ustom
R ev 0.3
LA-5752P
D ate: Thursday, October 29, 2009
Sheet 1
31
of
51
A
B
C
D
E
F
G
H
1
1
SATA HDD Conn. JHDD1 2
SATA_ITX_DRX_P0 SATA_ITX_DRX_N0
<13> SATA_ITX_DRX_P0 <13> SATA_ITX_DRX_N0 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0
<13> SATA_DTX_C_IRX_N0 <13> SATA_DTX_C_IRX_P0
C434 1 C433 1
2 0.01U_0402_16V7K 2 0.01U_0402_16V7K
SATA_DTX_IRX_N0 SATA_DTX_IRX_P0
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
+3VS
+5VS
+5VS
+3VS
1
2
1 C125 1000P_0402_50V7K
2
1 C126 0.1U_0402_16V4Z
2
1 C124 1U_0603_10V4Z
2
1 C123 10U_0805_10V4Z
2
1 C122 10U_0805_10V4Z
2
1 2 3 4 5 6 7
@ C121 0.1U_0402_16V4Z
2
GND A+ AGND BB+ GND
SATA ODD Conn. JODD1
<13> SATA_ITX_DRX_P1 <13> SATA_ITX_DRX_N1
VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 VCC12
<13> SATA_DTX_C_IRX_N1 <13> SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1
2 0.01U_0402_16V7K 2 0.01U_0402_16V7K
R380 1 2 @ 10K_0402_5%
+3VS
<34> ODD_Power_ON#
C426 1 C425 1
1 2 3 4 5 6 7
SATA_ITX_DRX_P1 SATA_ITX_DRX_N1 SATA_DTX_IRX_N1 SATA_DTX_IRX_P1
8 9 10 11 12 13
+5V_ODD
ODD_Power_ON#
1 R379 @
2 0_0402_5%
GND A+ AGND BB+ GND DP +5V +5V MD GND GND
GND GND
17 16
OCTEK_SLS-13SB1G_RV ME@
SUYIN_127043FB022G208ZR_RV ME@
ODD Power Control
3
3
J6 2
1
1
@
2
JUMP_43X79
+5VS
Q37
AO3413_SOT23-3
1
+5V_ODD
D
S
3
1 1
@ R378 10K_0402_5%
2
G
2 C423
2
@
1
1
1
2 @ @
OUT 3
IN
GND
2
<34> ODD_OFF#
0.01U_0402_16V7K
C424 0.1U_0402_16V4Z
2
C431 10U_0805_10V4Z
Q36 @ DTC124EKAT146_SC59-3
4
4
Issued Date
2007/10/15
2008/10/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Compal Electronics, Inc.
Compal Secret Data
Security Classification
E
F
Title
HDD/ODD Connector Size B
Document Number
R ev 0.3
LA-5752P
Date:
Thursday, October 29, 2009 G
Sheet
32 H
of
51
5
4
3
2
1
CX20671 High Definition Audio Codec SoC With Integrated Class-D Stereo Amplifier. An integrated 5 V to 3.3 V Low-dropout voltage regulator (LDO). An integrated 3.3 V to 1.8V Low-dropout voltage regulator (LDO).
HDA_RST_CODEC# H D A_SY NC_CODEC
EMI
HDA_SDOUT_CODEC 1 33_0402_5%
2
@
2
@
2 R331
HDA_BITCLK_CODEC
1 22P_0402_50V8J C 370
2
@
1 22P_0402_50V8J C 378
D
1 22P_0402_50V8J C 376
22P_0402_50V8J C 375
1
2 D
0.1U_0402_16V4Z
C410
2
1
2
0.1U_0402_16V4Z
2
1
10U_0805_10V4Z C409
1
0.1U_0402_16V4Z
C414
+LDO_OUT_3.3V 1
2
AVDD_3.3 pinis output of internal LDO. NOT connect to external supply.
PC_BEEP
0_0402_5% EC_MUTE# 0_0402_5%
1 2
C416 1 2 0.1U_0402_16V4Z
10
2 R338 1 R343
38 37
SPK_L2+ SPK_L1-
11 13
SPK_R2+ SPK_R1-
16 14
Internal SPEAKER
0.1U_0402_16V4Z
PORTB_R PORTB_L B_BIAS
12 15 17
C_BIAS PORTC_R PORTC_L GPIO0/EAPD# GPIO1/SPK_MUTE#
DMIC_CLK DMIC_1/2
NC NC NC
LEFT+ LEFTRIGHT+ RIGHT-
AVEE FLY_P FLY_N
2
MIC_INR MIC_I NL
C
R344
1
2 5.11K_0402_1%
R345 R346
1 1
2 10K_0402_1% 2 39.2K_0402_1%
R352 R351
+MICBIASC
23 22
HP_OUTR _R 5.1_0402_5% 1 HP_OUT L_R 5.1_0402_5% 1
C403 C415
+VAUX_3.3 M IC_JD <38> Port PLUG_IN <38> Port
2.2K_0402_5% 2.2K_0402_5%
2 2.2U_0603_10V7K 2 2.2U_0603_10V7K
1 1
2 R601 2 R602
HP_OUTR <38> HP_OUTL <38>
C A
Sense resistors must be connected same power that is used for VAUX_3.3
+MICBIASC
R350
100_0402_1%
R356
100_0402_1%
EXT_MIC_R <38> EXT_MIC_L <38>
External MIC
Headphone
24 25 39 21 19 20
1 C401
2 1U_0603_10V4Z
1
2
CX20671-11Z_QFN40_6X6
1
2
B
+MICBIASB 1
MIC_INR 1 0_0402_5%
2 MIC_I NL R 600
2
R349 4.7K_0402_5% MIC1 1 2
SHORT PADS
GND
+5VS
Internal MIC
+MICBIASB
32 31 30
2
0.1_1206_1%
Please bypass caps very close to device.
36 35 34 33
1
10U_0805_10V4Z
2
10U_0805_10V4Z C 399
0.1U_0402_16V4Z C 390
2
1
PC_BEEP
41
C405 1 2 0.1U_0402_16V4Z R355 1 2 0_0402_5% R354 1 2 0_0402_5% R362 1 2 0_0402_5% J7 1 2
0.1U_0402_16V4Z C 392
C 391 C393
SENSE_A
2
GND
C395 1 2 0.1U_0402_16V4Z
LPWR_5.0 RPWR_5.0 CLASS-D_REF
PORTA_R PORTA_L 40 1
C396 1 2 0.1U_0402_16V4Z
BIT_CLK SYNC SDATA_IN SDATA_OUT
2 1
1
10U_0805_10V4Z
5 8 6 4
RESET#
1 R348
1
0.1U_0402_16V4Z
9
10U_0805_10V4Z C411
C413
HDA_RST_CODEC#
2
27 28 26
U 17
29
2
1
C 406
<34> E APD <34> EC_MUTE#
2
1
0.1U_0402_16V4Z C 404
EAPD active low 0=power down ex AMP 1=power up ex AMP
1
HDA_BITCLK_CODEC H D A_SY NC_CODEC 1 R 336 2 33_0402_5% HDA_SDOUT_CODEC
<13> HDA_RST_CODEC# <13> HDA_BITCLK_CODEC <13> H D A_SY NC_CODEC <13> H D A_SDIN1 <13> HDA_SDOUT_CODEC
2
FILT_1.65
2
C
1
AVDD_3.3 AVDD_5V AVDD_HP
R 332
FILT_1.8 VDD_IO VAUX_3.3 DVDD_3.3
2
+5VS
10K only needed if supply to VAUX_3.3 is removed during system re-start.
3 7 2 18
1
0.1U_0402_16V4Z
1
10U_0805_10V4Z C379
R 329
10K_0402_5% C371
C369
1
2
B
2
1U_0603_10V4Z C412
C381
1 @
1
Layout Note:Path from +5VS to LPWR_5.0 RPWR_5.0 must be very low resistance (<0.01 ohms)
R 328 2
2
1 R 330
0_0402_5% 0_0402_5%
2
1
2
+3VS +3VALW
1
0.1U_0402_16V4Z
@
2
1U_0603_10V4Z C377
0_0402_5% 2
1
1
0.1U_0402_16V4Z C408
@ 2 1 0_0402_5% R 337 To suuport W ake-on-Jack or W ake-on-Ring, the CODEC VAUX_3.3 & VDD_IO pins must be powerd by a rail that is not removed unless AC power is removed. *DSH page42 has more detail.
1
2 0.1U_0402_16V4Z
R 339
+3VALW
+1.5V
C407
+ VAUX_3.3
1
0_0402_5%
10U_0805_10V4Z C380
2
+3VS
10U_0805_10V4Z C400
+3VS
GNDA
C394
1
2 2.2U_0603_10V7K
MIC_INR
C402
1
2 2.2U_0603_10V7K
MIC_I NL
GN DA
WM-64PCY_2P 45@ @ 1
PC Beep
+3VS
2
R325 10K_0402_1% 1C 368
wide 20MIL
1
2
1U_0603_10V4Z
R311
@
2
1
2
C635
C634
1
1
2
5 6
GND1 GND2
A
ACES_88231-04001 ME@
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
Security Classification D 15 @ RB751V_SOD323
R309
2008/03/25
Deciphered Date
2008/04/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
10K_0402_5%
Title
CX20671 Codec Size C
Document Number
4
3
2
R ev 0 .3
LA-5752P
Date: Thursday, October 29, 2009 5
1 2 3 4
2
560_0402_5%
1
1 1
1U_0603_10V4Z
2
R 335 20K_0402_5% 1
2
1
1 2 3 4
1000P_0402_50V7K
E
Q30 2SC2411KT146_SOT23-3
C633
SPK_R1-_CONN SPK_R2+_CONN SPK_L1-_C ONN SPK_L2+_CONN
0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%
1000P_0402_50V7K
2 B
560_0402_5%
2
2 2 2 2
2
C 2
1
ICH Beep
R 310
1U_0603_10V4Z
C352 <13> P CH_SPKR
1 1 1 1
1000P_0402_50V7K
1 1
1 C 345 @ 0.1U_0402_16V4Z
PC_BEEP
L19 L20 L22 L23
C632
2 C351 2
BEEP#
3
EC Beep <34>
2
A
2PC_BEEP1 R 327 20K_0402_5%
SPK_R1SPK_R2+ SPK_L1SPK_L2+
1
1
C 374 1U_0603_10V4Z 2 1
1000P_0402_50V7K
JSPK1 R326 10K_0402_1%
Sheet 1
33
of
51
+3VALW +EC_AVCC
EC_RST# EC_SCI# EC_ID
12 13 37 20 38
<16> CLK_PCI_LPC <16,28> PCI_RST#
2 47K_0402_5% 2 C323 0.1U_0402_16V4Z
<16>
EC_SCI#
+3VALW R614 @ 1 2 4.7K_0402_5% R615 @ 1 2 4.7K_0402_5%
1
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
<35> KSI3 <35> KSI4 KSO[0..17]
KSO[0..17]
<35>
KSI[0..7]
KSI[0..7]
+3VALW R265 1
2 47K_0402_5% KSO1
R263 1
2 47K_0402_5% KSO2
ENE UPDATE 08/10/21
55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82
+3VS +3VALW 2
1
<41> <41> <14> <14>
R292 10K_0402_5%
D
3
PCI_PME#
1
2
G
+3VALW
EC_PME#
2 @ 0_0402_5%
S
@ Q26 2N7002_SOT23
changed
+3VALW
<31>
EC_SMI# LID_SW# ESB_CLK ESB_DAT
<35> EC_TACH KILL_SW#
EC_TACH
<28> 3G_OFF# <28,35> EC_TX_P80_DATA <28,35> EC_RX_P80_CLK <38> ON/OFF# <5,48> H_PROCHOT# 09.09.08 <38> NUM_LED#
EC_TX_P80_DATA EC_RX_P80_CLK H_PROCHOT#
XCLKI XCLKO
+3VS
1 67
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F
DA Output
21 23 26 27
INVT_PWM BEEP# EC_FAN_PWM ACOFF
63 64 65 66 75 76
BATT_TEMP BATT_OVP
68 70 71 72
PCH_TEMP_ALERT# ODD_Power_ON# DAC_BRIG IR EF
INVT_PWM <27> BEEP# <33> EC_FAN_PWM <31> ACOFF <40,42>
FAN control by EC 09.09.08
TP_CLK TP_DATA
97 98 99 109
+5VS TP_CLK
DAC_BRIG <27>
R236 1
2 4.7K_0402_5%
+3VALW TP_DATA R235 1
IREF <42> CHGVADJ <42>
USB_ON
R613 10K_0402_5% @
BATT_TEMP <41> BATT_OVP <42> ADP_I <42> 09.09.08 NOVO# <38> changed 09.09.08 PCH_TEMP_ALERT# <16> changed ODD_Power_ON# <32>
EC_MUTE# 83 84 85 86 87 88
2
AVCC
9 22 33 96 111 125 VCC VCC VCC VCC VCC VCC
AD
BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43
KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 PSCLK1/GPIO4A KSI4/GPIO34 PSDAT1/GPIO4B KSI5/GPIO35 PSCLK2/GPIO4C PS2 Interface KSI6/GPIO36 PSDAT2/GPIO4D KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 SDICS#/GPXOA00 KSO4/GPIO24 SDICLK/GPXOA01 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 KSO6/GPIO26 Matrix SDIDI/GPXID0 SPI Device Interface KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 SPIDI/RD# KSO10/GPIO2A SPIDO/WR# SPI Flash ROM SPICLK/GPIO58 KSO11/GPIO2B KSO12/GPIO2C SPICS# KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F CIR_RX/GPIO40 KSO16/GPIO48 CIR_RLC_TX/GPIO41 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 GPIO BATT_LOW_LED#/GPIO54 SCL1/GPIO44 SDA1/GPIO45 SUSP_LED#/GPIO55 S M Bus SCL2/GPIO46 SYSON/GPIO56 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59
FRD#SPI_SO 2 @ 100K_0402_1%
1
2 4.7K_0402_5%
ESB_CLK
2 4.7K_0402_5%
ESB_DAT
6 14 15 16 17 18 19 25 28 29 30 31 32 34 36
122 123
PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A
FSEL#SPICS# 2 @ 100K_0402_1%
2 4.7K_0402_5%
+3VALW BATT_OVP R238 1
1 C297 1 C298 1 C328
10K_0402_5%
2
EC_MUTE# <33> USB_ON# R237 1 USB_ON# <37> ME_FLASH <13> SUS_PWR_DN_ACK <15> +3VALW TP_CLK <35> TP_DATA <35> 4.7K_0402_5% 1 2 R607 R234 1 2 @ 4.7K_0402_5%
BATT_TEMP 2 10K_0402_5%
AC IN
2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J
KB926 SPI STRAP PIN
EN_WOL# <29> BATT_SEL_EC <42> CMOS_OFF# <27>
+3VS 119 120 126 128
FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#
73 74 89 90 91 92 93 95 121 127
PM_BTN# I2C_INT CHARGE_LED0# CAPS_LED# CHARGE_LED1# SYSON AC IN
FRD#SPI_SO FWR#SPI_SI SPI_CLK FSEL#SPICS#
<36> <36> <36> <36>
R241 10K_0402_5%
PM_BTN# <38> I2C_INT <38> FSTCHG <42> CHARGE_LED0# <36> CAPS_LED# <38> CHARGE_LED1# <36> PWR_LED# <36> SYSON <28,39,44> VR_ON <48> ACIN <40>
I2C_INT
PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
GPI
V18R
KB926QFA1_LQFP128
100 101 102 103 104 105 106 107 108 110 112 114 115 116 117 118
EC_LID_OUT# EC_ON ODD_OFF# ICH_POK_EC BKOFF# RST#
EC_RSMRST# <15> EC_LID_OUT# <14> EC_ON <38> D11 ODD_OFF# <32> 1
@ RB751V_SOD323 ICH_POK 2
ICH_POK <15> BKOFF# <27> 1 2 1 2 +3VS WL_OFF# <28> R258 0_0402_5% R251 10K_0402_5% AC_PRESENT <15> @ RST# <38>
6
SLP_S4# <15> ENBKL <27> EAPD <33>
DRAMRST_CNTRL_EC <5>
SUSP# PBTN_OUT#
SUSP# <16,28,39,42,44,46> PBTN_OUT# <15> BT_OFF# <37>
124 1
2
SUSP# C320 4.7U_0805_10V4Z
1
2
@ C318 1000P_0402_50V7K
ECAGND
1
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 G PO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11
XCLK1 XCLK0
R294 1 R271
PWM Output
GND GND GND GND GND
R291 1 R262
needed to update to D3 version SA00001J580
+3VALW R240 EC_SMB_CK1 2 4.7K_0402_5%
1 R239
EC_SMB_DA1 2 4.7K_0402_5%
1
+3VS
1
2
C322 @
R227 2.2K_0402_5%
@
EC_SMB_CK2 EC_SMB_DA2 1
2
@ C291 100P_0402_50V8J
1
2
@ C292 100P_0402_50V8J
15P_0402_50V8J XCLKO
32.768KHZ_12.5PF_1TJS125DJ4A420P 3 NC OUT 4 2
NC
IN
1
R226 2.2K_0402_5%
@ R264 20M_0603_5%
1 2
<16>
<15> SLP_S3# <15> SLP_S5# <16> EC_SMI# <35> LID_SW# <38> ESB_CLK <38> ESB_DAT
2 0_0402_5%
1 R303
INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13
AGND
1 R293
<29> LAN_WAKE#
77 78 79 80
EC_FAN_PWM
1
EC_TACH
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
U13
69
2
R611 10K_0402_5%
PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D
EC_ID
EC_ID to identify KB926 D or E <35>
GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC
11 24 35 94 113
1 R266
10_0402_5%
+3VS
2
1
LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
1 2 3 4 5 7 8 10
2
1
2
KB_RST#
1
C327 1000P_0402_50V7K
+3VALW
2
GATEA20
KB_RST#
2 1 2 1 @ C340 22P_0402_50V8J @ R289
2
<13> SERIRQ <13,28> LPC_FRAME# <13,28> LPC_AD3 <13,28> LPC_AD2 <13,28> LPC_AD1 <13,28> LPC_AD0
<16> <16>
2
1
C341 1000P_0402_50V7K
2 1 ECAGND 2 FBM-11-160808-601-T_0603
1 L13
2
1
C329 0.1U_0402_16V4Z
C294 1000P_0402_50V7K
C339 0.1U_0402_16V4Z
+EC_AVCC
1
1
C319 0.1U_0402_16V4Z
2
C293 0.1U_0402_16V4Z
C290 0.1U_0402_16V4Z
L14 1 2 +3VALW FBM-11-160808-601-T_0603
1
X2 1 C321
2 15P_0402_50V8J
XCLKI
Compal Secret Data
Security Classification Issued Date
2007/10/15
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc. BIOS & EC I/O Port
Size Document Number Custom Date:
R ev 0.3
LA-5752P
Thursday, October 29, 2009
Sheet
34
of
51
5
4
3
2
1
reversal of NIWE1 JP5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
INT_KBD Conn. KSI[0..7] KS O[0..17]
KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 K SI0 KSO1 KSO5 K SI3 K SI2 KSO0 K SI5 K SI4 KSO9 K SI6 K SI7 K SI1
<34>
KSO[0..17] <34>
KSO16
C636 1
2 @ 100P_0402_50V8J
KSO17
C637 1
2 @ 100P_0402_50V8J
KSO2
C203 1
2 @ 100P_0402_50V8J
KSO1
C205 1
2 @ 100P_0402_50V8J
KSO15
C153 1
2 @ 100P_0402_50V8J
KSO7
C186 1
2 @ 100P_0402_50V8J
KSO6
C175 1
2 @ 100P_0402_50V8J
K SI2
C226 1
2 @ 100P_0402_50V8J
KSO8
C185 1
2 @ 100P_0402_50V8J
KSO5
C206 1
2 @ 100P_0402_50V8J
KSO13
C172 1
2 @ 100P_0402_50V8J
K SI3
C225 1
2 @ 100P_0402_50V8J
KSO12
C173 1
2 @ 100P_0402_50V8J
KSO14
C156 1
2 @ 100P_0402_50V8J
KSO11
C155 1
2 @ 100P_0402_50V8J
K SI7
C236 1
2 @ 100P_0402_50V8J
KSO10
C154 1
2 @ 100P_0402_50V8J
K SI6
C235 1
2 @ 100P_0402_50V8J
KSO3
C174 1
2 @ 100P_0402_50V8J
K SI5
C228 1
2 @ 100P_0402_50V8J
KSO4
C187 1
2 @ 100P_0402_50V8J
K SI4
C233 1
2 @ 100P_0402_50V8J
K SI0
C204 1
2 @ 100P_0402_50V8J
KSO9
C234 1
2 @ 100P_0402_50V8J
KSO0
C227 1
2 @ 100P_0402_50V8J
K SI1
C241 1
2 @ 100P_0402_50V8J
EC DEBUG PORT D
JP11 +3VALW <28,34> EC_TX_P80_DATA <28,34> EC_RX_P80_CLK
1 2 3 4
ACES_85205-0400 ME@
G1 G2
Lid Switch
31 32
ACES_85201-3005N ME@
1 R347
+3VALW
+VC C_LID
2 0_0402_5%
CONN PIN define need double check
R353 1
2
C
EC_TX_P80_DATA EC_RX_P80_CLK
1 2 3 4
1
To TP/B Conn.
C
A3212ELHLT-T_SOT23W -3
OUTPUT
3
LID_SW # <34>
2
GND
C398 0.1U_0402_16V4Z
2 100K_0402_5%
VDD
D
KSI[0..7]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
2
1
+5VS
U18
1
C397 10P_0402_50V8J
C150 0.1U_0402_16V4Z JP4 <34> <34>
TP_CLK TP_DATA
TP_CLK TP_DATA
1
2
@ C151 100P_0402_50V8J
1
2
@ C152 100P_0402_50V8J
4 3 2 1
4 3 2 1
Kill Switch
+3VALW
100K_0402_5%
2 R295
E&T_6905-E04N-00R ME@
<34>
KILL_SW #
1
LSSM12-P-V-T-R_3P
3
3
2
2
1
1
KILL_SW#
CONN PIN define need double check
Kill STATUS 1,2(LOW) 2,3(HI)
OFF ON
B
B
SW 2
A
A
Compal Secret Data
Security Classification 2007/10/15
Issued Date
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
Compal Electronics, Inc. KB /SW /LPC Debug Conn.
Size B D ate:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet 1
35
of
51
FOR EC 256KB SPI ROM (150mil PACKAGE) P/N : SA00003GK00 +3VALW
20mils C265 0.1U_0402_16V4Z
R217 10K_0402_5% U9
<34> FSEL#SPICS# <34> FRD#SPI_SO
FRD#SPI_SO
R218 1
FSEL#SPICS# SPI_SO 2 15_0402_5%
1 2 3 4
Changed to BEAD for EMI. Close to EC after C1059.
2
2
1
1
CS# DO WP# GND
8 7 6 5
VCC HOLD# CLK DIO
HOLD# SPI_CLK_R
R215
SPI_SI_EC
MX25L2005CMI-12G SOP
1
FBMA-10-100505-101T 0402 SPI_CLK 2
1
2 15_0402_5%
FWR#SPI_SI
SPI_CLK <34> SPI_CLK_R
FWR#SPI_SI <34>
1
R201
Colse to EC
2
R216 0_0402_5% @ 1
1
C266 10P_0402_50V8J 2
C264 12P_0402_50V8J @
EMI
LED
FD1
3G
FD4
1
2
1
FD2 1
FD3 1
LED1
SC500005B00
1
<34> PWR_LED#
2
2 300_0402_5%
1 R357
A:H_2P8
+5VALW H24 HOLEA
19-213A-T1D-CP2Q2HY-3T_WHITE
H1 HOLEA
H11 HOLEA
H15 HOLEA
H2 HOLEA
H12 HOLEA
W
2 300_0402_5%
1 R359
+5VALW
H22 HOLEA
1 R360
+5VS H6 HOLEA
White
2
1
H7 HOLEA
H9 HOLEA
H14 HOLEA
H4 HOLEA
2
2 300_0402_5%
1 R361
H23 HOLEA
D:H_3P8 X2
+5VS
H13 HOLEA
19-213A-T1D-CP2Q2HY-3T_WHITE
H10 HOLEA
1
1
1
J:H_2P8 X1
LED4
H20 HOLEA
1
1
White
H16 HOLEA
H_4P5X3P0N
H_6P0N
H19 HOLEA
G:H_3P2 X2
H8 HOLEA
H17 HOLEA
1
1
1
1
H_3P0X4P0N
G:H_3P2 X2
H21 HOLEA
1
H27 HOLEA
1
<13> HDD_LED#
1 H3 HOLEA
C:H_3P8
1
2 300_0402_5%
RB751V_SOD323
SC500005B00
1
I:H_3P0 X1 2
1
1
19-213A-T1D-CP2Q2HY-3T_WHITE
D16 1
H5 HOLEA
LED3 2
RB751V_SOD323
<37> BT_LED#
H18 HOLEA
1
1
1
1 +3VALW
4
1
SC500005B00
1 R358
18-225A-S2T3D-C01-3T_ORG-WHITE D17
<28> WLAN_LED#
2 300_0402_5%
1
BATT_CHG_LED#
White
2
1
3
<34> CHARGE_LED0#
O
1
1
1
SC500006M00
LED2
BATT_LOW_LED#
1
Amber <34> CHARGE_LED1#
1
White
Compal Secret Data
Security Classification Issued Date
2007/10/15
Deciphered Date
2008/10/15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Compal Electronics, Inc. LED/EC SPI ROM
Size B Date:
Document Number
R ev 0.3
LA-5752P Thursday, October 29, 2009
Sheet
36
of
51
A
B
C
D
+USB_VCCA +USB_VCCA
1 2 3 USB_ON# 4
GND IN IN EN
8 7 6 5
OUT OUT OUT OC#
+
C430
RIGHT USB PORT X1
150U_B2_6.3VM_R35M USB_OC#1 <16>
W=80mils
+USB_VCCA 1
1
U19 C421 0.1U_0402_16V4Z 2 1 <34> USB_ON#
2
2
JUSB1
1 2 3 4 5 6
USB20_N3 USB20_P3
<16> USB20_N3 <16> USB20_P3
C432 470P_0402_50V7K
APL3510BKI_SO8 C429 @ 1000P_0402_50V7K
W=80mils
2
JUSB2
1 2 3 USB_ON# 4
GND IN IN EN
OUT OUT OUT OC#
8 7 6 5
1 C615 150U_B2_6.3VM_R35M
USB_OC#0 <16>
1
+
2
C622 470P_0402_50V7K
1
C610 @ 1000P_0402_50V7K
2
<13> SATA_DTX_C_IRX_N4 <13> SATA_DTX_C_IRX_P4
USB20_N1
SATA_DTX_C_IRX_N4 SATA_DTX_C_IRX_P4
1 2 3 4
USB20_N1 USB20_P1
SATA_ITX_DRX_P4_CONN SATA_ITX_DRX_N4_CONN ESATA@ 1 C624 SATA_DTX_IRX_N4 1 C623 SATA_DTX_IRX_P4 ESATA@
<13> SATA_ITX_DRX_P4_CONN <13> SATA_ITX_DRX_N4_CONN 0.01U_0402_16V7K 2 2 0.01U_0402_16V7K
2
3
D10 @ +5VALW
BT@
C353
1 R616 2 100K_0402_5% BT@
1
5 6 7 8 9 10 11
GND A+ ESATA AGND BB+ GND
12 13 14 15
GND GND GND GND
USB A+ = RXP A- = RXN B- = TXN B+ = TXP
0.1U_0402_16V4Z
3
2 BT@
OUT
1
2
R304 100K_0402_5%
USB
VBUS DD+ GND
TYCO_1759576-1 ME@
BT MODULE CONN
1 1
PJDLC05_SOT23-3
USB20_P1
3
2
JESAT1
<16> USB20_N1 <16> USB20_P1
2
APL3510BKI_SO8
Low Active
SUYIN_020173MR004S558ZL ME@
W=80mils
+USB_VCCB
E-SATA COMBO LEFT USB PORT
D7 @
1 2 3 4 GND GND GND GND
1
+USB_VCCB +USB_VCCB
2
C237 470P_0402_50V7K
ESATA and USB Conn.
+5VALW
1 2 3 4 5 6 7 8
USB20_N0 USB20_P0
<16> USB20_N0 <16> USB20_P0
1
U27
1
Left USB Conn. +USB_VCCB
3
1
2
C621 0.1U_0402_16V4Z 2 1 <34> USB_ON#
1 2 3 4 G5 G6
ACES_85205-04001 ME@
Low Active
PJDLC05_SOT23-3
1
2
E
Right USB Conn.
+5VALW
2
IN
+3VS Q32
AO3413_SOT23-3 +3VS_BT D
Q31 DTC124EKAT146_SC59-3 BT@
S
GND
BT_OFF#
3
30mils
1 1
BT@
3
<34>
2
G
2
BT_LED#
Q29 DTC124EKAT146_SC59-3 BT@ <16> <16> IN 2 <28>
JP7
USB20_P11 USB20_N11 BT_ACTIVE
1 2 3 4 5 6
USB20_P11 USB20_N11 BTON_LED BT_ACTIVE
1 2 3 4 5 G1 6 G2
7 8
ACES_87213-0600G ME@
3
GND
OUT
1
<36>
0.1U_0402_16V4Z C354 BT@
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2006/08/18
Deciphered Date
2007/8/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
USB ports/BT/E-SATA Size Document Number Custom Date:
R ev 0.3
LA-5752P
Thursday, October 29, 2009
Sheet E
37
of
51
ON/OFF switchSW 1
3
2
4
Power Bottom Board Conn. 8pin SMT1-05_4P
6 5
Power Button TOP Side
+3VALW
2
1
ME@
+5VS
J5
2
ACES_85201-08051
SHORT PADS
Bottom Side
Cap Sensor Board Conn. 6pin ENE SB3534
@
1
R272 100K_0402_5%
1
D14 ON /OFFBTN#
3
ON/O FF#
2
51_ON#
1
ON/OFF# <34>
<34> NUM_LED# <34> CAPS_LED# <34> PM_BTN#
1 2 3 4 5 6 7 8 9 10
PM_BTN# NOVO_BTN# ON /OFFBTN#
51_ON# <40>
DAN202UT106_SC70-3
1 2 3 4 5 6 7 8 GND GND
<34> I2C_INT <34> ESB_DAT <34> ESB_CLK <34> RST#
1
+5VS @ C1 33P_0402_50V8J
S
1
1
@ C2 33P_0402_50V8J
2
3
1
2 1
D20 PJSOT24C 3P C/A SOT-23 @
1
2 51_ON#
PM_BTN#
2
3
ON /OFFBTN#
D19 PJSOT24C 3P C/A SOT-23 @
D13
1
NOVO#
2
1
NOVO_BTN#
R296 100K_0402_5%
51_ON#
2
R603 100K_0402_1%
+3VALW
<40>
2
GND GND 8 7 6 5 4 3 2 1 JP1
ME@
+3VS
PM_BTN#
NOVO#
2 0_0402_5% I2C_ INT_R 2 0_0402_5% 2 0_0402_5%
D
R302 10K_0402_5%
<34>
1 1 1
1
2
2 G Q28 2N7002_SOT23-3
3
E C_ON
EC_ON
R3 R2 R1 +3VS
ACES_85201-08051
<34>
10 9 8 7 6 5 4 3 2 1
JP3
NOVO_BTN#
3 DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00 2ST = SCA00000R00
Card Reader/Audio Jack SB CONN JP8
+3VALW
<33> PLUG_IN <33> HP_OUTR <33> HP_OUTL
PLU G_IN HP_OUTR HP_OUTL
<33> MIC_JD <33> EXT_MIC_L <33> EXT_MIC_R
MIC_ JD EXT_MIC_L EXT_MIC_R
<16> <16>
USB20_P5 USB20_N5
USB20_P5 USB20_N5
1 2 3 4 5 6 7 8 9 10 11 12
1 2 3 4 5 6 7 8 9 10 11 12
GND GND
13 14
ACES_85201-1205N ME@
Issued Date
Compal Electronics,Ltd.
Compal Secret Data
Security Classification 2008/03/25
Deciphered Date
2008/04/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Audio Jack & SW connector Size Document Number C ustom D ate: Thursday, October 29, 2009
R ev 0.3
LA-5752P Sheet
38
of
51
A
B
C
+5VALW TO +5VS
D
+3VALW TO +3VS
E
+1.5V to +1.5VS
B+
R202 470_0603_5% @
1
2
1 C134 10U_0805_10V4Z
2
C135 1U_0603_10V4Z
B+
D
+1.8VS
1
2
100K_0402_5% R312
2 C278 0.1U_0603_25V7K
SUSP
+1.5V
+VCCP
D
R88 0_0402_5%
Q9 2N7002_SOT23
2 G
+0.75VS
S
@
Q33
1
2
C144 0.1U_0603_25V7K
D
1
2 G 2N7002_SOT23S
2 SUSP G Q34 2N7002_SOT23 @
1.5VS_GATE 1 1 DIS@ C373 C361 0.1U_0603_25V7K 2 2 0.1U_0603_25V7K
R313 0_0402_5%
SUSP
3
2
S
S
2 1
1
3
15VS_GATE_R
10K_0402_5% Q20 2N7002_SOT23
1
D
2 G
3
1
5VS_GATE2 R228 SUSP
S R89 47K_0402_5%
2 SUSP G Q6 2N7002_SOT23 @
R314 470_0603_5% @
D
B+
D 2 SUSP G Q16 2N7002_SOT23 @
3
3
S R229 20K_0402_5%
R87 470_0603_5% @
3
2
C276 1U_0603_10V4Z
2
2 SI4800BDY-T1-E3_SO8
C277 10U_0805_10V4Z
1
1
1
1
1
1
1 2 3 4
1
S S S G
1 2
2
D D D D
1 2
1
8 7 6 C279 5 10U_0805_10V4Z
2
U4 8 D 1 S 7 D S 2 6 D S 3 C127 5 D G 4 10U_0805_10V4Z 2 SI4800BDY-T1-E3_SO8
U10 1
+1.5VS U16 8 D 1 S 7 1 1 1 D S 2 6 D 3 S C389 C362 C363 5 G 4 10U_0805_10V4Z D 10U_0805_10V4Z 1U_0603_10V4Z 2 2 2 SI4800BDY-T1-E3_SO8
+3VS
1
+3VALW
1
+5VS
1
+1.5V
+5VALW
@
+1.05VS
S
3
S
D 2 SUSP G Q15 2N7002_SOT23 @
R143 470_0603_5% @
D 2 SUSP G Q40 2N7002_SOT23
S
3
D 2 SYSON# G Q35 2N7002_SOT23 @
1 2
R568 22_0603_5% 1 2
R174 470_0603_5% @
1
1
1
S
3
3
S
D 2 SUSP G Q10 2N7002_SOT23 @
3
D
R342 470_0603_5% @
1 2
R142 470_0603_5% @
1 2
1 2
1
2
1
2
2 SUSP G Q11 2N7002_SOT23 @
For Intel S3 Power Reduction.
3
RTCVREF
3
+5VALW
@ R5 100K_0402_5%
SYSON
2
IN
2 1 3
<28,34,44> SYSON
3
IN
GND
2
<16,28,34,42,44,46> SUSP#
OUT
SYSON# Q2 DTC124EKAT146_SC59-3 @
OUT
Q1 DTC124EKAT146_SC59-3
GND
2
@ R6 100K_0402_5%
1
SUSP
2
R4 100K_0402_5% <8,44,45> SUSP
1
1
1
+5VALW
4
4
2006/08/18
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2007/8/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
D
Title
DC Interface Size Document Number Custom Date:
R ev 0.3
LA-5752P Sheet
Thursday, October 29, 2009 E
39
of
51
B
C
D
ACIN
2
VIN
PQ26 TP0610K-T1-E3_SOT23-3
PR38 1K_1206_5% 1 2
1
3
PR31 1K_1206_5% 1 2 PR143 100K_0402_1% 2 1
PD13 RLS4148_LL34-2
V IN
VS
<34,42>
2
ACOFF
PQ11
3 2
2
1 2
1
PC12 0.01U_0402_25V7K
1 2 8
2
1
2 1 PR22 499K_0402_1% 2 G
PR136 47K_0402_5% 1
PACIN <42>
VS
3
2
-
JRTC
1
+RTCBATT
@ MAXEL_ML1220T10
1
2
+CHGRTC
RB751V-40_SOD323-2 4
RTC Battery
2
PC91 10U_0603_6.3V6M
+ 1
PR123 200_0603_5%
2CHGRTCIN 1
IN GND
PQ25 DTC115EUA_SC70-3
PD8
PC90 1U_0805_25V6K
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2
OUT
1
3
+5VALW
2
51ON-3
PU8 G920AT24U_SOT89-3
3.3V
2
PQ3 SSM3K7002F_SC59-3
PC16 0.1U_0603_25V7K
1
+CHGRTC
2009/01/06
Deciphered Date
2010/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
D
3
3
1
1
3
RTCVREF PR125 PR124 560_0603_5% 560_0603_5% 1 2RTCVREF-1 1 2
PR17 10K_0402_5% 2 1
RTCVREF
2
4
6
2
1
PC4 0.22U_0603_25V7K
2
1 2
PR16 22K_0402_1% 1 2
5
-
S 51ON-2
PR15 100K_0402_1%
<38> 51_ON#
PR140 68_1206_5% 2
PR141 PQ4 68_1206_5% TP0610K-T1-E3_SOT23-3 PR122 200_0603_5% CHGRTCP 1 2
2
51ON-1 1
1
PD12 LL4148_LL34-2 2 1
1
BATT+
+
O
PC98 0.1U_0603_25V7K
PD2 LL4148_LL34-2
P 7
PU10B LM393DG_SO8
2
<42> ACON
G
VIN
PD10 RB715F_SOT323-3 2 1 3
4
<41,43> MAINPWON
2 1 PR24 499K_0402_1%
2
VS
3.3V
3
2
PR25 2.2M_0402_5% 2 1
VL
1 PR23 205K_0402_1%
<42>
PC99 0.01U_0402_25V7K
PACIN
PC11 1000P_0402_50V7K
<34>
2 1 PR137 100K_0402_1%
RTCVREF
AC IN
1 PR19 10K_0402_5%
1 2
PD9 LLZ4V3B_LL34-2 PR20 10K_0402_5% 2 1
B+ PQ12 DTC115EUA_SC70-3
PACIN
1
O
PU10A LM393DG_SO8
DTC115EUA_SC70-3 2
3
PR18 10K_0402_1% 1 2
2
1 P
-
G
8 +
4
1 2
1 2
PR135 20K_0402_1%
3 VINDE-3 2
PC13 0.1U_0402_16V7K
2
PR27 22K_0402_1% 1 2
VINDE-1 PC14 1000P_0603_50V7K 2 1
2
PR134 84.5K_0402_1%
1 PR21 10K_0805_5%
PC97 0.01U_0402_25V7K
1
2
PRG++ 2
VINDE-2 V IN
1
PR26 1M_0402_1% 1 2
1 2
1
1
Max. 18.384V 17.728V
1
1
Vin Detector Min. typ. L-->H 17.430V 17.901V H-->L 16.976V 17.262V
1
PR142 1K_1206_5% 1 2
2
1 2
PC5 1000P_0402_50V7K
1 2
PC6 100P_0402_50V8J
2
1
PC7 0.1U_0603_25V7K
1 2
2
@ 4602-Q04C-09R 4P P2.5 J DC IN
PC10 100P_0402_50V8J
1
1
2
1
2
3
2
PL2 SMB3025500YA_2P 1 2
PC9 1000P_0402_50V7K
3
PF1 7A_24VDC_429007.W RML APDIN 1 2 APDIN1
1
4
PC8 0.1U_0603_25V7K
1
4
PR138 100K_0402_1% 2 1
DC030006J00
BATT ONLY Precharge detector Min. typ. Max. L-->H 7.196V 7.349V 7.505V H-->L 6.138V 6.214V 6.056V
Precharge detector Min. typ. Max. L-->H 14.991V 15.381V 15.782V H-->L 13.860V 14.247V 14.621V
VIN
PR39 100K_0402_1%
A
B
C
Title
DCIN & DETECTOR Size Document Number Custom Date:
R ev 0.1
Thursday, October 29, 2009 D
Sheet
40
of
51
A
B
C
D
1
1
VMB
VS
PH1 100K_0402_1%_TSM0B104F4251RZ
2
PR84 47K_0402_1% TM-2
TM-1
3 2
+
O -
1
1
1
D
S
PQ20 SSM3K7002FU_SC70-3
2 G
PU4A LM393DG_SO8
1
VL
PR85 100K_0402_1% PR86 100K_0402_1% 5
+
6
-
O G
A/D
BATT_TEMP <34>
P
2
2
2
TM-3
1
4
1 2 PR5 10K_0402_5%
+3VALW
PC64 1000P_0402_50V7K
1 2 PR6 6.49K_0402_1%
2
PC63 0.22U_0603_25V7K 2 1
EC_SMB_DA1 <34>
PR88 15.4K_0402_1%
4
TM_REF1
EC_SMB_CK1 <34>
MAINPW ON <40,43> 2
8
PR87 13.7K_0402_1% 1 2
PR83 47K_0402_1% 1
1
PC109 0.01U_0402_25V7K
VL
3
1
2
1 2
2
PC110 1000P_0402_50V7K
2
TYCO_1775789-1 @
2 1 PR3 100_0402_1%
1
1
EC_SMCA EC_SMDA
2
VL
1
BATT+
8
PL3 SMB3025500YA_2P 1 2
P
1 2 3 4 5 6 7 8 9
2 1 PR4 100_0402_1%
2
1 2 3 4 5 6 7 GND GND
G
PF2 12A_65V_451012MRL 1 2
JBATT
PC62 0.01U_0402_25V7K
VMB2
PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C
3
7
PU4B LM393DG_SO8
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2009/01/06
Deciphered Date
2010/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A
B
C
Title
BATTERY CONN / OTP Size Date:
Document Number
R ev 0.1
Thursday, October 29, 2009 D
Sheet
41
of
51
5
4
3
2
1
B+
P3 P2
PR152 0.02_1206_1%
8 7 6 5
CHG_B+ PJ11
1 2 3
PR28 47K_0402_1% 1 2
2 1 1 18
VREF
UGATE
17
9
CHLIM
BOOT
16
10
ACLIM
VDDP
15
11
VADJ
LGATE
14
12
GND
PGND
13
DH_CHG PR157 2.2_0402_5% BST_CHG 1 2
PC120 0.1U_0603_25V7K BST_CHGA 2 1
DL_CHG
4
PD14 RB751V-40TE17_SOD323-2
6251_VDDP
2
PR2 31.6K_0402_1%
1
26251_VDD
1
PR163 4.7_0402_5% PC122 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
Connect to EC A/D Pin.
CHGVADJ=(Vcell-4)/0.10627 CHGVADJ
BATT+
+
5
-
6
<34> BATT_OVP
+
3
-
2
1
4
4
PR11 @ 105K_0402_1%
2
1
2
2
PR12 100K_0402_1% 1
A
PQ38 DTC115EUA_SC70-3
3
2
5
2
FSTCHG
3
SUSP#
1
PD1 RB715F_SOT323-3
FSTCHG <34>
2007/6/22
Issued Date
3
2 1
1
3
5 4
2
1 PR177 @ 0_0402_5%
<34> BATT_SEL_EC PQ1B @ 2N7002KDW -2N_SOT363-6
A
Compal Electronics, Inc. 2008/6/22
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
2
PQ1A @ 2N7002KDW -2N_SOT363-6
Compal Secret Data
Security Classification
SUSP# <16,28,34,39,44,46>
PR176 0_0402_5%
2
1 2 PU1A @ LM358DT_SO8 1 0
8
PR139 @ 10K_0402_1% 1 2
CELLS
PR10 @ 499K_0402_1%
1
6251_DCIN
8
PU1B @ LM358DT_SO8 7 0
P
1
PR14 10_0603_5% 1 2
Per cell=3.5V
G
3 PR13 100K_0402_1% 2 1
P3
TP0610K-T1-E3_SOT23-3
BATT-OVP=0.1112*VMB
P
PQ2
LI-3S :13.5V----BATT-OVP=1.5012V
G
VCHLIM need over 95mV
PC100 @0.01U_0402_25V7K
DIS CP mode Vaclim=2.39*{(31.6K//514K)/((31.6K//514K)+(21K//514K))}=1.425V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) VS where Vaclim=1.425V, Iinput=4A
2
IREF=1.016*Icharge IREF=0.254V~3.048V
PR168 PR178 @ 100K_0402_1% @ 100K_0402_1%
PR9 @ 340K_0402_1%
6
VS
6251_VDD
2
VMB2
1
CC=0.25A~3A
B
6251_VDD
PR1 31.6K_0402_1%
1
3.2935V
UMA CP mode Vaclim=2.39*{(2.26K//514K)/((2.26K//514K)+(21K//514K))}=0.239V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.239V, Iinput=2.75A
2
1.882V
2 1 PC101 @0.01U_0402_25V7K
4.35V
3
1
4.2V
<34> CHGVADJ
4
2
0V 1
4V
C1HG
PR171 15.4K_0402_1% 1 2
2
Vcell B
2
PR151 0.02_1206_1%
C
PC105 10U_1206_25V6M 2 1
PHASE
ICM
PL5 10U_LF919AS-100M-P3_4.5A_20%
PQ5 2N7002KW _SOT323-3
PC103 10U_1206_25V6M 2 1
19
1
CSIP
PACIN
2 G S
3
VCOMP
V IN
D
PC106 10U_1206_25V6M 2 1
6
4
PC121 0.1U_0603_25V7K 2 1
20
3
CSIN
1
ICOMP
2
5
CSOP
PR162 200K_0402_1% 1 2
2
PR154 4.7_1206_5%
21
PD3 RB715F_SOT323-3
1
CSOP
PQ29 SIS412DN-T1-GE3 _PAK1212-8
CELLS
5
4
CSON
PC124 0.047U_0402_16V7K 1 2 PR160 20_0402_5% 2 1 PR159 PC123 20_0402_5% 0.1U_0402_16V7K 1 2 PR158 2.2_0402_5% LX_CHG
3 2 1
22
1
CSON
2
1 2
3
PR167 100K_0402_1%
EN
1 2 7 PR174 100_0402_1% 6251_VREF 8
1 2 PC1 0.1U_0402_16V7K PR172 21K_0402_1% 6251_VREF 1 2
ACOFF
3
PC118 680P_0603_50V7K
IREF
2
3
PR161 20_0402_5% 1 2
PQ31 SI7716ADN-T1-GE3 _PAK1212-8
<34> ACOFF
ADP_I PR173 154K_0402_1% 2 1
23
5
1 2 PC130 @ 100P_0402_50V8J
ACSET ACPRN
1
1
<34>
ACOFF
VIN
1
PQ32 DTC115EUA_SC70-3
3 2 1
0.01U_0402_25V7K
6.81K_0402_1% 2
2
1
1
ACON PQ10 DTC115EUA_SC70-3
<34,40>
PR175 2
24
2
PC3 1
2 G
6800P_0402_25V7K 2
DCIN
1
3
S
PC131 1
VDD
2
1
PQ9 D 2N7002KW _SOT323-3
PC2 0.01U_0402_25V7K 2 1
<40>
PACIN
1 2
CELLS
C
PR37 3K_0402_1% PACIN 1 2
6251_EN
1
PC125 0.1U_0603_25V7K 6251_DCIN2 1
2
S 2
3
2 G
PR8
1
PR29 150K_0402_1%
1
PQ8 D 2N7002KW _SOT323-3
2 PC132 0.1U_0402_16V7K
PU11
2
3
<34> FSTCHG
1
<40>
D
2
1
PR7 10K_0402_1% 2 1 100K_0402_1%
PQ28 DTC115EUA_SC70-3
PR155 10K_0402_1%
PC128 2.2U_0603_6.3V6K 2 1
PD15 RB751V-40TE17_SOD323-2 6251_VDD 1 2
1 2
8 7 6 5 4
PC111 2200P_0402_50V7K
CS IN CSIP
PC113 4.7U_1206_25V6K 1 2
1 2
@ JUMP_43X118
1
2
PC107 0.1U_0603_25V7K 2 1 PR30 200K_0402_1%
3
PQ7
PQ34 FDS6675BZ_SO8
1
1
PC114 4.7U_1206_25V6K 1 2
3
2
2
2
2
1
4
PC112 4.7U_1206_25V6K 1 2
1
2
4
4
1 PR145 47K_0402_5%
DTA144EUA_SC70-3
2
D
1 2 3
1
VIN
PQ6 FDS6675BZ_SO8 1 2 3
PC15 470P_0603_50V8J
PQ27 FDS6675BZ_SO8 8 7 6 5
2
Title
CHARGER Size Date:
Document Number
R ev 0.1
Thursday, October 29, 2009
Sheet 1
42
of
51
5
4
3
ISL6237_B+
PHASE2
PHASE1
16
LG3
23
LGATE2
LGATE1
18
LG5
FB3
PGND
22
30
OUT2 OUT1
10
FB1
11
BYP
9
SKIP
29
NC
POK2
28
EN_LDO
POK1
13
EN1
ILIM1
12
ILM1
ILIM2
31
ILIM2
32
VL
2
1
REF
8
LDOREFIN
PC102 0.22U_0603_25V7K PD11 2
3/5V_EN1 14
PC42 0.22U_0603_25V7K
3/5V_EN2 27
EN2
GND
4
5V_SKIP
2
2
21
2
PU2 ISL6237IRZ-T_QFN32_5X5
PC37 0.1U_0402_25V6 2 1
+
PC117 150U_B2_6.3VM_R45M
2
C
VL
2VREF_ISL6237
2 1 PR34 301K_0402_1% 2 1 PR147 301K_0402_1% B
13/5V_TON
PR50 0_0402_5%
2 1 PR150 @ 0_0402_5% 1 2 PR149 0_0402_5% 2 1 PR51 @ 0_0402_5%
PR43 0_0402_5%
PJ10
+3VALWP
2
1
0_0402_5% <40,41>
PC36 2200P_0402_50V7K 2 1
FB5
2
2
1
1
+3VALW
@ JUMP_43X118 2VREF_ISL6237
PR33 @ 47K_0402_1%
1
MAINPW ON
1
2VREF_ISL6237 1
1
PR32 2
PC108 0.047U_0402_16V7K 2 1
RB751V-40_SOD323-2
PC104 0.047U_0402_16V7K
2
PR146
1
2
PD4
806K_0603_1%
VL
B
PC28 1U_0603_10V6K 2 13/5V_NC 5
2
LLZ5V1B_LL34-2
EN_LDO
TON
20
PR44 100K_0402_1% 2
NC
1
2
EN_LDO-1
PR144 200K_0402_1% 1 2
2
1
PD5 1
PC25 10U_1206_25V6M 2 1
PQ33 SI7716ADN-T1-GE3_PAK1212-8
RB751V-40_SOD323-2
VS
PC119 680P_0402_50V7K
REFIN2
2VREF_ISL6237 1
PC22 0.1U_0603_25V7K
1
2
25
SW 5
4 1
SW 3
PR156 4.7_1206_5%
1BST5A-1
PR36 @ 61.9K_0402_1% 1 2
BST5A2 PR40 2.2_0603_5%
+5VALWP
1
HG5
17
15V_SNB 2
15
BOOT1
PC43 0.1U_0603_25V7K
@
1
3 2 1
UGATE1
5
7
19
PQ13 SIS412DN-T1-GE3_PAK1212-8 PL6 4.7UH_PCMC063T-4R7MN_5.5A_20% 2 1
3 2 1
BOOT2
LDO
VCC
UGATE2
24
PC40 1U_0603_10V6K 1 2
PVCC
2
2
VIN
26
4.7U_0805_6.3V6K
PC23 2 1
PC41 3/5V_VCC 1 2 3
1U_0603_10V6K
3/5V_VIN
2 1
UG3 BST3A
1 2 3
1
2 1 PR42 2.2_0603_5%
4
D
PR35 0_0402_5% 1 2
2
TP
PQ30 SI7716ADN-T1-GE3_PAK1212-8
PR148 10K_0402_1%
1
C
VL
1 2 3 1
PC115 680P_0402_50V7K
4
2
2
BST3A-1
13V_SNB 2
2 1
+
PR153 4.7_1206_5%
PR52 0_0402_5%
1
33 5
PL4 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2
+3VALWP
PC27 0.1U_0603_25V7K
PQ14 4 SIS412DN-T1-GE3_PAK1212-8
6
5
5
PC39 2200P_0402_50V7K 2 1
PC26 10U_1206_25V6M 2 1
PR41 0_0402_5% 1 2
PC38 0.1U_0402_25V6 2 1
PC21 330P_0402_50V7K 2 1
PJ4 @ JUMP_43X118 2 2 1 1
PC116 150U_B2_6.3VM_R45M
1
ISL6237_B+
B+
D
2
@
PJ12
+5VALWP
2
2
1
1
+5VALW
@ JUMP_43X118
A
A
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
3VALW/5VALW
Size Document Number Custom Date:
R ev 0.1
Thursday, October 29, 2009
Sheet 1
43
of
51
5
4
3
2
1
PJ20
1 PU14 TPS51117RGYR_QFN14_3.5x3.5
PC183 4.7U_0805_6.3V6K
2 1 PC174 2200P_0402_50V7K
2 1 PC173 0.1U_0402_25V6
+ 2
1
TP
7
PC179 @0.1U_0402_16V7K
DRVL
4
1
B+
+1.5VP
2
LG_1.5V
PR241 4.7_1206_5%
1
PC177 10U_0603_6.3V6M
9
+5VALW
1
D
PC172 220U_B2_2.5VM_R15M
V5DRV
10
SW 1 _1.5V 2 PR245 7.15K_0402_1%
PGND
PGOOD
1
PC181 PR243 @ 47P_0402_50V8J @ 100K_0402_1% 1 2
8
6
GND
2
2
2
PC178 4.7U_0603_6.3V6K
1
1
1.5V_TRIP
11
1.5V_SNB 2
12
1
VFB
LL TRIP
1
5
UG_1.5V
2
@ JUMP_43X79
PC180 680P_0402_50V7K
2
1.5V_FB
PQ48 SI4686DY-T1-E3_SO8 PL13 1UH_PCMB103E-1R0MS_20A_20% 1 2 TPCA8028-H_SOP-ADVANCE8-5
V5FILT
13
PQ49
VOUT
4
DRVH
5
3 1.5V_V5FILT
VBST
TON
3 2 1
15
1
PR242 100_0603_1% 1 2
+5VALW
2
EN_PSV
2
PC184 @0.1U_0402_16V7K
2BST_1.5V-1 1 2 PC182 0.1U_0603_25V7K
3 2 1
BST_1.5V 1 PR249 2.2_0603_5% 14
1.5V_EN 1
<28,34,39> SYSON
4
2
PR248 0_0402_5% 1 2
2 1 PC175 10U_1206_25V6M
PR247 240K_0402_1% 1 2
1.5V_TON
D
2
2 1 PC169 10U_1206_25V6M
5 6 7 8
1.5V_IN
1.5V_PGOOD
1
PR244 31.6K_0402_1% 1 2
C
C
PR246 30.1K_0402_1% 2
PJ16
VCCP_EN
B+
@
@
DRVL
9
LG_VCCP
4
PU9 @ TPS51117RGYR_QFN14_3.5x3.5
PC92 4.7U_0805_6.3V6K @
+ 2
@
1
1
B
@ PC135 @ 680P_0402_50V7K
PQ40 SI7716ADN-T1-GE3_PAK1212-8 @
1.05V_PGOOD <46>
PR129 13.7K_0402_1% 2 @1
PR181 @ 4.7_1206_5%
2
1 +5VALW
PC137 10U_0603_6.3V6M
10
+1.05VSP PC136 220U_B2_2.5VM_R15M
V5DRV
VCCP_TRIP 1 2 PR128 @ 23.7K_0402_1%
2
SW _VCCP
11
1
12
5
VBST
LL TRIP
2
PR126 100K_0402_1%
TP
EN_PSV
PGOOD
2
6 PC94 @ 47P_0402_50V8J 1 2
UG_VCCP
3 2 1
VFB
13
1
5
DRVH
2
VCCP_FB
PGND
V5FILT
8
VOUT
4
PL9 @ 2.2UH_PCMC063T-2R2MN_8A_20% 1 2
14
15
1 3 VCCP_V5FILT
1
2
TON
GND
1 PC93 4.7U_0603_6.3V6K @
B
@
VCCP_SNB
+3VS
2
7
2
PC96 0.22U_0402_6.3V6K @
PR127 100_0603_1% 1@ 2
+5VALW
1
0.1U_0603_25V7K
1
<16,28,34,39,42,46> SUSP#
4
PR131 @ PC95 2.2_0603_5% @ BST_VCCP1 2BST_VCCP-1 1 2
3 2 1
PR132 @ 100K_0402_1% 1 2
@
1
2 1 PC141 2200P_0402_50V7K
VCCP_TON
2
@ JUMP_43X79
2 1 PC138 0.1U_0402_25V6
PQ41 SIS412DN-T1-GE3_PAK1212-8 @ PR133 240K_0402_1% 1 2
2
2 1 PC140 10U_1206_25V6M
5
VCCP_IN
1
@
PR130 31.6K_0402_1% @
PJ17 @ JUMP_43X79
2
1
1
2
+1.5V
PJ21
5
6
2
GND
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
2
+1.5VP
+3VALW
2
1
1
+1.5V
@ JUMP_43X118
2
PC151 1U_0402_6.3V6K PJ14
+1.05VSP
2
2
PJ19 1
1
+1.05VS
2
+0.75VSP
@ JUMP_43X118
2
1
1
+0.75VS
@ JUMP_43X79
G2992F1U_SO8
1
+0.75VSP
S PQ46 SSM3K7002FU_SC70-3
PC149 10U_0603_6.3V6M
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
1
1 PC176 0.1U_0402_16V7K 2
PR240 1K_0402_1%
2
PC147 @ 0.1U_0402_16V7K
3
1
SUSP
D
2
<8,39,45>
0.75V_REF
PR190 0_0402_5% 1 20.75V_EN 2 G
2
<5> S3_0.75V_EN
VCNTL
2
PR250 0_0402_5% 1 2
1
@
A
VIN
1
1
PR239 1K_0402_1%
2
PC146 4.7U_0805_6.3V6K
1
1
2
PU13 0. 75V_IN
2010/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4
3
2
Title
1.5V/VCCP/0.75V Size Date:
Document Number
R ev 0.1
Thursday, October 29, 2009
Sheet 1
44
of
51
A
5
4
3
2
1
PJ3 2
2
1
VG A_IN
1
+3VS 2 1 PC185 2200P_0402_50V7K
UG_VGA @ PR47 10K_0402_5% 1 2
BST_VGA 1 2 PR48 2.2_0603_5%
BST_VGA-1 1 2 PC49 0.1U_0603_25V7K
+5VALW 1
2 1 PC186 0.1U_0402_25V6
2
1
PC35 10U_1206_25V6M
2
1
PC24 10U_1206_25V6M
@ JUMP_43X79
D
PR49 0_0603_5%
D
5
B+
2
15
1 2
1 2
1
+ 2
PC18 10U_0603_6.3V6M
2
1
2
+
PC19 10U_0603_6.3V6M
1
5 6 7 8 PQ36 SI4634DY-T1-E3_SO8
3 2 1
10
1
C
VGA_FB-1 1 PR179 1.82K_0402_1%
1
PR71 0_0402_5% 2
+VGASENSE <21>
1
PJ2
+VGA_COREP
PR180 5.36K_0402_1%
2
2
1
1
+VGA_CORE
@ JUMP_43X118
2
PJ13 2
2
3 2 PQ37B 2N7002KDW -2N_SOT363-6
PJ606 1
+1.8VSP
4
5
1
1
@ JUMP_43X118
PC129 0.01UF_0402_25V7K
1
B
2
2
+1.8VS
@ JUMP_43X39
2
2
3 2 1
VO
Rds=4.0mΩ
4
1 2 PR69 42.2K_0402_1%
7 VGA_FB
1VGA_COMP-1 2 1 PR68 22.1K_0402_1%
PR67 6.04K_0402_1%
1
1
2 1 PC55 FSET_VGA9 0.01U_0402_25V7K
6 PQ37A 2N7002KDW -2N_SOT363-6
4
@
VFB=0.6V
2 1GVID0-1 PR170 10K_0402_1%
PR72 10K_0402_5%
2
PR63 3.6K_0402_1%
2
22P_0402_50V8J PC54 6800P_0402_25V7K
PR169 22.6K_0402_1% 1 2 GVID1-2
PC127 0.01UF_0402_25V7K
2
<19> GPU_VID0
B
ISEN_VGA1
+VGA_COREP
1
6 2
PR165 10K_0402_5%
11
2
1
1
1
<19> GPU_VID1
2
PC134
1
GPIO5 GPIO6 N11M-GE1/LP1
2 1GVID1-1 2 PR166 10K_0402_1%
FSET
FB
COMP
1
VGA_COMP C
GPU_VID0 GPU_VID1 VGA_CORE 0.8V 0 0 0 1 0.85V N11M-GE1/LP1 PR620=22.6k 1 1 0.9V
ISEN
EN
2
PC51 1U_0402_6.3V6K
12
PQ39 SI4634DY-T1-E3_SO8
5
PGND
PC20 10U_0603_6.3V6M
3 2 1 5 6 7 8
PC50 2.2U_0603_6.3V6K
1 2VGA_EN_2 PR62 2.2K_0402_5%
VGA_EN
PL7 0.88UH_PCMB103E-R88MS_20A_20% 1 2
SW _VGA
1 2 <16>
TPCA8030-H_SOP-ADV8-5
PC133 330U_D2_2.5VY_R9M
13
2
PC17 330U_D2_2.5VY_R9M
LG
PC52 2.2U_0603_6.3V6K LG_VGA
PR70 100_0402_5% 2 1
VCC
+VGA_PVCC 1
PR164 4.7_1206_5%
BOOT
PU3 ISL6268CAZ-T_SSOP16
14
1VGA_SNB 2
16 UG
PVCC
2
4
1
2
VIN
4
PC126 680P_0402_50V7K
VGA_VCC
PHASE
3
PGOOD
GND
8
PQ35 PR46 4.7_0603_5% 1 2 VGA_VCC
2
PU6 1
VIN
VCNTL
6
2
GND
NC
5
3
VREF
NC
7
4
VOUT
NC
8
TP
9
2
2
A
LDO_1.8V_REF
5
A
G2992F1U_SO8 +1.8VSP
1
PC78 10U_0603_6.3V6M
PQ22 SSM3K7002FU_SC70-3
2
S
4
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification 1
PC77 0.1U_0402_16V7K 2
PR105 1.24K_0402_1% 2
3
PC76 0.1U_0402_16V7K
PC79 1U_0402_6.3V6K
1 1
D
1
SUSP
2
<8,39,44>
PR103 100K_0402_1% 1 2LDO_1.8V_EN 2 G
+5VS
1 PR104 1K_0402_1%
2
PC75 4.7U_0805_6.3V6K
1
2
LDO_1.8V_IN
1
PJ8 @ JUMP_43X39
1
1
+3VS
2010/01/06
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3
2
Title
VGA_CORE/1.8VS/1.1VS Size Date:
Document Number
R ev 0.1
Thursday, October 29, 2009
Sheet 1
45
of
51
5
4
3
2
1
D
D
PJ9 VTT_B+
1
+5VS
SW_VTT PR112 2.2_0603_5% 2 VTT_BOOT-1
ISEN
11
VO
5
C
PR107 4.7_1206_5%
1 +
VTT_SNB 2
PC80 1000P_0603_50V7K
1 + 2
@
PR110 10_0402_5%
PC82 0.01U_0402_25V7K @
1
2
1
2
10
3 2 1
Rds=4.0mΩ
4
3 2 1
4
PR109 3K_0402_1%
PQ23 TPCA8028-H_SOP-ADVANCE8-5
5 2
+1.1V_VCCPP
1
VTT_COMP-1 2
9
6
1
1
VFB=0.6V
1
2 PR121 35.7K_0402_1%
VTT_ISEN 1
PL8 0.56UH_MMD-10CZ-R56M-M1_19A_20% 1 2
PC139 330U_D2E_2.5VM
12
TPCA8030-H_SOP-ADV8-5
PC74 330U_D2E_2.5VM
PGND
2
1
UG
BOOT LG
13
PC81 2.2U_0603_6.3V6K LG_VTT
2
PC89 6800P_0402_25V7K
1 2
PC88
22P_0402_50V8J
1
VTT_COMP
<8> VTT_SELECT
FB
1 2
PC87 @ 0.1U_0402_16V7K
FSET
EN COMP
5
2 1 VTT_FSET PR113 42.2K_0402_1%
VTT_EN-1
7
PR117 0_0402_5% 1 2
PC86 2.2U_0603_6.3V6K
PR118 22.1K_0402_1% VTT_FB
@ <44> 1.05V_PGOOD
2
C
B
14
4
1 2
VCC
PQ24
PR108 4.7_0603_5% 1 2 VTT_VCC
VTT_PVCC 1
PVCC
PU7 ISL6268CAZ-T_SSOP16
5
1
PR106 0_0603_5%
2
4
VIN
2
1
<16,28,34,39,42,44> SUSP#
VTT_VCC
PHASE
PGOOD
GND 3 PR116 0_0402_5% 1 2
1
PC84 0.1U_0603_25V7K
+5VALW
PQ21 TPCA8028-H_SOP-ADVANCE8-5
VTT_BOOT1
3 2 1
UG_VTT
2
8
1.1VS_PGOOD
<5> VCCP_POK
2
PR114 0_0402_5% 1 2
15
1
2 1 PC187 2200P_0402_50V7K
PC85 10U_1206_25V6M 2 1 PC188 0.1U_0402_25V6
1 2
PC83 10U_1206_25V6M 2 1
@ JUMP_43X118
16
1
PR115 1K_0402_5%
2
1
2
2
B+
H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V
2 PR120 1.58K_0402_1%
VTT_FB-1
2
PR111 0_0402_5% 1
B
VTT_SENSE <8>
2
PR119 1.96K_0402_1%
PJ15
+1.1V_VCCPP
2
2
1
1
+VCCP
@ JUMP_43X118 PJ7 2
2
1
1
@ JUMP_43X118
PJ1
+1.1V_VCCPP
2
2
1
1
+1.05VS
@ JUMP_43X118 A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification 2009/01/06
Issued Date
Deciphered Date
2010/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Title
+1.1VS_VTT Size Document Number Custom Date:
R ev 0.1
Thursday, October 29, 2009
Sheet 1
46
of
51
5
4
3
2
1
D
D
B+
PR224 @ 0_0402_5%
1
VSS_AXG_SENSE <8>
ISUM+
14
3 2 1
PL12 0.56UH_MMD-10CZ-R56M-M1_19A_20% 1 2
@
GFX_SN
@
+ P R81 2 0_0402_5%
1 2ISUM-2 1 PR227 @ 2.61K_0402_1% P C60 @ @ 680P_0402_50V7K
1 + 2
2 PH 4 10KB_0603_5%_ERTJ1VR103J @ @
@
1 2 P R90 11K_0402_1%
@
@
@ @ @ @ @ @ @ @
1 2 PC70 0.068U_0402_10V6K P R93 @ 3.01K_0402_1% PR94 82.5_0402_1% 1 2ISUM-3 1 2
GFXVR_VID_0 <8> GFXVR_VID_1 <8> GFXVR_VID_2 <8> GFXVR_VID_3 <8> GFXVR_VID_4 <8> GFXVR_VID_5 <8> GFXVR_VID_6 <8> GFXVR_EN <8>
1
PR237
P R89 @ 100_0402_1%
P C68 @ 0.01U_0402_25V7K ISUM+
0_0402_5% 2
2
PR228 PR229 PR231 PR232 PR233 PR234 PR235 PR236
1 1 1 1 1 1 1 1
2ISUM-4 1
2 2 2 2 2 2 2 2
B
@
P C69 @ 180P_0402_50V8J
@
1
0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
ISUM-1
@ 1 2 P C65 0.1U_0402_16V7K
@
GFXVR_CLKEN#
PR82 3.65K_0402_1%
PC158
330U_D2_2.5VY_R9M
2 @
62881_VID0
62881_VID1
@ P C66 2.2U_0603_6.3V6K
P R80 2.2_1206_5%
1
PR225 2 +5VALW 0_0603_5% 4
20
2
1
19 62881_VCCP1
21
1 @ 1
18 LG_GFX
VID2 22
VID3 23
VID4 24
VID5 25
VID6 26
+GFX_COREP P C67
17
330U_D2_2.5VY_R9M
16 LX_GFX
1
11
10
13 IMON
VIN
VDD
9
8 RTN
BOOT
15 UG_GFX
2
@
SI4686DY-T1-E3_SO8
1
GFXVR_PWRGD
62881_VID2
B
@
62881_VID3
@
VID1
62881_VID4
@
VID0
CLK_EN#
62881_VID5
1
P R98 8.06K_0402_1%
1 PR238 10K_0402_1%
@
2
2
@
1
PR100 17.8K_0402_1%
2
1GF 2 X_FB-2
2 PC73 150P_0402_50V8J
PC170 22P_0402_50V8J 1 2
VCCP
PGOOD
@
@
LGATE
RBIAS
+GFX_COREP
1 PR97 1.91K_0402_1%
@
VW
62881_VID6
1 P C71 100P_0402_50V8J
VSSP
VR_ON
@
2
@
2
162881_RBIAS 3
2
COMP
DPRSLPVR
PR230 PC171 47K_0402_1% 1000P_0402_50V7K 2 1
UGATE
27
P R99 825K_0402_1% 1 2GF 1 X_FB-1 2
@
P U5 ISL62881HRZ-T_QFN28_4X4 PHASE
62881_VR_ON
PR226 10K_0402_1% 2@ 1
4
PQ47
2
PC162 0.22U_0603_16V7K 4 @
2
62881_VW
VSEN FB
2BST_GFX1 1
2
62881_COMP 5
@ P R92 2.2_0603_5%
5
6
C
BST_GFX 1
@
3 2 1
7 62881_FB
ISUM+
@ @
ISUM
PC72 330P_0402_50V7K
@
62881_DPR SLPVR 28
2
29
@
PC167 330P_0402_50V7K
AGND
1
PR102 +GFX_COREP 10_0402_5% 1 2
2
<8> VCC_AXG_SENSE
1
1 2 PC166 1000P_0402_50V7K
<8> VSS_AXG_SENSE @
12 62881_VIN
@ ISUM-
C
1
@
2
PQ19 TPCA8028_PSO8
@
2
2
2
PC165 1U_0603_10V6K
@
@
GFXVR_IMON <8>
1
5 6 7 8
@
2 1 P R91 22.6K_0402_1%
@ @
PR101 10_0402_5% 1 2
PC163 0.22U_0402_6.3V6K
2 1_0603_5%
62881_VDD
1
1 1
PR96
PC164 0.22U_0603_25V7K
P R95 0_0603_5% +5VALW 2
1
1 2
PC161 0.1U_0402_25V6
1 2
1 2
1 2
P C59 10U_1206_25V6M
GFX_B+
1
1
P C61 10U_1206_25V6M
2
@ JUMP_43X118
PC160 2200P_0402_50V7K
PJ5 2
GFXVR_DPRSLPVR <8> ISUM-
@
PJ18 +GFX_COREP
2
2
1
1
+GFX_CORE
@ JUMP_43X118 P J6
A
2
2
A
1
1
@ JUMP_43X118
(15A,600mils ,Via NO.= 30)
Compal Secret Data
Security Classification Issued Date
2009/01/06
Deciphered Date
2010/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
GFX_CORE Size Date:
5
4
3
2
Compal Electronics, Inc. Document Number
R ev 0 .1
Thursday, October 29, 2009 1
Sheet
47
of
51
8
7
6
5
4
3
2
1
H
H
1
2
+3VS
<15>
VGATE
<12>
CLK_EN#
1 PR199 1 PR200 1 PR209
G
<34>
VR _ON
2
PR76 1K_0402_5% 1
P R77 1.91K_0402_1%
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
G
CPU_B+
2 10U_0603_6.3V6M
21
PC148 100U_25V_M
PC168 100U_25V_M
PC31 10U_1206_25V6M 2 1
1
PC30 10U_1206_25V6M 2 1
2
PC29 10U_1206_25V6M
P C47 2200P_0402_50V7K 2 1
PC48 0.1U_0402_25V6 2 1
5
PR182 17.8K_0402_1% 2 1
1C PU_SNB2 2
C PU_CSP2
2
C P U_CSN2
3 2 1
D
UGATE_C PU1 4 PQ15
TPCA8030-H_SOP-ADV8-5 @
TPCA8030-H_SOP-ADV8-5
PL11 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4
4
1C PU_SNB1 2
@ 4
CPU_CSP1-1 2 PR185 4.7_1206_5%
PQ45
PR186 17.8K_0402_1% 2 1
5
1
3 2 1
PQ16
PQ44
C PU_CSP1
1
3
P R64 69.8K_0402_1% 2 PH 3 100K_0402_1%_TSM0B104F4251RZ 2 CPU_SN-1 1 2
1 PR188 28.7K_0402_1% 1 2 PC159 0.033U_0402_16V7K
C
<8>
<8>
2
3 2 1
PC143 680P_0402_50V7K TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5
<8>
PC34 10U_1206_25V6M 2 1
BOOT_CPU1 2 1 BOOT_CPU1-1 1 2 PR187 2.2_0603_5% PC144 UGATE_C PU1 0.22U_0603_10V7K 1 2 +5VS P D6 1SS355_SOD323-2
C P U_CSN1
PHASE_CPU1
22
PC32 10U_1206_25V6M 2 1
23
4
<8>
<8> H _VID0
<8> H _VID1
<8> H _VID2
H _VID4 <8> <8> H _VID3
<8> H _VID5
PSI#
H _VID6
5
CPU_B+
LGATE_CPU1
<5,34> 1 PR215 P ROC_DPRSLPVR 1 PR214 PSI# 1 PR213 H _VID6 1 PR208 H _VID5 1 PR207 H _VID4 1 PR206 H _VID3 1 PR205 H _VID2 1 PR196 H _VID1 1 PR195 H _VID0 1 PR194 P ROC_DPRSLPVR
3 2 1
3 2 1
+5VS
E
+ VCCP
<8>
IMVP_IMON
3 2 1
1
24
VID0
VID1
1 P C53
PR222 69.8K_0402_1% 2 PH 2 100K_0402_1%_TSM0B104F4251RZ 2 CPU_SN-2 1 2
25
20
19
VID3
VID2 18
17
VID4 16
VID5 15
VID6 14
PSI#
DRVH1
13
12
11
IMON
VR_TT#
DPRSLPVR
LL1 VBST1
26
+ CPU_CORE
3
1 PR183 28.7K_0402_1% 1 2 P C56 0.033U_0402_16V7K
PC33 10U_1206_25V6M 2 1
DRVL1
VSNS
LGATE_CPU2
5
GNDSNS
27
PC142 680P_0402_50V7K TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5
2 BOOT_CPU2-1 1 2 2.2_0603_5% PC145 0.22U_0603_10V7K
P C45 2200P_0402_50V7K 2 1
V5IN PGND
28
PHASE_CPU2
1
3 2 1
CSN1
BOOT_CPU2 1 PR189
CPU_CSP2-1 2 PR184 4.7_1206_5%
PC46 0.1U_0402_25V6 2 1
DRVL2
UGATE_C PU2
29
+ 2
F
5
CSN2
30
3 2 1
LL2
P U12 TPS51621RHAR_QFN40_6X6
@ 4
5
CSP2
THERM
5
2 VBST2
2
1
PL10 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 4
TPCA8030-H_SOP-ADV8-5
PQ42
4
1
DRVH2
GND
CSP1
5
+5VS 2
2 1
2
2 1
CPU_TRI1PSEL
CPU_OSRSEL 1 32
31
33
OSRSEL
TRIPSEL
CPU_CLK_EN#
C PU_PGOOD
34
PGOOD
CLK_EN#
C P U_VR_ON 35 VR_ON
38
2 CPU_TON SEL 1 36
2 C PU_ISLEW 1 37
TONSEL
ISLEW
V5FILT
C P U_DROOP 39 DROOP
C P U_VREF
40
41
PQ43
PD 7 1SS355_SOD323-2
+
PQ17
TPCA8030-H_SOP-ADV8-5
CPU_IMON 2 0_0402_5% 2C PU_DPRSLPVR 0_0402_5% CPU_PSI# 2 0_0402_5% V ID6 2 0_0402_5% V ID5 2 0_0402_5% V ID4 2 0_0402_5% V ID3 2 0_0402_5% V ID2 2 0_0402_5% V ID1 2 0_0402_5% V ID0 2 0_0402_5%
1 PR216 +VCCP
H_PROCHOT#
2 1 P C44 0.22U_0402_6.3V6K
<8> VSSSENSE
2 1 P R45 12.4K_0402_1%
2 1 PR212 0_0402_5%
<8>
V CCSENSE
VREF
GND 2CPU_VR_TT# 0_0402_5%
10 2 68_0402_5%
9
2 20K_0402_1%
8
CPU_TH ERM
1 P R53
PR65 0_0402_5%
PR66 0_0402_5% 2 1
C PU_VSNS
1 PR217
1 2 1 2 1 2 VSSSENSE
B
7
PR198
@
6
PQ18 @
+5VS
1
B+
UGATE_C PU2 4
4
PR197
C
5
@
0_0402_5%
D
4
P R79
2 CPU_CSN2-1 33P_0402_50V8J 2 CPU_CSN1-1 33P_0402_50V8J 2 CPU_CSP1-2 33P_0402_50V8J C PU _GNDSNS
0_0402_5%
C PU_CSP1 2 PR219
PC153 100P_0402_50V8J 1 470_0402_1%
1 PC157 1 PC155 1 PC154 1 PC152
MODE
P R78
C P U_CSN2 2 PR221 C P U_CSN1 2 PR220
PC156 100P_0402_50V8J 1 470_0402_1% 1 470_0402_1%
2 CPU_CSP2-2 3 33P_0402_50V8J
0_0402_5%
1 470_0402_1%
PR210
C PU_CSP2 2 PR223
P R74
2CPU_MODE 1 0_0402_5% 2
1 P R73 E
249K_0402_1%
1 2 P C57 0.22U_0603_10V7K
0_0402_5%
F
@ 0_0402_5%
2 PC150 2.2U_0603_6.3V6K 1 2 P C58 68P_0402_50V8J 2 1 PR218 5.11K_0402_1%
1
+3VS
1
C P U_VREF
2 PR75 @ 1K_0402_5% +5VS
PL1 HCB4532KF-800T90_1812 1 2
H _VID0
2
1P R61 @ 1K_0402_5%
H _VID0
2
1PR191
1K_0402_5%
H _VID1
2
1P R60 @ 1K_0402_5%
H _VID1
2
1PR192
1K_0402_5%
H _VID2
2
1P R59
1K_0402_5%
H _VID2
2
1PR193 @ 1K_0402_5%
H _VID3
2
1P R58
1K_0402_5%
H _VID3
2
1PR201 @ 1K_0402_5%
H _VID4
2
1P R57
1K_0402_5%
H _VID4
2
1PR202 @ 1K_0402_5%
H _VID5
2
1P R56 @ 1K_0402_5%
H _VID5
2
1PR203
1K_0402_5%
H _VID6
2
1P R55 @ 1K_0402_5%
H _VID6
2
1PR204
1K_0402_5%
1P R54
P ROC_DPRSLPVR 2
P ROC_DPRSLPVR 2
10K_0402_5%
B
1PR211 @ 1K_0402_5%
Clarkfield:VID(0-5):001101 Auburndale:VID(0-5):001110 A
A
Compal Secret Data
Security Classification 2009/01/06
Issued Date
Deciphered Date
2010/01/06
Title
CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size Date:
8
7
6
5
4
3
Compal Electronics, Inc.
2
Document Number Thursday, October 29, 2009
R ev 0 .1 Sheet
48 1
of
51
5
4
3
2
Version change list (P.I.R. List) Item D
1
Page 1 of 2 for PWR
Reason for change
PG#
Modify List
Date
Phase
1
D
2 3 4 5 6 C
C
7
8
9 10
B
B
11
12 13 14 15 16 A
20081022
17
2009/01/06
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
2009/01/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
A
2
Title
PIR (PWR) Size Document Number Custom
R ev 0.1
Date:
Thursday, October 29, 2009
Sheet 1
49
of
51
5
4
3
NO DATE PAGE MODIFICATION LIST PURPOSE -------------------------------------------------------------------------------------------------------------
2
1
EVT TO DVT
D
D
C
C
B
B
A
A
Title
Compal Electronics, Inc. HW PIR
Size B Date: 5
4
3
2
Document Number LA-5752P Thursday, October 29, 2009
Rev 0.3 Sheet 1
50
of
51
5
4
3
2
1
D
D
C
C
B
B
A
A
Title
Compal Electronics, Inc. HW PIR
Size B Date: 5
4
3
2
Document Number LA-5751 Thursday, October 29, 2009
Rev 0.3 Sheet 1
51
of
51
