Loop Bandwidth Optimization And Jitter Measurement Techniques For

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/RRSEDQGZLGWKRSWLPL]DWLRQDQGMLWWHUPHDVXUHPHQW WHFKQLTXHVIRUVHULDO+'79V\VWHPV 8VLQJFRPPHUFLDOO\DYDLODEOHJHQHUDOSXUSRVHWHVWXQLWVDQGVRPH FXVWRPEXLOWERDUGV\RXFDQHDVLO\PHDVXUHVRPHRIWKHLPSRUWDQW MLWWHUSDUDPHWHUVDVVRFLDWHGZLWKVHULDO+'79 $WXO.ULVKQD*XSWD$DSRRO%LPDQDQG'LQR7RIIRORQ*HQQXP&RUSRUDWLRQ The HDTV (high-definition TV) data rate is 5.5 times that of SDTV (standarddefinition TV), which allows little design margin for jitter. Certain design guidelines for video sources, routers, digital-signal-processing units with serial interface, distribution amplifiers, and production switchers reinforce the Society of Motion Picture and Television Engineers (SMPTE) 292M standard and other recommended practices, such as EG33-1998. The SMPTE 292M standard regulates HDTV (Reference 1). Several electrical characteristics of SMPTE 292M are similar to those of SMPTE 259M (Reference 2). The randomizing polynomial and channel coding pose the same pathological signal challenges (Reference 3). Table 1 compares jitter specifications for the SMPTE 259M and 292M standards. Figure 1 graphically illustrates the SMPTE-292M jitter specification. Table 1—Jitter specifications for the SMPTE 259M and 292M standards Jitter parameter B1 (f1) (Timing-jitter lower band edge) B2 (f3) (Alignmentjitter lower band edge) B3 (f4) (Upper band edge) A1 (Timing jitter) A2 (Alignment jitter) Test signal Clock divider ratio (n) 1page of 20 SMPTE 259M-1993 10 Hz SMPTE 292M-1996 10 Hz 1 kHz 100 kHz >27 MHz >148.5 MHz 1.0 UI 0.2 UI Color-bar test signal Except 10 1.0 UI 0.2 UI Color-bar test signal Except 10 (preferred) Timing Jitter 1.0UI A1 -20dB/decade slope Sinusoidal Input Jitter Amplitude Alignment Jitter 0.2UI A2 10Hz B1 (f1) 20kHz (f2) 100kHz B2 (f3) 148.5MHz B3 (f4) Jitter Frequency for HDTV Figure 1—A jitter template graphically illustrates the SMPTE 292Mjitter specification. According to Table 1, the source should not have jitter more than 1 UI (673 psec) in the frequency band above 10 Hz. The alignment jitter should not be more than 0.2 UI (135 psec) in the frequency band beyond 100 kHz. The alignment-jitter lower frequency changes from 1 to 100 kHz from SMPTE 259M to SMPTE 292M. Even though the alignment jitter is defined from 100 kHz to greater than 1/10th the serial clock frequency, it is important to make sure that the jitter is not more than 0.2 UI to one-half the serial clock frequency. The SDI (Serial Digital Interface) signal may have jitter in that band that could cause errors when it is sampled at the receiver or the retimer. A fair amount of jitter could be present in the frequency band around one-half the serial clock frequency, because any data duty-cycle distortion appears as jitter at half the serial clock frequency. The need for video field-and-line synchronization and unique channel coding make the SMPTE standard different from other digital-communication protocols, such as SONET and Fiber channel. 7KHVWXGLRPRGHO Figure 2 illustrates a simplified studio model. Distribution amplifiers, DSPs, and routers can be used several times in one signal stream. You must synchronize all the sources to the master clock or the "house synch." You use the house synch to synchronize lines and frames so that switching does not create partially blank screens during multiplexing of various sources. Because both front end (sources) and back end (production switcher) are synchronized with the same master clock, it is important to control jitter and provide sufficient input-jitter tolerance in individual blocks to prevent errors. 2page of 20 House synch for Genlock Camera Distribution Amplifier (DA) VTR N inputs X M outputs Router Other sources SDI Sources Digital Signal Processing Unit Monitor Production Switcher Transmitter Figure 2--In this simplified model of a TV Studio, distribution amplifiers, DSPs, and routers can be used several times in one signal stream. 6RXUFHVRIMLWWHUDQGWKHLUIUHTXHQF\VSHFWUXP Bandwidth-limited devices in the signal chain, such as cable drivers, cable equalizers, and crosspoints all add jitter. Assume that there is an NRZI (Non-Return-to-Zero Inverted) signal passing through a bandwidth-limited device. Figure 3 shows the generation of phase error by bandwidth-limited circuits in the time domain. 3page of 20 R=75, C=4pF Bandwidth limited channel Input Output (A) Input Zero crossing Input Output Output Shifted output to determine phase error (C) Phase =0 UI Phase =0 UI Phase =0 UI Phase =-0.5 UI Phase =0 UI (B) 0.1UI Output 0.0UI Phase -0.1UI time Pseudo R andom Pathological (27 us) (D) Pseudo Random Jitter Histogram Figure 3—A bandwidth-limited circuit (a), the waveform of the I/O of a bandwidth-limited system (b), the eye diagram of the waveform in (b), and the phase plot with respect to time (d), illustrate time-domain jitter introduction in a bandwidth-limited system. This effect introduces systematic jitter, which accumulates as arithmetic addition in a cascaded system. In some cases, it can also subtract. However, to build a robust system, you must consider that jitter adds in every pass. This type of timing problem is also known as intersymbol interference. Most types of equipment used in the studio are based on PLLs because they are either synchronized to the house synch or to the received serial digital data. Depending on the loop bandwidth of the PLL, low-frequency jitter will be passed, and high-frequency jitter will be filtered. Figure 4 shows a typical second-order traditional PLL (Reference 4). White noise in the VCO (voltage-controlled oscillator) is assumed. Figure 4c shows the typical open-loop VCO and PLL-VCO phase noise, which shows that the noise is also present within the loop bandwidth. The pathological pattern, which is unique to SMPTE signals, may last as long as the active video line. Similar to bandwidth-limited circuits, the PLL could also have time-domain jitter, as shown Figure 3d. This situation is especially true for data-recovery circuits, which extract clock from data and are inevitably pattern-dependent. The noise in PLLs inside serializers is not directly related to the data pattern, because the PLL locks on to a clock that has no pattern. However, board noise is often related to the data pattern and, thus, could introduce jitter that has similar time-domain characteristics (Figure 3). Delay in most microchips is a function of temperature. When the temperature changes over time, the output phase changes. However, the temperature change in microchips is slow, and the drift in the output phase happens slowly. This kind of jitter will fall into the “wander-jitter” category, and it poses no problems. While evaluating any unit for jitter, it is recommended that the unit be temperature-stabilized to isolate timing jitter and alignment jitter from wander jitter. 4page of 20 White Noise Input Phase Phase Detector Charge pump Loop Filter Output Phase VCO (A) Open loop VCO noise spectrum (1/f2 noise) Loop bandwidth pole Loop Bandwidth Zero 0db -20dB/decade Slope Gain Loop Bandwidth Pole Noise PLL VCO noise spectrum Frequency (B) Frequency (C) Figure 4—A block diagram shows a typical linear PLL (a). For a linear PLL, the jitter-transfer function is a lowpass response (b). For the same PLL, the noise-spectrum density is a bandpass response (c). 7LPLQJDQGLQWULQVLFMLWWHUPHDVXUHPHQW The clock-extractor method is generally used to measure jitter. You measure the timing jitter with a 10-Hz, low-bandwidth clock extractor, and you measure alignment jitter with 100-kHz, low-bandwidth clock extractor. It is difficult to attain a clock-extraction loop bandwidth of 10 Hz without adding the intrinsic jitter of the clock extractor. As an alternative, try measuring the intrinsic jitter of the individual units as shown in Figure 5. This method is based on the assumption that the timing jitter of a device can be approximated to the intrinsic jitter of the device. The intrinsic jitter is the amount of jitter present in the entire jitter-frequency spectrum with respect to a clean reference input. The timing jitter excludes jitter content in the frequency band from dc to 10 Hz. Thus, intrinsic jitter overestimates timing jitter. However, in the case of a PLL (Figure 4), the presence of a zero reduces the content of the jitter in the lower frequency band. In most cases, the zero occurs beyond 10 Hz. As long as this assumption is true, timing jitter is very close to the intrinsic jitter. Figure 6 illustrates intrinsic jitter, timing jitter, and alignment jitter. 5page of 20 Index Single ended signals Jitter Reconditioning Unit Any HDTV source Differential signal Parallel data Receiver LBW=4.2MHz Parallel Clock PLL LBW < BW of DUT Serializer LBW=1.41MHz Clock Multiplier CSA803 Scope Device Under Test (DUT) With Known LBW Ch 1 Direct Trigger Figure 5—An alternative to the clock-extractor method of jitter measurement is shown, which approximates the timing jitter of a device as being equivalent to the intrinsic jitter of the device. Intrinsic Jitter Timing Jitter Alignment Jitter Noise Power 1 / Persistence Time 10Hz 100kHz 1/2 Data Rate Frequency Figure 6—This plot shows the relationship between the intrinsic-, timing-, and alignment-jitter spectrum. It is important to verify that the loop bandwidth of the jitter-reconditioning unit is 6page of 20 much lower than the loop bandwidth of the device under test. If the loop bandwidth of the jitter-reconditioning unit is greater than the device under test, and if there is fair amount of jitter present in that frequency band, the trigger will have more jitter than the device under test. In this case, the intrinsic-jitter measurement will be greater than the actual jitter of the device under test. Figure 7 illustrates a case in which a cleaner PLL with narrow loop bandwidth is measured with a source having jitter beyond the loop bandwidth of the device under test. Noise Power Spectrum Source Jitter Spectrum f Noise Power Spectrum Jitter Reconditioning Board Jitter Spectrum f Noise Power Spectrum Device Under Test Jitter Spectrum f Noise Power Spectrum Measured Intrinsic Jitter Not Due to DUT f Figure 7—If the loop bandwidth of the jitter-reconditioning unit is greater than the device under test, and there is fair amount of jitter present in that frequency band, the trigger will have more jitter than the device under test. The jitter-reconditioning unit must be checked for its own intrinsic jitter before it can be used to precisely characterize other units. For this article, a pristine bit-error-rate tester was used to test the jitter-reconditioning unit. The intrinsic jitter was verified using a special signal pattern programmed in the bit-error-rate tester, which accurately models the SMPTE pathological signal. A jitter-reconditioning unit was realized with a loop bandwidth of approximately 1.0 kHz at 0.2-UI input-jitter modulation. The PLL used, with a VCXO, behaved partially as a slew PLL when used with a specific loop filter to achieve low loop bandwidth. The intrin23 sic jitter of the unit measured was approximately 60 psec p-p for a 2 21 pseudorandom pattern and 70 psec p-p for a pseudopathological pattern. $OLJQPHQWMLWWHU The high-frequency (more-than-100-kHz) component of the timing jitter is classified as alignment jitter. The limits for the alignment jitter are tighter than those for timing jitter. As a result, you may have to isolate the alignment jitter if timing jitter is more than the SMPTE alignment-jitter limit, to make sure that the unit is tested according to SMPTE specifications. You can test the alignment jitter using a calibrated 100-kHz linear clock 7page of 20 extractor. To measure the alignment jitter in accordance with the SMPTE guidelines, you can devise a unit using a wide low-bandwidth clock-recovery circuit. A secondary PLL locked to the clock-recovery circuit’s extracted clock sets the 100-kHz loop bandwidth, as shown in Figure 8. In most cases, the intrinsic-jitter measurement alone is sufficient. A pristine data source measured alignment jitter of approximately 30 psec for a pseudorandom pattern and 50 psec for a pseudopathological pattern. This value could be considered as the intrinsic jitter of this test setup. It is not obvious whether you should use rms or arithmetic subtraction to find the true alignment jitter of the device under test. You should mention the intrinsic jitter of the test instrument when you describe the jitter of any device. CSA803 Scope Ch 1 Device Under Test Direct Trigger Bypass Output Differential Input 100kHz Clock Extractor Board Clock Recovery Circuit LBW=1.41MHz VCO output Div 2 Div 2 Phase frequency Detector Charge Pump Buffer Extracted Clock VCO Loop filter LBW= 100kHz Figure 8—You can measure alignment jitter using a clock extractor. 6OHZ3// Most PLLs in electronic circuits are linear. A slew PLL is a nonlinear PLL in which the change in the output phase variation is limited. A slew PLL offers significant advantages over linear PLLs for SMPTE SDI signals. You design PLLs with two main objectives: jitter attenuation and VCO/board noise immunity. You achieve jitter attenuation by lowering the loop bandwidth, whereas you achieve noise tolerance by increasing the loop bandwidth. Slew PLLs conveniently meet these two contradicting requirements. Figure 9 compares linear and slew PLLs. For a fair comparison, the phase slew of the slew PLL and the loop bandwidth of the linear PLL are chosen such that at 0.2-UI input-jitter modulation, both achieve 3-dB attenuation at 1.4-MHz modulation frequency (Reference 1). The jitter-transfer function is plotted at 2.8 MHz to show how the PLL attenuates input jitter at higher frequency. It can be seen that the output jitter of the slew PLL attains a maximum and then it is limited. This is an attribute of the nonlinearity present in the slew PLL. 8page of 20 A linear PLL is unaffected by the input-jitter-modulation index. You can calculate the slope of the jitter-transfer line by the jitter-transfer function of a first-order lowpass filter. By contrast, in a slew-PLL transfer function at 2.8 MHz, the 3-dB attenuation occurs at 0.1-UI input-jitter modulation. In other words, if you lower the input-jitter modulation, the 3-dB loop bandwidth increases. For an infinitesimal input signal, the slew PLLs have infinitely large loop bandwidth, whereas the loop bandwidth of linear PLLs is fixed. In a careful design, you can consider the intrinsic VCO noise and board interference as a small signal noise. Higher loop bandwidth cancels more VCO noise, but PLLs with wider loop bandwidth tend to be more robust. Therefore, slew PLLs are more robust than their linear counterparts. Because of the nonlinear characteristics, slew PLLs achieve higher jitter attenuation in the presence of large input jitter while providing small signal VCO/board noise immunity. For this discussion, the bandwidth of a slew PLL, unless otherwise noted, is defined at 0.2-UI (135-psec) input-jitter modulation. 0.5 0.4 Linear PLL Input Jitter Modulation At 1.4MHz Slew PLL 0.3 Output Jitter (UI) 0.2 At 2.8MHz 0.1 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Input Jitter (UI) Figure 9—This figure shows the differences in the jitter transfer function of a linear PLL and a slew PLL. /RZEDQGZLGWKRSWLPL]DWLRQIRUXQLWVLQWKHVWXGLR As previously mentioned, you can cascade several units in a studio. In such a signal chain, jitter will accumulate from unit to unit. For error-free operation, the loop bandwidth of the receiver of the subsequent units should be wider to track the accumulated jitter. Table 2 recommends bandwidth ranges for different units. This scheme guarantees trouble-free interfacing between units. 9page of 20 Table 2—Recommended bandwidth ranges for units in studios Type of unit Transmitter (serializer) Retimer Receiver (deserializer) Bandwidth range 1 Hz to 100 kHz 500 kHz to 2 MHz 3 to 6 MHz 9LGHRVRXUFHV In a studio, you define a source as a unit that generates serial digital data, such as a camera and a VTR. For synchronous use, the source must be genlocked to the house synch. Generally, you use a very stable controlled crystal with very little intrinsic jitter for this purpose. Figure 10 shows a simple diagram of a source. The house synch reference could have jitter. The specification on the synchronization pulse is mentioned in RP 154. The genlock using a VCXO may be used with very low loop bandwidth (less than 10 Hz), such that the recovered parallel clock (p-clock) meets the SMPTE 292M jitter specification, in which jitter is measured in time; A1=673 psec; and A2=135 psec (Table 1). Ideally, the jitter on the genlock-generated parallel clock should be much better than the SMPTE specifications to accommodate jitter accumulation in the serializer and subsequent cascaded units. The design of the genlock circuit is beyond the scope of this article. Because the parallel clock is derived from a clean VCXO, there is no need to further filter the jitter using the PLL in the serializer. In this case, you can use the optimum bandwidth recommended by the manufacturer. 2 UI 0.05 UI Serializer & Cable Driver LBW=(129Kz1.4MHz) Data Source Parallel clock clean reference signal VCXO Genlock PLL House Synch Figure 10—A block diagram shows a possible HDTV source. -LWWHUFKDUDFWHUL]DWLRQRIYLGHRVRXUFHV You can measure the intrinsic jitter of the serializer output using the Tektronix CSA 803 scope, triggered by the genlocked parallel clock. The output of the serializer could have a parallel clock-jitter component, which may be unseen in this case, as it is synchronous to the parallel clock. To accurately measure the jitter, you should multiply the parallel clock to the HDTV rate and use this clock to trigger the serial data stream. However, the multiplied clock may add some jitter. The jitter-reconditioning unit mimics a video source (Figure 5). It also has an onboard clock multiplier. Table 3 summarizes the achievable jitter measurements of these units. 10page of 20 Table 3—Achievable jitter measurements of the jitter-reconditioning units Video Pattern SMPTE specification Color bars Pathological Intrinsic jitter of the serializer at 129-kHz loop bandwidth (psec) 673 (timing) 135 (alignment) 30 to 60 40 to 60 Because the intrinsic jitter is less than the SMPTE alignment-jitter specification, there is no need to isolate alignment jitter. 5RXWHUV Figure 11 shows a simplified router. You can model the cable driver, the cable equalizer, and the crosspoint as a bandwidth-limited channel. Figure 11 shows the jitter addition and jitter filtering inside a router. It is assumed that the equalizer jitter is 0.2-UI p-p at the input of the retimer, and the source is clean. During the pseudorandom section of the data pattern, the jitter is attenuated. During the pathological section, the retimer follows the input jitter. The loop bandwidth decides how quickly the VCO will follow the input jitter. If you set the loop bandwidth low, you can reduce the jitter of the router, however, it takes significant time to settle during synchronous switching. In synchronous switching, the worst-case phase offset could be 0.5 UI. If it takes several lines to recover the 0.5-UI step, then during this time, the phase offset will look like input jitter. If the phase offset is more than the input-jitter tolerance, errors will result. The best compromise is to set the loop bandwidth between 500 kHz and 2 MHz. 11page of 20 Equalizer Re-timer & Cable Driver Equalizer Re-timer & Cable Driver Cross Point Equalizer Re-timer & Cable Driver Figure 11—In a simplified router, you can model the cable driver, the cable equalizer, and the crosspoint as a bandwidth-limited channel. 0.05UI Input phase of the Re-timer Output phase of the Re-timer Pseudo random pattern output peak-peak jitter Output 0.0UI Phase Pathological pattern output peak-peak jitter -0.05UI time Pseudo Random Pathological (27 us) Pseudo Random Figure 12—A graph illustrates jitter filtering within a router. Due to the synchronous-lock-time specification, you should not use a very narrow loop bandwidth. Conversely, if you use a very high loop bandwidth, some of the highfrequency jitter will be passed onto next unit in the chain, causing jitter accumulation. 12page of 20 The jitter peaking in retimers is usually less than 0.1 dB, which adds approximately 1% jitter. Thus, in most cases, you can ignore the effects of jitter peaking. -LWWHUFKDUDFWHUL]DWLRQRIURXWHUV You can use an application circuit board containing an equalizer and a retimer (loop bandwidth of 1.4 MHz) to model the router. The intrinsic jitter of the router can be characterized according to the Figure 5. Table 4 summarizes the achievable intrinsic jitter for 0 and 100m of Belden 8281 cable between the jitter-reconditioning unit and the device under test. Table 4— Achievable intrinsic jitter for Belden cable between the jitterreconditioning unit and the device under test Video Pattern SMPTE specification Color Bars Pathological 0m Belden 8281 Cable (psec) 673 (timing) 135 (alignment) 30 to 60 40 to 70 100m Belden 8281 Cable (psec) 673 (timing) 135 (alignment) 30 to 80 40 to 100 You can assume that the jitter that the crosspoint adds is bandwidth-limited and systematic, and you should not add it to the intrinsic jitter for worst-case analysis. 6(5'(6XQLWV SERDES (serializer/deserializer) units receive serial digital signals and convert them it into 20-bit words. They also generate a parallel clock, which is 1/20th the serial clock rate. Digital signal processing is then done on the parallel, 20-bit data, after which a serializer converts the 20-bit words into the serial digital stream. The interface between the serializer and the deserializer is a 20-bit parallel bus. Because of this interface, there is a built-in data buffer, which increases the jitter tolerance (specified as setup-and-hold time) between these two microchips. Ideally this could be accommodated with 61 bits of data buffering. However, because of slower rise and fall times and setup-and-hold times, 65 bits of data buffer is usually achieved. You should choose the loop bandwidth of the deserializer to be 3 to 6 MHz and the loop bandwidth of the serializer to be less than 100 kHz. This combination allows the input-jittertolerance template to overlap with the jitter-transfer function. If the receiver’s loop bandwidth is 4.2 MHz, and the router’s loop bandwidth is 1.4 MHz, the receiver will follow the jitter of the router during the pathological video line. Both, the receiver and retimer could be based on the slew PLL. The phase at the retimer at 1.4 MHz slews slowly so that a 4.2-MHz receiver could closely track it even for the worst-case manufacturing-lowbandwidth tolerances. By judiciously choosing the loop bandwidth, a robust system design is achievable. The parallel clock interface is single-ended, and the presence of single-ended 20-bit parallel data could add fair amount of systematic jitter (approximately 0.7 UI) during pathological signal. Noise resulting from parallel DSP microchips is another source of systematic jitter introduction. You can differentiate SERDES units as being one of two types. The first type filters the jitter in the parallel clock using a VCXO/PLL; the second type of unit circuit does not filter the parallel clock that feeds the serializer. 13page of 20 9&;2EDVHG6(5'(6XQLWV The VCXO-based PLL is the most commonly used approach for SERDES units. Figure 13 shows the block diagram. 0.3 UI 0.2 UI De-serializer (LBW =3MHz6MHz) Equalizer 1.0 UI 0.073 UI 3.0 UI Serializer & Cable Driver (LBW = 129kHz1.4MHz) DSP Core 0.023 UI 1.0 UI 0.023 UI VCXO Slew PLL 1kHz-3kHz Loop BW Figure 13—A VXCO-based PLL is the most commonly used approach for SERDES units. Assuming that the alignment jitter of the source is 0.2 UI and that the equalizer adds 0.1 UI of jitter, the jitter seen by the deserializer is 0.3 UI. The typical input-jitter tolerance of the deserializer is about 0.5 UI. The wider loop bandwidth follows input jitter as closely as possible. You should properly consider the delay between the clock and the output data of the DSP core. The PLL with a VCXO is used to clean the jitter present in the parallel clock from the receiver. The data input to the serializer is from a DSP microchip or an FPGA, whereas the clock sampling the parallel data is from the clean VCXO output. The alignment and jitter of the parallel data may stress the input-jitter tolerance (setup-and-hold time) of the serializer. Designers should watch for two potential pitfalls in today’s off-the-shelf PLL microchips designed to work with the VCXO. Some PLL microchips could have a dead zone, which may result in abnormally high jitter when the input phase aligns in the dead zone of phase detector. This occurrence happens because there is no corrective feedback for the VCO phase when the phase alignment is in the dead zone of the phase detector. To avoid a dead zone, you should use a shunt resistor to ground or the power supply at the phase-frequency-detector output. This shunt resistor may cause a phase offset. When choosing between a shunting resistor to ground or a power supply, choose the method that provides the best setup-and-hold time for the serializer. PLLs that do not have a charge pump could have input phase offset due to a different locking position for the VCXO. By choosing the proper loop bandwidth or phase slew, you can choose a phase drift during one video line of as little as 15 to 20 psec. Due to the clean reference available, the PLL within the serializer need not filter any jitter; thus you can use a wider loop 14page of 20 bandwidth, which is more tolerant to board noise. However, phase-detector noise passes through the wider loop bandwidth. Therefore, excessively increasing the loop bandwidth may also increase the output jitter. You should therefore keep loop bandwidth within 129 kHz to 1.4 MHz. -LWWHUFKDUDFWHUL]DWLRQRI9&;2EDVHG6(5'(6XQLWV You can test a VCXO-based SERDES unit for intrinsic jitter using a jitterreconditioning unit (Figure 5). In this case, you should set the loop bandwidth of the jitter-reconditioning unit lower than the VCXO-based SERDES unit under test. Table 5 summarizes the achievable jitter. Table 5—Typically achievable jitter for VXCO-based SERDES units. Video pattern SMPTE specification Color bars Pathological pat- Intrinsic jitter (psec) 673 (timing), 135 (alignment) 30 to 100 30 to 100 tern Because the total jitter is less than the alignment jitter, there is no need to isolate timing jitter and the alignment jitter. 6(5'(6XQLWVZLWKRXWD9&;2 In certain situations, it is desirable to have a low-cost option by just using a serializer and a deserializer without filtering the parallel clock. Figure 14 shows a block diagram of such a SERDES unit. The source is assumed to have 0.2-UI jitter, and the jitter added by the equalizer is assumed to be 0.1 UI. The jitter is additive, assuming systematic jitter. The jitter that is added at the parallel clock generation from the deserializer is assumed to be 0.7 UI. The jitter that is added by the DSP core is assumed to be 2 UI. Therefore, the total phase step (jitter) could be as high as 3.0 UI into the serializer. With a narrow loop bandwidth, the serializer can be designed with a phase slew, which results in 0.4-UI phase drift during the pathological line. Depending on the pattern dependency, the peak-to-peak systematic jitter would be 230.450.8 UI. Adding 0.05 UI random jitter, the total output jitter would be 0.85 UI, which is less than the SMPTE 1UI timing-jitter specification. Most of the jitter component is around 37 kHz (pathological line), thereby making it low-frequency jitter. The timing jitter extracted using a 10-Hz clock extractor will be close to the intrinsic jitter. Thus, the timing jitter can be considered as intrinsic jitter, and there is no need to use the clock-extraction method to measure it. Because the timing jitter is greater than the alignment-jitter specification, you must measure the alignment jitter. As previously mentioned, you should use a clock extractor with a 100-kHz low-bandwidth setting. This architecture meets the SMPTE requirement, however, it may require careful board layout because of the low loop bandwidth involved. Also, it does not provide superior jitter performance. Consider how jitter accumulates in the time domain when similar SERDES units are cascaded (Figure 14). The longest run of pattern dependency in an SMPTE SDI signal is about 27 µsec (equal to one active video line). Because the PLL slew determines the phase drift in every unit, you can set the slew such that the maximum phase drift is limited to 0.85 UI. As a first order of approximation, the overall phase will not drift more than 0.85 UI even when similar units are cascaded. 15page of 20 De-serializer Serializer LBW=50kHz DSP Core 1.0 UI 3.0 UI 0.3 UI 0.85 UI Equalizer 0.2 UI 0.85 UI De-serializer DSP Core 1.65 UI Serializer LBW=50kHz 3.65 UI 0.95 UI Equalizer 0.85 UI Clock Extractor 100KHz loop BW 0.85 UI 0.85 UI Figure 14—A typical SERDES allows jitter filtering without VCXO filtering of the parallel clock. Table 6 summarizes the expected jitter of SERDES units without a VCXO. Table 6—Expected jitter of SERDES units with a VXCO Video pattern SMPTE specification Color bars Pathological pattern Intrinsic (timing) jitter (psec) 673 50 to 300 400 to 600 Alignment jitter (psec) 135 40 to 80 50 to 110 'LVWULEXWLRQDPSOLILHUV Two types of distribution amplifiers can be realized depending on the performance necessary and the cost target: retimer-based units and SERDES-based units. Figure 15 shows a block diagram of a retimer-based distribution amplifier. 16page of 20 Equalizer Re-timer Cable Driver Cable Driver Cable Driver Cable Driver Figure 15—A block diagram depicts a retimer-based distribution amplifier. The retimer-based distribution amplifier is the simplest type. Because the retimer has no data buffer, the typical input-jitter tolerance is 0.5 UI p-p beyond the loop bandwidth. This architecture is very similar to that of the router; jitter filtering happens in the same way as shown in Figure 11. In a system, you can use a distribution amplifier directly after the source or cascade it in front of another similar distribution amplifier or a router. Figure 16 shows how jitter accumulates in a multiple-pass situation. Consider jitter from a router as a first pass (Figure 11). The output phase of the router’s retimer is the input of the distribution amplifier through a bandwidth-limited channel (shown with the thick line in Figure 16). The jitter during a pseudorandom pattern does not add arithmetically, however during pathological line, the jitter from one pass to the next adds arithmetically. This is because the response time, which is related to the loop bandwidth of the retimer, is less than the pathological line duration. If all the distribution amplifiers and routers in a chain have exactly the same loop bandwidth, then the next retimer will follow the accumulative jitter. However, in manufacturing it is impossible to manufacture PLLs with exactly the same loop bandwidth. The bandwidth of similar retimer microchips may vary over process (approximately 645%), and from manufacturer to manufacturer it may vary even more (by as much as 500%). The worst case results when retimers earlier in the chain have a wider loop bandwidth, causing accumulation of jitter in that frequency band, and the last retimer with a nominal loop bandwidth or lower loop bandwidth does not track the accumulated jitter. When the accumulated jitter exceeds the input-jitter tolerance of the last retimer, errors will be generated. The jitter peaking, which is typically less than 0.1db or 1%, is not a major reason for jitter build-up in SMPTE signals, because the pathological-line-induced jitter dominates. 17page of 20 Output Phase Output phase of the first Re-timer + Jitter of Bandwidth limited channel before second Re-timer 0.05UI Output phase of the second Re-timer Pseudo random pattern output peak-peak jitter 0.0UI Pathological pattern output peak-peak jitter of second DA -0.05UI -0.10UI time Pseudo Random Pathological (27 us) Pseudo Random Figure 16—A graph illustrates jitter accumulation in a multiple-pass system in terms of output phase versus time. 6(5'(6EDVHG GLJLWDODPSOLILHUV To ensure a large number of passes, the jitter may be filtered in the parallel domain to use the data buffer provided by the deserializer and serializer interface. This type of distribution amplifier is very similar to the SERDES units, and a similar design criterion could be used. Again, a VCXO-based or a non-VCXO-based distribution amplifier could be realized. 3URGXFWLRQVZLWFKHU 18page of 20 Input Channel 1 House Synch Input Channel 2 Equalizer De-serializer LBW 4.2MHz Genlock P-clock Vertical Synch and Horizontal Synch Recovery Block Equalizer P-clock V-Synch H-Synch De-serializer LBW 4.2MHz +/-1 Video Line FIFO Digital Multiplexor and FIFO Controller Digital Signal Processor Block Serializer LBW (129kHz 1.4MHz) +/-1 Video Line FIFO Figure 17—A production switcher uses a combination of deserializer/serializer units and a source. Figure 17 illustrates a production-switcher representation. The output jitter is a function of the genlocked parallel clock and the serializer jitter, irrespective of the input jitter. Because the internal parallel clock is not derived from the input data, it may momentarily drift from the input-data alignment. If there is an insufficient amount of data buffer, it could cause bit errors. Generally SERDES units have latency on the order of one video line, thus a production switcher uses one line’s worth of FIFO. This FIFO also takes care of the momentarily drift of the internal parallel clock. The jitter of the production switcher should be characterized just like a video source, because the output is referenced to the house synch. 0LVFHOODQHRXVWLSVRQ3//EDVHGV\VWHPGHVLJQ You may encounter several configurations of video equipment in the studio. One element common to most of the configurations is a PLL. The following design tips are useful in such systems. Wider low-bandwidth PLLs are more immune to the board noise. They are the best choice when jitter filtering is not required, as in the case of a serializer when a clean parallel clock is available. However, phase-detector noise may increase the total output jitter at a high loop bandwidth. Therefore, the loop bandwidth should be optimized for the minimum output jitter. You should use a regulated or filtered power supply when designing low-loopbandwidth circuits. Even VCXO-based PLLs may require clean power supplies when you are designing a bandwidth around 1 kHz at 0.2-UI phase modulation. A loop-through output derived from a deserializer may have jitter content of as much as 6 MHz because of the higher loop bandwidth. If total jitter content increases more than the 0.4-UI limit of a retimer, it could cause errors. Thus, you should not use loop19page of 20 through outputs for cascading units. If you must, this signal should be retimed with a lower loop bandwidth to provide a clean output. References 1. ANSI/SMPTE 292M-1996, "Bit-Serial Digital Interface for High-Definition Television Systems." 2. ANSI/SMPTE 292M-1993, "10-Bit 4:2:2 Component and 4fsc Composite Digital Signals—Serial Digital Interface." 3. Waschura, JR, “Testing in Uncompressed HDTV Signals,” 140th Annual SMPTE Technical Conference and Exhibit, Oct 28 to 31, 1998, pg 528 to 551. 4. Hajimiri, A, TH Lee, “Low Noise Oscillators,” Phase Noise and Jitter in PhaseLocked Loops, Kluwer Academic Publishers, pg 166 to 178. This paper was presented at the SMPTE 141st Technical Conference in New York, Nov 19 to 22, 1999. Acknowledgment The authors would like to thank J Francis, T Kapucija, E Fankhauser, and D Lynch for their helpful advice and contributions. 20page of 20