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Low Power, High Speed Rail-to-rail Input/output Amplifier /

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Low Power, High Speed Rail-to-Rail Input/Output Amplifier AD8029/AD8030/AD8040 Data Sheet CONNECTION DIAGRAMS Automotive safety and vision systems Battery-powered instrumentation Filters A-to-D drivers Buffering DISABLE 7 +VS +IN 3 6 VOUT –VS 4 5 NC NC = NO CONNECT VOUT 1 –VS 2 + +IN 3 Figure 1. SOIC-8 (R) – 6 +VS 5 DISABLE 4 –IN 03679-A-002 8 Figure 2. SC70-6 (KS) VOUT 1 1 14 VOUT 4 –IN 1 2 13 –IN 4 +IN 1 3 12 +IN 4 +VS 4 11 –VS +VOUT 2 +IN 2 5 10 +IN 3 –IN 2 –IN 2 6 9 –IN 3 VOUT 2 7 8 VOUT 3 VOUT 1 1 8 +VS –IN 1 2 7 +IN 1 3 6 –VS 4 5 +IN 2 Figure 3. SOIC-8 (R) and SOT23-8 (RJ) 03679-A-001 APPLICATIONS NC 1 –IN 2 03679-A-003 Qualified for automotive applications Low power: 1.3 mA supply current/amplifier High speed 125 MHz, –3 dB bandwidth (G = +1) 60 V/µs slew rate 80 ns settling time to 0.1% Rail-to-rail input and output No phase reversal, inputs 200 mV beyond rails Wide supply range: 2.7 V to 12 V Offset voltage: 6 mV maximum Low input bias current +0.7 µA to –1.5 µA Small packaging SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14 03679-A-004 FEATURES Figure 4. SOIC-14 (R) and TSSOP-14 (RU) GENERAL DESCRIPTION The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail input and output high speed amplifiers with a quiescent current of only 1.3 mA per amplifier. Despite their low power consumption, the amplifiers provide excellent performance with 125 MHz small signal bandwidth and 60 V/µs slew rate. Analog Devices, Inc., proprietary XFCB process enables high speed and high performance on low power. systems where component density requires lower power dissipation. The AD8040W is an automotive grade version, qualified for automotive applications. The AD8029/AD8030 are the only low power, rail-to-rail input and output high speed amplifiers available in SOT23 and SC70 micro packages. The amplifiers are rated over the extended industrial temperature range, –40°C to +125°C. This family of amplifiers exhibits true single-supply operation with rail-to-rail input and output performance for supply voltages ranging from 2.7 V to 12 V. The input voltage range extends 200 mV beyond each rail without phase reversal. The dynamic range of the output extends to within 40 mV of each rail. The versatility of the AD8029/AD8030/AD8040 allows the user to operate the amplifiers on a wide range of supplies while consuming less than 6.5 mW of power. These features extend the operation time in applications ranging from battery-powered systems with large bandwidth requirements to high speed Rev. B INPUT 4.5 4.0 OUTPUT 3.5 VOLTAGE (V) The AD8029/AD8030/AD8040 provide excellent signal quality with minimal power dissipation. At G = +1, SFDR is –72 dBc at 1 MHz and settling time to 0.1% is only 80 ns. Low distortion and fast settling performance make these amplifiers suitable drivers for single-supply analog-to-digital converters. 5.0 3.0 2.5 2.0 1.5 1.0 G = +1 0.5 VS = +5V RL = 1kΩ TIED TO MIDSUPPLY 0 TIME (µs) 1µs/DIV 03679-A-010 Figure 5. Rail-to-Rail Response Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8029/AD8030/AD8040 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications ....................................................................................... 1 Input Stage ................................................................................... 16 Connection Diagrams ...................................................................... 1 Output Stage................................................................................ 16 General Description ......................................................................... 1 Applications..................................................................................... 17 Specifications..................................................................................... 3 Wideband Operation ................................................................. 17 Specifications with ±5 V Supply ................................................. 3 Output Loading Sensitivity ....................................................... 17 Specifications with +5 V Supply ................................................. 4 Disable Pin .................................................................................. 18 Specifications with +3 V Supply ................................................. 5 Circuit Considerations .............................................................. 19 Absolute Maximum Ratings............................................................ 7 Design Tools and Technical Support ....................................... 19 Maximum Power Dissipation ..................................................... 7 Outline Dimensions ....................................................................... 20 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 21 Typical Performance Characteristics ............................................. 8 REVISION HISTORY 10/12—Rev. A to Rev. B Added Automotive Model, AD8040W ............................ Universal Changes to Features Section............................................................ 1 Changes to General Description Section ...................................... 1 Changes to Specifications Section, Table 1, Added Automotive Specifications..................................................................................... 3 Moved ESD Caution to Absolute Maximum Ratings Section .... 7 Changes to Figure 17 ........................................................................ 9 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 11/03—Rev. 0 to Rev. A Added AD8040 part ....................................................... Universal Change to Figure 5 ....................................................................... 1 Changes to Specifications ............................................................ 3 Changes to Figures 10–12 ............................................................ 7 Change to Figure 14 ..................................................................... 8 Changes to Figures 20 and 21 ..................................................... 9 Inserted new Figure 36............................................................... 11 Change to Figure 40 ................................................................... 12 Inserted new Figure 41............................................................... 12 Added Output Loading Sensitivity section ............................. 16 Changes to Table 5 ...................................................................... 17 Changes to Power Supply Bypassing section .......................... 18 Changes to Ordering Guide ...................................................... 20 Rev. B | Page 2 of 24 Data Sheet AD8029/AD8030/AD8040 SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY Table 1. VS = ±5 V @ TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted. All specifications are per amplifier. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Conditions Min Typ G = +1, VO = 0.1 V p-p AD8040W only: TMIN to TMAX G = +1, VO = 2 V p-p AD8040W only: TMIN to TMAX G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = –1, VO = 2 V Step G = +2, VO = 2 V Step 80 80 14 9 125 Max Unit 6 62 63 80 MHz MHz MHz MHz MHz V/μs V/μs ns Input Voltage Noise fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz –74 –56 16.5 dBc dBc nV/√Hz Input Current Noise f = 100 kHz 1.1 Crosstalk (AD8030/AD8040) f = 5 MHz, VIN = 2 V p-p –79 pA/√Hz dB PNP Active, VCM = 0 V 1.6 Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) DC PERFORMANCE Input Offset Voltage 19 AD8040W only: TMIN to TMAX NPN Active, VCM = 4.5 V 2 AD8040W only: TMIN to TMAX Input Offset Voltage Drift Input Bias Current1 TMIN to TMAX NPN Active, VCM = 4.5 V TMIN to TMAX AD8040W only: TMIN to TMAX PNP Active, VCM = 0 V TMIN to TMAX AD8040W only: TMIN to TMAX 30 0.7 1 –1.7 2 Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio ±0.1 AD8040W only: TMIN to TMAX Vo = ±4.0 V AD8040W only: TMIN to TMAX 65 62 5 mV 9.5 mV 6 mV 9.5 mV 1.3 1.3 –2.8 –2.8 ±0.9 ±0.9 74 μV/°C μA μA μA μA μA μA μA μA dB dB 6 2 –5.2 to +5.2 90 MΩ pF V dB dB DISABLE Low Voltage –VS + 0.8 V DISABLE Low Current –6.5 μA DISABLE High Voltage –VS + 1.2 V 0.2 μA 150 ns 85 ns VCM = –4.5 V to +3 V, RL = 10 kΩ AD8040W only: TMIN to TMAX 80 80 DISABLE PIN (AD8029) DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 VIN = +6 V to –6 V, G = –1 RL = 1 kΩ AD8040W only: TMIN to TMAX RL = 10 kΩ AD8040W only: TMIN to TMAX Rev. B | Page 3 of 24 55/45 –VS + 0.22 –VS + 0.22 –VS + 0.05 –VS + 0.05 +VS – 0.22 +VS – 0.22 +VS – 0.05 +VS – 0.05 ns V V V V AD8029/AD8030/AD8040 Parameter Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Data Sheet Conditions Min Sinking and Sourcing VIN = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot Typ 20 pF 1.4 AD8040W only: TMIN to TMAX 1 DISABLE = Low, AD8029 only Power Supply Rejection Ratio Vs ± 1 V AD8040W only: TMIN to TMAX 150 73 72 Unit mA dB 2.7 Quiescent Current (Disabled) Max 170/160 –55 12 1.5 V mA 1.85 mA 200 µA 80 dB dB Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. SPECIFICATIONS WITH +5 V SUPPLY Table 2. VS = 5 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Conditions Min Typ G = +1, VO = 0.1 V p-p 80 80 13 8 120 G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = –1, VO = 2 V Step G = +2, VO = 2 V Step 6 55 60 82 fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 5 MHz, VIN = 2 V p-p –73 –55 16.5 1.1 –79 dBc dBc nV/√Hz pA/√Hz dB PNP Active, VCM = 2.5 V 1.4 G = +1, VO = 2 V p-p AD8040W only: TMIN to TMAX Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Crosstalk (AD8030/AD8040) DC PERFORMANCE Input Offset Voltage 18 AD8040W only: TMIN to TMAX NPN Active, VCM = 4.5 V 1.8 AD8040W only: TMIN to TMAX Input Offset Voltage Drift Input Bias Current1 TMIN to TMAX NPN Active, VCM = 4.5 V TMIN to TMAX PNP Active, VCM = 2.5 V TMIN to TMAX 25 0.8 1 –1.8 2 ±0.1 Input Offset Current AD8040W only: TMIN to TMAX Open-Loop Gain Vo = 1 V to 4 V AD8040W only: TMIN to TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio Unit MHz MHz MHz MHz MHz V/µs V/µs ns AD8040W only: TMIN to TMAX Bandwidth for 0.1 dB Flatness Slew Rate Max VCM = 0.25 V to 2 V, RL = 10 kΩ AD8040W only: TMIN to TMAX DISABLE PIN (AD8029) DISABLE Low Voltage DISABLE Low Current DISABLE High Voltage Rev. B | Page 4 of 24 65 62 80 80 74 5 8.5 6 8.5 1.2 –2.8 ±0.9 ±0.9 mV mV mV mV µV/°C µA µA µA µA µA µA dB dB 6 2 –0.2 to +5.2 90 MΩ pF V dB dB –VS + 0.8 –6.5 –VS + 1.2 V µA V Data Sheet Parameter DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing AD8029/AD8030/AD8040 Conditions Min 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 Max VIN = –1 V to +6 V, G = –1 RL = 1 kΩ ns 45/50 –VS + 0.17 –VS + 0.17 –VS + 0.04 –VS + 0.04 RL = 10 kΩ AD8040W only: TMIN to TMAX Sinking and Sourcing Vin = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot +VS – 0.17 +VS – 0.17 +VS – 0.04 +VS – 0.04 95/60 –55 15 2.7 12 1.5 1.75 200 1.3 AD8040W only: TMIN to TMAX Quiescent Current (Disabled) Power Supply Rejection Ratio DISABLE = Low, AD8029 only VS ± 1 V 140 80 73 72 AD8040W only: TMIN to TMAX 1 Unit µA ns 90 AD8040W only: TMIN to TMAX Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Typ 0.2 155 ns V V V V mA dB pF V mA mA µA dB dB Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. SPECIFICATIONS WITH +3 V SUPPLY Table 3. VS = +3 V @ TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Conditions Min Typ G = +1, VO = 0.1 V p-p 80 80 13 8 112 G = +2, VO = 0.1 V p-p G = +1, VO = 2 V Step G = –1, VO = 2 V Step G = +2, VO = 2 V Step 6 55 57 110 fC = 1 MHz, VO = 2 V p-p fC = 5 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 5 MHz, VIN = 2 V p-p –72 –60 16.5 1.1 –80 dBc dBc nV/√Hz pA/√Hz dB PNP Active, VCM = 1.5 V 1.1 G = +1, VO = 2 V p-p AD8040W only: TMIN to TMAX Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) Input Voltage Noise Input Current Noise Crosstalk (AD8030/AD8040) DC PERFORMANCE Input Offset Voltage 18 AD8040W only: TMIN to TMAX NPN Active, VCM = 2.5 V 1.6 AD8040W only: TMIN to TMAX Input Offset Voltage Drift Input Bias Current1 Input Bias Current1 Unit MHz MHz MHz MHz MHz V/µs V/µs ns AD8040W only: TMIN to TMAX Bandwidth for 0.1 dB Flatness Slew Rate Max TMIN to TMAX NPN Active, VCM = 2.5 V TMIN to TMAX PNP Active, VCM = 1.5 V TMIN to TMAX Input Offset Current AD8040W only: TMIN to TMAX Rev. B | Page 5 of 24 24 0.7 1 –1.5 1.6 ±0.1 5 8 6 8 1.2 –2.5 ±0.9 ±0.9 mV mV mV mV µV/°C µA µA µA µA µA µA AD8029/AD8030/AD8040 Parameter Open-Loop Gain Data Sheet Conditions Vo = 0.5 V to 2.5 V AD8040W only: TMIN to TMAX INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio VCM = 0.25 V to 1.25 V, RL = 10 kΩ AD8040W only: TMIN to TMAX DISABLE PIN (AD8029) DISABLE Low Voltage DISABLE Low Current DISABLE High Voltage DISABLE High Current Turn-Off Time Turn-On Time OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) Output Voltage Swing 78 78 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 50% of DISABLE to <10% of Final VO, VIN = –1 V, G = –1 VIN = –1 V to +4 V, G = –1 RL = 1 kΩ AD8040W only: TMIN to TMAX RL = 10 kΩ AD8040W only: TMIN to TMAX Short-Circuit Current Off Isolation (AD8029) Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Min 64 62 Typ 73 MΩ pF V dB dB –VS + 0.8 –6.5 –VS + 1.2 0.2 165 V µA V µA ns 95 ns 75/100 –VS + 0.09 –VS + 0.09 –VS + 0.04 –VS + 0.04 Sinking and Sourcing VIN = 0.1 V p-p, f = 1 MHz, DISABLE = Low 30% Overshoot +VS – 0.09 +VS – 0.09 +VS – 0.04 +VS – 0.04 80/40 –55 10 2.7 1.3 DISABLE = Low, AD8029 only VS ± 1 V AD8040W only: TMIN to TMAX 1 Plus, +, (or no sign) indicates current into pin; minus (–) indicates current out of pin. Rev. B | Page 6 of 24 70 68 Unit dB dB 6 2 –0.2 to +3.2 88 AD8040W only: TMIN to TMAX Quiescent Current (Disabled) Power Supply Rejection Ratio Max 145 76 12 1.4 1.75 200 ns V V V V mA dB pF V mA mA µA dB dB Data Sheet AD8029/AD8030/AD8040 ABSOLUTE MAXIMUM RATINGS RMS output voltages should be considered. If RL is referenced to VS–, as in single-supply operation, then the total drive power is VS × IOUT. Table 4. AD8029/AD8030/AD8040 Stress Ratings Rating 12.6 V See Figure 6 ±VS ± 0.5 V ±1.8 V –65°C to +125°C –40°C to +125°C 300°C If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply: PD = (VS × I S ) + RL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the AD8029/AD8030/ AD8040 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8029/AD8030/AD8040. Exceeding a junction temperature of 175°C for an extended period can result in changes in silicon devices, potentially causing failure. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduce the θJA. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in the PCB Layout section. Figure 6 shows the maximum safe power dissipation in the package versus the ambient temperature for the SOIC-8 (125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W), TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a JEDEC standard 4-layer board. θJA values are approximations. 2.5 The still-air thermal properties of the package and PCB (θJA), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as 2.0 SOIC-14 1.5 TSSOP-14 SOIC-8 1.0 0.5 SOT-23-8 SC70-6 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) TJ = TA + (PD × θJA) 03679-A-018 150°C Figure 6. Maximum Power Dissipation The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. Output Short Circuit Shorting the output to ground or drawing excessive current from the AD8029/AD8030/AD8040 could cause catastrophic failure. ESD CAUTION PD = Quiescent Power + (Total Drive Power – Load Power) V V PD = (VS × I S ) +  S × OUT RL  2 (VS /4 )2 In single-supply operation with RL referenced to VS–, worst case is VOUT = VS/2. MAXIMUM POWER DISSIPATION (W) Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature  VOUT 2 –  RL  Rev. B | Page 7 of 24 AD8029/AD8030/AD8040 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = 5 V (TA = 25°C, RL = 1 kΩ tied to midsupply, unless otherwise noted.) 0.2 1 NORMALIZED CLOSED-LOOP GAIN (dB) –1 –2 G = +10 RF = 9kΩ, RG = 1kΩ –3 –4 –5 G = +1 RF = 0Ω G = +2 RF = RG = 1kΩ –6 –7 –8 –9 –10 –11 –12 –13 –14 0.1 VO = 0.1V p-p 1 0 –0.1 G = +1 –0.2 –0.3 –0.4 G = +2 –0.5 –0.6 –0.7 –0.8 10 FREQUENCY (MHz) 100 1 1000 NORMALIZED CLOSED-LOOP GAIN (dB) CLOSED-LOOP GAIN (dB) Figure 10. 0.1 dB Flatness Frequency Response +3V ±5V –1 100 03679-A-011 1 G = +1 VO = 0.1V p-p 0 10 FREQUENCY (MHz) 03679-0-004 Figure 7. Small Signal Frequency Response for Various Gains 1 RF = 1kΩ DASHED LINES: VOUT = 2V p-p 0.1 SOLID LINES: VOUT = 0.1V p-p NORMALIZED CLOSED-LOOP GAIN (dB) G = –1 RF = RG = 1kΩ 0 –2 –3 –4 +5V –5 –6 –7 G = +2 VO = 0.1V p-p RF = 1kΩ 0 –1 –2 –3 ±5V –4 –5 –6 +5V –7 +3V –8 –8 1 10 100 FREQUENCY (MHz) 1000 1 Figure 8. Small Signal Frequency Response for Various Supplies 1 1 NORMALIZED CLOSED-LOOP GAIN (dB) ±5V CLOSED-LOOP GAIN (dB) –1 –2 +3V –3 –4 –5 –6 +5V –7 100 03679-A-012 Figure 11. Small Signal Frequency Response for Various Supplies G = +1 VO = 2V p-p 0 10 FREQUENCY (MHz) 03679-0-005 –8 G = +2 VO = 2V p-p 0 RF = 1kΩ –1 VS = ±5 –2 VS = +5 –3 –4 VS = +3 –5 –6 –7 –8 1 10 FREQUENCY (MHz) 100 1 03679-0-006 Figure 9. Large Signal Frequency Response for Various Supplies 10 FREQUENCY (MHz) 100 03679-A-013 Figure 12. Large Signal Frequency Response for Various Supplies Rev. B | Page 8 of 24 Data Sheet AD8029/AD8030/AD8040 2 6 CLOSED-LOOP GAIN (dB) 3 2 G = +1 1 VO = 0.1V p-p 20pF 10pF 5pF 1 0 –1 0pF –2 VICM = VS+ – 0.2V VICM = 0V 0 CLOSED-LOOP GAIN (dB) G = +1 5 V = 0.1V p-p O 4 –3 –4 –5 –1 VICM = VS– + 0.2V –2 –3 –4 –5 –6 –6 –7 –7 –8 –8 1 10 100 FREQUENCY (MHz) 1000 1 Figure 13. Small Signal Frequency Response for Various CLOAD 1 NORMALIZED CLOSED-LOOP GAIN (dB) 2 +125°C +85°C +25°C CLOSED-LOOP GAIN (dB) –2 –3 –4 –5 2V p-p 1V p-p –6 0.1V p-p 1 10 FREQUENCY (MHz) 0 –40°C –1 –2 –3 –4 –5 –7 –8 –6 100 1 10 100 FREQUENCY (MHz) 03679-A-014 80 225 1 70 G = +1 VO = 2V p-p 0 50 40 135 30 20 90 10 0 45 +125°C –1 CLOSED-LOOP GAIN (dB) 180 OPEN-LOOP PHASE (Degrees) 60 1000 03679-0-014 Figure 17. Small Signal Frequency Response vs. Temperature Figure 14. Frequency Response for Various Output Amplitudes OPEN-LOOP GAIN (dB) G = +1 VO = 0.1V p-p 1 –1 +25°C –2 +85°C –3 –4 –40°C –5 –6 –7 –10 –20 10 1000 03679-0-013 Figure 16. Small Signal Frequency Response for Various Input Common-Mode Voltages G = +2 RF = 1kΩ 0 10 100 FREQUENCY (MHz) 03679-0-010 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 0 1G –8 1 03679-0-054 Figure 15. Open-Loop Gain and Phase vs. Frequency 10 FREQUENCY (MHz) 100 03679-0-015 Figure 18. Large Signal Frequency Response vs. Temperature Rev. B | Page 9 of 24 AD8029/AD8030/AD8040 Data Sheet –40 G = +1 VOUT = 2V p-p –45 RL = 1kΩ SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE –55 –50 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) –35 –65 VS = +3V –75 –85 VS = +5V VS = ±5V G = +1 VOUT = 2V p-p SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE –60 –70 RL = 1kΩ –80 –90 RL = 5kΩ –100 –95 RL = 2kΩ –105 0.01 0.1 1 FREQUENCY (MHz) –110 0.01 10 –40 –40 VS = +5V VS = +3V –55 –60 –65 –70 –75 G = +1 VOUT = 2V p-p FREQ = 1MHz –50 VS = +10V HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) G = +2 FREQ = 1MHz –45 RF = 1kΩ –80 0.5 2.5 3.5 4.5 5.5 6.5 7.5 OUTPUT AMPLITUDE (V p-p) 8.5 VS = +5V VS = +3V –60 –70 –80 –90 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 1.5 10 03679-0-075 Figure 22. Harmonic Distortion vs. Frequency and Load Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage –50 0.1 1 FREQUENCY (MHz) 03679-0-016 –100 1.0 9.5 1.5 03679-A-015 2.0 2.5 3.0 3.5 INPUT COMMON-MODE VOLTAGE (V) 4.0 03679-0-020 Figure 23. Harmonic Distortion vs. Input Common Mode Voltage Figure 20. Harmonic Distortion vs. Output Amplitude –30 1000 100 100 10 G = +2 –60 G = –1 –70 –80 –90 VOLTAGE NOISE 1 10 CURRENT NOISE G = +1 –100 –110 0.01 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE 0.1 1 FREQUENCY (MHz) 1 10 10 03679-A-016 100 1k 10k 100k FREQUENCY (Hz) 0.1 10M 1M 03679-0-069 Figure 24. Voltage and Current Noise vs. Frequency Figure 21. Harmonic Distortion vs. Frequency and Gain Rev. B | Page 10 of 24 CURRENT NOISE (pA/ Hz) –50 VOLTAGE NOISE (nV/ Hz) HARMONIC DISTORTION (dBc) VS = +5V VOUT = 2.0V p-p –40 R = 1kΩ L RF = 1kΩ Data Sheet AD8029/AD8030/AD8040 100 100 75 G = +1 VS = ±2.5V 75 25 0 –25 –50 25 0 –25 –50 –75 –75 25mV/DIV 25mV/DIV 20ns/DIV TIME (ns) TIME (ns) 03679-0-022 2.5 G = +1 2.0 VS = ±2.5V 5.0 4V p-p INPUT 4.5 4.0 1.0 3.5 2V p-p VOLTAGE (V) 0.5 0 –0.5 –1.0 3.0 2.5 2.0 1.5 –1.5 1.0 G = +1 0.5 VS = +5V RL = 1kΩ TIED TO MIDSUPPLY 0 TIME (Seconds) –2.0 0.5V/DIV 25ns/DIV TIME (ns) 03679-A-023 Figure 26. Large Signal Transient Response OUTPUT 1µs/DIV 03679-0-059 Figure 29. Rail-to-Rail Response, G = +1 4 4 INPUT 3 G = –1 (RF = 1kΩ) RL = 1kΩ VS = ±2.5V INPUT 3 2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.5 OUTPUT VOLTAGE (V) 03679-0-025 Figure 28. Small Signal Transient Response with Capacitive Load Figure 25. Small Signal Transient Response 1 20ns/DIV –100 –100 –2.5 CL = 20pF CL = 10pF CL = 5pF 50 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (mV) 50 G = +1 VS = ±2.5V OUTPUT 0 –1 G = +1 RL = 1kΩ VS = ±2.5V 2 OUTPUT 1 0 –1 –2 –2 –3 –3 1V/DIV 200ns/DIV 1V/DIV –4 200ns/DIV –4 TIME (ns) TIME (ns) 03679-0-024 Figure 30. Input Overdrive Recovery Figure 27. Output Overdrive Recovery Rev. B | Page 11 of 24 03679-0-027 AD8029/AD8030/AD8040 Data Sheet VIN (250mV/DIV) VOUT (500mV/DIV) G = +2 VS = ±2.5V G = +2 +1V +0.1% +0.1% VOUT – 2VIN (0.1%/DIV) VOUT – 2VIN (0.1%/DIV) –0.1% –0.1% VOUT (500mV/DIV) –1V 500ns/DIV 20ns/DIV 03679-0-062 03679-0-063 Figure 31. Long-Term Settling Time Figure 34.0.1% Short-Term Settling Time 0 –20 –10 –30 –20 +PSRR –40 –30 PSRR (dB) CMRR (dB) –50 –60 –70 –40 –50 –60 –70 –PSRR –80 –80 –90 –90 –100 1k –100 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 10k 100M 1G 03679-0-033 –30 VIN G = +1 RL = 1kΩ DISABLE = LOW VIN = 0.1V p-p –40 DRIVE AMP 50Ω 1kΩ –50 –60 CROSSTALK (dB) –40 OUTPUT (dB) 10M Figure 35. PSRR vs. Frequency –20 –50 –60 LISTEN AMP VOUT –70 1kΩ –80 CROSSTALK = 20log –90 ( ) VOUT VIN AD8030 (AMP 2 DRIVE AMP 1 LISTEN) –100 –110 –70 AD8040 (AMP 4 DRIVE AMP 1 LISTEN) –120 –80 0.1 1M FREQUENCY (Hz) Figure 32. Common-Mode Rejection Ratio vs. Frequency –30 100k 03679-0-078 1 10 FREQUENCY (MHz) 100 1000 –130 0.01 03679-0-055 Figure 33. AD8029 Off-Isolation vs. Frequency 0.1 1.0 10 FREQUENCY (MHz) 100 Figure 36. AD8030/AD8040 Crosstalk vs. Frequency Rev. B | Page 12 of 24 1000 03679-A-005 1k Data Sheet AD8029/AD8030/AD8040 4 2.5 2.0 VS = +10V INPUT OFFSET VOLTAGE (mV) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.5 –1 0 1 2 3 4 5 6 7 8 9 INPUT COMMON-MODE VOLTAGE (V) 10 1 0 –1 –2 –4 –1 11 –1.2 0.8 NPN ACTIVE VS = +5 0.6 VS = +3 0.4 –1.6 PNP ACTIVE –1.8 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 0.2 95 110 2 3 4 5 6 7 8 9 INPUT COMMON-MODE VOLTAGE (V) 10 11 Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage 4 3 INPUT OFFSET VOLTAGE (mV) 1.0 VS = ±5 1 03679-A-017 INPUT BIAS CURRENT (NPN ACTIVE) (µA) –1.0 –1.4 0 03679-0-074 Figure 37. Input Bias Current vs. Input Common-Mode Voltage 2 VS = ±5V 1 VS = +5V 0 –1 VS = +3V –2 –3 –4 –40 0 125 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 03679-0-073 Figure 41. Input Offset Voltage vs. Temperature Figure 38. Input Bias Current vs. Temperature 120 1.8 COUNT = 1088 MEAN = 0.44mV STDEV = 1.05mV 1.7 100 1.6 VS = +5V 1.5 80 VS = ±5V 1.4 FREQUENCY SUPPLY CURRENT (mA) INPUT BIAS CURRENT (PNP ACTIVE) (µA) VS = +10V –3 –2.0 –2.0 –40 VS = +5V 2 1.3 VS = +3V 1.2 1.1 1.0 60 40 20 0.9 0.8 –40 0 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 –5 –4 –3 –2 –1 0 1 2 3 INPUT OFFSET VOLTAGE (mV) 03679-0-067 Figure 42. Input Offset Voltage Distribution Figure 39 Quiescent Supply Current vs. Temperature Rev. B | Page 13 of 24 4 5 03679-0-064 03679-A-006 INPUT BIAS CURRENT (µA) VS = +5V VS = +3V 1.5 RL = 1kΩ TO MIDSUPPLY G = +1 VS = +3V 3 AD8029/AD8030/AD8040 Data Sheet 1M 1000 G = +1 DISABLE = LOW OUTPUT IMPEDANCE (Ω) OUTPUT IMPEDANCE (Ω) 100k 10k 1k 100 100 10 1 10 1 100k 1M 10M FREQUENCY (Hz) 100M 0.1 1k 1G 100k 1M 10M FREQUENCY (Hz) 100M 2.0 0.5 LOAD RESISTANCE TIED TO MIDSUPPLY 0.4 0.2 VOL – VS 0.1 VS = +3V 0 VS = ±2.5V 1.5 INPUT ERROR VOLTAGE (mV) 0.3 VS = +5V VS = ±5V –0.1 VOH – VS –0.2 –0.3 1.0 0.5 RL = 10kΩ 0 RL = 1kΩ –0.5 –1.0 –1.5 –0.4 –0.5 100 1000 LOAD RESISTANCE (Ω) –2.0 –2.5 10000 –2.0 –1.5 –1.0 –0.5 –0 0.5 1.0 OUTPUT VOLTAGE (V) 1.5 03679-0-041 Figure 46. Input Error Voltage vs. Output Voltage Figure 44. Output Saturation Voltage vs. Load Resistance 170 OUTPUT SATURATION VOLTAGE (mV) 1G 03679-0-060 Figure 45. Output Impedance vs. Frequency, Enabled Figure 43. AD8029 Output Impedance vs. Frequency, Disabled OUTPUT SATURATION VOLTAGE (V) 10k 03679-0-061 150 VS = ±5V 130 110 90 VS = +5V 70 50 30 –40 RL = 1kΩ TIED TO MIDSUPPLY SOLID LINE: VS+ – VOH DASHED LINE: VOL – VS– VS = +3V –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 03679-0-066 Figure 42. Output Saturation Voltage vs. Temperature Rev. B | Page 14 of 24 2.0 2.5 03679-0-072 Data Sheet AD8029/AD8030/AD8040 1 1.5 DISABLE (–0.5V TO –2V) VS = +3V, +5V, +10V 0 DISABLE PIN CURRENT (µA) OUTPUT AMPLITUDE (V) 1.0 0.5 RL = 100Ω 0 OUTPUT DISABLED RL = 1kΩ RL = 10kΩ –0.5 –1 –2 –3 –4 –5 –1.0 –6 VS = ±2.5V G = –1 (RF = 1kΩ) –1.5 0 50 100 150 200 TIME (ns) 250 300 –7 0 350 03679-A-020 1.5 DISABLE (–2V TO –0.5V) OUTPUT AMPLITUDE (V) OUTPUT ENABLED 0.5 0 RL = 100Ω RL = 1kΩ RL = 10kΩ –0.5 –1.0 –1.5 VS = ±2.5V G = –1 (RF = 1kΩ) 0 50 100 150 200 TIME (ns) 250 3 03679-A-022 Figure 49. AD8029 DISABLE Pin Current vs. DISABLE Pin Voltage Figure 47. AD8029 DISABLE Turn-Off Timing 1.0 0.8 1 1.2 2 DISABLE PIN VOLTAGE (V) 300 350 03679-A-021 Figure 48. AD8029 DISABLE Turn-On Timing Rev. B | Page 15 of 24 AD8029/AD8030/AD8040 Data Sheet THEORY OF OPERATION +VS RTH ITAIL SPD +VS –1.2V DISABLE Q9 TO DISABLE CIRCUITRY ITH –VS Q10 AD8029 ONLY MTOP Q1 IN– OUTPUT BUFFER R3 R4 R 1 R2 Q5 CMT Q2 Q6 VOUT CMB Q7 Q8 Q3 IN+ Q4 MBOT R5 R6 R7 R8 Q11 OUT IN COM –VS 03679-0-051 Figure 50. Simplified Schematic OUTPUT STAGE The AD8029 (single), AD8030 (dual), and AD8040 (quad) are rail-to-rail input and output amplifiers fabricated using Analog Devices’ XFCB process. The XFCB process enables the AD8029/ AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a 120 MHz bandwidth and a 60 V/µs slew rate. A simplified sche-matic of the AD8029/AD8030/AD8040 is shown in Figure 50. The currents derived from the PNP and NPN input differential pairs are injected into the current mirrors MBOT and MTOP, thus establishing a common-mode signal voltage at the input of the output buffer. INPUT STAGE 1. It buffers and applies the desired signal voltage to the output devices, Q10 and Q11. 2. It senses the common-mode current level in the output devices. 3. It regulates the output common-mode current by establishing a common-mode feedback loop. For input common-mode voltages less than a set threshold (1.2 V below VCC), the resistor degenerated PNP differential pair (comprising Q1 toQ4) carries the entire ITAIL current, allowing the input voltage to go 200 mV below –VS. Conversely, input common-mode voltages exceeding the same threshold cause ITAIL to be routed away from the PNP differential pair and into the NPN differential pair through transistor Q9. Under this condition, the input common-mode voltage is allowed to rise 200 mV above +VS while still maintaining linear amplifier behavior. The transition between these two modes of operation leads to a sudden, temporary shift in input stage transconductance, gm, and dc parameters (such as the input offset voltage VOS), which in turn adversely affect the distortion performance. The SPD block shortens the duration of this transition, thus improving the distortion performance. As shown in Figure 50, the input differential pair is protected by a pair of two series diodes, connected in anti-parallel, which clamp the differential input voltage to approximately ±1.5 V. The output buffer performs three functions: The output devices Q10 and Q11 work in a common-emitter configuration, and are Miller-compensated by internal capacitors, CMT and CMB. The output voltage compliance is set by the output devices’ collector resistance RC (about 25 Ω), and by the required load current IL. For instance, a light equivalent load (5 kΩ) allows the output voltage to swing to within 40 mV of either rail, while heavier loads cause this figure to deteriorate as RC × IL. Rev. B | Page 16 of 24 Data Sheet AD8029/AD8030/AD8040 APPLICATIONS WIDEBAND OPERATION For example, if using the values shown in Table 5 for a gain of 2, with resistor values of 2.5 kΩ, the effective load at the output is 1.67 kΩ. For inverting configurations, only the feedback resistor RF is in parallel with the output load. If the load is greater than that specified in the data sheet, the amplifier can introduce nonlinearities in its open-loop response, which increases distortion. Figure 53 and Figure 54 illustrate effective output loading and distortion performance. Increasing the resistance of the feedback network can reduce the current consumption, but has other implications. RF C2 10µF C1 0.1µF RG – AD8029 VOUT R1 + DISABLE C4 0.1µF C3 10µF –VS –40 VS = 5V 0.1V p-p VOUT = 2.0V –50 SECOND HARMONIC – SOLID LINES THIRD HARMONIC – DOTTED LINES 03679-0-052 HARMONIC DISTORTION (dBc) R1 = RF||RG Figure 51. Wideband Non-inverting Gain Configuration RF +VS C2 10µF C1 0.1µF VIN RG – AD8029 + VOUT RL = 1kΩ –80 –90 RL = 2.5kΩ 0.1 1.0 FREQUENCY (MHz) 10 10 Figure 53. Gain of 1 Distortion C3 10µF –VS RL = 5kΩ –100 –120 0.01 C4 0.1µF R1 –70 –110 DISABLE R1 = RF||RG –60 03679-A-008 VIN 03679-A-009 +VS –40 VS = 5V 0.1V p-p VOUT = 2.0V –50 SECOND HARMONIC – SOLID LINES THIRD HARMONIC – DOTTED LINES 03679-0-053 OUTPUT LOADING SENSITIVITY To achieve maximum performance and low power dissipation, the designer needs to consider the loading at the output of AD8029/AD8030/AD8040. Table 5 shows the effects of output loading and performance. When operating at unity gain, the effective load at the amplifier output is the resistance (RL) being driven by the amplifier. For gains other than 1, in noninverting configurations, the feedback network represents an additional current load at the amplifier output. The feedback network (RF + RG) is in parallel with RL, which lowers the effective resistance at the output of the amplifier. The lower effective resistance causes the amplifier to supply more current at the output. Lower values of feedback resistance increase the current draw, thus increasing the amplifier’s power dissipation. HARMONIC DISTORTION (dBc) Figure 52. Wideband Inverting Gain Configuration Rev. B | Page 17 of 24 –60 RF = RL = 1kΩ –70 –80 RF = RL = 5kΩ –90 –100 RF = RL = 2.5kΩ –110 –120 0.01 0.1 1.0 FREQUENCY (MHz) Figure 54. Gain of 2 Distortion AD8029/AD8030/AD8040 Data Sheet Table 5. Effect of Load on Performance Noninverting Gain 1 1 1 2 2 2 –1 –1 –1 RF (kΩ) 0 0 0 1 2.5 5 1 2.5 5 RG (kΩ) N/A N/A N/A 1 2.5 5 1 2.5 5 RLOAD (kΩ) 1 2 5 1 2.5 5 1 2.5 5 –3 dB SS BW (MHz) 120 130 139 36 44.5 43 40 40 34 The feedback resistance (RF || RG) combines with the input capacitance to form a pole in the amplifier’s loop response. This can cause peaking and ringing in the amplifier’s response if the RC time constant is too low. Figure 55 illustrates this effect. Peaking can be reduced by adding a small capacitor (1 pF–4 pF) across the feedback resistor. The best way to find the optimal value of capacitor is to empirically try it in your circuit. Another factor of higher resistance values is the impact it has on noise performance. Higher resistor values generate more noise. Each application is unique and therefore a balance must be reached between distortion, peaking, and noise performance. Table 5 outlines the trade-offs that different loads have on distortion, peaking, and noise performance. In gains of 1, 2, and 10, equivalent loads of 1 kΩ, 2 kΩ, and 5 kΩ are shown. With increasing load resistance, the distortion and –3 dB bandwidth improve, while the noise and peaking degrade slightly. VS = 5V VOUT = 0.1V p-p 1 RF = RL = 2.5kΩ Disable Pin Voltage Low (Disabled) High (Enabled) RL = 5kΩ RF = RL = 1kΩ –3 –4 G = +1 –5 –6 G = +2 –7 –8 1 10 100 FREQUENCY (MHz) 1000 Output Noise (nV/√Hz) 16.5 16.5 16.5 33.5 34.4 36 33.6 34 36 Table 6. Disable Pin Control Voltage RL = 2.5kΩ –2 HD3 at 1 MHz, 2 V p-p (dB) –72 –83 –92.5 –60 –72.5 –86 –57 –68 –80 The AD8029 disable pin allows the amplifier to be shut down for power conservation or multiplexing applications. When in the disable mode, the amplifier draws only 150 µA of quiescent current. The disable pin control voltage is referenced to the negative supply. The amplifier enters power-down mode any time the disable pin is tied to the most negative supply or within 0.8 V of the negative supply. If left open, the amplifier will operate normally. For switching levels, refer to Table 6. RF = RL = 5kΩ RL = 1kΩ 0 –1 HD2 at 1 MHz, 2 V p-p (dB) –80 –84 –87.5 –72 –79 –84 –68 –74 –78 DISABLE PIN 03679-A-007 NORMALIZED CLOSED-LOOP GAIN (dB) 2 Peaking (dB) 0.02 0.6 1 0 0.2 2 0.01 0.05 1 Figure 55. Frequency Response for Various Feedback/Load Resistances Rev. B | Page 18 of 24 Supply Voltage +3 V +5 V ±5 V 0 V to <0.8 V 0 V to <0.8 V –5 V to <–4 .2 V 1.2 V to 3 V 1.2 V to 5 V –3.8 V to +5 V Data Sheet AD8029/AD8030/AD8040 CIRCUIT CONSIDERATIONS PCB Layout Power Supply Bypassing High speed op amps require careful attention to PCB layout to achieve optimum performance. Particular care must be exercised to minimize lead lengths of the bypass capacitors. Excess lead inductance can influence the frequency response and even cause high frequency oscillations. Using a multilayer board with an internal ground plane can help reduce ground noise and enable a more compact layout. Power supply pins are actually inputs to the op amp. Care must be taken to provide the op amp with a clean, low noise dc voltage source. To achieve the shortest possible trace length at the inverting input, the feedback resistor, RF, should be located the shortest distance from the output pin to the input pin. The return node of the resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor. On multilayer boards, all layers beneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. This is especially true at the summing junction, i.e., the inverting input, –IN. Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin. Grounding To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. Fast current changes in an inductive ground return will create unwanted noise and ringing. The length of the high frequency bypass capacitor pads and traces is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as from ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Power supply bypassing is employed to provide a low impedance path to ground for noise and undesired signals at all frequencies. This cannot be achieved with a single capacitor type; but with a variety of capacitors in parallel the bandwidth of power supply bypassing can be greatly extended. The bypass capacitors have two functions: 1. Provide a low impedance path for noise and undesired signals from the supply pins to ground. 2. Provide local stored charge for fast switching conditions and minimize the voltage drop at the supply pins during transients. This is typically achieved with large electrolytic capacitors. Good quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package. A parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic covers a wide range of rejection for unwanted noise. The 10 µF capacitor is less critical for high frequency bypassing and, in most cases, one per supply line is sufficient. The values of capacitors are circuit-dependant and should be determined by the system’s requirements. DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools. ADI offers technical support via free evaluation boards, sample ICs, Spice models, interactive evaluation tools, application notes, phone and email support—all available at www.analog.com. Rev. B | Page 19 of 24 AD8029/AD8030/AD8040 Data Sheet OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 5 1 4 4.00 (0.1575) 3.80 (0.1496) 6.20 (0.2441) 5.80 (0.2284) 8 14 1 7 6.20 (0.2441) 5.80 (0.2283) 1.27 (0.0500) BSC 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 0.25 (0.0098) 0.10 (0.0039) 8° 0° COPLANARITY 0.10 0.25 (0.0098) 0.17 (0.0067) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A 5.10 5.00 4.90 5 4 1 2 3 2.40 2.10 1.80 14 8 4.50 4.40 4.30 0.65 BSC 6.40 BSC 1 PIN 1 SEATING PLANE 0.30 0.15 0.65 BSC 0.46 0.36 0.26 0.22 0.08 COMPLIANT TO JEDEC STANDARDS MO-203-AB 1.05 1.00 0.80 6 5 1 2 3 4 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 0.38 MAX 0.22 MIN 0.22 MAX 0.08 MIN SEATING PLANE 8° 4° 0° 0.60 BSC COMPLIANT TO JEDEC STANDARDS MO-178-BA 0.60 0.45 0.30 12-16-2008-A 1.45 MAX 0.95 MIN 8° 0° 0.75 0.60 0.45 Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.00 2.80 2.60 1.30 1.15 0.90 0.30 0.19 SEATING PLANE 0.20 0.09 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 3.00 2.90 2.80 7 1.20 MAX 0.15 0.05 COPLANARITY 0.10 Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6) Dimensions shown in millimeters 8 7 0.40 0.10 1.10 0.80 072809-A 1.00 0.90 0.70 Figure 58. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters Rev. B | Page 20 of 24 061908-A 6 1.30 BSC 0.15 MAX 0.05 MIN 45° 8° 0° Figure 59. 14-Lead Standard Small Outline Package [SOIC_N] (R-14) Dimensions shown in millimeters and (inches) 2.20 2.00 1.80 1.70 1.60 1.50 0.50 (0.0197) 0.25 (0.0098) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) 0.10 MAX COPLANARITY 0.10 SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 1.35 1.25 1.15 1.75 (0.0689) 1.35 (0.0531) 060606-A 8 4.00 (0.1574) 3.80 (0.1497) 8.75 (0.3445) 8.55 (0.3366) Data Sheet AD8029/AD8030/AD8040 ORDERING GUIDE Model1, 2 AD8029ARZ AD8029AR-REEL AD8029ARZ-REEL AD8029AR-REEL7 AD8029ARZ-REEL7 AD8029AKSZ-R2 AD8029AKSZ-REEL AD8029AKSZ-REEL7 AD8030AR AD8030ARZ AD8030ARZ-REEL AD8030ARZ-REEL7 AD8030ARJZ-R2 AD8030ARJZ-REEL AD8030ARJZ-REEL7 AD8040ARZ AD8040ARZ-REEL AD8040ARZ-REEL7 AD8040ARUZ AD8040ARU-REEL AD8040ARUZ-REEL AD8040ARUZ-REEL7 AD8040WARUZ-REEL7 AD8029AR-EBZ AD8029AKS-EBZ AD8030AR-EBZ AD8030ARJ-EBZ AD8040AR-EBZ AD8040ARU-EBZ 1 2 Minimum Ordering Quantity 98 2,500 2,500 1,000 1,000 250 10,000 3,000 98 98 2,500 1,000 250 10,000 3,000 56 2,500 1,000 96 2,500 2,500 1,000 1,000 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 6-Lead SC70 6-Lead SC70 6-Lead SC70 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOT23-8 8-Lead SOT23-8 8-Lead SOT23-8 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Evaluation Board for AD8029, 8-Lead SOIC_N Evaluation Board for AD8029, 6-Lead SC70 Evaluation Board for AD8030, 8-Lead SOIC_N Evaluation Board for AD8030, 8-Lead SOT23-8 Evaluation Board for AD8040, 14-Lead SOIC_N Evaluation Board for AD8040, 14-Lead TSSOP Package Option R-8 R-8 R-8 R-8 R-8 KS-6 KS-6 KS-6 R-8 R-8 R-8 R-8 RJ-8 RJ-8 RJ-8 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14 RU-14 Branding H03 H03 H03 H7B H7B H7B Z = RoHS Compliant Part. W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8040W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. B | Page 21 of 24 AD8029/AD8030/AD8040 Data Sheet NOTES Rev. B | Page 22 of 24 Data Sheet AD8029/AD8030/AD8040 NOTES Rev. B | Page 23 of 24 AD8029/AD8030/AD8040 Data Sheet NOTES ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03679-0-10/12(B) Rev. B | Page 24 of 24

Low Power, High Speed Rail-to-rail Input/output Amplifier /

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