Transcript
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual February 1999
Order Number: 273235-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Pentium® processor with MMX™ technology may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1999. Portions of this manual Copyright © 1999 General Software, Inc. All rights reserved. *Third-party brands and names are the property of their respective owners.
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Contents 1
About This Manual ..................................................................................................1-1 1.1 1.2 1.3
1.4 1.5
2
Getting Started .........................................................................................................2-1 2.1
2.2 2.3
2.4 2.5 2.6
3
Content Overview...............................................................................................1-1 Text Conventions ...............................................................................................1-1 Technical Support ..............................................................................................1-2 1.3.1 Electronic Support Systems ..............................................................1-2 1.3.1.1 Online Documents ...............................................................1-2 1.3.1.2 Intel Product Forums ...........................................................1-3 1.3.2 Telephone Technical Support ...........................................................1-3 Product Literature...............................................................................................1-3 Related Documents............................................................................................1-4 Overview ............................................................................................................2-1 2.1.1 Processor Assembly Features ..........................................................2-1 2.1.2 Baseboard Features ..........................................................................2-1 Included Hardware .............................................................................................2-2 Software Key Features.......................................................................................2-2 2.3.1 Annasoft Systems .............................................................................2-2 2.3.2 General Software, Inc........................................................................2-3 2.3.3 QNX Software Systems, Ltd..............................................................2-3 2.3.4 RadiSys Corporation .........................................................................2-4 2.3.5 VenturCom, Inc. ................................................................................2-4 2.3.5.1 Real-Time Extension* (RTX) ...............................................2-4 2.3.5.2 Component Integrator* (CI) .................................................2-4 2.3.6 WindRiver Systems ...........................................................................2-5 Before You Begin ...............................................................................................2-5 Setting up the Evaluation Platform .....................................................................2-6 Configuring the BIOS .........................................................................................2-8
Theory Of Operation ..............................................................................................3-1 3.1 3.2 3.3
Block Diagram ....................................................................................................3-1 Mechanical Design .............................................................................................3-1 System Operation...............................................................................................3-2 3.3.1 82439TX System Controller ..............................................................3-2 3.3.2 Processor ..........................................................................................3-2 3.3.3 L2 Cache ...........................................................................................3-2 3.3.4 ITP .....................................................................................................3-3 3.3.5 82371EB PCI to ISA/IDE Xcelerator (PIIX4E) ...................................3-3 3.3.6 DRAM................................................................................................3-3 3.3.7 Power ................................................................................................3-3 3.3.8 Boot ROM..........................................................................................3-3 3.3.9 RTC/NVRAM .....................................................................................3-3 3.3.10 Legacy I/O .........................................................................................3-3 3.3.11 IDE Support .......................................................................................3-4 3.3.12 Floppy Disk Support ..........................................................................3-4 3.3.13 Keyboard/Mouse ...............................................................................3-4 3.3.14 USB ...................................................................................................3-4
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3.3.15 3.3.16 3.3.17 3.3.18 3.3.19 3.3.20 3.3.21 3.3.22 3.3.23
4
Hardware Reference ..............................................................................................4-1 4.1 4.2 4.3 4.4 4.5 4.6 4.7
4.8
5
Processor Assembly ..........................................................................................4-1 In-Circuit BIOS Update.......................................................................................4-1 Post Code Debugger..........................................................................................4-2 ITP Debugger Port .............................................................................................4-2 ISA and PCI Expansion Slots.............................................................................4-2 PCI Device Mapping ..........................................................................................4-2 Connector Pinouts..............................................................................................4-3 4.7.1 ATX Power Connector.......................................................................4-3 4.7.2 ITP Debugger Connector ..................................................................4-4 4.7.3 Stacked USB .....................................................................................4-4 4.7.4 Mouse and Keyboard Connectors.....................................................4-4 4.7.5 Parallel Port.......................................................................................4-5 4.7.6 Serial Ports........................................................................................4-5 4.7.7 IDE Connector...................................................................................4-6 4.7.8 Floppy Drive Connector.....................................................................4-7 4.7.9 PCI Slot Connector............................................................................4-8 4.7.10 ISA Slot Connector............................................................................4-9 Jumpers ...........................................................................................................4-10 4.8.1 Clock Frequency Selection (J15) ....................................................4-10 4.8.2 Enable Spread Spectrum Clocking (J14) ........................................4-10 4.8.3 SMI# Source Control (J23)..............................................................4-10 4.8.4 CMOS RAM Clear (J24)..................................................................4-11 4.8.5 Flash BIOS VPP Select (J21)..........................................................4-11 4.8.6 Flash BIOS Boot Block Control (J22) ..............................................4-11 4.8.7 On/Off (J20).....................................................................................4-11 4.8.8 Push Button Switches .....................................................................4-11
BIOS Quick Reference ..........................................................................................5-1 5.1 5.2 5.3
5.4 5.5 5.6 5.7
iv
RS232 Ports ......................................................................................3-4 IEEE 1284 Parallel Port.....................................................................3-4 PCI Connectors .................................................................................3-4 ISA Connectors .................................................................................3-4 AGP Connector .................................................................................3-5 Post Code Debugger.........................................................................3-5 Clock Generation...............................................................................3-5 Interrupt Map .....................................................................................3-5 Memory Map .....................................................................................3-6
BIOS and Pre-Boot Features .............................................................................5-1 Power-On Self-Test (POST) ..............................................................................5-1 Setup Screen System ........................................................................................5-3 5.3.1 Basic CMOS Configuration Screen ...................................................5-3 5.3.2 Configuring Drive Assignments .........................................................5-4 5.3.2.1 Configuring Floppy Drive Types ..........................................5-4 5.3.3 Configuring IDE Drive Types.............................................................5-5 Configuring Boot Actions....................................................................................5-6 Custom Configuration Setup Screen..................................................................5-6 Shadow Configuration Setup Screen .................................................................5-7 Standard Diagnostics Routines Setup Screen ...................................................5-8
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5.8 5.9 5.10
5.11 5.12
Start System BIOS Debugger Setup Screen......................................................5-8 Start RS232 Manufacturing Link Setup Screen..................................................5-9 Manufacturing Mode...........................................................................................5-9 5.10.1 Console Redirection ..........................................................................5-9 5.10.2 CE-Ready Windows CE Loader ......................................................5-10 5.10.3 Integrated BIOS Debugger ..............................................................5-10 Embedded BIOS POST Codes ........................................................................5-12 Embedded BIOS Beep Codes..........................................................................5-15
A
PLD Code Listing ................................................................................................... A-1
B
Bill of Materials ....................................................................................................... B-1
C Index
Schematics ............................................................................................................... C-1 .................................................................................................................................Index-1
Figures 2-1 3-1 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9
Evaluation Platform Jumpers and Connectors ...................................................2-7 Evaluation Platform Block Diagram....................................................................3-1 BIOS POST Pre-Boot Environment....................................................................5-2 Embedded BIOS Setup Screen Menu................................................................5-3 Embedded BIOS Basic Setup Screen................................................................5-4 Embedded BIOS Custom Setup Screen ............................................................5-6 Embedded BIOS Shadow Setup Screen............................................................5-7 Standard Diagnostic Routines Setup Screen .....................................................5-8 Start RS232 Manufacturing Link Setup Screen..................................................5-9 CE-Ready Boot Feature ...................................................................................5-11 Integrated BIOS Debugger Running Over a Remote Terminal ........................5-12
1-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 5-1 B-1 B-2
Related Resources.............................................................................................1-4 Interrupts ............................................................................................................3-5 Memory Map ......................................................................................................3-6 PCI Device Mapping...........................................................................................4-2 Primary Power Connector (J11) .........................................................................4-3 ITP Connector Pin Assignment (J1 on the Processor Module) ..........................4-4 USB Connector Pinout (J2) ................................................................................4-4 Keyboard and Mouse Connector Pinouts (J1 on the Baseboard) ......................4-4 DB25 Parallel Port Connector Pinout (J3)..........................................................4-5 Serial Port Connector Pinout (J4).......................................................................4-5 PCI IDE1 (JP3) and IDE2 (JP4) Connector........................................................4-6 Diskette Drive Header Connector (JP1) .............................................................4-7 PCI Slots J7, J8, J9)...........................................................................................4-8 ISA Slots (J5, J6)................................................................................................4-9 Default Jumper Settings ...................................................................................4-10 IDE0-IDE3 Drive Assignments ...........................................................................5-5 Baseboard Bill of Materials................................................................................ B-1 Processor Assembly Bill of Materials ................................................................ B-4
Tables
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About This Manual
1
This manual tells you how to set up and use the Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform.
1.1
Content Overview Chapter 1, “About This Manual” - This chapter contains a description of conventions used in this manual. The last few sections tell you how to obtain literature and contact customer support. Chapter 2, “Getting Started” - Provides complete instructions on how to configure the board by setting jumpers, connecting peripherals, providing power, and configuring the BIOS. Chapter 3, “Theory Of Operation” - This chapter provides information on the system design. Chapter 4, “Hardware Reference” - This chapter provides a description of jumper settings and functions, and pinout information for each connector. Chapter 5, “BIOS Quick Reference” - This chapter describes how to configure the BIOS for your system configuration. A summary of all BIOS menu options is provided. Appendix A, “PLD Code Listing” - This appendix includes a sample code listing for the Post Code Debugger. Appendix B, “Bill of Materials” - This appendix contains the bill of materials for the development platform. Appendix C, “Schematics” - This appendix contains schematics for selected connectors and subsystems for the evaluation platform.
1.2
Text Conventions The following notations may be used throughout this manual. #
The pound symbol (#) appended to a signal name indicates that the signal is active low.
Variables
Variables are shown in italics. Variables must be replaced with correct values.
Instructions
Instruction mnemonics are shown in uppercase. When you are programming, instructions are not case-sensitive. You may use either upper- or lowercase.
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About This Manual
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits followed by the character H. A zero prefix is added to numbers that begin with A through F. (For example, FF is shown as 0FFH.) Decimal and binary numbers are represented by their customary notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is added for clarity.)
Units of Measure
The following abbreviations are used to represent units of measure: A Gbyte Kbyte KΩ mA Mbyte MHz ms mW ns pF W V µA µF µs µW
Signal Names
amps, amperes gigabytes kilobytes kilo-ohms milliamps, milliamperes megabytes megahertz milliseconds milliwatts nanoseconds picofarads watts volts microamps, microamperes microfarads microseconds microwatts
Signal names are shown in uppercase. When several signals share a common name, an individual signal is represented by the signal name followed by a number, while the group is represented by the signal name followed by a variable (n). For example, the lower chip-select signals are named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#. A pound symbol (#) appended to a signal name identifies an active-low signal. Port pins are represented by the port abbreviation, a period, and the pin number (e.g., P1.0).
1.3
Technical Support
1.3.1
Electronic Support Systems Intel’s site on the World Wide Web (http://www.intel.com/) provides up-to-date technical information and product support. This information is available 24 hours per day, 7 days per week, providing technical information whenever you need it.
1.3.1.1
Online Documents Product documentation is provided online in a variety of web-friendly formats at: http://developer.intel.com/design/litcentr/index.htm
1-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
About This Manual
1.3.1.2
Intel Product Forums Intel provides technical expertise through electronic messaging. With publicly accessible forums, you have all of the benefits of email technical support, with the added benefit of the option of viewing previous messages written by other participants, and providing suggestions and tips that can help others. Each of Intel’s technical support forums is based on a single product or product family. Questions and replies are limited to the topic of the particular forum. Intel also provides several non-technical support related forums. Complete information on Intel forums is available at: http://support.intel.com/newsgroups/index.htm
1.3.2
Telephone Technical Support In the U.S. and Canada, technical support representatives are available to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response by phone or by fax). Outside the U.S. and Canada, please contact your local distributor.
1.4
1-800-628-8686
U.S. and Canada
916-356-7599
U.S. and Canada
916-356-6100 (fax)
U.S. and Canada
Product Literature You can order product literature from the following Intel literature centers. 1-800-548-4725
U.S. and Canada
708-296-9333
U.S. (from overseas)
44(0)1793-431155
Europe (U.K.)
44(0)1793-421333
Germany
44(0)1793-421777
France
81(0)120-47-88-32
Japan (fax only)
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About This Manual
1.5
Related Documents
Table 1-1. Related Resources Document Title
Low-Power Embedded Pentium® Processor with MMX™ Technology datasheet ®
Pentium Processor for Embedded Applications Specification Update ®
Embedded Pentium Processor Family Developer’s Manual
Order Number 273184 273183 273204
®
1-4
Embedded Pentium Processor with MMX™ Technology Flexible Motherboard Design Guidelines
273206
Voltage Guidelines for Pentium® Processors with MMX™ Technology
243186
Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture
243190
Intel Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference
243191
Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide
243192
Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet
290559
Intel 430TX PCIset (MTXC) Specification Update
290615
Intel®
273134
430TX PCIset System Controller (MTXC) Timing Specification
82371AB (PIIX4) and 82371EB (PIIX4E) PCI-TO-ISA/IDE Xcelerator datasheet
290562
Intel 82371EB (PIIX4E) Specification Update
290635
Intel 82371AB PCI ISA IDE Xcelerator (PIIX4) Timing Specification
273135
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Getting Started
2
This chapter identifies the evaluation platform kit’s key components, features and specifications, and tells you how to set up the board for operation.
2.1
Overview The evaluation platform consists of a baseboard and a processor assembly.
• The processor assembly contains a low-power Pentium® processor with MMX™ technology and the System Controller from the Intel® 430TX PCIset chipset.
• The baseboard contains the 82371EB PCI ISA IDE Xcelerator (PIIX4E) and other system board components and peripheral connectors. Warning:
2.1.1
The assembly is attached to the baseboard at the factory. Do not remove the processor assembly from the baseboard. Intel will not support the processor assembly or the baseboard if the assembly is removed by the customer for any reason.
Processor Assembly Features The processor assembly contains:
• • • • •
166 MHz or 266 MHz low-power Pentium processor with MMX technology 512 Kbyte L2 cache Intel 430TX PCIset: 82439TX System Controller (MTXC) with 66 MHz front side bus Core voltage regulator It is populated with an ITP connector to interface to an ITP debugger
See the Low-Power Embedded Pentium® Processor with MMX™ Technology datasheet for more information on the processor. See the Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet for more information on the system controller.
2.1.2
Baseboard Features The evaluation platform baseboard has these features:
• ATX form factor • Flash system BIOS ROM
• •
— General Software system BIOS — In-circuit BIOS upgradability 2 SDRAM DIMM connectors 32-Mbyte SDRAM DIMM included — 4 Mbyte x64, 3.3 V, 66 MHz with a CAS latency of 2
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Getting Started
• User-accessible on-board connectors include: — — — — — — —
•
2.2
Two serial RS-232 ports; COM1, COM2 One EPP/ECP parallel port PS/2 keyboard and PS/2 mouse (6-pin mini-DIN connectors) Two USB ports Two IDE bus connectors One floppy connector Three PCI expansion slots and two ISA expansion slots. There are no shared slots so all are usable. — One AGP connector (reserved for future use) — Standard ATX power supply connector Miscellaneous features include: — On board post-code debugger (Port 80) — Reset push button — Stand-off feet for table-top operation
Included Hardware • • • • • • •
2.3
Evaluation platform (baseboard and processor assembly combination) 3.2-Gbyte hard disk drive pre-loaded with the QNX Real Time Operating System* 32-Mbyte SDRAM DIMM Attached heat sink and fan PCI video graphics adapter using the CHIPS* 69000 HiQVideo* Accelerator Mounting hardware IDE cable for the hard disk drive
Software Key Features The software in the kit was chosen to facilitate development of real-time applications based on the components used in the evaluation platform. The software tools included in your kit are described in this section. Note:
2.3.1
Software in the kit is provided free by the vendor and is only licensed for evaluation purposes. Customers using the tools that work with Microsoft products must have licensed those products. Any targets created by those tools should also have appropriate licenses.
Annasoft Systems Annasoft Systems is extending support for the Microsoft Windows CE PC platform found in Windows CE 2.0 Embedded Toolkit for Visual C++ (ETK). With Windows CE PC, embedded developers can now develop Windows CE applications on an inexpensive and readily available PC
2-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Getting Started
platform. Annasoft takes Windows CE one step closer to your solution with the creation of CE Launcher. The CE Launcher allows you to boot Windows CE from any PC disk without the help of MS-DOS. Now any Pentium or 486 processor-based embedded PC platform can run Windows CE. Jump Start your Windows CE PC development with Annasoft’s CE Launcher. Features include:
• • • •
2.3.2
Launch Windows CE without the need for MS-DOS Small 11K footprint Any Pentium or 486 embedded PC can run Windows CE Boot Windows CE from any type of disk media
General Software, Inc. Embedded BIOS is a full-featured BIOS for x86-based handheld, embedded, and volume consumer electronics applications. This product offers a winning combination of superior OEM configurability and superior embedded features. Embedded BIOS leads the industry with all the on-target embedded features that OEMs making embedded, handheld, mobile, and consumer electronics demand:
• • • • • • • • • • • • • •
2.3.3
CE Ready*, the Windows CE* launcher Integrated BIOS-aware debugger Resident Flash Disk disk emulator ROM disk and RAM disk emulators Manufacturing Mode for in-field diagnosis and software upgrades Power management that can operate in an APM or stand-alone environment PCI resource management Matrix keyboard support LCD panel drivers Console redirection over RS232 ports Flexibility to boot from many disk servers OEM-configurable setup screen system Embedded DOS*-ROM (adaptation kit and license) Total compatibility with industry standards
QNX Software Systems, Ltd. QNX Real Time Operating System for Intel Architecture.
• • • • • •
Small memory footprint of the QNX operating system with microGUI QNX microGUI is a full featured graphical user interface (GUI) and windowing system Photon Application Builder QNX Development kit provides the basic utilities to build and program Intel Flash Watcom C/C++ Development Suite: is a full featured development suite Includes compiler, assembler and debugger with full support for the QNX microGUI function library
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Getting Started
• Makes development of the QNX executables fast, easy and optimized
2.3.4
RadiSys Corporation INtime* provides real-time control with industry standard Windows NT.
• Field-proven real-time technology to maximize the reliability of your products • Win32 API extensions provide real-time capabilities in a Windows NT environment • Robust, non-intrusive integration with Windows NT ensures continued future compatibility with Windows NT
• Fully featured, high-end real-time capabilities for even the most demanding applications • Fully integrated with Microsoft Visual Developer Studio C/C++, including real-time Wizard extensions
• Patented architecture provides protected real-time execution • Full memory protection for real-time kernel and real-time tasks • Ensures survival of real-time threads in the event of total Windows failure
2.3.5
VenturCom, Inc.
2.3.5.1
Real-Time Extension* (RTX) • • • • • • • • •
2.3.5.2
Deterministic response times Fixed-priority scheduling with 128 priorities IPC with semaphores, mail slots, and shared memory objects Real-time process and thread management Memory locking, mapping and management functions High-speed clocks and timers Perform direct I/O register reads and writes Manage hardware interrupts
Component Integrator* (CI) • • • • • • •
2-4
Delivers real-time response for Windows NT applications
Configuration management tools to efficiently build dedicated Windows NT systems Import custom applications and commercial-off-the-shelf components Build embedded Windows NT systems Utilize VenturCom’s embedded and real-time extensions Analyze RAM and persistent storage requirements Validate system completeness Preconfigure operating system and applications
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2.3.6
WindRiver Systems Tornado* Evaluation Kit 1.0.1; Tornado Development Environment
• • • • • • • •
2.4
A superior development and deployment platform for the embedded developer Makes all tools available regardless of target resources or connection strategy Runs on UNIX workstation or PCs using Microsoft Windows 95 or Windows NT Offers published APIs for easy customization and third-party tool integration Provides central “control panel” and productivity-enhancing GUI Supports industry standards including ANSI-C, POSIX, and Tcl Includes the proven, high-performance VxWorks* operating system Scalable across all real-time implementations
Before You Begin Before you set up and configure your evaluation board, you may want to gather some additional hardware and software. VGA Monitor
You can use any standard VGA or multi-resolution monitor. The setup instructions in this chapter assume that you are using a standard VGA monitor.
Power Supply
You must use an ATX-type PC power supply.
Keyboard
You need a keyboard with a PS/2 style connector or adapter.
Mouse
Optional. You can use a mouse with a PS/2 style connector or adapter.
Floppy or CD-ROM Drive
You can connect up to four IDE drives and a floppy drive to the evaluation platform. Two devices (master and slave) can be attached to each IDE connector. You will need to provide the cables for these drives. You may have all these storage devices attached to the board at the same time.
Video Adapter
You can use the Chips and Technologies video adapter supplied with your kit, or you can use a different adapter. The evaluation board supports both PCI and ISA video cards. It is up to you to install the correct drivers for video adapters other than the one provided. The AGP slot located on the board is reserved for future use.
Other Devices and Adapters
The evaluation platform behaves much like a standard desktop computer motherboard. Most PC compatible peripherals can be attached and configured to work with the evaluation board. For example, you may want to install a sound card or network adapter.
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Getting Started
2.5
Setting up the Evaluation Platform Once you have gathered the hardware described in the last section, follow the steps below to set up your evaluation platform. This manual assumes you are familiar with basic concepts involved with installing and configuring hardware for a personal computer system. Refer to Figure 2-1 for locations of connectors, jumpers, etc. 1. Make sure you are in a static-free environment before removing any components from their anti-static packaging. The evaluation board is susceptible to electro-static discharge damage; such damage may cause product failure or unpredictable operation. 2. Inspect the contents of your kit. Check for damage that may have occurred during shipment. Contact your sales representative if any items are missing or damaged.
Caution:
Connecting the wrong cable or reversing the cable can damage the evaluation board and may damage the device being connected. Since the board is not in a protective chassis, use caution when connecting cables to this product.
Figure 2-1. Evaluation Platform Jumpers and Connectors PCI Connectors
AGP Connector
Non-Standard PCI Connector
USB
Keyboard (Top) COM1 (Top)/ /Mouse COM2 Parallel Port
ISA Connectors
J2
LEDs
J3
J1 J12 J5
D1 D2
J4
J12 J6
J7
J8
J9
ATX Power Connector
J10
JP2
J14 J15
J13 J14 J15
JP1
J17
J11
J18
Floppy Connector ITP Debugger Port
J1
J20 J20
J21 J22
J21 J22
U12 U13 U11
Post Code Debugger
J23
JP2 JP2 IDE2
JP3 IDE1
J24
Battery
JP2
J24
J23
IDE Connectors
SDRAM DIMM Slots
Special Mounting Holes
3. Make sure the board’s jumpers are set to the following default locations.
• • • • • • • 2-6
J14 - Not installed J15 - Installed J20 - Jumper pins 2-3 J21 - Jumper pins 2-3 J22 - Jumper pins 2-3 J23 - Jumper pins 2-3 J24 - Jumper pins 1-2
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Getting Started
4. Mount the hardware: •
Table-top operation: The evaluation platform is shipped with standoff “feet” for use in a table-top environment. These feet are installed on the evaluation platform to raise it off the table surface.Your kit contains two bags of mounting hardware. One bag contains eight standoff feet, eight mounting screws, and eight washers. Another bag has three shorter feet that must be attached slightly differently. — To mount the eight standard feet, insert a washer onto a screw, then push the screw through the top of the board. From below the board, thread one of the longer feet onto the screw. — To mount the three special feet, screw the three shorter feet onto the existing screws. See Figure 2-1 for the location of the three special holes.
Warning:
Do not remove the nuts from these three holes! This will detach the processor assembly from the baseboard, and Intel will no longer support the evaluation platform. •
The evaluation platform can also be mounted in a standard ATX-style chassis.
5. Connect desired storage devices to the evaluation platform: The evaluation platform supports Primary and Secondary IDE interfaces that can each host one or two devices (master/slave). When you are using multiple devices, such as a hard disk and a CD-ROM drive, make sure the hard disk drive has a jumper in the master position and the CD-ROM has a jumper in the slave position. When you are using a single IDE device with the evaluation board, be sure that the jumpers set correctly for single master operation. For jumper settings for other configurations, consult the drive’s documentation. Note:
The evaluation platform BIOS only supports hard drives of 16 Gbytes or less. •
Installing the IDE hard disk drive included in your kit: — Connect the hard drive’s IDE connector to the JP4 connector on the evaluation board. Be sure to align Pin 1 of the cable connector with pin 1 of JP4. — Connect the other end to the hard disk drive.
Caution:
Make sure the tracer on the ribbon cable is aligned with pin 1 on both the hard disk and the IDE connector header. Connecting the cable backwards can damage the evaluation platform or the hard disk. — Connect the hard drive to the power supply.
Note:
The hard disk is already formatted and is pre-loaded with the QNX Real-Time Operating System for Intel Architecture. — You may have to make changes to the system BIOS to enable this hard disk. See Chapter 5, “BIOS Quick Reference” for more information. •
Floppy drive: A floppy disk drive connected to the evaluation board is the most direct method for loading software. — Insert floppy cable into JP1 (be sure to orient Pin 1 correctly). — Connect the other end of the ribbon cable to the floppy drive. — Connect a power cable to the floppy drive. — You must make changes to the system BIOS to enable this floppy disk. See Chapter 5, “BIOS Quick Reference” for more information.
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Getting Started
6. Make sure the SDRAM DIMM is installed in the socket labeled J18. 7. Connect a PS/2 mouse and keyboard (see Figure 2-1 for connector locations). Note:
J1 (on the baseboard) is a stacked PS/2 connector. The bottom connector is for the mouse and the top is for the keyboard. 8. Make sure the fan’s power connector is plugged into Jumper J12. 9. Install the Chips and Technologies PCI video adapter into one of the available PCI slots. Connect the monitor cable to the VGA port on the card. 10. Connect the power supply: You’ll need a standard ATX PC power supply. Make sure the power supply is unplugged (or turned off), then connect the power supply cable to the power header (J11).
Note:
Some ATX power supplies do not have an on/off switch. In this case remove jumper J20 before plugging in the ATX power connector. J20 controls an internal power supply on/off switch. When you are ready to apply power, insert the jumper on pins 2-3. You may want to wire this header up to a toggle switch for convenience. When the power is on you should see two power-indicator LEDs light up (located next to the ATX power connector in the upper right corner of the board, see Figure 2-1). Check to see that the fan on the processor is operating. Follow the instructions in the next section for entering the BIOS setup screens and configuring the BIOS according to your needs (hard drive parameters, floppy drive, operating system, etc.).
2.6
Configuring the BIOS General Software’s BIOS software is pre-loaded on the evaluation platform. You will have to make changes to the BIOS to enable hard disks, floppy disks and other supported features You can use the Setup program to modify BIOS settings and control the special features of the system. Setup options are configured through a menu-driven user interface. Chapter 5, “BIOS Quick Reference” contains a description of BIOS options. BIOS updates may periodically be posted to Intel’s Developers’ web site at http://developer.intel.com/.
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Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
3
Theory Of Operation 3.1
Block Diagram
Figure 3-1. Evaluation Platform Block Diagram
Processor Assembly L2 Cache
Tag
Front Side Bus
72-Bit DIMM
Voltage Regulator
Low-Power Pentium® Processor with MMX™ Technology
72-Bit DIMM
ITP
82439TX System Controller
DRAM Bus Clock Generator PCI Bus
PCI Connectors Non-Standard PCI Connector
USB
PIIX4E
I/O APIC
Boot Flash
ISA Bus ISA Connectors
PS/2 Mouse PS/2 Keyboard
IEEE 1284 Parallel Port SMCFDC37B8x SuperI/O*
Floppy Drive
3.2
Bus Master IDE
COM1 COM2
Mechanical Design The evaluation board conforms to the ATX form factor. For extra protection in a development environment users may want to install the evaluation board in an ATX chassis. The evaluation board has two ISA connectors, four PCI connectors and two DRAM DIMM connectors across the back. The I/O connectors are in the rear of the board in the defined ATX I/O window.
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
3-1
Theory Of Operation
3.3
System Operation The low-power Pentium® processor with MMX™ technology evaluation platform is a fullfeatured ATX form-factor system board and processor assembly that includes a 166 MHz or 266 MHz low-power Pentium processor with MMX technology. The evaluation platform also features 512 Kbytes of L2 cache, the Intel 82439 TX (MTXC) system controller, the Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E), and other system and I/O peripherals.
3.3.1
82439TX System Controller The 82439TX System Controller (MTXC) provides a completely integrated solution for the system controller and data path components in a Pentium processor system. The MTXC has a 64-bit host and DRAM bus interface, a 32-bit PCI bus interface, a second level cache interface and it integrates the PCI arbiter. The MTXC interfaces with the Pentium processor host bus, a dedicated memory data bus, and the PCI bus. The MTXC bus interfaces are designed to interface with 2.5 V, 3.3 V and 5 V busses. The MTXC implements 2.5 V and 3.3 V drivers and 5 V tolerant receivers. The MTXC connects directly to the Pentium processor 3.3 V or 2.5 V host bus, directly to 5 V or 3.3 V DRAMs, and directly to the 5 V or 3.3 V PCI bus. The 430TX also interfaces directly to the 3.3 V or 5.0 V TAG RAM and 3.3 V Cache.
3.3.2
Processor The low-power embedded Pentium processors with MMX technology for high performance embedded applications (166 and 266 MHz) are fully compatible with the existing Pentium processors with MMX technology (200 and 233 MHz) with the following differences: voltage supplies, power consumption, and performance. The low-power embedded Pentium processor with MMX technology has several features which allow for high-performance embedded designs. These features include the following:
• 1.8 V core (HL-PBGA – 166), 2.0 V core (HL-PBGA – 266) • 2.5 V I/O buffer VCC3 inputs to reduce power consumption • SL Enhanced feature set The processor used on the evaluation platform is a low-power embedded Pentium processor with MMX technology in a 352-ball High-Thermal Low-Profile–Plastic Ball Grid Array (HL-PBGA) package. The HL-PBGA package allows designers to use surface mount technology to create small form-factor designs.
3.3.3
L2 Cache The second level cache is direct mapped and supports a 512-Kbyte SRAM configuration using pipeline burst SRAM or DRAM cache SRAM. The cache line read/write performance is 3-1-1-1 and the performance for back-to-back reads that are pipelined is 3-1-1-1-1-1-1-1.
3-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Theory Of Operation
3.3.4
ITP The evaluation platform is populated with a 2.5 V ITP debugger port. The ITP port provides a path for debugger tools like emulators, in-target probes, and logic analyzers to gain access to the Pentium processor’s registers and signals without affecting high speed operation. This allows the system to operate at full speed with the debugger attached.
3.3.5
82371EB PCI to ISA/IDE Xcelerator (PIIX4E) The 82371EB is the PCI south bridge. The 82371EB connects to the PCI bus and requests control of the PCI bus via the PHOLD# signal and becomes the PCI master upon receipt of the PHOLDA# signal from the processor assembly. The PIIX4E contains the PCI and ISA interrupt controller, along with legacy functions such as a DMA controller, a bus master IDE interface, an ISA bus interface, and a boot ROM interface. A USB hub controller is also included.
3.3.6
DRAM The evaluation platform provides two 168-pin DIMM module connectors. The DRAM interface is a 64-bit data path that supports Synchronous DRAM (SDRAM). The DRAM interface supports 4 Mbytes to 256 Mbytes of 4-Mbit, 16-Mbit and 64-Mbit DRAM and SRAM technology (both symmetrical and asymmetrical). Parity is not supported. One 32-Mbyte SDRAM DIMM is included in the kit.
3.3.7
Power The evaluation board uses an industry standard ATX-style power supply with a 20-pin connector. A 230-watt (minimum) supply is recommended. Note that the ATX power connector is keyed to prevent incorrect insertion. See “ATX Power Connector” on page 4-3 for a detailed description of the power connector. Make sure that the ATX power supply is not plugged into the wall when connecting or disconnecting it from the evaluation board.
3.3.8
Boot ROM The system boot ROM installed at U11 is a 2-Mbit 28F002BC flash device. The system is set up for in-circuit reprogramming of the BIOS, but the flash device is also socketed. This device is addressable on the XD bus extension of the ISA bus.
3.3.9
RTC/NVRAM The RTC and NVRAM are contained within the 82371EB PIIX4E device. CMOS NVRAM backup is provided by a 3-V lithium-ion battery.
3.3.10
Legacy I/O Support for legacy I/O functions is provided by the Intel 82371EB PIIX4E and the SMC FDC37B8X SuperI/O* device.
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3-3
Theory Of Operation
3.3.11
IDE Support The evaluation board supports both a primary and secondary IDE interface via two 40-pin IDE connectors. The connector labeled IDE1 is the primary interface. IDE2 is the secondary interface.
3.3.12
Floppy Disk Support Floppy disk support is provided by the SMC FDC37B8X SuperI/O device. One 34-pin floppy connector is provided on the evaluation board.
3.3.13
Keyboard/Mouse Keyboard and mouse support are provided by the SMC FDC37B8X SuperI/O device. The keyboard and mouse connectors (J1) are PS/2 style, 6-pin stacked miniature DIN connectors. The top connector is for the keyboard and the bottom connector is for the mouse.
3.3.14
USB USB support is provided through the PIIX4E and can be used through connectors J2.
3.3.15
RS232 Ports Two serial I/O ports provided by the SMC FDC37B78X SuperI/O device. Two 9-pin RS232 connectors are provided on a single stacked connector (J4).
3.3.16
IEEE 1284 Parallel Port One 25-pin IEEE 1284 parallel port connector controlled by the SMC FDC37B78X SuperI/O device is provided (J3).
3.3.17
PCI Connectors Three industry standard 32-bit, 5-V PCI connectors are provided on the evaluation platform. The connectors are designed to handle either a 5-V only card or a universal card. 3.3-V cards are not supported. There is a fourth connector, J10, which is a custom PCI expansion connector. This connector is reserved for future devices that may be included with the kit at a later date. This connector is not compliant with any PCI industry standard and is not supported outside the scope of this evaluation board.
3.3.18
ISA Connectors Two 16-bit ISA connectors are provided on the evaluation board.
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Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Theory Of Operation
3.3.19
AGP Connector Connector J13 is reserved for AGP graphics cards. These cards are not supported with this version of the evaluation boards, since the Pentium processor and 82439TX Host System controller combination does not support AGP.
3.3.20
Post Code Debugger The evaluation board has an on-board Post Code Debugger. Data from any program that does an I/O write to 0080H is latched and displayed on the two LEDs (U12 and U13). During BIOS startup, codes are posted to these LEDs to indicate what the BIOS is doing. Application programs can post their own data to these LEDs by writing to I/O address 0080H.
3.3.21
Clock Generation There are three devices on the baseboard which generate and distribute the clocks used by the entire system. These are the CY2280 clock synthesizer, CY2318NZ clock buffer and the CY23009 zero delay buffer. Not all of these devices are used on this version of the evaluation platform. The CY2280 generates the clocks for the processor, System Controller, cache, PCI, USB and ISA bus. The processor clock runs at 66 MHz. The PCI clocks run at 33 MHz. This device is capable of spread spectrum clocking. If spread spectrum clocking is enabled, a 0.5% down spread will be introduced in the processor and PCI clocks. The CY2309 Zero Delay Buffer is used to buffer the clock signals sent to the SDRAM DIMMS. The SDRAM interface operates at 66 MHz. The CY2318NZ clock buffer is not used by the evaluation platform.
3.3.22
Interrupt Map
Table 3-1. Interrupts IRQ NMI
System Resources I/O Channel Check
0
Reserved, Interval Timer
1
Reserved, Keyboard buffer full
2
Reserved, Cascade interrupt from slave PIC
3
Serial Port 2
4
Serial Port 1
5
Parallel Port (PNP0 option)
6
Floppy
7
Parallel Port 1
8
Real Time Clock
9
IRQ2 Redirect
10
Reserved. Not supported.
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Theory Of Operation
Table 3-1. Interrupts IRQ
3.3.23
System Resources
11
Reserved. Not supported.
12
Onboard Mouse Port if present, else user available
13
Reserved, Math coprocessor
14
Primary IDE if present, else user available
15
Reserved. Not supported.
Memory Map
Table 3-2. Memory Map Address Range (Hex)
Size
100000-8000000
127.25M
E0000-FFFFF
128K
Extended Memory BIOS
C8000-DFFFF
Available expansion BIOS area (Flash disk memory window)
A0000-C7FFF
Off-board video memory and BIOS
9FC00-9FFFF
3-6
Description
1K
Extended BIOS Data (movable by QEMM, 386MAX)
80000-9FBFF
127K
Extended conventional
00000-7FFFF
512K
Conventional
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Hardware Reference
4
This section provides reference information on the system design. Included in this section is connector pinout information, jumper settings, and other system design information.
• • • • • • • •
4.1
Processor Assembly In-Circuit BIOS Update Post Code Debugger ITP Debugger Port ISA and PCI Expansion Slots PCI Device Mapping Connector Pinouts Jumpers
Processor Assembly The processor assembly contains all of the host bus devices such as the low power Pentium processor with MMX technology, the 82439TX System Controller (MTXC), L2 cache, and tag RAM. The processor assembly also includes a voltage regulator and an ITP debugger connector. The assembly connects to the baseboard via a 400-pin connector.
Warning:
4.2
The assembly is attached to the baseboard at the factory. Do not remove the processor assembly from the baseboard. Intel will not support the processor assembly or the baseboard if the assembly is removed by the customer for any reason.
In-Circuit BIOS Update The BIOS can be upgraded in-circuit. BIOS updates may periodically be posted to Intel’s Developers’ site at http://www.intel.com/design/. To reprogram the BIOS: 1. Download the new BIOS upgrade file from Intel’s Developers’ web site. 2. Extract the BIOS upgrade zip file onto a bootable floppy. 3. Insert the floppy disk into the floppy drive attached to the evaluation board. 4. Reboot the evaluation board so that it reboots from the floppy. 5. Follow the on-screen instructions.
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4-1
Hardware Reference
4.3
Post Code Debugger The evaluation board has an on-board Post Code Debugger. Data from any code that does an I/O write to 80H is latched on the two led displays (U12/U13). During BIOS startup, code is posted to these LEDs to indicate what the BIOS is doing. Application code can post its own data to these LEDs by doing an I/O write to address 80H. The 22V10 PLD code used to implement this function is included in Appendix A, “PLD Code Listing.”
4.4
ITP Debugger Port The evaluation platform is populated with a 2.5 V ITP debugger port. The ITP port provides a path for debugger tools like emulators, in-target probes, and logic analyzers to gain access to the Pentium processor’s registers and signals without affecting high speed operation. This allows the system to operate at full speed with the debugger attached.
4.5
ISA and PCI Expansion Slots The evaluation platform has three PCI expansion slots and two ISA slots.
4.6
PCI Device Mapping On the evaluation platform the PCI devices are mapped to PCI device numbers by connecting an address line to the IDSEL signal of each PCI device. Table 4-1 shows the mapping of PCI devices.
Table 4-1. PCI Device Mapping Device
4-2
Address Line
PCI Device Number
PIIX4E
AD18
7
PCI Slot 0 (J7)
AD28
17
PCI Slot 1 (J8)
AD29
18
PCI Slot 2 (J9)
AD30
19
PCI Connector 3 (J10)
AD31
20
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Hardware Reference
4.7
Connector Pinouts
4.7.1
ATX Power Connector Table 4-2 shows the signals assigned to the ATX style power connector.
Table 4-2. Primary Power Connector (J11) Pin
Name
Function
1
3.3 V
3.3 V
2
3.3 V
3.3 V
3
GND
Ground
4
+5V
+5 V VCC
5
GND
Ground
6
+5V
+5 V VCC
7
GND
Ground
8
PWRGD
Power Good
9
5VSB
Standby 5 V
10
+12 V
+12 V
11
3.3 V
3.3 V
12
–12 V
–12 V
13
GND
Ground
14
PS_ON#
15
GND
Ground
16
GND
Ground
17
GND
Ground
18
–5 V
–5 Volts
19
+5 V
+5 V VCC
20
+5 V
+5 V VCC
Soft-off control
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Hardware Reference
4.7.2
ITP Debugger Connector
Table 4-3. ITP Connector Pin Assignment (J1 on the Processor Module)
4.7.3
Pin
Signal
Pin
Signal
1
INIT
11
PRDY
2
DBRESET
12
TDI
3
RESET
13
TDO
4
GND
14
TMS
5
N/C
15
GND
6
3.3V
16
TCLK
7
R/S#
17
GND
8
GND
18
TRST#
9
N/C
19
N/C
10
GND
20
N/C
Stacked USB P0 is the bottom connector. P1 is on top.
Table 4-4. USB Connector Pinout (J2) Pin
4.7.4
P0 Signals
P1 Signals
1
VCC0
VCC1
2
D0-
D1-
3
D0+
D1+
4
GND0
GND1
Mouse and Keyboard Connectors The keyboard port is on top. The mouse port is on the bottom.
Table 4-5. Keyboard and Mouse Connector Pinouts (J1 on the Baseboard) Pin
4-4
Signal Name
1
Data
2
No Connect
3
Ground
4
+5 V (fused)
5
Clock
6
No Connect
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Hardware Reference
4.7.5
Parallel Port
Table 4-6. DB25 Parallel Port Connector Pinout (J3) Signal Name
Pin
4.7.6
Signal Name
Pin
1
Strobe#
14
Auto Feed#
2
Data Bit 0
15
Fault#
3
Data Bit 1
16
INIT#
4
Data Bit 2
17
SLCT IN#
5
Data Bit 3
18
Ground
6
Data Bit 4
19
Ground
7
Data Bit 5
20
Ground
8
Data Bit 6
21
Ground
9
Data Bit 7
22
Ground
10
ACK#
23
Ground
11
Busy
24
Ground
12
Paper end
25
Ground
13
SLCT
Serial Ports COM1 is the top connector. COM2 is the bottom connector.
Table 4-7. Serial Port Connector Pinout (J4) Pin
Signal Name
1
DCD
2
Serial In (SIN)
3
Serial Out (SOUT)
4
DTR
5
GND
6
DSR
7
RTS
8
CTS
9
RI
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
4-5
Hardware Reference
4.7.7
IDE Connector
Table 4-8. PCI IDE1 (JP3) and IDE2 (JP4) Connector Pin
4-6
Signal Name
Pin
Signal Name
1
Reset IDE
2
Ground
3
Host Data 7
4
Host Data 8
5
Host Data 6
6
Host Data 9
7
Host Data 5
8
Host Data 10
9
Host Data 4
10
Host Data 11
11
Host Data 3
12
Host Data 12
13
Host Data 2
14
Host Data 13
15
Host Data 1
16
Host Data 14
17
Host Data 0
18
Host Data 15
19
Ground
20
Key
21
DRQ3
22
Ground
23
I/O Write#
24
Ground
25
I/O Read#
26
Ground
27
IOCHRDY
28
BALE
29
DACK3#
30
Ground
31
IRQ14
32
IOCS16#
33
Addr 1
34
Ground
35
Addr 0
36
Addr 2
37
Chip Select 0#
38
Chip Select 1#
39
Activity
40
Ground
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Hardware Reference
4.7.8
Floppy Drive Connector
Table 4-9. Diskette Drive Header Connector (JP1) Pin
Signal Name
Pin
Signal Name
1
Ground
2
FDHDIN
3
Ground
4
Reserved
5
Key
6
FDEDIN
7
Ground
8
Index
9
Ground
10
Motor Enable A#
11
Ground
12
Drive Select B#
13
Ground
14
Drive Select A#
15
Ground
16
Motor Enable B#
17
Ground
18
DIR#
19
Ground
20
STEP#
21
Ground
22
Write Data#
23
Ground
24
Write Gate#
25
Ground
26
Track 00#
27
Ground
28
Write Protect#
29
Ground
30
Read Data#
31
Ground
32
Side 1 Select#
33
Ground
34
Diskette Change#
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
4-7
Hardware Reference
4.7.9
PCI Slot Connector
Table 4-10. PCI Slots J7, J8, J9) Pin
4-8
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
VCC
B1
- 12V
A32
AD16
B32
AD17
A2
+ 12V
B2
GND
A33
3.3V
B33
CBE2#
A3
VCC
B3
GND
A34
FRAME#
B34
GND
A4
VCC
B4
No Connect
A35
GND
B35
IRDY#
A5
VCC
B5
VCC
A36
TRDY#
B36
3.3 V
A6
PIRQ1#
B6
VCC
A37
GND
B37
DEVSEL#
A7
PIRQ3#
B7
PIRQ2#
A38
STOP#
B38
GND
A8
VCC
B8
PIRQ0
A39
3.3 V
B39
LOCK#
A9
No Connect
B9
PRSNT1B#
A40
SDONE
B40
PERR#
A10
VCC
B10
No Connect
A41
SBO#
B41
3.3 V
A11
No Connect
B11
PRSNT2B#
A42
GND
B42
SERR#
A12
GND
B12
GND
A43
PAR
B43
3.3V
A13
GND
B13
GND
A44
AD15
B44
CBE1#
A14
No Connect
B14
No Connect
A45
3.3V
B45
AD14
A15
RST#
B15
GND
A46
AD13
B46
GND
A16
VCC
B16
PCLK3
A47
AD11
B47
AD12
A17
GNT1#
B17
GND
A48
GND
B48
AD10
A18
GND
B18
REQ#
A49
AD9
B49
GND
A19
Reserved
B19
VCC
A50
KEY
B50
KEY
A20
AD30
B20
AD31
A51
KEY
B51
KEY
A21
3.3V
B21
AD29
A52
CBEO#
B52
AD8
A22
AD28
B22
GND
A53
3.3 V
B53
AD7
A23
AD26
B23
AD27
A54
AD6
B54
3.3 V
A24
GND
B24
AD25
A55
AD4
B55
AD5
A25
AD24
B25
3.3 V
A56
GND
B56
AD3
A26
IDSEL
B26
CBE3#
A57
AD2
B57
GND
A27
3.3V
B27
AD23
A58
AD0
B58
AD1
A28
AD22
B28
GND
A59
VCC
B59
VCC
A29
AD20
B29
AD21
A60
REQ64#
B60
ACK64#
A30
GND
B30
AD19
A61
VCC
B61
VCC
A31
AD18
B31
3.3 V
A62
VCC
B62
VCC
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Hardware Reference
4.7.10
ISA Slot Connector
Table 4-11. ISA Slots (J5, J6) Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
A1
IOCHK#
B1
GND
A26
SA5
B26
DACK2#
A2
SD7
B2
RSTSLOT
A27
SA4
B27
TC
A3
SD6
B3
VCC
A28
SA3
B28
BALE
A4
SD5
B4
IRQB9
A29
SA2
B29
VCC
A5
SD4
B5
–5V
A30
SA1
B30
OSC
A6
SD3
B6
DREQ2
A31
SA0
B31
GND
A7
SD2
B7
–12V
C1
SBHE#
D1
MEMCS16#
A8
SD1
B8
ZEROWS#
C2
LA23
D2
IOCS16#
A9
SD0
B9
+12V
C3
LA22
D3
IRQB10
A10
IOCHRDY
B10
GND
C4
LA21
D4
IRQB11
A11
AEN
B11
SMEMW#
C5
LA20
D5
IRQB11
A12
SA19
B12
SMEMR#
C6
LA19
D6
IRQ15
A13
SA18
B13
IOW#
C7
LA18
D7
IRQ14
A14
SA17
B14
IOR#
C8
LA17
D8
DACK0
A15
SA16
B15
DACK3#
C9
MEMR#
D9
DREQ0
A16
SA15
B16
DREQ3
C10
MEMW#
D10
DACK5
A17
SA14
B17
DACK1#
C11
SD8
D11
DREQ5
A18
SA13
B18
DREQ1
C12
SD9
D12
DACK6#
A19
SA12
B19
REFRESH#
C13
SD10
D13
DREQ6
A20
SA11
B20
SYSCLK
C14
SD11
D14
DACK7#
A21
SA10
B21
IRQA7
C15
SD12
D15
DREQ7#
A22
SA9
B22
IRQA6
C16
SD13
D16
VCC
A23
SA8
B23
IRQA5
C17
SD14
D17
MASTER#
A24
SA7
B24
IRQA4
C18
SD15
D18
GND
A25
SA6
B25
IRQA3
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
4-9
Hardware Reference
4.8
Jumpers Table 4-12 shows default Jumper settings.
Table 4-12. Default Jumper Settings Jumper
Function
J14
Enable Spread Spectrum Clocking
J15
Clock Frequency Selection
J20
On/Off
Settings In – Enable Spread Spectrum Out – Disable Spread Spectrum (Default) In – 66 MHz Processor Clock (Default) Out – Reserved 1-2 Reserved 2-3 On (Default) No Jumper Installed – Off
4.8.1
J21
Flash BIOS VPP Select
J22
Flash BIOS boot block control
J23
SMI# Source
J24
CMOS RAM Clear
1-2 12 V 2-3 5 V (Default) 1-2 12 V 2 –3 5 V (Default) 1-2 SMI# controlled by IOAPIC 2-3 SMI# controlled by PIIX4E (Default) 1-2 Normal Operation (Default) 2-3 Clear CMOS RAM
Clock Frequency Selection (J15) This jumper controls the frequency of the processor clock. When the jumper is in 66 MHz operation is supported. This is the only setting supported by this evaluation kit.
Caution:
4.8.2
Leave this jumper installed. When the jumper is out, 100 MHz processor clocks will be generated. This position is not supported and may cause damage to the processor.
Enable Spread Spectrum Clocking (J14) This jumper is used to enable or disable spread spectrum clocking on the clock synthesizer. When this jumper is in, a 0.5% down spread will be introduced into the PCI and CPU clocks. The default setting is no jumper installed, which disables spread spectrum clocking.
4.8.3
SMI# Source Control (J23) This jumper selects the source of the SMI# interrupt to the processor. Only the 2-3 position which selects the PIIX4E is supported. The 1-2 position is reserved for future use.
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4.8.4
CMOS RAM Clear (J24) This jumper controls power to the battery backed-up CMOS RAM. This RAM is used to store information about the system configuration that is required by the BIOS. The 1-2 position is for normal operation. The 2-3 position allows for the RAM to be cleared. To clear the RAM perform the following steps: 1. Remove power from the evaluation platform by removing jumper J20 2. Move J24 to the 2-3 position for a few seconds. 3. Install J24 in the 1-2 position. 4. Reboot the system and enter the BIOS setup screen to configure the system.
4.8.5
Flash BIOS VPP Select (J21) This jumper controls the voltage presented to the flash BIOS VPP pin. The 2-3 position supplies 5 V and is the default for normal operation. This position inhibits programming or erasing the flash BIOS. The 1-2 position supplies 12 V and should only be used if directed to do so by a utility that is used to reprogram the BIOS.
4.8.6
Flash BIOS Boot Block Control (J22) This jumper controls the Boot Block protection of the Flash BIOS. When this jumper is in the 2-3 position, the boot block is locked and cannot be programmed. This is the default position of this jumper. The 1-2 position unlocks the boot block so that it can be erased and reprogrammed. This position should only be used under the direction of a utility that is designed to reprogram the boot block of the flash device.
4.8.7
On/Off (J20) This jumper is used to control the state of the ATX power supply. When this jumper is removed, the power supply will be turned off. Placing the jumper in the 2-3 position will turn the power supply on. The 1-2 position is reserved and should not be used.
4.8.8
Push Button Switches There are two push button switches on the evaluation board labeled S1 and S2. S1 is non-functional and reserved for future use. S2 is the reset button. Pressing S2 will force a complete hardware reset of the system.
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5
The Low-Power Pentium® processor with MMX™ Technology Evaluation Platform is licensed with a single copy of Embedded BIOS and Embedded DOS software from General Software, Inc.1 This software is provided for demonstration purposes only and must be licensed directly from General Software, Inc. for integration with new designs. General Software may be reached at (800) 850-5755, on the web at http://www.gensw.com, or via email at
[email protected].
5.1
BIOS and Pre-Boot Features The system’s pre-boot environment is managed with an adaptation of Embedded BIOS from General Software. The pre-boot environment includes POST, Setup Screen System, Manufacturing Mode, Console Redirection, Windows CE Loader (CE Ready), and Integrated BIOS Debugger. A REFLASH tool is also available to update the BIOS image with new builds of Embedded BIOS that may be obtained from General Software. Before using the system, please read the following to properly configure CMOS settings, and learn how to use the embedded features of the pre-boot firmware, Embedded BIOS. The last two sections of this chapter provide the BIOS POST Codes and Beep codes.
5.2
Power-On Self-Test (POST) When the system is powered on, Embedded BIOS tests and initializes the hardware and programs the chipset and other peripheral components. During this time, POST progress codes are written by the system BIOS to I/O port 80H, allowing the user to monitor the progress with a special monitor. “Embedded BIOS POST Codes” on page 5-12 lists the POST codes and their meanings. During early POST, no video is available to display error messages should a critical error be encountered; therefore, POST uses beeps on the speaker to indicate the failure of a critical system component during this time. Consult “Embedded BIOS Beep Codes” on page 5-15 for a list of Beep codes used by the system’s BIOS. POST displays its progress on the system video device, which may be the video screen if a VGA card is used, or on a terminal emulation program’s screen if output is redirected over a serial port.
1.
General Software™, the GS Logo, Embedded BIOS™, BIOStart™, CE-Ready™, and Embedded DOS™ are trademarks or registered trademarks of General Software, Inc.
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Figure 5-1. BIOS POST Pre-Boot Environment
When the system is powered on for the first time, you’ll need to configure the system through the Setup Screen System (described later) before peripherals, such as disk drives, are recognized by the BIOS. The information is written to battery-backed CMOS RAM on the board’s Real Time Clock. Should the board’s battery fail, this information will be lost and the board will need to be reconfigured. OEMs can modify the look-and-feel of POST with the Embedded BIOS adaptation kit. While the demonstration BIOS looks and feels like a desktop PC, it is possible to eliminate messages, sounds, delays, to make the POST effectively invisible.
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5.3
Setup Screen System The system is configured from within the Setup Screen System, which is a series of menus that can be invoked from POST by pressing the
key if the main keyboard is being used, or by pressing ^C if the console is being redirected to a terminal program.
Figure 5-2. Embedded BIOS Setup Screen Menu
Once in the Setup Screen System (Figure 5-2), the user can navigate with the UP and DOWN arrow keys from the main console, or use the ^E and ^X keys from the remote terminal program to accomplish the same thing. TAB and ENTER are used to advance to the next field, and ‘+’ and ‘-’ keys cycle through values, such as those in the Basic Setup Screen, or the Diagnostics Setup Screen.
5.3.1
Basic CMOS Configuration Screen The system’s drive types, boot activities, and POST optimizations are configured from the Basic Setup Screen (Figure 5-3). In order to use disk drives with your system, you must select appropriate assignments of drive types in the left-hand column. Then, if you are using true floppy and IDE drives (not memory disks that emulate these drives), you need to configure the drive types themselves in the Floppy Drive Types and IDE Drive Geometry sections. Finally, you’ll need to configure the boot sequence in the middle of the screen. Once these selections have been made, your system is ready to use.
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Figure 5-3. Embedded BIOS Basic Setup Screen
5.3.2
Configuring Drive Assignments Embedded BIOS allows the user to map a different file system to each drive letter. The BIOS allows file systems for each floppy (Floppy0 and Floppy1), each IDE drive (Ide0, Ide1, Ide2, and Ide3), and memory disks when configured (Flash0, ROM0, RAM0, etc.) Figure 5-3 shows how the first floppy drive (Floppy0) is assigned to drive A: in the system, and then how the first IDE drive (Ide0) is assigned to drive C: in the system. To switch two floppy disks around or two hard disks around, just map Floppy0 to B: and Floppy1 to A:, and for hard disks map Ide0 to D: and Ide1 to C:.
Caution:
Take care to not skip drive A: when making floppy disk assignments, as well as drive C: when making hard disk assignments. The first floppy should be A:, and the first hard drive should be C:. Also, do not assign the same file system to more than one drive letter. Thus, Floppy0 should not be used for both A: and B:. The BIOS permits this to allow embedded devices to alias drives, but desktop operating systems may not be able to maintain cache coherency with such a mapping in place. A special field in this section entitled “Boot Method: (Windows CE/Boot Sector)” is used to configure the CE Ready feature of the BIOS. For normal booting (DOS, Windows NT, etc.), select “Boot Sector” or “Unused”.
5.3.2.1
Configuring Floppy Drive Types If true floppy drive file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the floppy drives themselves must be configured in this section. Floppy0 refers to the first floppy disk drive on the drive ribbon cable (normally drive A:), and Floppy1 refers to the second drive (drive B:).
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5.3.3
Configuring IDE Drive Types If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the IDE drives themselves must be configured in this section. The following table shows the drive assignments for Ide0-Ide3:
Table 5-1. IDE0-IDE3 Drive Assignments File System Name
Controller
Master/Slave
Ide0
Primary (1f0h)
Master
Ide1
Primary (1f0h)
Slave
Ide2
Secondary (170h)
Master
Ide3
Secondary (170h)
Slave
To use the primary master IDE drive in your system (the typical case), just configure Ide0 in this section, and map Ide0 to drive C: in the Configuring Drive Assignments section. The IDE Drive Types section lets you select the type for each of the four IDE drives: None, User, Physical, LBA, or CHS. User
This type allows the user to select the maximum cylinders, heads, and sectors per track associated with the IDE drive. This method is now rarely used since LBA is now in common use.
Physical
This type instructs the BIOS to query the drive’s geometry from the controller on each POST. No translation on the drive’s geometry is performed, so this type is limited to drives of 512 Mbytes or less. Commonly, this is used with embedded ATA PC Cards.
LBA
This type instructs the BIOS to query the drive’s geometry from the controller on each POST, but then translate the geometry according to the industrystandard LBA convention. This supports up to 16-Gbyte drives. Use this method for all new drives.
CHS
This type instructs the BIOS to query the drive’s geometry from the controller on each POST, but then translate the geometry according to the Phoenix CHS convention. Using this type on a drive previously formatted with LBA or Physical geometry might show data as being missing or corrupted.
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5.4
Configuring Boot Actions Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the entire system has been initialized, POST executes these steps in order until an operating system successfully loads. In addition, other pre-boot features can be run before, after, or between operating system load attempts. The following actions can be used:
5.5
Drive A: - K:
Boot operating system from specified drive. If “Loader” is set to “BootRecord” or “Unused”, then the standard boot record will be invoked, causing DOS, Windows95/98, Windows NT, or other industry-standard operating systems to load. If “Boot Method” is set to “Windows CE”, then the boot drive’s boot record will not be used, and instead the BIOS will attempt to load and execute the Windows CE Kernel file, NK.BIN, from the root directory of each boot device.
Debugger
Launch the Integrated BIOS Debugger. To return to the boot process from the debugger environment, type “G” at the debugger prompt and press ENTER.
MFGMODE
Initiate Manufacturing Mode, allowing the system to be configured remotely via an RS232 connect to a host computer.
WindowsCE
Execute a ROM-resident copy of Windows CE, if available. This feature is not applicable unless properly configured by the OEM in the BIOS adaptation.
DOS in ROM
Execute a ROM-resident copy of DOS, if available. This feature is not applicable unless an XIP copy of DOS, such as Embedded DOS-ROM, has been stored in the BIOS boot ROM. Copies of Embedded DOS-ROM may be obtained from General Software.
None
No action; POST proceeds to the next activity in the sequence.
Custom Configuration Setup Screen The system’s hardware-specific features are configured with the Custom Setup Screen (Figure 5-4). All features are straightforward except for the Redirect Debugger I/O option, which is an extra embedded feature that allows the user to select whether the Integrated BIOS Debugger should use standard keyboard and video or RS232 console redirection for interaction with the user. If no video is available, the debugger is always redirected.
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Figure 5-4. Embedded BIOS Custom Setup Screen
5.6
Shadow Configuration Setup Screen The system’s Shadow Configuration Setup Screen (Figure 5-5) allows the selective enabling and disabling of shadowing in 16 Kbyte sections, except for the top 64 Kbytes of the BIOS ROM, which is shadowed as a unit. Normally, shadowing should be enabled at C000/C400 (to enhance VGA ROM BIOS performance), and then E000-F000 should be shadowed to maximize system ROM BIOS performance.
Figure 5-5. Embedded BIOS Shadow Setup Screen
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5.7
Standard Diagnostics Routines Setup Screen Embedded systems may require automated burn-in testing in the development cycle. This facility is provided directly in the system’s system BIOS through the Standard Diagnostics Routines Setup Screen (Figure 5-6). To use the system, selectively enable or disable features to be tested, and then enable the “Tests Begin on ESC?” option to cause the system test suite to be invoked. To repeat the system test battery continuously, you should also enable the “Continuous Testing” option. When continuous testing is started, the system will continue until an error is encountered.
Caution:
The disk I/O diagnostics perform write operations on those drives; therefore, only spare drives should be used which do not contain data that could be harmed by the test.
Caution:
The keyboard test may fail when in fact the hardware is operating within reasonable limits. This is because although the device may produce occasional errors, the BIOS retries operations when failures occur during normal operation of the system.
Figure 5-6. Standard Diagnostic Routines Setup Screen
5.8
Start System BIOS Debugger Setup Screen The Embedded BIOS Integrated Debugger may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, the debugger will display the debugger prompt: EB42DBG: and await debugger commands. To resume back to the Setup Screen main menu, type the following command, which instructs the debugger to “go”: EB42DBG: G
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5.9
Start RS232 Manufacturing Link Setup Screen The Embedded BIOS Manufacturing Mode may be invoked from the Setup Screen main menu, as well as a boot activity. Once invoked, Manufacturing Mode takes over the system and freezes the console of the system (Figure 5-7). The host can resume operation of the system and give control back to the system Setup Screen system with special control software.
Figure 5-7. Start RS232 Manufacturing Link Setup Screen
5.10
Manufacturing Mode The system’s BIOS provides a special mode, called Manufacturing Mode, that allows the target to be controlled by a host computer such as a laptop or desktop PC. Running special software supplied by General Software, the host can access the target’s drives and manage the file systems on the target, reprogram flash memories, and test target hardware. A full discussion of the uses of Manufacturing Mode is beyond the scope of this chapter. Complete documentation and host-side software is available directly from General Software. For more information, visit the General Software web site at http://www.gensw.com.
5.10.1
Console Redirection The system can operate either with a standard PC/AT or PS/2 keyboard and VGA video monitor, or with a special emulation of a console over an RS232 cable connected to a host computer running a terminal program. To see an example session with HYPERTERMINAL, see the debugger section’s screen display (Figure 5-9). To use the Console Redirection feature, simply remove the video display card from the system so that no video ROM is available for the BIOS to detect. In the absence of any video support, the BIOS automatically switches its keyboard and screen functions to serial I/O over COM1 on the board. The hardware connection to the host computer requires a null modem cable.
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The software on the target can be any terminal emulation program that supports ANSI terminal mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The program must be set to not use flow control, or the console may seem to stall or not accept input. Caution:
5.10.2
HYPERTERMINAL’s default setting is to use flow control, which will render the console inoperative. To change this, create a new session, change the flow control setting to “none”, save the session, and exit HYPERTERMINAL. Then reinvoke HYPERTERMINAL with the session and it will operate with the new flow control setting.
CE-Ready Windows CE Loader Your system’s BIOS is “CE-Ready” and can directly boot Windows CE* without loading an intermediate operating system such as DOS and LOADCEPC. Instead, the NK.BIN file can be placed on a disk drive or drive emulator, and then the BIOS can be configured through the Basic CMOS Configuration Setup Screen to boot the NK.BIN file from the boot drives instead of the boot records on those drives. To configure your system to boot Windows CE natively from a disk drive, set the “Boot Method” field to “Windows CE” in the Basic CMOS Configuration Setup Screen. Then, place a copy of NK.BIN suitable for execution by LOADCEPC in the root directory of your normal boot drive, such as drive C:. Then, reboot the system. The configuration box should be displayed (Figure 5-8), and immediately following should be the message “Loading Windows CE…” followed by a series of dots, indicating that the loading process is continuing. Once fully loaded, Windows CE takes over the system and runs using the standard PC keyboard, screen, and PS/2 mouse.
Figure 5-8. CE-Ready Boot Feature
5.10.3
Integrated BIOS Debugger The system’s BIOS contains a built-in debugger that can be a valuable tool to aid the board bringup process on new designs similar to the evaluation platform. It supports a DOS SYMDEB-style command line interface, and can be used on the main console’s keyboard and screen, or over a redirected connection to a terminal program (see “Console Redirection” on page 5-9).
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To activate the debugger at any time from the main console, press the left shift and the control keys together. A display similar to the one in the HYPERTERMINAL session below (Figure 5-9) will appear, containing the title, “Embedded BIOS Debugger Breakpoint Trap” and a snapshot of the processor general registers. Figure 5-9. Integrated BIOS Debugger Running Over a Remote Terminal
To leave the debugger and resume the interrupted activity (whether POST, BIOS, DOS, Windows, or an application program), enter the “G” command (short for “go”) and press ENTER. If you were at a DOS prompt when you entered the debugger, then DOS will still be waiting for its command, and will not prompt again until you press ENTER again. The debugger can also be entered from the Setup Screen System, and as a boot activity (see “Basic CMOS Configuration Screen” on page 5-3), as a last ditch effort during board bring-up and development if no bootable device is available. If your version of DOS, an application, or any OEM-supplied BIOS extensions have debugging code (i.e., “INT 3” instructions) remaining, then these will invoke the debugger automatically, although this is not an error. To continue, use the “G” command. When Embedded BIOS is adapted by the OEM, the debugger can be removed from the final production BIOS, and superfluous debugging code in the application will not cause the debugger to be invoked.
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A complete discussion of the debugger is beyond the scope of this chapter; however, complete documentation is available from General Software via the web at http://www.gensw.com.
5.11
Embedded BIOS POST Codes Embedded BIOS writes progress codes, also known as POST codes, to I/O port 80H during POST, in order to provide information to OEM developers about system faults. These POST codes may be monitored on the on-board Post Code Debugger located at U12 and U13. They are not displayed on the screen. For more information about POST codes, contact General Software.
Mnemonic Code POST_STATUS_START POST_STATUS_CPUTEST POST_STATUS_DELAY POST_STATUS_DELAYDONE POST_STATUS_KBDBATRDY POST_STATUS_DISABSHADOW POST_STATUS_CALCCKSUM POST_STATUS_CKSUMGOOD POST_STATUS_BATVRFY POST_STATUS_KBDCMD POST_STATUS_KBDDATA POST_STATUS_BLKUNBLK POST_STATUS_KBDNOP POST_STATUS_SHUTTEST POST_STATUS_CMOSDIAG POST_STATUS_CMOSINIT POST_STATUS_CMOSSTATUS POST_STATUS_DISABDMAINT POST_STATUS_DISABPORTB POST_STATUS_BOARD POST_STATUS_TESTTIMER POST_STATUS_TESTTIMER2 POST_STATUS_TESTTIMER1 POST_STATUS_TESTTIMER0 POST_STATUS_MEMREFRESH POST_STATUS_TESTREFRESH POST_STATUS_TEST15US POST_STATUS_TEST64KB POST_STATUS_TESTDATA POST_STATUS_TESTADDR POST_STATUS_TESTPARITY POST_STATUS_TESTMEMRDWR POST_STATUS_SYSINIT POST_STATUS_INITVECTORS POST_STATUS_8042TURBO POST_STATUS_POSTTURBO POST_STATUS_POSTVECTORS POST_STATUS_MONOMODE POST_STATUS_COLORMODE POST_STATUS_TOGGLEPARITY POST_STATUS_INITBEFOREVIDEO
5-12
Code 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2ah 2bh
System Progress Report Start POST (BIOS is executing). Start CPU register test. Start power-on delay. Power-on delay finished. Keyboard BAT finished. Disable shadowing & cache. Compute ROM CRC, wait for KBC. CRC okay, KBC ready. Verifying BAT command to KB. Start KBC command. Start KBC data. Start pin 23,24 blocking & unblocking. Start KBC NOP command. Test CMOS RAM shutdown register. Check CMOS checksum. Initialize CMOS contents. Initialize CMOS status for date/time. Disable DMA, PICs. Disable Port B, video display. Initialize board, start memory bank detection. Start timer tests. Test 8254 T2, for speaker, port B. Test 8254 T1, for refresh. Test 8254 T0, for 18.2Hz. Start memory refresh. Test memory refresh. Test 15usec refresh ON/OFF time. Test base 64KB memory. Test data lines. Test address lines. Test parity (toggling). Test Base 64KB memory. Prepare system for IVT initialization. Initialize vector table. Read 8042 for turbo switch setting. Initialize turbo data. Modification of IVT. Video in monochrome mode verified. Video in color mode verified. Toggle parity before video ROM test. Initialize before video ROM check.
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POST_STATUS_VIDEOROM POST_STATUS_POSTVIDEO POST_STATUS_CHECKEGAVGA POST_STATUS_TESTVIDEOMEMORY POST_STATUS_RETRACE POST_STATUS_ALTDISPLAY POST_STATUS_ALTRETRACE POST_STATUS_VRFYSWADAPTER POST_STATUS_SETDISPMODE POST_STATUS_CHECKSEG40A POST_STATUS_SETCURSOR POST_STATUS_PWRONDISPLAY POST_STATUS_SAVECURSOR POST_STATUS_BIOSIDENT POST_STATUS_HITDEL POST_STATUS_VIRTUAL POST_STATUS_DESCR POST_STATUS_ENTERVM POST_STATUS_ENABINT POST_STATUS_CHECKWRAP1 POST_STATUS_CHECKWRAP2 POST_STATUS_HIGHPATTERNS POST_STATUS_LOWPATTERNS POST_STATUS_FINDLOWMEM POST_STATUS_FINDHIMEM POST_STATUS_CHECKSEG40B POST_STATUS_CHECKDEL POST_STATUS_CLREXTMEM POST_STATUS_SAVEMEMSIZE POST_STATUS_COLD64TEST POST_STATUS_COLDLOWTEST POST_STATUS_ADJUSTLOW POST_STATUS_COLDHITEST POST_STATUS_REALMODETEST POST_STATUS_ENTERREAL POST_STATUS_SHUTDOWN POST_STATUS_DISABA20 POST_STATUS_CHECKSEG40C POST_STATUS_CHECKSEG40D POST_STATUS_CLRHITDEL POST_STATUS_TESTDMAPAGE POST_STATUS_VRFYDISPMEM POST_STATUS_TESTDMA0BASE POST_STATUS_TESTDMA1BASE POST_STATUS_CHECKSEG40E POST_STATUS_CHECKSEG40F POST_STATUS_PROGDMA POST_STATUS_INITINTCTRL POST_STATUS_STARTKBDTEST POST_STATUS_KBDRESET POST_STATUS_CHECKSTUCKKEYS POST_STATUS_INITCIRCBUFFER POST_STATUS_CHECKLOCKEDKEYS POST_STATUS_MEMSIZEMISMATCH POST_STATUS_PASSWORD
2ch 2dh 2eh 2fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3ah 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4ah 4bh 4ch 4dh 4eh 4fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 60h 61h 62h 63h 64h 65h 66h 67h 80h 81h 82h 83h 84h 85h
Passing control to video ROM. Control returned from video ROM. Check for EGA/VGA adapter. No EGA/VGA found, test video memory. Scan for video retrace signal. Primary retrace failed. Alternate found. Verify video switches. Establish display mode. Initialize ROM BIOS data area. Set cursor for power-on msg. Display power-on message. Save cursor position. Display BIOS identification string. Display "Hit to ..." message. Prepare protected mode test. Prepare descriptor tables. Enter virtual mode for memory test. Enable interrupts for diagnostics mode. Initialize data for memory wrap test. Test for wrap, find total memory size. Write extended memory test patterns. Write conventional memory test patterns. Find low memory size from patterns. Find high memory size from patterns. Verify ROM BIOS data area again. Check for pressed. Clear extended memory for soft reset. Save memory size. Cold boot: Display 1st 64KB memtest. Cold boot: Test all of low memory. Adjust memory size for EBDA usage. Cold boot: Test high memory. Prepare for shutdown to real mode. Return to real mode. Shutdown successful. Disable A20 line. Check ROM BIOS data area again. Check ROM BIOS data area again. Clear "Hit " message. Test DMA page register file. Verify from display memory. Test DMA0 base register. Test DMA1 base register. Checking ROM BIOS data area again. Checking ROM BIOS data area again. Program DMA controllers. Initialize PICs. Start keyboard test. Issue KB reset command. Check for stuck keys. Initialize circular buffer. Check for locked keys. Check for memory size mismatch. Check for password or bypass setup.
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POST_STATUS_BEFORESETUP POST_STATUS_CALLSETUP POST_STATUS_POSTSETUP POST_STATUS_DISPPWRON POST_STATUS_DISPWAIT POST_STATUS_ENABSHADOW POST_STATUS_STDCMOSSETUP POST_STATUS_MOUSE POST_STATUS_FLOPPY POST_STATUS_CONFIGFLOPPY POST_STATUS_IDE POST_STATUS_CONFIGIDE POST_STATUS_CHECKSEG40G POST_STATUS_CHECKSEG40H POST_STATUS_SETMEMSIZE POST_STATUS_SIZEADJUST POST_STATUS_INITC8000 POST_STATUS_CALLC8000 POST_STATUS_POSTC8000 POST_STATUS_TIMERPRNBASE POST_STATUS_SERIALBASE POST_STATUS_INITBEFORENPX POST_STATUS_INITNPX POST_STATUS_POSTNPX POST_STATUS_CHECKLOCKS POST_STATUS_ISSUEKBDID POST_STATUS_RESETID POST_STATUS_TESTCACHE POST_STATUS_DISPSOFTERR POST_STATUS_TYPEMATIC POST_STATUS_MEMWAIT POST_STATUS_CLRSCR POST_STATUS_ENABPTYNMI POST_STATUS_INITE000 POST_STATUS_CALLE000 POST_STATUS_POSTE000 POST_STATUS_DISPCONFIG POST_STATUS_INT19BOOT POST_STATUS_LOWMEMEXH POST_STATUS_EXTMEMEXH POST_STATUS_PCIENUM
5-14
86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 0a0h 0a1h 0a2h 0a3h 0a4h 0a5h 0a6h 0a7h 0a8h 0a9h 0b0h 00h 0b1h 0b2h 0b3h
Password accepted. Entering setup system. Setup system exited. Display power-on screen message. Display "Wait..." message. Shadow system & video BIOS. Load standard setup values from CMOS. Test and initialize mouse. Test floppy disks. Configure floppy drives. Test hard disks. Configure IDE drives. Checking ROM BIOS data area. Checking ROM BIOS data area. Set base & extended memory sizes. Adjust low memory size for EBDA. Initialize before calling C800h ROM. Call ROM BIOS extension at C800h. ROM C800h extension returned. Configure timer/printer data. Configure serial port base addresses. Prepare to initialize coprocessor. Initialize numeric coprocessor. Numeric coprocessor initialized. Check KB settings. Issue keyboard ID command. KB ID flag reset. Test cache memory. Display soft errors. Set keyboard typematic rate. Program memory wait states. Clear screen. Enable parity and NMIs. Initialize before calling ROM at E000h. Call ROM BIOS extension at E000h. ROM extension returned. Display system configuration box. Call INT 19h bootstrap loader. Test low memory exhaustively. Test extended memory exhaustively. Enumerate PCI busses.
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5.12
Embedded BIOS Beep Codes Embedded BIOS tests much of the system hardware early in POST before messages can be displayed on the screen. When system failures are encountered at these early stages, POST uses beep codes (a sequence of tones on the speaker) to identify the source of the error. The following is a comprehensive list of POST beep codes for the system BIOS. BIOS extensions, such as VGA ROMs and SCSI adapter ROMs, may use their own beep codes, including short/long sequences, or possibly beep codes that sound like the ones below. When diagnosing a system failure, remove these adapters if possible before making a final determination of the actual POST test that failed.
Mnemonic Code POST_BEEP_REFRESH POST_BEEP_PARITY POST_BEEP_BASE64KB POST_BEEP_TIMER POST_BEEP_CPU POST_BEEP_GATEA20 POST_BEEP_DMA POST_BEEP_VIDEO POST_BEEP_KEYBOARD POST_BEEP_SHUTDOWN POST_BEEP_CACHE POST_BEEP_BOARD POST_BEEP_LOWMEM POST_BEEP_EXTMEM POST_BEEP_CMOS POST_BEEP_ADDRESS_LINE POST_BEEP_DATA_LINE POST_BEEP_INTERRUPT POST_BEEP_PASSWORD
Beep CountDescription of Problem 1 Memory refresh is not working. 2 Parity error found in 1st 64KB of memory. 3 Memory test of 1st 64KB failed. 4 T1 timer test failed. 5 CPU test failed. 6 Gate A20 test failed. 7 DMA page/base register test failed. 8 Video controller test failed. 9 Keyboard test failed. 10 CMOS shutdown register test failed. 11 External cache test failed. 12 General board initialization failed. 13 Exhaustive low memory test failed. 14 Exhaustive extended memory test failed. 15 CMOS restart byte test failed. 16 Address line test failed. 17 Data line test failed. 18 Interrupt controller test failed. 1 Incorrect password used to access SETUP.
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
5-15
PLD Code Listing
A
The code listing below is for the 22V10 PLD.
TITLE PATTERN REVISION AUTHOR COMPANY DATE
22V10 PORT 80 ADDRESS DECODER / FLASH DECODE 1 B CHRIS BANYAI INTEL CORPORATION 10/1/97
OPTIONS SECURITY = OFF
; ( part was 22V10FN before conversion ) CHIP P80B iPLD22V10N PIN PIN PIN PIN PIN PIN PIN PIN PIN
19 3 [6:7] [9:13] 16 [5:4] [26:23] [21:20] 2
PIN PIN PIN
18 17 27
IOWR_BAR AEN SA[0:1] SA[2:6] SA7 SA[8:9] SA[19:16] SA[15:14] SEL /CS_BAR /CS_DOC OX
EQUATIONS CS_BAR = /IOWR_BAR * /AEN * /SA0 * /SA1 * /SA2 * /SA3 * /SA4 * /SA5 * /SA6 * SA7 * /SA8 * /SA9 CS_BAR.TRST = VCC CS_DOC = /SEL * /AEN * SA19 * SA18 * /SA17 * /SA16 * SA15 * /SA14 + SEL * /AEN * SA19 * SA18 * /SA17 * SA16 * /SA15 * /SA14 CS_DOC.TRST = VCC OX = /IOWR_BAR OX.TRST = VCC SIMULATION SETF SETF SETF SETF
/AEN /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 IOWR_BAR SA7 IOWR_BAR /IOWR_BAR IOWR_BAR
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
A-1
PLD Code Listing
SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF SETF
A-2
AEN /IOWR_BAR /AEN IOWR_BAR SA0 /IOWR_BAR /SA0 /IOWR_BAR IOWR_BAR /SA0 /SA1 /SA2 /SA3 /SA4 /SA5 /SA6 /SA7 /SA8 /SA9 /SA19 /SA18 /SA17 /SA16 /SA15 /SA14 /SEL SA19 SA18 /SA17 /SA16 SA15 /SA14 /SEL /AEN /SA19 SA19 /SA18 SA18 SA17 /SA17 SA16 /SA16 /SA15 SA15 SA14 /SA14 /SEL SA19 SA18 /SA17 SA16 /SA15 /SA14 /SEL /AEN SEL /SA19 SA19 /SA18 SA18 SA17 /SA17 /SA16 SA16 SA15 /SA15 SA14 /SA14 /SEL
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Bill of Materials
B
Table B-1 is the bill of materials for the baseboard. Table B-2 is the bill of materials for the processor assembly. Table B-1. Baseboard Bill of Materials (Sheet 1 of 4) Qty
Reference
Description
Manufacturer
Manufacturer P/N
240
J14,J15
Conn,Jumper2,1X2 25-mil sq/100mil space,HDR2
3M
929647-09-02
570
J20-24
Conn,Jumper3,1X3 25-mil sq/100mil space,HDR3
3M
929647-09-03
130
JP2
Conn,Speaker,1X4 25-mil sq/100-mil space,HDR4
3M
929647-09-04
130
J10
Conn,FLASH,2X70 C19 Recept
AMP
1-316077-0
130
J12
Conn,Fan
AMP
173981-3
130
J25
Conn,2x70 Plug /Flash Daughtercard
AMP
6-353185-1
130
XU9
PLCC, Socket 28
AMP
822271-1
130
J19
Conn,CPU,400 Pin Array (BGA),BGA40X10-400R
Berg
74219-002
130
U6
IC,Clock Generator,CK100,SSOP30048(PIN)
Cypress
CY2280PVC-11S
130
U26
IC,Clock Buffer,Zero Delay 3.3V,16PIN,150MIL,TSSOP,PSSOP 16
Cypress
CY2309ZC-1H
130
U16
IC,Clock Buffer,18 Output low skew,SSOP300-48(PIN)
Cypress
CY2318ANZPVC-1
130
Y2
Crystal,32.768KHz,XTAL/MC-405
Epson
MC-405
240
J17,J18
Conn,SDRAM DIMM,168 Pin Recept
FOXCONN
AT08403-K8
130
J4
Conn, Serial Stack,DB9MX2
FOXCONN
DM10156-73
130
J3
Conn, DB25,DB25FM1
FOXCONN
DT11323-R5T
350
J7,J8,J9
Conn,PCI Edge Recept,145154-120
FOXCONN
EH06001-PC-W
240
J5,J6
Conn,ISA Edge Recept.,isa-98
FOXCONN
EQ04901-S6
130
JP1
Conn,Floppy,17X2 Header
FOXCONN
HL07173-P4
240
JP3,JP4
Conn, IDE,20X2 Header
FOXCONN
HL07206-D2
130
J11
Conn,Power,5566DP-20/ATX
FOXCONN
HM20100-P2
130
J1
Conn,PS2 Keyboard / Mouse Connector
FOXCONN
MH11067-D2
130
J13
Conn,AGP Edge Recept., 120 pins,AGP-124
FOXCONN
PC1243K-10
130
J2
2 USB Stack Connectors
FOXCONN
UB1112C-D3
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
B-1
Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 2 of 4) 130
U11
BIOS FLASH Memory,TSOP12X20/ 40S
INTEL
28F002BC
130
U8
VLSI,PIIX4,PCI to IDE &ISA Bridge,324 mBGA,BGA20x20-324
Intel
FW82371EB
460
U17-20
MEMORY,FLASH, StrataFlash,BGA8x9-56
Intel
G28F640J5-150
130
U14
IC,Interrupt Controller, 82093AA,QFP16x22-64
INTEL
S82093AA
680
C99,C100,C132,C133,C209,C2 14
Chip Capacitor,10pF, 50V,CC0603
Kemet
C0603C100J5GAC
9260
C: 22,42-43,48-49,54,5965,70-71,73,75-76,85-87,9092,96-97, 102,106-108,111112,114,116-118, 126-127,129131, 136,137,139-140, 142144,146-147, 151,157,159-162, 174-176,181-183, 187-200,205206,208,218-219,226-229
Chip Capacitor,0.1uF, 16V,CC0603
Kemet
C0603C104K4RAC
2550
C27-C41,C44-C47,C50-C53
Chip Capacitor,470pF, 50V,CC0603
Kemet
C0603C471K5RAC
1670
C3-5,C8,C55-57, C94,C119121, C134,C138,C145, C153
Cap,Tant,10uF,15V,C Case,6032
Kemet
T491C106K016AS
1120
C93,C103-105, C128,C135,C152, C154-156
Cap,Tant,47uF, 20V,D Case,7343
Kemet
T491D476M020AS
1010
C2,C6,C58,C72, C84,C88,C89,C95, C109
Cap,Tant,100uF, 10V,D Case,7343
Kemet
T495D107M010AS
5630
C1,C7,C23,C66-C68,C74,C77C82, C101,C113,C115, C141,C158,C163-173,C177180, C184-186,C201202,C204,C207, C211213,C216-217,C220-C225
Chip Capacitor,0.01uF 50V,CC0603
Kemet
C0603C103J5RAC
130
U9
IC,PLD,PLCC28,Socket28
LATTICE
GAL22V10B-7LJ
130
U23
IC,Linear Voltage Regulator,SOT223
Linear Tech.
LT1117-3.3cst
130
U5
IC,Linear Voltage Regulator,SOT223
Linear Tech.
LT1117CST
130
XU11
40TSOP BIOS Socket,TSOP12X20/ 40S
Meritec
980020-40-01
240
XU12,XU13
TIL311 SOCKET,DIP14
MILLMAX
110-99-314-41-001
130
U25
IC,Logic,74ACT05,SO14
Motorola
MC74ACT05DR
1010
FB1-FB9
Ferrite Bead,SM1806,Z-Bead
Murata
BLM41A800S
130
U22
IC,Logic,74ALS00,SOIC14
National
DM74ALS00M
130
U7
IC,Tranciever,8-Bit Bidirectional Buffer,SOIC20,SO20W
National
DM74ALS245AWM
460
C69,C83,C98,C110
Cap,Electrolitic,220uF, 25v,6.3mmx11.2mm,PCAPR200300
Panasonic
ECE-A1EU221
2550
R33,R35,R37,R48,R52,R98R100, R106,R108-R116,R118R122
Chip Resistor,0 Ohm Shunt,5%,CR0805
Panasonic
ERJ6GEY0R00V
B-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 3 of 4) 1230
R6,R25,R42,R45,R49,R60R63,R101,R102
Chip Resistor,1K,5%,CR0805
Panasonic
ERJ6GEYJ102V
2000
R2,R4,R5,R11,R40,R41,R43,R 53R56,R59,R97,R105,R117,R123 -124,R127
Chip Resistor,10K,5%,CR0805
Panasonic
ERJ6GEYJ103V
680
R1,R3,R88,R89.R90,R91
Chip Resistor,15K,5%,CR0805
Panasonic
ERJ6GEYJ153V
130
R9
Chip Resistor,22,5%,CR0805
Panasonic
ERJ6GEYJ220V
790
R10,R12,R13,R14,R39,R58,R7 0
Chip Resistor,220,5%,CR0805
Panasonic
ERJ6GEYJ221V
460
R92-R95
Chip Resistor,27,5%,CR0805
Panasonic
ERJ6GEYJ270V
460
R20,R44,R57,R71
Chip Resistor,2.7K,5%,CR0805
Panasonic
ERJ6GEYJ272V
1890
R17-R19,R21-R24,R26R32,R34,R36,R38
Chip Resistor,33,5%,CR0805
Panasonic
ERJ6GEYJ330V
240
R103,R104
Chip Resistor,470,5%,CR0805
Panasonic
ERJ6GEYJ471V
1120
R7,R64-R69, R125,R126,R128
Chip Resistor,4.7k,5%,CR0805
Panasonic
ERJ6GEYJ472V
2000
R72-R87,R96,R107
Chip Resistor,8.2K,5%,CR0805
Panasonic
ERJ6GEYJ822V
240
S1,S2
Switch-Push Button,PBSW/ PNASNC2
Panasonic
EVQ-PHP03T
1670
RP2,RP3,RP41-RP47,RP54RP56, RP58,RP60,RP61
Res,Array,SMT,33,5%,EXB-V
Panasonic
EXB33V330JV
350
RP10,RP18,RP23
Res,Array,SMT,1K,5%,EXB-V
Panasonic
EXB38V102JV
2990
RP8-9,RP11,RP13-17,RP19RP22, RP24,RP26-33, RP3536, RP39, RP51-52,RP59
Res,Array,SMT,10K,5%,EXB-V
Panasonic
EXB38V103JV
350
RP1,RP4,RP48
Res,Array,SMT,22,5%,EXB-V
Panasonic
EXB38V220JV
790
RP25,RP37,RP38,RP40,RP49, RP50,RP53
Res,Array,SMT,2.7K,5%,EXB-V
Panasonic
EXB38V272JV
130
RP57
Res,Array,SMT,47,5%,EXB-V
Panasonic
EXB38V470JV
350
RP5,RP6,RP7
Res,Array,SMT,4.7K,5%,EXB-V
Panasonic
EXB38V472JV
240
RP12,RP34
Res,Array,SMT,5.6k,5%,EXB-V
Panasonic
130
U24
IC,Logic,Inverter, Schmitt Trigger,SOIC14
Philips
74HCT14D
130
U10
IC,Logic,10 Bit Bus Switch,QSOP,SO24W
Quality Semi
QS3384SO
130
Y1
Crystal,14.318MHz,XTAL,FOXHC495D
Raltron
AS-14.31818-20
350
F1-F3
Fuse,Drawing,SM250
RayChem
SMD250-2
130
XBT1
Battery Holder Socket
Renata
HU-2032-1
130
BT1
Battery
Reneta
CR2032
350
D1,D2,D5
Diode,LED,SOT23-A
Siemens
LGS260-DO
130
U1
VLSI,Super I/O,QFP128
SMSC
FDC37B78X
460
C122-C125
Chip Capacitor,47pF,CC0603
TDK
C1608C0G1H470JT$
1780
C9-C21,C24-C26
Chip Capacitor,220pF,CC0603
TDK
C1608X7R1H221KT0 09A
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
B-3
Bill of Materials
Table B-1. Baseboard Bill of Materials (Sheet 4 of 4) 130
U15
IC,Logic,3 state buffer,SOP-14
TI
74LVC125A
130
U21
IC,Logic,SOP-14
TI
74LVC14A
240
U3,U4
IC,RS232 Transceiver, SOIC20,SO20W
TI
GD75232DW
130
U27
IC,Logic,PCI to CardBus Controller,SQFP20x20-144
TI
PCI1210PGE
130
U2
IC,Logic,Open Drain Buffer,SOP-14
TI
SN7407D
240
U12,U13
7 Segment LED display,DIP14
TI
TIL311
460
D3-D4,D6-D7
Schottky Diode,SOT23-E
ZETEX
BAT54
570
R8,R15,R16,R46,R47
Chip Resistor,124,1%,CR0805
105
SDRAM DIMMS
Table B-2. Processor Assembly Bill of Materials (Sheet 1 of 2) Qty
Reference
Description
Manufacturer
Manufacturer P/N
130
J1
ITP
AMP
104068-1
570
C13,C21,C81-83
100uF
AVX
TPSD107M010R0065
240
C35,C107
150uF 10V 20%
AVX
TPSD157M010R0100
790
C12,C36-37,C48,C50,C108109
220uF
AVX
TPSD227M006R0100
130
U8
BGA,40x10-400
Berg
74221-001
240
D3-4
CMDSH-3
Central Semi
CMDSH-3
130
R26
0.02
Dale Elect
WSL-2010R020F
130
R10
0.075
Dale Elect
WSL-2010R075F
570
R7,R37-39,R41
22
Digikey
Y4220CT-ND
350
R34,R36,R42
4.7K
Digikey
Y4472CT-ND
130
R9
8.2K
Digikey
Y4822CT-ND
240
U3,U7
PBSRAM,64Kx32,QFP14x21100
Etron
EM542323TQ-11
130
U2
SOJ28/300
IDT
71V256SB15Y
130
U4
BGA 20x20-324
Intel
82439TX
130
U5
BGA 26X26-352W/HS
Intel
GC80503CSM66266 SL389
2770
C8,C16,C22,C62,C6768,C70,C77-C78,C80,C8586,C90,C93-97,C99,C101-106
0.01uF,5%,50V
Kemet
C0603C103J5RAC
5630
C3-5,C7,C9-11,C1415,C18,C2327,C29,C32,C40,C45-46,C5161,C63-66,C69,C7176,C79,C84,C87-89,C9192,C98,C100
0.1uF 16V 10%
Kemet
C0603C104K4RAC
570
C30-31,C39,C42,C44
1000pF 50V 10%
Kemet
C0805C102J5RAC
130
C17
1uF 20% 10V
Kemet
T491A105M010AS
0
C38
10uF,10%,16v
Kemet
T491C106K016AS
B-4
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Bill of Materials
Table B-2. Processor Assembly Bill of Materials (Sheet 2 of 2) 460
C1,C2,C16,C19
22uF 20% 16V
Kemet
T491C226M016AS
130
C20
130
u1
33uF 20% 16V
Kemet
T491D336M016AS
SSOP28
Linear Tech.
LTC1438CG-ADJ
240
D2,D5
MBRS140T3
Motorola
MBRS140T3
130
R23
30K 0.1%
Panasonic
ERA-6YEBxxx
130
R12
39K 0.1%
Panasonic
ERA-6YEBxxx
350
R11,R20,R24
43K 0.1%
Panasonic
ERA-6YEBxxx
130
R19
47K 0.1%
Panasonic
ERA-6YEBxxx
350
R2-3,R17,R45
0 1/10W
Panasonic
ERJ6GEY0R00V
570
R13-15,R21-22
10 1/10W 5%
Panasonic
ERJ6GEYJ100V
460
R1,R4,R8,R43
1K,1/10W,5%
Panasonic
ERJ6GEYJ102V
350
R18,R25,R35
10K 1/10W 5%
Panasonic
ERJ6GEYJ103V
130
R33
2K 1/10W 5%
Panasonic
ERJ6GEYJ202V
130
R5
22K 1/10W 5%
Panasonic
ERJ6GEYJ223V
240
R27-R28
270 1/10W 5%
Panasonic
ERJ6GEYJ271V
240
R16,R30
3.3K 1/10W 5%
Panasonic
ERJ6GEYJ332V
240
R6,R40,R44
4.7K,1/10W,5%
Panasonic
ERJ6GEYJ472V
130
D1
BAT54C
Philips
BAT54C
130
L1
33uH/1.68A
Sumida
CDH115
130
L2
15uH/4.50A
Sumida
CDRH127
350
C33,C47,C49
220pF 50V 10%
TDK
C1608X7R1H221KT009A
350
C28,C41,C43
100pF 50V 5%
TDK Corp
C2012COG1H101JT009A
130
U1
SN74LVC04A-DB
TI
SN74LVC04A-DB
440
X3-6
MNT_HOLE,MTG125/300V
PCB FEATURE
3960
TP1-36
Test Point,TSTPAD/030
PCB FEATURE
240
Q1-2
SO8
Si4412DY
240
Q3-Q4
S08
Si9426DY
130
C34
68pF 5% 16V
Note:
The following devices are not to be populated: R6,R29,R31,R32,R2, C38
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
B-5
Schematics
C
The most current schematics, including "flat" schematics (without the 400-pin connector), are located on Intel’s Developer Web site at: http://www.intel.com/design/intarch/schems/. Schematics are provided for the following items: Baseboard
• • • • • • • • • • • • • • • • • • • • •
Block Diagram Mini PCI Connector CPU Connector DIMM0 DIMM1 DIMM2 Clocks ISA/PCI Pullups PCI Slots 0 & 1 PCI Slot 2 AGP Connector PIIX4 Part 1 PIIX4 Part 2 IDE Connectors Super I/O USB Connectors ISA Connectors COMx, DB25, Floppy BIOS/ Port 80 ATX Power Connector Unused Gates
Processor Assembly
• • • • • • •
Low-Power Pentium Processor with MMX Technology 82439TX System Controller Cache and Tags ITP / Strapping Options Regulators Connector CPU Decoupling
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
C-1
A
B
C
D
5
5
Revision D
Evaluation Platform System Electronic s Board
3
History
No license, express or implied, by estoppe l or otherwise, to any intellectual property righ ts is granted herein. Intel disclaims all liability, including liab ility for infringement of any proprietary rights, rel ating to use of information in this specification. Intel does not warrant or represent that such use wil l not infringe such rights .
(Pullups for mouse and k eyboard.)
4
3
2
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
8. Changed Bulk decoupling cap C154 from 10uF to 47uF to reduce BO M line items.
7. Changed Bulk decoupling on +12 and -12 to 2x220uF fro m 2x400uF.
6. Inverted POWERON# signal (SUSC#) from PIIX4 to control soft- on feature.
5. Changed RP48 to 4.7K.
4. Tied VBAT (pin 65) to 5.0V on Sup er I/O.
3. Swapped pins 1 and 3 (V5 with TP) on CPU-Fan c onnector.
2. Separated CSEL on IDE0 and IDE1
1. Swapped AD23 and AD19 on 400 pin con nector.
Changes made to Revisio n B.
Tied VBAT (pin 65) to 3.3V on Supe r I/O.
Changes made to Revisio n C.
3. Added C229 to -PC IRST
2. Moved J2 0
1. Added Signals PWROK(A24) +12V(A33) MB12#_R(B33 ) to J19A.
Changes made to Revisio n D.
1.
2
THIS SCHEMATIC IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,NCLUDING I ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE , OR ANY WARRANTY OTHERWISE ARISING OUT OF PROPOSAL, SPECIFICATION OR SAMPLE.
4
Date:
Size C
Title
1
Sheet
Changes Thursday, February 25, 1999
Document Number
1
1
of
22
D
Rev
A
B
C
D
1
2
3
4
A
Pullups Page 9
Power Page 21
Clocks Page 8
A
USB Page 17
IDE Page 15
B
B
PIIX4 Page 13,14
Unused Devices Page 22
PS2 KBD/MS Page 16
Flash Bios Port 80 Page 20
APIC Page 13
Serial Page 19
C
Floppy Page 19
ISA Connectors Page 18
ISA BUS
PCI BUS
PCI Connectors Page 10,11
DRAM (DIMM) Page 5,6,7
AGP Port Page 12
D
D
Date:
Size C
Title
E
E
Thursday, February 25, 1999
Document Number {Doc}
Shakopee
Micro Flash Connector Page 3
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
Parallel Page 19
Super I/O Page 16
CPU Module Connector Page 4
C
Sheet
2
of
22
D
Rev
1
2
3
4
1
2
3
4
A
A
8
4,10,11,13 -C/BE[3:0]
4,10,11,13 AD[31:0]
PCICLK4
B
B
V5_0
-C/BE3
-C/BE2
-C/BE1 AD31
-C/BE0
AD29 AD30
AD28
AD26 AD27
AD25
AD23 AD24
AD22
AD18 AD19 AD20 AD21
AD17
AD15 AD16
AD14
AD10 AD11 AD12 AD13
AD9
AD7 AD8
AD6
AD2 AD3 AD4 AD5
AD1
AD0
V3_3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
J10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 2X70RCPT
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
C
IDSELF
PIRQA# -PERR
PIRQB#
PIRQD# PIRQC#
V5_0
CLKRUN#
-PGNT3
R70 220
AD31
9,10,11,13,14 9,10,11
9,10,11,12,13,14
9,10,11,13,14 9,10,11,12,13,14
4,13
4,9
4,9,13
4,9,10,11,13
-PREQ3
4,9,10,11,13
-SERR
4,10,11,12,13
4,9,10,11,13
4,9,10,11,13
4,9,10,11,13
PAR
-PCIRST
-STOP
-TRDY
-IRDY
4,9,10,11,13
4,9,10,11
-PLOCK
-DEVSEL
4,9,10,11,13
-FRAME
D
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
V3_3
V5_0
C
E
Thursday, February 25, 1999
Document Number {Doc}
Mini PCI Connector
E
Sheet
3
of
22
D
Rev
1
2
3
4
1
2
3
4
+12V
MD41 MD43
MECC4 CS_B5# CS_B1# SCASA#
SRASB# CS_A1# SRASA# PWROK MAA4 MAA8 MAA12
5,6,7 5,6,7
5,6,7 7 5 5,7
6 5 5,7 14,21 5,6 5,6 5,6
-PGNT2 -PGNT4 -PHOLDA
MD57 MECC7 MD48 MD16 MD17 MD49 MD27 MD29
9,11 9 9,13
5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7
9,13 -PHOLD 3,9,10,11,13 - F R A M E
3,10,11,13 A D 3 0 3,10,11,13 A D 2 2
AD4 -C/BE0 AD10 AD13 PAR -TRDY
GST1 GST2 GSB_STB GSTOP# GPAR
12 12 12 12 12
3,10,11,13 3,10,11,13 3,10,11,13 3,10,11,13 3,9,10,11,13 3,9,10,11,13
CONFIG1
8,14
CKE1 CKE5
MD36 MD7
5,6,7 5,6,7
5 7
MD0 MD2
GRBF#
5,6,7 5,6,7
12
A
RSV10
RSV9
GAD14
GAD15
MAB#13
MAB#8
SBA5 GAD25 GAD30
A
TP26
TP
1
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
ST1 ST2 SB_STB G_STOP# G_PAR G_AD15 GND G_AD14 V3_3 AD4 C/BE0# AD10 AD13 PAR TRDY# V5_0 AD30 AD22 V5_0 PHOLD# FRAME# V5_0 GND Reserved9 GNT2# GNT4# PHLDA# GND Reserved10 V3_3 MD57 MECC7 MD48 MD8 MD9 MD49 MD27 MD29 V3_3 V5_0
J19D
SBA5 G_AD25 G_AD30 RBF# GND V3_3 MD0 MD2 GND MD36 MD7 V3_3 MD41 MD43 GND MECC4 CSB5# CSB1# SCASA# GND SRASB# CSA1# SRASA# Reserved0 MAA4 MAA8 MAA12 MAB8# GND MAB13# CKE1 CKE5 Reserved1 V3_3 V3_3 V3_3 V3_3 GND V3_3 CPU_TYPE
J19A B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40
950554-00x
PIPE# SBA1 GND G_AD16 G_AD18 V3_3 G_C/BE1# G_TRDY# G_DEVSEL# GND AD2 AD6 AD7 GND AD15 STOP# AD17 AD24 Reserved11 GND V5_0 C/BE3# AD20 AD31 V5_0 REQ2# GNT0# V3_3 Reserved12 MD26 MD58 MD50 MD10 GND MD13 MD12 MD28 MD61 VR_PWRGD V5_0
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40
950554-00x
AD_STBB G_AD24 GND G_AD29 V3_3 G_AD1 MD1 MD33 MD4 MD38 MD42 MD19 MD45 MD22 MECC0 GND CSB4# SCASB# V3_3 WEA# DQMA4 CSA2# CSA5# GND MAA2 MAB4# MAA5 GND MAB11# Reserved2 MAA13 CKE2 Reserved3 GND V3_3 SUS_STAT1# SUS_CLK V3_3 WSC# GND
T P 36 TP 1
RSV12
MECC5 DQMA0 CS_B2# DQMB5 CS_A4#
5,6,7 5,6,7 6 7 7
RSV6 RSV7
1 1
5,6,7 5,6,7 5,6,7 5,6,7 21
MD21 MD20 MD28 MD61 CPUPWROK
B
5,6,7 5,6,7 5,6,7 5,6,7
SBA[7:0]
12
7 MAB#[13:0]
GAD[31:0] GC/BE#[3:0]
12
APICD1
12
9,11,13 9,10
3,10,11,13 3,10,11,13 3,10,11,13
MD26 MD58 MD50 MD18
-PREQ2 -PGNT0
-C/BE3 AD20 AD31
3,10,11,13 3,9,10,11,13 3,10,11,13 3,10,11,13
RSV5
1
AD15 - S T OP AD17 AD24
RSV4
1
3,10,11,13 3,10,11,13 3,10,11,13
RSV2
1
AD2 AD6 AD7
12 12
TP TP37
TP TP35
TP TP32
TP TP28
TP TP33
9,13
13
WSC#
DQMA2
MAA11 CKE3
SUS_STAT1# SUSCLK
5,6,7
5,6 6
MAA0
MD44 MD15
5,6,7 5,6,7
5,6
MD3 MD37 MD40
5,6,7 5,6,7 5,6,7
14 ZZ 5,6,7,8,9,14 S M B C L K 1 4 5,6,7,8,9,14 S M B D A T A 14
GTRDY# GDEVSEL#
GC/BE#1
GAD16 GAD18
SBA1
5,6
MAA5
12
5,6
MAA2
5,6 6
5,7 5,6,7 6 7
WE_A# DQMA4 CS_A2# CS_A5#
MAA13 CKE2 MAB#12_R
7 6
5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7
12
CS_B4# SCASB#
MD1 MD33 MD4 MD38 MD42 MD11 MD45 MD14 MECC0
GAD_STB1
GPIPE#
MAB#11 RSV2
MAB#4
GAD1
GAD29
GAD24
B
TP T P 27
TP T P 29
TP T P 24
TP T P 30
TP T P 31
TP T P 25
RSV7
RSV6
RSV5
MAB#5 RSV4 MAB#12
MAB#0 MAB#2
SBA6 GAD26 GAD4 GAD3 GAD2
1
1
1
1
1
1
RSV16
RSV14
RSV13
RSV12
RSV10
RSV9
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 V3_3 SBA6 G_AD26 G_AD4 G_AD3 G_AD2 GND MD3 MD37 MD40 GND MD44 MD23 V3_3 MECC5 DQMA0 CSB2# DQMB5 CSA4# V3_3 MAB0# MAB2# V3_3 MAA0 MAB5# Reserved4 MAB12# MAA11 CKE3 Reserved5 DQMA1 Reserved6 V3_3 L2_ZZ SM_CLK SM_DATA GND Reserved7 PICD1 V3_3
J19B D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40
1
GFRAME# GIRDY#
MD51 MD52 MD19 MD53 MD22 MD62 MD30
5,6,7 5,6,7
-PREQ1 -PREQ3 -PREQ4
5,6,7 5,6,7 5,6,7 5,6,7 5,6,7
9,10,13 3,9,13 9
AD26 AD28 AD29
3,10,11,13 -C/BE2 3,10,11,13 3,10,11,13 3,10,11,13
FERR# IGNNE# A20M# STPCLK# DBRESET
SLP#
DQMA3
BXDCLKO
DQMB1 CS_A0# CS_B3# MAA1
MD34 MD5 MD8 MD9 MD12 MD46
RSV14
RSV13
SBA3 SBA2 GC/BE#3 GAD20 GAD17 GC/BE#2
8 9,14 9,14 9,14 9,13,14 9,14 9,14 9,14 8 9,14 9,13 21
RSV8
3,10,11,13 A D 3
12 12
TP23
TP
APICCLK1 APICD0
BxFBCLK NMI INIT INTR
5,6 5 8 7 5,65,6,7
5,6
MAA9 CKE0 CKE4 MAA10
6
MAA3
5,6
5,67 5,65 6 6
12 3,13 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7
WE_B#
DQMA1 DQMA5 CS_A3#
MD13 MD47
GAD_STB0 CLKRUN# MD32 MD35 MD6 MD39 MD10
3,10,11,13 A D 8 3,10,11,13 A D 1 2 3,10,11,13 -C/BE1 3,9,10,11,13 -DEVSEL
MAB#9
MAB#1 RSV8
GAD31 SBA4 GAD27 GAD6 GAD5
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40
SBA3 SBA2 G_C/BE3# G_AD20 G_AD17 G_C/BE2# G_FRAME# G_IRDY# V3_3 AD3 GND GND GND AD8 AD12 C/BE1# DEVSEL# V5_0 C/BE2# V5_0 AD26 AD28 AD29 Reserved13 REQ1# REQ3# REQ4# Reserved14 GND V3_3 MD51 MD52 MD11 MD53 MD14 V3_3 MD62 MD30 V5_0 V5_0
J19E
MAB#6 MAB#7 MAB#10
MAB#3
GAD7 GAD0
GAD8 GC/BE#0
SBA7 SBA0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40
RSV16
GAD22 GAD21 GAD19 GAD28
C
D
SMI# CPURST
MECC2 DQMA7 MECC6 MECC3
MAA6 MAA7 MD25 MD60 DQMA6
CS_B0# -IRDY -PGNT3 -PGNT1
AD23 AD19 AD27 -PCIRST
AD0 MECC1 -SERR AD16
GREQ# GST0 GGNT#
13 9,14
5,6,7 5,6,7 5,6,7 5,6,7
5,6 5,6 5,6,7 5,6,7 5,6,7
5 3,9,10,11,13 3,9 9,10
3,10,11,13 3,10,11,13 3,10,11,13 3,10,11,12,13
3,10,11,13 5,6,7 3,9,10,11,13 3,10,11,13
12 12 12
8
Date:
Size C
Title
8
8
CPUCLK2
CPUCLK0 CPUCLK1
5,6,7 5,6,7 5,6,7 5,6,7 5,6,7 5,6,7
5,6,7 5,6,7
12
E
E
Thursday, February 25, 1999
Document Number {Doc}
CPU Connector
3,10,11,13 9,10,13
3,10,11,13 3,10,11,13 3,10,11,13 3,10,11,13 3,10,11,13 3,9,10,11 3,10,11,13 3,10,11,13 8
GCLK
Note:GFBCLK must be 3.0" longer than GCKOUT
GAD13 GAD12 GAD10 GAD11 GAD9
MD24 MD23 MD55 MD56 MD63 MD31
MD59 MD54
AD25 -PREQ0
AD1 AD5 AD9 AD11 AD14 -PLOCK AD18 AD21 PCICLK7
GFBCLK
GAD23
950554-00x
GND G_REQ# ST0 G_GNT# G_AD13 G_AD12 G_AD10 G_AD11 G_AD9 GND AD0 MECC1 SERR# AD16 V3_3 AD23 AD19 AD27 PCI_RST# GND CSB0# IRDY# GNT3# GNT1# GND GND MAA6 MAA7 MD25 MD60 DQMA6 V3_3 MECC2 DQMA7 MECC6 MECC3 GND SMI# CPU_RST V5_0
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40
950554-00x
GND GCLKIN GCLKO G_AD23 GND G_AD22 G_AD21 G_AD19 G_AD28 AD1 AD5 AD9 AD11 AD14 PLOCK# AD18 AD21 PCLK V5_0 AD25 REQ0# V5_0 MD59 MD54 Reserved16 MD24 MD15 MD55 MD56 MD63 MD31 GND HCLK0 GND HCLK1 GND HCLK2 GND HCLK3 V5_0
SBA7 SBA0 V3_3 G_AD8 G_C/BE0# GND G_AD7 G_AD0 V3_3 MD34 MD5 MD16 MD17 MD20 MD46 GND DQMB1 CSA0# CSB3# MAA1 MAB3# V3_3 GND MAB6# MAB7# MAB10 GND DCLKO V3_3 DQMA3 V3_3 SLP# GND V3_3 FERR# IGNNE# A20M# STPCLK# DB_RST V3_3
J19C
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
950554-00x
G_AD31 SBA4 G_AD27 G_AD6 G_AD5 AD_STBA CLKRUN# MD32 MD35 MD6 MD39 MD18 GND MD21 MD47 V3_3 DQMA2 DQMA5 CSA3# MAB1# Reserved8 WEB# GND MAA3 MAB9# GND MAA9 CKE0 CKE4 MAA10 GND DCLKWR NMI INIT# INTR GND V3_3 PIC_CLK PICD0 GND
C
Sheet
4
of
22
D
Rev
1
2
3
4
1
2
3
4
A
C105 47uF
A
C155 47uF
C226 0.1uF
V3_3
MD[63:0]
CS_B0# DQMA2 DQMA3
SDCLK0
8 SDCLK2
4 CKE1
4 4,6,7 4,6,7
8
WE_A# DQMA0 DQMA1 CS_A0#
MAA[13:0]
4,6,7
4,7 4,6,7 4,6 4
MECC[7:0]
4,6
C228 0.1uF
4,6,7
C175 0.1uF
4,6,7,8,9,14 S M B D A T A 4,6,7,8,9,14 S M B C L K
C199 0.1uF
B
B
C202 0.01uF
MD28 MD29 MD30 MD31
MD24 MD25 MD26 MD27
MD21 MD22 MD23
MD20
MD16 MD17 MD18 MD19
MECC2 MECC3
MAA0 MAA2 MAA4 MAA6 MAA8 MAA10 MAA12
MD14 MD15 MECC0 MECC1
MD9 MD10 MD11 MD12 MD13
MD8
MD4 MD5 MD6 MD7
MD0 MD1 MD2 MD3
C201 0.01uF
C207 0.01uF
A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10
CK1 A12 GND CKE0 /S3 DQMB6 DQMB7 A13 V3_3 NC NC CB6 CB7 GND DQ48 DQ49 DQ50 DQ51 V3_3 DQ52 NC DU REGE GND DQ53 DQ54 DQ55 GND DQ56 DQ57 DQ58 DQ59 V3_3 DQ60 DQ61 DQ62 DQ63 GND CK3 NC SA0 SA1 SA2 V3_3
DQ40 GND DQ41 DQ42 DQ43 DQ44 DQ45 V3_3 DQ46 DQ47 CB4 CB5 GND NC NC V3_3 /CAS DQMB4 DQMB5 /S1 /RAS GND A1 A3 A5 A7 A9 BA0 A11 V3_3
GND DQ32 DQ33 DQ34 DQ35 V3_3 DQ36 DQ37 DQ38 DQ39
SDRAM DIMM
V3_3 CK0 GND DU /S2 DQMB2 DQBM3 DU V3_3 NC NC CB2 CB3 GND DQ16 DQ17 DQ18 DQ19 V3_3 DQ20 NC VREF (NC) CKE1 GND DQ21 DQ22 DQ23 GND DQ24 DQ25 DQ26 DQ27 V3_3 DQ28 DQ29 DQ30 DQ31 GND CK2 NC WP SDA SCL V3_3
DQ8 GND DQ9 DQ10 DQ11 DQ12 DQ13 V3_3 DQ14 DQ15 CB0 CB1 GND NC NC V3_3 WE0 DQMB0 DQMB1 /S0 DU GND A0 A2 A4 A6 A8 A10(AP) BA1 V3_3
GND DQ0 DQ1 DQ2 DQ3 V3_3 DQ4 DQ5 DQ6 DQ7
J18
B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165 B166 B167 B168
B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124
B85 B86 B87 B88 B89 B90 B91 B92 B93 B94
Socket 0
C204 0.01uF
MD60 MD61 MD62 MD63
MD56 MD57 MD58 MD59
MD53 MD54 MD55
MD52
MD48 MD49 MD50 MD51
MECC6 MECC7
MAA12
MAA1 MAA3 MAA5 MAA7 MAA9 MAA11 MAA13
MD46 MD47 MECC4 MECC5
MD41 MD42 MD43 MD44 MD45
MD40
MD36 MD37 MD38 MD39
MD32 MD33 MD34 MD35
R48 0
C
SDCLK3
R52 0
V3_3
CKE0 CS_B1# DQMA6 DQMA7
SDCLK1
SCASA# DQMA4 DQMA5 CS_A1# SRASA#
8
4 4 4,6,7 4,6,7
8
4,7 4,6,7 4,6 4 4,7
D
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N. Date:
Slave address 10100000b
C
DIMM0
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
5
of
22
D
Rev
1
2
3
4
1
2
3
4
C104 47uF
A
C103 47uF
V3_3
A
C182 0.1uF
MD[63:0]
8 SDCLK6
4 CKE3
4 4,5,7 4,5,7
8 SDCLK4
CS_B2# DQMA2 DQMA3
WE_B# DQMA0 DQMA1 CS_A2#
MAA[13:0]
4,5,7
4 4,5,7 4,5 4
MECC[7:0]
4,5
C198 0.1uF
4,5,7
C183 0.1uF
4,5,7,8,9,14 S M B D A T A 4,5,7,8,9,14 S M B C L K
C181 0.1uF
B
MD28 MD29 MD30 MD31
MD24 MD25 MD26 MD27
MD21 MD22 MD23
MD20
MD16 MD17 MD18 MD19
MECC2 MECC3
MAA0 MAA2 MAA4 MAA6 MAA8 MAA10 MAA12
MD14 MD15 MECC0 MECC1
MD9 MD10 MD11 MD12 MD13
MD8
MD4 MD5 MD6 MD7
MD0 MD1 MD2 MD3
Socket 1
B
A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10
CK1 A12 GND CKE0 /S3 DQMB6 DQMB7 A13 V3_3 NC NC CB6 CB7 GND DQ48 DQ49 DQ50 DQ51 V3_3 DQ52 NC DU REGE GND DQ53 DQ54 DQ55 GND DQ56 DQ57 DQ58 DQ59 V3_3 DQ60 DQ61 DQ62 DQ63 GND CK3 NC SA0 SA1 SA2 V3_3
DQ40 GND DQ41 DQ42 DQ43 DQ44 DQ45 V3_3 DQ46 DQ47 CB4 CB5 GND NC NC V3_3 /CAS DQMB4 DQMB5 /S1 /RAS GND A1 A3 A5 A7 A9 BA0 A11 V3_3
GND DQ32 DQ33 DQ34 DQ35 V3_3 DQ36 DQ37 DQ38 DQ39
SDRAM DIMM
V3_3 CK0 GND DU /S2 DQMB2 DQBM3 DU V3_3 NC NC CB2 CB3 GND DQ16 DQ17 DQ18 DQ19 V3_3 DQ20 NC VREF (NC) CKE1 GND DQ21 DQ22 DQ23 GND DQ24 DQ25 DQ26 DQ27 V3_3 DQ28 DQ29 DQ30 DQ31 GND CK2 NC WP SDA SCL V3_3
DQ8 GND DQ9 DQ10 DQ11 DQ12 DQ13 V3_3 DQ14 DQ15 CB0 CB1 GND NC NC V3_3 WE0 DQMB0 DQMB1 /S0 DU GND A0 A2 A4 A6 A8 A10(AP) BA1 V3_3
GND DQ0 DQ1 DQ2 DQ3 V3_3 DQ4 DQ5 DQ6 DQ7
J17
B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165 B166 B167 B168
B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124
B85 B86 B87 B88 B89 B90 B91 B92 B93 B94
R99 0
C
SDCLK7
R108 0
V3_3
CKE2 CS_B3# DQMA6 DQMA7
SDCLK5
SCASB# DQMA4 DQMA5 CS_A3# SRASB#
8
4 4 4,5,7 4,5,7
8
4 4,5,7 4,5 4 4
R125 4.7K
V3_3
D
D
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
Slave address 10100001b
MD60 MD61 MD62 MD63
MD56 MD57 MD58 MD59
MD53 MD54 MD55
MD52
MD48 MD49 MD50 MD51
MECC6 MECC7
MAA12
MAA1 MAA3 MAA5 MAA7 MAA9 MAA11 MAA13
MD46 MD47 MECC4 MECC5
MD41 MD42 MD43 MD44 MD45
MD40
MD36 MD37 MD38 MD39
MD32 MD33 MD34 MD35
C
Date:
Size C
Title
DIMM1
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
6
of
22
D
Rev
1
2
3
4
1
2
3
4
A
C156 47uf
A
8
C128 47uF
C197 0.1uF
MAB#12_R
V3_3
R97
MD[63:0]
8 SDCLK10
4 CKE5
4 4,5,6 4,5,6
8 SDCLK8
10K
CS_B4# DQMA2 DQMA3
WE_A# DQMA0 DQMB1 CS_A4#
MAB#[13:0]
4,5,6
4,5 4,5,6 4 4
MECC[7:0]
4
C176 0.1uF
4,5,6
C174 0.1uF
4,5,6,8,9,14 S M B D A T A 4,5,6,8,9,14 S M B C L K
C227 0.1uF
B
MD28 MD29 MD30 MD31
MD24 MD25 MD26 MD27
MD21 MD22 MD23
MD20
MD16 MD17 MD18 MD19
MECC2 MECC3
MAB#0 MAB#2 MAB#4 MAB#6 MAB#8 MAB#10 MAB#12
MD14 MD15 MECC0 MECC1
MD9 MD10 MD11 MD12 MD13
MD8
MD4 MD5 MD6 MD7
MD0 MD1 MD2 MD3
Socket 2
B
A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10
CK1 A12 GND CKE0 /S3 DQMB6 DQMB7 A13 V3_3 NC NC CB6 CB7 GND DQ48 DQ49 DQ50 DQ51 V3_3 DQ52 NC DU REGE GND DQ53 DQ54 DQ55 GND DQ56 DQ57 DQ58 DQ59 V3_3 DQ60 DQ61 DQ62 DQ63 GND CK3 NC SA0 SA1 SA2 V3_3
DQ40 GND DQ41 DQ42 DQ43 DQ44 DQ45 V3_3 DQ46 DQ47 CB4 CB5 GND NC NC V3_3 /CAS DQMB4 DQMB5 /S1 /RAS GND A1 A3 A5 A7 A9 BA0 A11 V3_3
GND DQ32 DQ33 DQ34 DQ35 V3_3 DQ36 DQ37 DQ38 DQ39
SDRAM DIMM
V3_3 CK0 GND DU /S2 DQMB2 DQBM3 DU V3_3 NC NC CB2 CB3 GND DQ16 DQ17 DQ18 DQ19 V3_3 DQ20 NC VREF (NC) CKE1 GND DQ21 DQ22 DQ23 GND DQ24 DQ25 DQ26 DQ27 V3_3 DQ28 DQ29 DQ30 DQ31 GND CK2 NC WP SDA SCL V3_3
DQ8 GND DQ9 DQ10 DQ11 DQ12 DQ13 V3_3 DQ14 DQ15 CB0 CB1 GND NC NC V3_3 WE0 DQMB0 DQMB1 /S0 DU GND A0 A2 A4 A6 A8 A10(AP) BA1 V3_3
GND DQ0 DQ1 DQ2 DQ3 V3_3 DQ4 DQ5 DQ6 DQ7
J16
B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165 B166 B167 B168
B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 B124
B85 B86 B87 B88 B89 B90 B91 B92 B93 B94
MD60 MD61 MD62 MD63
MD56 MD57 MD58 MD59
MD53 MD54 MD55
MD52
MD48 MD49 MD50 MD51
MECC6 MECC7
MAB#12
MAB#1 MAB#3 MAB#5 MAB#7 MAB#9 MAB#11 MAB#13
MD46 MD47 MECC4 MECC5
MD41 MD42 MD43 MD44 MD45
MD40
MD36 MD37 MD38 MD39
MD32 MD33 MD34 MD35
C
D
CKE4 CS_B5# DQMA6 DQMA7
SDCLK9
SCASA# DQMA4 DQMB5 CS_A5# SRASA#
8
R126 4.7K
V3_3
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
SDCLK11
R106 0
4 4 4,5,6 4,5,6
8
4,5 4,5,6 4 4 4,5
Note: J16 is not popula ted
R100 V3_3 0
Slave address 10100010b
C
DIMM2
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
7
of
22
D
Rev
1
2
3
4
1
2
3
4
7
MAB#12_R
R35 R33 R37
0 0 0
BXDCLKO
4,5,6,7,9,14 S M B D A T A 4,5,6,7,9,14 S M B C L K
4
A
CONFIG1
This circuit is only used for BX/PentiumII Designs. Note three DIMMS are supported.
14 CPU_STOP# 14 PCI_STOP# 1 4 SUSA#
Stuff only to enable stopping of clocks
2.7K
R20
J14 HDR2
C165 0.01uF
V3_3
24 25
1 2 47 48
38
11
SDATA SCLK
NC NC NC NC
OE
CY2318NZ
CLK_IN
U16
SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM13 SDRAM14 SDRAM15 SDRAM16 SDRAM17
4 5 8 9 13 14 17 18 31 32 35 36 40 41 44 45 21 28
B
1
2
C101 0.01uF
0 0 0 0 0 0 0
R120 R118 R115 R113 R111 R109 R122
SDCLKR10 SDCLKR11 SDCLKR7 SDCLKR6 SDCLKR4 SDCLKR5
B
0 0 0 0 0 0
R110 R112 R114 R116 R119 R121
SDCLKR0 SDCLKR1 SDCLKR2 SDCLKR3 SDCLKR8 SDCLKR9
C223 0.01uF
C100 10pf
14.318MHz
C217 0.01uF
C99 10pf
Y1
C169 0.01uF
C213 0.01uF
RP22 10K
C173 0.01uF
Keep crystal close to cl ock and caps close to crystal. All lead lengths should be equal.
J15 JUMP2
RP20 10K
C93 47uF
V3_3
8 7 6 5
1 2 3 4
A
1
2
1
2
C170 0.01uF
XTALIN XTALOUT
RESERVED
SEL0 SEL1 SEL100 SEL_SS#
CPU_STOP# PCI_STOP# PWR_DWN#
U6
C221 0.01uF
4 5
42
27 26 25 28
30 31 29
C171 0.01uF
15 9 21 48 19 33 CY2280
VDDPCI VDDPCI VDDUSB VDDREF AVDD AVDD
8 7 6 5 1 2 3 4
3 7 12 16 20 23 29 33 37 42 46
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
6 10 15 19 22 26 27 30 34 39 43
37 41 46 VDDCPU VDDCPU VDDAPIC
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS SDCLK10 SDCLK11 SDCLK7 SDCLK6 SDCLK4 SDCLK5 BxFBCLK
SDCLK0 SDCLK1 SDCLK2 SDCLK3 SDCLK8 SDCLK9
C212 0.01uF
7 7 6 6 6 6 4
5 5 5 5 7 7
C225 0.01uF
C224 0.01uF
APIC0 APIC1
REF0 REF1 REF2
USBCLK0 USBCLK1
PCICLK_F PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 PCI_CLK6 PCI_CLK7
CPUCLK0 CPUCLK1 CPUCLK2 CPUCLK3
4,14 CONFIG1
C220 0.01uF
3 6 12 18 20 24 32 34 38 43
C211 0.01uF
C
74HCT14
2
C149 15uF
CONFIG1#
C148 15uF
C163 0.01uF
V2.5
1
2 4
L T 1 17
Adj/GND
Out In OutTab
3 C162 0.1uF
V5_0
C94 10uF
CPUCLK3
APICCLK0 APICCLK1
REF0 REF1 REF2
USBCLK0
PCLKAPIC PCICLK7
PCICLKF PCICLK1 PCICLK2 PCICLK3 PCICLK4
CPUCLK0 CPUCLK1 CPUCLK2
13 4
18 16 14
14
13 4
14 10 10 11 3
4 4 4
SDCLKR6 SDCLKR7
CPUCLK3 SDCLKR5 SDCLKR4
1 2 3 4 5 6 7 8
U26 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 Zero Delay Buffer
Ref CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
16 15 14 13 12 11 10 9
D
Date:
E
Clocks
SDCLKR2 SDCLKR3
SDCLKR0 SDCLKR1
C209 10pF
E
Thursday, February 25, 1999
Document Number {Doc}
C214 10pF
Sheet
These caps can be tuned to change delay through buffer.
Note: R11 and R12 should be placed as close as possible to U1
R16 124 1%
R15 124 1%
U5
This circuit is only used for TX/Pentium Designs. Note only two DIMMS are supported.
C95 100uF
TP17
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
C216 0.01uF
1
33 33
R19 R22
APICCLKR_0 APICCLKR_1
45 44
U21A
33 33 33
R18 R21 R17
REFR_0 REFR_1 REFR_2
1 2 47
C150 15uF
33
R38
USBCLKR_0
C222 0.01uF
33 33
R34 R36
PCICLKR_6 PCICLKR_7
22 23
33 33 33 33 33
R23 R26 R28 R30 R32
PCICLKF_R PCICLKR_1 PCICLKR_2 PCICLKR_3 PCICLKR_4
7 8 10 11 13 14 16 17
33 33 33 33
R24 R27 R29 R31
V3_3
V2.5
C164 0.01uF
CPUCLKR_0 CPUCLKR_1 CPUCLKR_2 CPUCLKR_3
C168 0.01uF
40 39 36 35
C
TP 1
8
of
22
D
Rev
1
2
3
4
1
2
3
4
LA[23:17]
IRQ6 IRQ7 IRQ9 IRQ10
IRQ11 IRQ12 IRQ14 IRQ15
13,14,16,18 13,14,16,18 13,14,18 13,14,16,18
13,14,18 13,14,16,18 13,14,15,16,18 13,14,15,16,18
14,18 D R Q 5 14,18 D R Q 6 14,18 D R Q 7
14,16,18 D R Q 0 14,16,18 D R Q 1 14,16,18 D R Q 2 14,16,18 D R Q 3
IRQ1 IRQ3 IRQ4 IRQ5
13,14,16 13,14,16,18 13,14,16,18 13,14,16,18
Note IRQ8 Pull-up is on PIIX4 page
13,18
13,16,18,20 SA[19:0]
13,16,18,20 SD[15:0]
A
A
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
SA8 SA9 SA10 SA11
SA12 SA13 SA14 SA15
SA16 SA17 SA18 SA19
LA17 LA18 LA19 LA20
LA21 LA22 LA23
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
SD12 SD13 SD14 SD15
SA4 SA5 SA6 SA7
1 2 3 4
SD8 SD9 SD10 SD11
1 2 3 4
1 2 3 4
SD4 SD5 SD6 SD7
SA0 SA1 SA2 SA3
1 2 3 4
SD0 SD1 SD2 SD3
5.6K
5.6K RP34
10K RP12
10K RP26
10K RP14
RP16
10K
10K RP24
10K RP27
10K RP11
10K RP13
10K RP15
10K RP17
RP19
10K
10K RP35
10K RP33
10K RP8
RP9
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
ISA Pullup s V5_0
MEMW# IOW# MEMR# IOR#
13,18 13,18 13,18 13,18
B
SMEMW# SMEMR# SBHE# BALE
13,18 IOCS16# 13,18 M E M C S 1 6 # 13,18 IOCHK#
13,18 REFRESH# 18 MASTER16# 13,16,18 IOCHRDY 13,18 Z E R O W S #
13,18,20 13,16,18,20 13,18,20 13,16,18
B
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
10K
RP21
1K
RP23
1K
10K RP10
RP29
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
-IRDY -TRDY -DEVSEL - S T OP
-PERR -SERR PAR -FRAME
SDONE -SBO REQ64# ACK64#
10,11 10,11 10,11 10,11
-PHOLD -PHOLDA
3,4 4,10 4,10 4,11
-PGNT3 -PGNT0 -PGNT1 -PGNT2
4 -PGNT4
4,13 4,13
3,4,10,11 - P L O C K 4 -PREQ4
-PREQ0 -PREQ1 -PREQ2 -PREQ3
4,10,13 4,10,13 4,11,13 3,4,13
3,10,11,13,14 PIRQA# 3,10,11,12,13,14 PIRQB# 3,10,11,12,13,14 PIRQC# 3,10,11,13,14 PIRQD#
3,4,10,11,13 3,4,10,11,13 3,4,10,11,13 3,4,10,11,13
3,10,11 3,4,10,11,13 3,4,10,11,13 3,4,10,11,13
APICD1
IGNNE#
A20M#
4,14 NMI 4,13,14 INTR 4,14 FERR# 4,14 STPCLK#
4,14
4,14
INIT CPURST
4,13 4,14 4,14
APICD0
4,13
1 2 3 4
R43
10K
C
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
1 2 3 4
1 2 3 4
1 2 3 4
2.7K
2.7K RP37
RP40
2.7K
RP38
8 7 6 5
8 7 6 5
8 7 6 5
1K 1K
124
R46 R45 R49
124
R47
V3_3
V5_0
V2.5
V3_3
D
D
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
8 7 6 5
10K
10K 10K
2.7K 2.7K
RP51
2.7K
RP25
10K
RP52
2.7K
RP49
2.7K
2.7K RP53
RP50
R41 R40
R71 R44
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
PCI Pullu ps
4,14 SLP# 13,14 APICCS# 4,5,6,7,8,14 S M B D A T A 4,5,6,7,8,14 S M B C L K
C
Date:
Size C
Title
ISA/PCI Pullups
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
9
of
22
D
Rev
1
2
3
4
1
2
3
4
A
| A1, A3, A4
J7/J8 +12V: -12V:
C77 0.01uF
A2 B1
A
8 PCICLK1
C80 0.01uF
-C/BE[3:0]
AD[31:0]
9,11 A C K 6 4 #
3,4,9,11 - P L O C K 3,9,11 -PERR 3,4,9,11,13 -SERR
3,4,9,11,13 -DEVSEL
3,4,9,11,13 -IRDY
4,9,13
PCICLK1
-PREQ0
3,9,11,12,13,14 PIRQB# 3,9,11,13,14 PIRQD#
1 1 PCI_TCLK
3,4,11,13 -C/BE[3:0]
3,4,11,13 AD[31:0]
J7/J8 GN D: A12, A13, A18, A24, A30, A35, A37, A42, A48, A56 B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, B57
J7/J8 N C: A9, A11, A1 4, A19 B10, B14
J7/J8 V3_ 3: A21, A27, A33, A39 A45, A53 B25, B31, B36, B41, B43, B54
J7/J8 V5_ 0: A5, A8, A10, A16, A59, A61, A62 B5, B6, B19, B22, B59, B61, B62
-C/BE0
-C/BE1
-C/BE2
-C/BE3
AD1
AD5 AD3
AD8 AD7
AD12 AD10
AD14
AD17
AD21 AD19
AD23
AD27 AD25
AD31 AD29
C55 10uF
B
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
C116 0.1uF
B
J7
C73 0.1uF
C/BE0 V3_3 AD[06] AD[04] GND AD[02] AD[00] V5_0 REQ64 V5_0 V5_0
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
C113 0.01uF
TRST +12V TMS TDI V5_0 INTA INTC V5_0 NC V5_0 NC GND GND NC RST V5_0 GNT GND NC AD[30] V3_3 AD[28] AD[26] GND AD[24] IDSEL V3_3 AD[22] AD[20] GND AD[18] AD[16] V3_3 FRAME GND TRDY GND STOP V3_3 SDONE SBO GND PAR AD[15] V3_3 AD[13] AD[11] GND AD[09]
PCI SLOT 0
PCI Conn
AD[08] AD[07] V3_3 AD[05] AD[03] GND AD[01] V5_0 ACK64 V5_0 V5_0
-12V TCK GND TDO V5_0 V5_0 INTB INTD PRSNT1 NC PRSNT2 GND GND NC GND CLK GND REQ V5_0 AD[31] AD[29] GND AD[27] AD[25] V3_3 C/BE3 AD[23] GND AD[21] AD[19] V3_3 AD[17] C/BE2 GND IRDY V3_3 DEVSEL GND LOCK PERR V3_3 SERR V3_3 C/BE1 AD[14] GND AD[12] AD[10] GND
C85 0.1uF
V5_0
C66 0.01uF
AD2 AD0
AD6 AD4
AD9
AD13 AD11
AD15
AD18 AD16
AD22 AD20
AD24
AD28 AD26
AD30
C119 10uF
REQ64#
SDONE -SBO PAR
C
9,11
-PREQ1
-PLOCK -PERR -SERR
-DEVSEL
-IRDY
C78 0.01uF
C81 0.01uF
AD1
AD5 AD3
AD8 AD7
AD12 AD10
AD14
AD17
AD21 AD19
AD23
AD27 AD25
-C/BE0
ACK64#
-C/BE1
-C/BE2
-C/BE3
AD31 AD29
PIRQA# PIRQC#
PCI_TCLK
C56 10uF
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
J8
C114 0.1uF
V5_0
C/BE0 V3_3 AD[06] AD[04] GND AD[02] AD[00] V5_0 REQ64 V5_0 V5_0
TRST +12V TMS TDI V5_0 INTA INTC V5_0 NC V5_0 NC GND GND NC RST V5_0 GNT GND NC AD[30] V3_3 AD[28] AD[26] GND AD[24] IDSEL V3_3 AD[22] AD[20] GND AD[18] AD[16] V3_3 FRAME GND TRDY GND STOP V3_3 SDONE SBO GND PAR AD[15] V3_3 AD[13] AD[11] GND AD[09]
C86 0.1uF
PCI SLOT 1
PCI Conn
AD[08] AD[07] V3_3 AD[05] AD[03] GND AD[01] V5_0 ACK64 V5_0 V5_0
-12V TCK GND TDO V5_0 V5_0 INTB INTD PRSNT1 NC PRSNT2 GND GND NC GND CLK GND REQ V5_0 AD[31] AD[29] GND AD[27] AD[25] V3_3 C/BE3 AD[23] GND AD[21] AD[19] V3_3 AD[17] C/BE2 GND IRDY V3_3 DEVSEL GND LOCK PERR V3_3 SERR V3_3 C/BE1 AD[14] GND AD[12] AD[10] GND
C117 0.1uF
D
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
C74 0.01uF
PIRQD# PIRQB#
PCI_TMS PCI_TDI
AD2 AD0
AD6 AD4
AD9
AD13 AD11
AD15
AD18 AD16
AD22 AD20
AD24
AD28 AD26
AD30
PCI_TRST
C67 0.01uF
D
C91 0.1uF
V3_3
SDONE -SBO PAR
-STOP
-TRDY
-FRAME
-PGNT1
-PCIRST
C120 10uF
4,9
PCIB2
AD29 R13 220
E
Thursday, February 25, 1999
Document Number {Doc}
E
C107 0.1uF
PCI Slots 0 & 1
REQ64#
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
9,11 9,11 3,4,9,11,13
3,4,9,11,13
3,4,9,11,13
-STOP
-TRDY
R12 220
3,4,9,11,13
PCIA2
-FRAME
-PGNT0
3,4,11,12,13 8 PCICLK2 4,9 4,9,13
3,9,11,13,14 3,9,11,12,13,14
PIRQA# PIRQC#
-PCIRST
11 11
PCI_TMS PCI_TDI
11
C90 0.1uF
AD28
PCI_TRST
C106 0.1uF
V3_3
C
Sheet
10
of
22
D
Rev
1
2
3
4
1
2
3
4
C79 0.01uF
1 0 PCI_TCLK
3,4,10,13 -C/BE[3:0]
3,4,10,13 AD[31:0]
C82 0.01uF
-PREQ2
PCICLK3
A
9,10 A C K 6 4 #
3,4,9,10 - P L O C K 3,9,10 -PERR 3,4,9,10,13 -SERR
3,4,9,10,13 -DEVSEL
3,4,9,10,13 -IRDY
4,9,13
8
3,9,10,13,14 PIRQD# 3,9,10,12,13,14 PIRQB#
A
-C/BE[3:0]
AD[31:0]
C57 10uF
-C/BE0
-C/BE1
-C/BE2
-C/BE3
C87 0.1uF
AD1
AD5 AD3
AD8 AD7
AD12 AD10
AD14
AD17
AD21 AD19
AD23
AD27 AD25
AD31 AD29
C75 0.1uF
V5_0
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
C118 0.1uF
C115 0.01uF
C/BE0 V3_3 AD[06] AD[04] GND AD[02] AD[00] V5_0 REQ64 V5_0 V5_0
TRST +12V TMS TDI V5_0 INTA INTC V5_0 NC V5_0 NC GND GND NC RST V5_0 GNT GND NC AD[30] V3_3 AD[28] AD[26] GND AD[24] IDSEL V3_3 AD[22] AD[20] GND AD[18] AD[16] V3_3 FRAME GND TRDY GND STOP V3_3 SDONE SBO GND PAR AD[15] V3_3 AD[13] AD[11] GND AD[09]
B
PCI SLOT 2
PCI Conn
AD[08] AD[07] V3_3 AD[05] AD[03] GND AD[01] V5_0 ACK64 V5_0 V5_0
-12V TCK GND TDO V5_0 V5_0 INTB INTD PRSNT1 NC PRSNT2 GND GND NC GND CLK GND REQ V5_0 AD[31] AD[29] GND AD[27] AD[25] V3_3 C/BE3 AD[23] GND AD[21] AD[19] V3_3 AD[17] C/BE2 GND IRDY V3_3 DEVSEL GND LOCK PERR V3_3 SERR V3_3 C/BE1 AD[14] GND AD[12] AD[10] GND
J9
C68 0.01uF
B
A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
C121 10uF
C108 0.1uF
V3_3
AD2 AD0
AD6 AD4
AD9
AD13 AD11
AD15
AD18 AD16
AD22 AD20
AD24
AD28 AD26
AD30
C92 0.1uF
REQ64#
SDONE -SBO PAR
-STOP
-TRDY
-FRAME
PCIC2
AD30
-PGNT2
9,10
9,10 9,10 3,4,9,10,13
3,4,9,10,13
3,4,9,10,13
3,4,9,10,13
R14 220
4,9
3,4,10,12,13
C
3,9,10,12,13,14 3,9,10,13,14
-PCIRST
10 10
PIRQC# PIRQA#
10
PCI_TMS PCI_TDI
PCI_TRST
C
R69 4.7K
PCI_TRST
PCI_TMS
R66 4.7K
R68 4.7K PCI_TCLK
R67 4.7K
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
PCI_TDI
V5_0
D
PCI Slot 2
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
11
of
22
D
Rev
1
2
3
4
1
2
3
4
3,9,10,11,13,14 PIRQC#
R87
R77
R76
R78
R79
R80
R82
R81
R72
R73
R74
R75
R86
R84
GAD_STB0
GAD_STB1
GSB_STB
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GREQ#
GGNT#
GPIPE#
GRBF#
GPAR
GPME#
A
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
V3_3
V3.3SUS
Stub length from connector to resistor must be less than 0.1"
A
2
74AS07
U2A
V3_3
7
1
14
V5_0
B
4 GC/BE#[3:0]
4 GAD[31:0]
4 GAD_STB0
R85
R83
4 GDEVSEL#
4 GIRDY#
4 GAD_STB1
4 GSB_STB
4 GST0 4 GST2 4 GRBF#
4 GCLK 4 GREQ#
4 SBA[7:0]
R64 4.7K
V3_3
B
8.2K
8.2K
SBA4 SBA6
SBA2
SBA0
GAD1
GAD5 GAD3
GAD7
GAD10 GAD8
GAD14 GAD12
GC/BE#1
GAD17 GC/BE#2
GAD21 GAD19
GAD23
GAD27 GAD25
GAD31 GAD29
V5_0
V3_3
C
J13
AD31 AD29 3.3V AD27 AD25 GND AD_STB1 AD23 VDDQ3.3 AD21 AD19 GND AD17 C/BE2# VDDQ3.3 IRDY# SPARE GND SPARE 3.3V DEVSEL# VDDQ3.3 PERR# GND SERR# C/BE1# VDDQ3.3 AD14 AD12 GND AD10 AD8 VDDQ3.3 AD_STB0 AD7 GND AD5 AD3 VDDQ3.3 AD1 SMB0
OVRCNT# 5.0V 5.0V USB+ GND INTB# CLK REQ# 3.3V ST0 ST2 RBF# GND SPARE SBA0 3.3V SBA2 SB_STB GND SBA4 SBA6
AGP Connector
AD30 AD28 3.3V AD26 AD24 GND RESERVED C/BE3# VDDQ3.3 AD22 AD20 GND AD18 AD16 VDDQ3.3 FRAME# NC GND NC 3.3V TRDY# STOP# PME# GND PAR AD15 VDDQ3.3 AD13 AD11 GND AD9 C/BE0# 3.3V RESERVED AD6 GND AD4 AD2 VDDQ3.3 AD0 SMB1
12V SPARE RESERVED USBGND INTA# RST# GNT# 3.3V ST1 RESERVED PIPE# GND SPARE SBA1 3.3V SBA3 RESERVED GND SBA5 SBA7
C186 0.01uF
A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
C185 0.01uF
C179 0.01uF
C178 0.01uF
D
C166 0.01uF
C167 0.01uF
C177 0.01uF
+12V V3_3
GAD0
GAD4 GAD2
GAD6
GAD9 GC/BE#0
GAD13 GAD11
GAD15
GAD18 GAD16
GAD22 GAD20
GC/BE#3
GAD26 GAD24
GAD30 GAD28
SBA5 SBA7
SBA3
SBA1
GPAR
GTRDY# GSTOP# GPME#
GFRAME#
GPIPE#
GST1
-PCIRST GGNT#
4
4
4 4 14
4
4
D
Date:
Size C
Title
R65 4.7K
V3_3
C172 0.01uF
3,4,10,11,13 4
Pin A3 is tied to ground per AGP Specification Rev 1.0
C184 0.01uF
V3_3
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21
C
74AS07
U2B 4
PIRQB#
E
Sheet
AGP Connector Thursday, February 25, 1999
Document Number
7
3
14
V5_0
C180 0.01uF
E
12
of
22
3,9,10,11,13,14
D
Rev
1
2
3
4
1
2
3
4
1 5 PDD[15:0]
Place near PIIX4
3,4,10,11,12 -PCIRST
PIIX4 is PCI device #8
AD18
C229 47pF
A
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15
-PREQ0 -PREQ1 -PREQ2 -PREQ3
SDA0 SDA1 SDA2 PDDACK# SDDACK# PDREQ SDREQ PDIOR# PDIOW# PIORDY SDIOR# SDIOW# SIORDY PDA0 PDA1 PDA2
4,9,10 4,9,10 4,9,11 3,4,9
4,9 -PHOLD 4,9 -PHOLDA 3,4,9,10,11 -SERR 3,4,9,10,11 - S T O P 3,4,9,10,11 -TRDY
3,4,9,10,11 -IRDY 3,4,9,10,11 PAR
3,4 CLKRUN# R _ A D 1 8 3,4,9,10,11 -DEVSEL 3,4,9,10,11 - F R A M E
3,4,10,11 -C/BE[3:0]
R39 220
3,4,10,11 AD[31:0]
A
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
-C/BE0 -C/BE1 -C/BE2 -C/BE3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C17 B17 A18 G19 A17 F18 A16 F17 F16 G20 C16 B16 D16 G16 G18 G17
F20 E18 E20 D18 D20 C20 B20 A20 A19 B19 C19 D19 D17 E19 E17 F19
E10 A11 B11 C11
C10 E5 A5 A3 B5 B6 A1 B12 A12 A6 D5 C5
C8 C6 D4 D2
B10 A10 D9 C9 B9 A9 D8 E8 B8 A8 D7 C7 B7 A7 D6 E6 E4 C4 B4 A4 D3 E3 C3 B3 E2 C2 B2 A2 D1 E1 C1 B1
U8A
PIIX4E
SDA0 SDA1 SDA2 PDDACK# SDDACK# PDREQ# SDREQ# PDIOR# PDIOW# PIORDY SDIOR# SDIOW# SIORDY PDA0 PDA1 PDA2
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
REQ0# REQ1# REQ2# REQ3#
CLOCKRUN# DEVSEL# FRAME# IDSEL IRDY# PAR PCIRST# PHOLD# PHOLDA# SERR# STOP# TRDY#
C/BE#0 C/BE#1 C/BE#2 C/BE#3
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
B
IDE SIGNALS
IDE SIGNALS
ISA/EIO SIGNALS
PIIX4
PCI SIGNALS
B
SBHE# RSTDRV IOR# IOW# IOCHRDY AEN
REFRESH# IOCS16# ZEROWS#
SMEMW# SYSCLK GPO0/BALE GPI0/IOCHK#
MEMCS16# MEMR# MEMW# SMEMR#
GPO1/LA17 GPO2/LA18 GPO3/LA19 GPO4/LA20 GPO5/LA21 GPO6/LA22 GPO7/LA23
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19
DS3S# DS3P# DS1S# DS1P#
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
LA17 LA18 LA19 LA20 LA21 LA22 LA23
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
14 XOE# 1 4 XDIR#
SBHE# RSTDRV IOR# IOW# IOCHRDY AEN
REFRESH# IOCS16# ZEROWS#
SMEMW# SYSCLK BALE IOCHK#
MEMCS16# MEMR# MEMW# SMEMR#
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
SDCS3# PDCS3# SDCS1# PDCS1#
9,18 16,18 9,16,18 9,16,18,20 9,16,18 16,18,20
9,18 9,18 9,18
9,18 18 9,18 9,18
9,18 9,18,20 9,18,20 9,18
LA[23:17]
SD[15:0]
SA[19:0]
15 15 15 15
SDD[15:0]
C
V5_0
15
8 7 6 5 10K
RP59
19 1
2 3 4 5 6 7 8 9 B1 B2 B3 B4 B5 B6 B7 B8
10K
PCLKAPIC
8
7
2
14
2
U15A 74LVC125
3
D4 Bat54
RSTDRV
SA4 SA0 SA1 MEMR# MEMW#
I13R I21R I22R
RSTDRV
APICCS# APICREQ# APICACK1# WSC#
9,14
18 17 16 15 14 13 12 11
14 14 4
1 2 3 4
74ALS245
G DIR
A1 A2 A3 A4 A5 A6 A7 A8
U7
R117
V3.3SUS
IRQ#8
9,18
9,16,18,20
9,16,18,20
RSTDRV
D
IRQ8_Buf
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
3
7 20 32 36 45 46 47 48 49 63
3
2 60
9 10 8
15 13 14 12 11 61
59 58 57 56 55 54 53 50
74HCT14
U21B
82093AA
NC NC NC NC NC NC NC NC NC NC
TESTIN#
PCICLK RESET
20
RSTDRV#
D
15
E
V5_0
17 34 35 25 26 27 28 29 31 30 24 23 22 16 18 21 37 38 39 40 41 42 43 44 6
4 5 62
C215 0.1uF
E
Thursday, February 25, 1999
Document Number {Doc}
PIIX4 Part 1
INTIN0 INTIN1 INTIN2 INTIN3 INTIN4 INTIN5 INTIN6 INTIN7 INTIN8 INTIN9 INTIN10 INTIN11 INTIN12 INTIN13 INTIN14 INTIN15 INTIN16 INTIN17 INTIN18 INTIN19 INTIN20 INTIN21 INTIN22 INTIN23/SMI# SMIOUT#
APICD0 APICD1 APICCLK
C203 0.1uF
1K
Sheet
1K
13
of
22
D
Rev
1
14
PX4_SMI#
R51
9,14,15,16,18 9,14,15,16,18 3,9,10,11,14 3,9,10,11,12,14 3,9,10,11,12,14 3,9,10,11,14 14
IRQ14 IRQ15 PIRQA# PIRQB# PIRQC# PIRQD# IRQ9OUT#
V2.5
9,14,18 9,14,16,18 9,14,18 9,14,16,18
IRQ9 IRQ10 IRQ11 IRQ12
4
4,9,14 9,14,16 14 9,14,16,18 9,14,16,18 9,14,16,18 9,14,16,18 9,14,16,18
INTR IRQ1 IRQ0 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
SMI#
4,9 4,9 8
2
3
4
APICD0 APICD1 APICCLK0
R50
JUMP3
2
J23
I21R I22R
I13R
IRQ8_Buf
C210 0.1uF
Note: U14, C203,C215, C210 , R50 and R51 are not popula ted
XD[7:0]
APICREQ# APICACK1# APICACK2#
D/I# A0 A1 RD# WR# CS#
D0 D1 D2 D3 D4 D5 D6 D7
U14
4
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N. Date:
14
This circuit is to prevent IOAPIC from being powered by IRQ#8 when in suspend and power is not applied to device.
W12 W1 Y5 T4 T3 Y4
W7 V12 Y3
U3 T7 U10 Y1
Y12 V15 U15 W4
Y15 T14 W14 U13 V13 Y13 T12
V3 W3 U2 T2 W2 Y2 T1 V1 W16 T16 Y17 V17 Y18 W18 Y19 W19
U11 T11 W11 Y11 T10 W10 U9 V9 Y9 T8 W8 U7 V7 Y7 V6 Y6 T5 W5 U4 V4
C18 H16 B18 H17
E15 B15 D14 C14 A14 C13 A13 C12 D12 B13 D13 B14 E14 A15 C15 D15
C
1 3 1
64 19 51 VCC VCC VCC GND GND GND 1 33 52
1 3
1
2
Bat54
BT1 BATTERY
D6
3
CPU Module must drive CONFIG1l to indicate processor type. 3.3V = PentiumII 0V = Pentium
V3_3
8 7 6 5
1
A
2
C147 0.1uF
D7 Bat54
V3.3SUS
Trace lengths should be equal
IRQ0 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ#8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15
TC APICACK1# APICCS# APICREQ#
DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7
DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7#
SLP# CPURST FERR# IGNNE# INIT INTR KBDA20GATE NMI PX4_SMI# STPCLK# KBDRST# A20M# PWROK SPKR
Y2 32.768KHz
13 XOE# 1 3 XDIR# 2 0 BIOSCS#
4,8 CONFIG1
4,9 4,9 4,9 4,9 4,9 4,9,13 16 4,9 13 4,9 16 4,9 4,21 21
R63 1K
JUMP3
2
J24
1-2 Normal Operation 2-3 Clear CMOS
10pF
C133
10pF
C132
16,18 13 9,13 13
13 9,13,16 9,13,16,18 9,13,16,18 9,13,16,18 9,13,16,18 9,13,16,18 13 9,13,18 9,13,16,18 9,13,18 9,13,16,18 9,13,15,16,18 9,13,15,16,18
10K
1 2 3 4
9,16,18 9,16,18 9,16,18 9,16,18 9,18 9,18 9,18 RP30
16,18 16,18 16,18 16,18 18 18 18
B
C193 0.1uF
REF2 PCICLKF
8 8
B
SUSCLK USBCLK0
4 8
CONFIG2
TEST#
SERIRQ
C191 0.1uF
V3_3
C188 0.1uF
V11 D11
P17 L3
R20 N19 L16
M4 M3 M2 L1 K2 K1
K20 M19 K19 L17 L18 L19 P1 L20 P20 J18 N20 M20 M18 K17 V18 R17 R18
J19 R3 R4 P5 G1
H20 J20 T9 W9 U8 V8 Y8 Y20 U1 U12 W13 T13 V14 Y14
V10 J17 H18 K18
M1 N2 P3 N1 P2 P4
W15 U6 V2 U5 Y16 U16 U17
U14 W6 Y10 V5 T15 V16 W17
C187 0.1uF
U8B
C190 0.1uF
PIIX4E
OSC PCICLK
SUSCLK 48Mhz
RTCX2 RTCX1 VBAT
XOE#/GPO23 XDIR#/GPO22 BIOSCS# RTCALE/GPO25 RTCCS#/GPO24 KBCCS#/GPO26
SLP# CPURST FERR# IGNNE# INIT INTR A20GATE# NMI SMI# STPCLK# RCIN# A20M# PWROK SPKR TEST# CONFIG1 CONFIG2
SERIRG/GPI7 PIRQA# PIRQB# PIRQC# PIRQD#
IRQ0/GP014 IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8/GPI6 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15
TC APICACK#/GPO12 APICCS#/GPO13 APICREQ#/GP15
REQA#/GPI2 REQB#/GPI3 REQC#/GPI4 GNTA#/GPO9 GNTB#/GPO10 GNTC#/GPO11
DREQ0 DREQ1 DREQ2 DREQ3 DREQ5 DREQ6 DREQ7
DACK0# DACK1# DACK2# DACK3# DACK5# DACK6# DACK7#
C192 0.1uF
SYSTEM
CPU INTERFAC E
X-BUS
VSSUSB J5
C
K5 N16 R16
C
USBP1+ USBP1USBP0+ USBP0OC0# OC1# EXTSMI# SUSA# GPO15/SUSB# GPO16/SUSC#
C194 0.1uF
V3.3SUS
L4 N5
N4
J4 N18 N3 M16 M5 R5
G4 T19 G5 F2 F3 F4
P19 L2 J3 L5 K3 K4 H1 H4 H5 G3
J16
R1 R2 K16 T17 T18 H19 U19 M17 U20 P16 T20 R19 N17 P18
V20 W20 V19 U18
F1 H2 G2 H3 J1 J2
TP4
LID
T P 15 TP5 TP3
C129 0.1uF
SMBALERT#
1 2 3 4
1
IRQ9OUT#
13
RP31 10K 8 7 6 5
R42 1K
8 7 6 5
1 2 3 4
10K
1 2 3 4
RP28 10K 8 7 6 5
3
RP32
D3 Bat54
12
GPME#
V5_0
4,5,6,7,8,9 4,5,6,7,8,9
SMBDATA SMBCLK
BATLOW#
C134 10uF
T P 13
21 21
8 8 4 4
TP11
RSMRST# PWRBTN#
CPU_STOP# PCI_STOP# ZZ SUS_STAT1#
8
SUSA#
THERM# BATLOW#
EXTSMI#
17 17 17 17 17 17
USBP1+ USBP1USBP0+ USBP0OC0# OC1#
D
10
V3.3SUS
7 4 L C T 14
U24E
V3_3
7
11
14
V3.3SUS
SMBALERT# T E ST# CONFIG2 IRQ#8
SERIRQ THERM# LID EXTSMI#
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
PCS0# PCS1#
MCCS#
N/C N/C N/C N/C N/C N/C
GPO0 GPO8 GPO27 GPO28 GPO29/IRQ9Out GPO30
GPI1 GPI13 GPI14 GPI15 GPI16 GPI17 GPI18 GPI19 GPI20 GPI21
VREF
GPO17/CPU_STP# GPO18/PCI_STP# GPO19/ZZ GPO20/SUS_STAT1# GPO21/SUS_STAT2# GPI8/HCT# GPI9/BATLOW# RSMRST# PWRBT# GPI10/LID SMBDATA SMBCLK GPI11/SMBALERT# GPI12/RI#A
USB SIGNALS
POWER MGMT.
PIIX4
DMA/IRQ SIGNALS
VSS - D10,E7,E13, J[9:12] K[9:12],L[9:12], M[9:12]
C189 0.1uF
R15 R6 F15 E11 F6 VCC VCC VCC VCC VCC
T6 P15 R7 G6 F14 F5 E16 E12 E9 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
C195 0.1uF
3,9,10,11,13 PIRQA# 3,9,10,11,12,13 PIRQB# 3,9,10,11,12,13 PIRQC# 3,9,10,11,13 PIRQD#
Keep crystal close to PIIX4 and caps close to crystal
A
TP 1
3
2
TP
1
TP 1
4
1
2
1
3
3
1
2
1
TP
1
TP 1
VCCSUSB VCCSUS VCCSUS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSUSB D10 E7 E13 J9 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 M12 J5
TP 1
2
RP36 10K 8 7 6 5
RP39 10K 8 7 6 5
E
Thursday, February 25, 1999
Document Number {Doc}
1 2 3 4
1 2 3 4
21
PIIX4 Part 2
PWRON#
E
Sheet
14
V3.3SUS
of
V3_3
22
D
Rev
1
2
3
4
1
2
3
13 13 13 13
PDA2 SDA2 PDCS3# SDCS3#
1 3 PIORDY 9,13,14,16,18 IRQ14 1 3 SIORDY 9,13,14,16,18 IRQ15
R102 1K
A
V5_0
1 2 3 4
1 2 3 4
R101 1K
RP54 33
RP57 47
8 7 6 5
8 7 6 5
PDA2R SDA2R PDCS3#R SDCS3#R
PDIORDYR PDIRQR SDIORDYR SDIRQR
PDREQ PDIOW# PDIOR# PDDACK# 13 13 13 13
PDA1 PDA0 PDCS1# RSTDRV#
R107 8.2K
1 2 3 4
RP58 33 8 7 6 5 1 2 3 4
RP60
RP55 33
PDD3 PDD2 PDD1 PDD0
PDD7 PDD6 PDD5 PDD4
13 13 13 13
SDREQ SDIOW# SDIOR# SDDACK#
R96 8.2K
13 SDA1 13 SDA0 13 SDCS1#
1 3 SDD[15:0]
1 2 3 4
B
8 7 6 5 1 2 3 RSTDRV# 4
RP41 33
RP56 33 8 7 6 5 IDERSTS#R
8 7 6 5 33
SDD3 SDD2 SDD1 SDD0
8 7 6 5
SDREQR SDIOW#R SDIOR#R SDIORDYR SDDACK#R SDIRQR SDA1R SDA0R SDCS1#R
RP46 33
IDERSTS#R
PDREQR PDIOW#R PDIOR#R PDIORDYR PDDACK#R PDIRQR PDA1R PDA0R PDCS1#R
8 7 6 5
IDERSTP#R
RP61 33
IDERSTP#R
8 7 6 5 33
1 2 3 4 1 2 3 4
8 7 6 5
1 2 3 4
1 2 3 4
SDD7 SDD6 SDD5 SDD4
RP43
Secondary IDE Connect or
13 13 13 13
1 3 PDD[15:0]
Primary IDE Connector
B
HD_ACT2#
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
C
HEADER 20X2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
JP3
HEADER 20X2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
JP4
C
RP45 33 8 7 6 5 1 2 3 4
2
CSEL2
RP42 33
R55 10k
1
RP44 33
CSEL1
1 2 3 4
8 7 6 5
8 7 6 5
SDD12 SDD13 SDD14 SDD15
SDD8 SDD9 SDD10 SDD11
74ALS00
U22A
PDD12 PDD13 PDD14 PDD15
PDD8 PDD9 PDD10 PDD11
R104 470
3
R103 470
7
1
14
SDD7
74ACT05
U25A
PDD7
2
R124 10k
R123 10k
D5 LGS260-DO
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
SDA2R SDCS3#R
1 2 3 4
R54 10k
V5_0
8 7 6 5
HD_ACT2#
PDA2R PDCS3#R
1 2 3 4
RP47 33
D
E
E
Thursday, February 25, 1999
Document Number {Doc} Sheet
15
HD Active LED
IDE Connectors
R58 220
V5_0
2 IN
1 NC
4
A
OUT 3
of
22
D
Rev
1
2
3
4
1
2
3
4
10K
R11
IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
9,13,14,18 IRQ12
9,13,14,18 IRQ10
9,13,14 9,13,14,18 9,13,14,18 9,13,14,18 9,13,14,18 9,13,14,18
A
PULL romCs# high so as not to interfere with boot rom!
This disables the ROM buffers. BIOS needs to enable and configure IRQs
V5_0
8
AEN IOCHRDY RSTDRV IRQ15 IRQ14 DRQ0 DRQ1 DRQ2 DRQ3 DACK0# DACK1# DACK2# DACK3# TC IOR# IOW#
14 KBDRST# 14 KBDA20GATE
13,18,20 9,13,18 13,18 9,13,14,15,18 9,13,14,15,18 9,14,18 9,14,18 9,14,18 9,14,18 14,18 14,18 14,18 14,18 14,18 9,13,18 9,13,18,20
9,13,18,20 SA[19:0]
9,13,18,20 SD[15:0]
REF1
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
V5_0
83 84 85 86 87 88 89 90 91 92
70 71 72 73 75 76
22 66 68 18
43 64 53 40 39 55 57 59 61 54 56 58 60 63 41 42
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
44 45 46 47 49 50 51 52
U1
C161 0.1uF
1
1
RP48 4.7K
2
2
2
2
1
BLM41A800S
1
FB7
1
BLM41A800S
1
FB8
FDC37B78X
IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ10 IRQ11/ROMCS# IRQ12
KDAT KCLK MDAT MCLK KBDRST# A20M
CLOCK14 XTL1 XTL2 CLK32OUT
FB6
2
2
2
2
B
BLM41A800S
1
V5_0
Floppy
Uarts
C29 470pF
Parallel
BLM41A800S
1
V3_3
62 93 121 69 65 VCC VCC VCC VTR VBAT
ISA/Host
FB5
C159 0.1uF
AEN IOCHRDY RESET_DRV SER/IRQ15 PCI_CLK/IRQ14/GP50 DRQ0 DRQ1 DRQ2 DRQ3 DACK0# DACK1# DACK2# DACK3# TC IOR# IOW#
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
C160 0.1uF
V5_0
B
19 20 21 POWERON BUTTON_IN PME#/IRQ9
AVSS VSS VSS VSS VSS 67 7 48 74 104
A
8 7 6 5
1 2 3 4
C30 470pF
GP10 GP11 GP12 GP13 GP14 GP15
PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCTIN# PINIT# ALF# STROBE# BUSY ACK# PE SLCT ERROR#
RXD1 TXD1 RTS1#/SYSOP CTS1# DTR1# DSR1# DCD1# RI1# RXD2/IRRX TXD2/IRTX RTS2# CTS2# DTR2# DSR2# DCD2# RI2#
RDATA# WGATE# WDATA# HDSEL# DIR# STEP# DSKCHG# DS0# DS1# MTR0# MTR1 WRTPRT# TRK0# INDEX# DRVDEN0 DRVDEN1
C28 470pF
77 78 79 80 81 82
96 97 98 99 100 101 102 103 95 94 110 111 107 108 106 105 109
112 113 115 116 117 114 119 118 123 124 126 127 128 125 122 120
16 11 10 12 8 9 17 5 6 3 4 15 14 13 1 2
SMD250-002 C31 470pF
C32 470pF
FB9 BLM41A800S
F3
V5_0
2 2 1 1
J1
B1 B2 B3 B4 B5 B6
C
19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19
PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 -SLCTRIN -INIT -ALF -STROBE -BUSY -ACK PE SLCT -ERR
BOTTOM
GND GND GND GND GND
TOP 13 14 15 16 17
Install only one resistor!
Install for 3F0 Config address
Do not stuff
1K
R6
10K
R5
V5_0
Install for 370 Config address
D
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N. Date:
PS2 STACK
MDATA NC GND M_VCC M_CLK NC
KBDATA NC GND KB_VCC KB_CLK NC
19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19
RXD0 TXD0 RTS0# CTS0# DTR0# DSR0# DCD0# RI0# RXD1 TXD1 RTS1# CTS1# DTR1# DSR1# DCD1# RI1#
T1 T2 T3 T4 T5 T6
19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19
-RDATA -WGATE -WDATA -SIDE1 -DIR -STEP -DSKCHG -DRVSA -DRVSB -MOTEA -MOTEB -WPT -TRK0 -INDEX HDEN DRATE0
C
Super I/O
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
16
of
22
D
Rev
1
2
3
4
1
2
3
A
USBP1-
USBP1+
14
USBP0+
14
14
USBP0-
14
OC1#
C122 47pF
27
27
C7 0.01UF
C125 47pF
C124 47pF
R92
R93
R88 15K
R90 15K
R3 15K
R4 10K
R89 15K
R91 15K
USBVFIL2
14 R1 15K
Z1_GND
Z1+
Z1-
PCB Trace 45 Ohm Matched, Routed Together Stripline width 0.015 (1 oz) 44.88/45.45 Ohm
Z0_GND
Z0+
Z0-
C2 100uF
Place these caps within 1 inch of USB Connector stack
C1 0.01UF
PCB Trace 45 Ohm Matched, Routed Together Stripline width 0.015 (1 oz) 44.88/45.45 Ohm
OC0#
R2 10K
USBVFIL1
C
FB1 BLM41A800S
C157 0.1uF
C158 0.01uF C6 100uF
USBVFIL1
B
NOTE 4: Poly-fuse min 1.5A max 5A.
NOTE 3: Place ferrites at connector.
FB2 BLM41A800S
C22 0.1uF
C
C23 0.01uF
FB4 BLM41A800S
F2
V5_0
D
Z1_VCC
Poly fuses should be in range of 1.5A to 5A
SMD250002 Poly-Fuse
Z0_VCC
5 6 7 8
1 2 3 4
USB Stack
VCC1 D1D1+ GND1
VCC0 D0D0+ GND0
J2
GND GND
GND GND
TOP of Stacked USB Connector
11 12
9 10
BOTTOM of Stacked USB Connector
8Ohm/100MHz/500mA 8Ohm/100MHz/500mA
FB3 BLM41A800S
F1
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
NOTE 2: Protect differential traces w/ guard traces or double space to any other signal.
SMD250-002 Poly-Fuse
USBVFIL2
NOTE 1: USB differential traces route together (Z0- & Z0+) and (Z1- & Z1+). Must be 45 Ohm Matched Stripline width 0.015 (for 1 oz)->44.88/45.45 Ohm.
27
27
Place As Close as Possible to PIIX4
C123 47pF
R94
R95
Place As Close as Possible to PIIX4
14
B
1 1 2 2
4
A
1 1 2 2
2 2 1
1
2 2 1 1
USB Connectors
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
17
of
22
D
Rev
1
2
3
4
1
2
3
4
9
9,13 9,13 9,13,14,16 9,13,14 9,13,14,16 9,13,14,15,16 9,13,14,15,16 14,16 9,14,16 14 9,14 14 9,14 14 9,14
8
9,13 9,13 9,13,16,20 9,13,16 14,16 9,14,16 14,16 9,14,16 9,13 13 9,13,14,16 9,13,14,16 9,13,14,16 9,13,14,16 9,13,14,16 14,16 14,16 9,13
MASTER16#
MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7
REF0
SMEMW# SMEMR# IOW# IOR# DACK3# DRQ3 DACK1# DRQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC BALE
9,13 Z E R O W S #
9,14,16 D R Q 2
9,13,14 IRQ9
C59 0.1uF
A
9,13
LA[23:17]
9,13,16,20 SD[15:0]
9,13,16,20 SA[19:0]
Note Cap Direc tion
C60 0.1uF
13,16 R S T D R V
C3 10uF
-5V
A
C62 0.1uF
-12V
-5V
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31
ISA Conn A
MCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 V5_0 MASTER GND
GND RSTDRV V5_0 IRQ9 -5V DRQ2 -12V 0WS +12V GND SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE V5_0 OSC GND
J5
Note Cap Direc tion
C63 0.1uF
+12V
LA[23:17]
SD[15:0]
SA[19:0]
C4 10uF
-12V
C5 10uF
B
C71 0.1uF
+12V
B
SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
C70 0.1uF
C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
C8 10uF
MEMR# MEMW#
SBHE#
IOCHRDY AEN
IOCHK#
C111 0.1uF
9,13,20 9,13,20
9,13
SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
C42 0.1uF
9,13,16 13,16,20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
9,13
C112 0.1uF
V5_0
LA23 LA22 LA21 LA20 LA19 LA18 LA17
C126 0.1uF
C
J5/J6 V5_ 0: B03, B29,
RSTDRV
MASTER16#
MEMCS16# IOCS16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0# DRQ0 DACK5# DRQ5 DACK6# DRQ6 DACK7# DRQ7
REF0
-12V
-5V
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31
ISA Conn B
MCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 V5_0 MASTER GND
GND RSTDRV V5_0 IRQ9 -5V DRQ2 -12V 0WS +12V GND SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE V5_0 OSC GND
J6
D
SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
D
Date:
Size C
Title
MEMR# MEMW#
SBHE#
IOCHRDY AEN
IOCHK#
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
J5/J6: +12V B09 -12V B07 -5V B05
+12V
MEMW# MEMR# IOW# IOR# DACK3# DRQ3 DACK1# DRQ1 REFRESH# SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2# TC BALE
ZEROWS#
DRQ2
IRQ9
B3 1, D16 J5/J6 GN D: B01, B10, D18
C127 0.1uF
ISA Slots
C
SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
LA23 LA22 LA21 LA20 LA19 LA18 LA17
E
Thursday, February 25, 1999
Document Number {Doc}
ISA Connectors
SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
E
Sheet
18
of
22
D
Rev
1
2
3
4
1
2
3
4
DCD0# DSR0# RXD0 RTS0# TXD0 CTS0# DTR0# RI0#
DCD1# DSR1# RXD1 RTS1# TXD1 CTS1# DTR1# RI1#
16 16 16 16 16 16 16 16
A
-DSKCHG -SIDE1 -RDATA -WPT -TRK0 -WGATE -WDATA -STEP -DIR -MOTEB -DRVSA -DRVSB -MOTEA -INDEX DRATE0
GD75232SOP
V5_0 +12V RY1 RA1 RY2 RA2 RY3 RA3 DA1 DY1 DA2 DY2 RY4 RA4 DA3 DY3 RY5 RA5 GND - 1 2 V
U3
GD75232SOP
V5_0 +12V RY1 RA1 RY2 RA2 RY3 RA3 DA1 DY1 DA2 DY2 RY4 RA4 DA3 DY3 RY5 RA5 GND - 1 2 V
U4
1 6 HDEN
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
SP_DCD0 SP_DSR0 SP_RXD0 SP_RTS0 SP_TXD0 SP_CTS0 SP_DTR0 SP_RI0
SP_DCD1 SP_DSR1 SP_RXD1 SP_RTS1 SP_TXD1 SP_CTS1 SP_DTR1 SP_RI1
+12V
-12V
1 2 3 4 5 6 7 8 9 10
-12V
1 2 3 4 5 6 7 8 9 10
+12V
COM0/COM1
R25 1K
C36 470pF
C52 470pF
C35 470pF
C46 470pF
C39 470pF
V5_0
C47 470pF
C40 470pF
C53 470pF
C49 0.1uF
RP18 1K
C34 470pF
C38 470pF
C45 470pF
C51 470pF
C50 470pF
34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
JP1
C43 0.1uF
B
C48 0.1uF
+12V
33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
FLOPPY
C33 470pF
C44 470pF
C37 470pF
C64 0.1uF
-12V
FLOPPY HEADER 17X2
C54 0.1uF
B
14 18 13 17 12 16 11 15 10
5 9 4 8 3 7 2 6 1
SERIAL STACK
14 18 13 17 12 16 11 15 10
5 9 4 8 3 7 2 6 1
J4
C65 0.1uF
V5_0
16 16 16 16
16 16 16 16
16 16 16 16
16 16 16 16
COM1
COM0
16
C
-ACK -BUSY PE SLCT
PDR4 PDR5 PDR6 PDR7
PDR0 PDR1 PDR2 PDR3
-INIT -ERR -ALF -STROBE
-SLCTRIN
C
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
22
RP4
33
RP3
33
RP2
22
RP1
8 7 6 5
8 7 6 5
8 7 6 5
8 7 6 5
RP5 4.7K
V5_0
RP6 4.7K
D
RP7 4.7K
C21 220pF
C20 220pF
C19 220pF
C18 220pF
C17 220pF
C16 220pF
C15 220pF
C14 220pF
C13 220pF
C26 220pF
C25 220pF
C10 220pF
C9 220pF
C24 220pF
C11 220pF
C12 220pF
PPSLCT
PPE
-PPBUSY
-PPACK
PPDR7
PPDR6
PPDR5
PPDR4
PPDR3
PPDR2
PPDR1
PPDR0
-PSTROBE
-PALF
-PPERR
-PPINIT
-PSLCTIN
PARALLEL
D
Date:
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N.
-ACK -BUSY PE SLCT
PDR4 PDR5 PDR6 PDR7
PDR0 PDR1 PDR2 PDR3
-INIT -ERR -ALF -STROBE
22
R9
R7 4.7K
8 7 6 5 1 2 3 4
V5_0
8 7 6 5 1 2 3 4
+12V
8 7 6 5 1 2 3 4
-12V
4 3 2 1 5 6 7 8
16 16 16 16 16 16 16 16
A
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
E
Thursday, February 25, 1999
Document Number {Doc}
COMx, DB25, Floppy
E
Sheet
J3 DB25
26 27
19
of
22
D
Rev
1
2
3
4
1
2
3
13,16,18
AEN
9,13,16,18
9,13,16,18 SA[19:0]
A
Expect All 0's except SA7=1 for P80 Decode
TP2
IOW#
SA[19:0]
SA9 SA8 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
SD[15:0]
22V10
I1/CLK I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12
Standard Stuff Option
2 3 4 5 6 7 9 10 11 12 13 16
U9
1 8 15 22
TP6
9,13,18 M E M W # 9,13,18 M E M R # 1 4 BIOSCS#
NC NC NC NC
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10
17 18 19 20 21 23 24 25 26 27
TP16 TP14 TP12 TP10
1
9,13,16,18 SD[15:0]
C196 0.1uF
V5_0
TP8
+12V
TP7
1
4
1
TP
TP 1
TP 1 TP
1 TP
R98
0
1
TP9
TP 1
TP 1 TP
1 TP
B
B
J22 HDR3
2
A
3
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40
C131 0.1uF
PWROK5
9 24 22 10
14 17 18 21 22
SD0 SD1 SD2 SD3
WE# OE# CE# RP#
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
U11
21
12
1 13
3 4 7 8 11
SD4 SD5 SD6 SD7
28F002BC
NC NC NC NC
VCC VCC GND GND
VPP
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
QST3384
GND
BEA BEB
2A1 2A2 2A3 2A4 2A5
1A1 1A2 1A3 1A4 1A5
U10
12 13 37 38
31 30 39 23
11
25 26 27 28 32 33 34 35
+12V
2B1 2B2 2B3 2B4 2B5
1B1 1B2 1B3 1B4 1B5
V5_0
C200 0.1uF
V5_0
15 16 19 20 23
2 5 6 9 10
24
1
Port 80
J21 1x3
2
3
XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7
C130 0.1uF
C
5
3 2 13 12
C208 0.1uF
V5_0
XD[7:0]
TIL311 SOCKET
LATCH
A B C D
U12
13
RTDEC LFTDEC GND GND
V5_0 V5_0
10 4 8 7
14 1
C206 0.1uF
V5_0
D
V5_0 R105 10K
5
3 2 13 12
D
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
V5_0
C
U13
Date:
Size C
Title
RTDEC LFTDEC GND GND
V5_0 V5_0
10 4 8 7
14 1
E
Thursday, February 25, 1999
Document Number {Doc}
BIOS/ Port 80
TIL311 SOCKET
LATCH
A B C D
E
Sheet
C205 0.1uF
V5_0
20
of
22
C145 10uF
D
Rev
1
2
3
4
1
2
3
14
14
PWRON#
2
RSMRST#
J20 JUMP3
1
3
J11
V3_3 -12V GND PS_ON GND GND GND -5V V5_0 V5_0
V3_3 V3_3 GND V5_0 GND V5_0 GND PW_OK 5VSB +12V
1 2 3 4 5 6 7 8 9 10
6
A
7 4 L C T 14
U24C
C61 0.1uF
7
5
14
V3_3
8
7
9
14
C58 100uF
7 4 L C T 14
U24D
V3.3SUS
C72 100uF
Place at ATX Connector
ATX POW CONN
11 12 13 14 15 16 17 18 19 20
C153 10uF
C96 0.1uF
2.7K
R57
V5_0
C84 100uF
B
TP18
C109 100uF
C152 47uF
V3.3SUS
C89 100uF
-5V
C102 0.1uF
C76 0.1uF
1
2 4
L T 1 1 7 - 3 .3
Adj/GND
Out In OutTab
U23
Note Cap Direction
C88 100uF
Place at ATX Connector
C97 0.1uF
Place at ATX Connector
Place at ATX Connector
Place at ATX Connector
3
C83 220uF
C110 220uF
C154 47uF
C98 220uF
Note Cap Dire ction
C69 220uF
+12V
-12V
V3.3SUS
4
POWER SWITCH
S1
C138 10uF
R53 10K
V5_0
14
C141 0.01uF
R56 10K
DBRESET
SPKR
74ACT05
U25B
V5_0
7 4 L C T 14
U24B
V3.3SUS
4
4 CPUPWROK
7
3
14 4
R10 220
1x4
5
4
PS_OK
C
D
C27 470pF
6
5
74HCT14
U21C 6
7
5
14
6
PWROK5
74ACT05
U25C
V5_0
20
E
PWRBTN#
14
Date:
Size C
Title
3
2
1
3
2
1
1
TP TP1
E
Thursday, February 25, 1999
Document Number {Doc}
AXT Power Connector
A M P 1 7 3 9 8 1 -3
J12
V5_0
2
21
7 4 L C T 14
U24A
V3.3SUS
Sheet
7
1
14
R127 10K
PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH
74ALS00
U22B
S2 RESET SWITCH
Open Collec tor
JP2 1 2 3 4
R8 124
Note: Add screen marking for V5_0 LED, V3_3 LED
C41 470pF
D1 LGS260-DO
V3_3
Power Indicator s
SPEAKER HEADER
C142 0.1uF
7
3
14
R128 4.7K
V5_0
D2 LGS260-DO
V5_0
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
C
2 IN
1 NC
B
OUT 3
2 IN
1 NC
4
A
TP 1
OUT 3
of
22
PWROK
D
Rev
1
2
4,14
3
4
1
2
3
4
A
7
13
14
Make these connections Cutable
V3.3SUS
7 4 L C T 14
U24F
12
Make these connections Cutable
V5_0
A
7
13
74HCT14
1 4 U21F
74HCT14
12
Make these connections Cutable
13 7
14 12
10 7
14 9
B
Make these connections Cutable
V5_0
7
13
14
7
11
14
7
7
9
10
14
7
5
14
11
74HCT14
8
V5_0
1 4 U21E
7
9
1 4 U21D
B
74ALS00
U22D
74ALS00
U22C
74AS07
U2F
74AS07
U2E
74AS07
U2D
74AS07
U2C
12
10
8
6
11
8
C
C
7
13
14
7
11
14
7
9
14
6
74ACT05
U25F
74ACT05
U25E
74ACT05
12
10
8
U15D 74LVC125
11
U15C 74LVC125
8
U15B 74LVC125
U25D
7
12
14
7
9
14
7
5
14
D
D
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER Title PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE Size C MISUSE OF THIS INFORMATIO N. Date:
Make these connections Cutable
V5_0
Make these connections Cutable
V3.3SUS
4 10 13
Unused Gates
E
Thursday, February 25, 1999
Document Number {Doc}
E
Sheet
22
of
22
D
Rev
1
2
3
4
A
B
C
D
5
5
4
4
3
2
8. Fixed Reference designators in notes -RMK 2/17/99
Board stack-up is 65 Ohm nominal, 8 layer, 1oz planes
Most netlisters do not like the global V(CPU) . The netlist was run and the node V(CPU) was changed to VCPU by hand.
6.
7.
Silkscreen updated to Rev B.
5.
Byte 1 and Byte 2 of DRAM bus swapped in layout to minimize line length. Bytes 5/6 also swapped. 4. To support the byte-swapping in item 3. Byte enables were also swapped. Done in schematics between the r-packs R7, R37 and U5 (TX). Notice DQM1 goes through R37 and connects to V20 of U4 (normally DQM2). Notice DQM2 goes through R7 and connects to W20 of U4 (normally DQM1). DQM5/6 are swapped similarly.
Date:
Size C
Title
1
1
Thursday, February 25, 1999
Document Number XXXX-XXX
Revision History
Power good timing cap (C38) net change so cap is between gnd and VR_PWRGD (page 6).
2. 3.
ITP Vsense reference changed from 3.3V to 2.5V (R1 page 7)
2
1.
REVISION HISTORY:
3
Sheet
1
of
8
Rev B.0
A
B
C
D
1
2
3
4
Do not populate.
BF2
Do not populate.
1
R28 270
1
TP
1
0 0 1 0
0 1 1 0
2/5 1/3 2/7 1/4
66/166 66/200 66/233 *66/266
BUS FRACTION
BF2 BF1 BF0
A
All other combinations are reserved.
0 0 0 1
SETTING BF2 BF1 BF0
R27 270
BF0
R31 2K
V2_5
TRST# TCK TMS TDI TDO
SMIACT#
ADS# D/C# W/R# M/IO#
CACHE#
PRDY
AP LOCK#
HITM#
FERR#
BE4# BE5# BE6# BE7#
BE0# BE1# BE2# BE3#
BF[2:0]
Do not populate.
TP28
TP
BF1
R32 2K
V2_5
T P 22
TP
BUS FRACTION BIT SETTING
R29 270
R33 2K
V2_5
T P 34
3. Place test points as close to U2 as possible. Can be a via pad.
2. Make sure BE0#-BE7#, CACHE#, and LOCK# have at least one accessable via.
1. See drawing for keep out mounting holes. Make 50mm x 50mm height restricted box around this. No parts in keepout. Parts <=5mm between keepout and restricted boundary.
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31
TP NA#
1
B
B7
AD22
E1 C8 AE23 AD23 AF22
AE16 AF16 AE15
AF19 AE22 AF20 AE21 AF21
A13 A12 B12 C11
R1 A14 B5
H2 F1 H1 A11
B10
C1 D2 D1 B3 B4 G3 G2
B13 C2 J3 J2 C4
M2 N1 P1 N2
K1 L2 L1 M1
AE6 AF5 AE5 AF4 AE4 AE3 AE2 AD2 AC2 AC1 AB1 AA1 Y1 W1 V1 U2 T2 U1 AF11 AE11 AF10 AF9 AE10 AF8 AE9 AF7 AE8 AF6 AE7
KAYENTA
NA#
GND
NC V(CPU) PICCLK PICD0 PICD1
BF2 BF1 BF0
TRST# TCK TMS TDI TDO
PM0/BP0 PM1/BP1 BP2 BP3
SCYC IERR# SMIACT#
ADS# D/C# W/R# M/IO#
CACHE#
HLDA AP LOCK# APCHK# PRDY PCD PWT
FERR# BREQ HITM# HIT# PCHK#
BE4# BE5# BE6# BE7#
BE0# BE1# BE2# BE3#
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
U5
D
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
C
Low Power Pentium(r) Processor with MMX(tm) Technology
C
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N. D
BUSCHK# WB/WT# INIT SMI# R/S# PEN# STPCLK# EWBE# HOLD
BOFF# A20M# INTR NMI IGNNE# KEN# FLUSH# AHOLD EADS# BRDY# RESET INV
CLK
DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7
D56 D57 D58 D59 D60 D61 D62 D63
D48 D49 D50 D51 D52 D53 D54 D55
D40 D41 D42 D43 D44 D45 D46 D47
D32 D33 D34 D35 D36 D37 D38 D39
D24 D25 D26 D27 D28 D29 D30 D31
D16 D17 D18 D19 D20 D21 D22 D23
D8 D9 D10 D11 D12 D13 D14 D15
D0 D1 D2 D3 D4 D5 D6 D7
K2 A6 AE14 AE13 AF12 AF15 AF17 A10 A5
A7 L3 AF13 AE12 AF14 A8 J1 A9 G1 B8 R2 B9
P2
W24 T25 N26 K26 D26 C23 A19 B14
B18 A18 B17 A17 B16 A16 B15 A15
B23 B22 B21 A22 A21 B20 A20 B19
E25 C26 D25 B26 C25 D24 B25 B24
H25 J26 H26 G25 G26 F26 E26 F25
M24 M25 K24 L25 M26 K25 L26 J25
T26 R25 R26 P26 P25 P24 N24 N25
Y26 V24 W25 V25 W26 U25 V26 U26
AC24 AC25 AB24 AB25 AA24 Y24 AA25 Y25
TP11 TP HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63
HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55
HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47
HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39
HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31
HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23
HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7
BRDY#
1 2 3 4
1 2 3 4
V(CPU)
8 7 6 5
8 7 6 5
R40 4.7K
HCLK_CPU
4.7K
4.7K R42
R36
V2_5
PLACE TEST POINTS AS CLOSE AS POSSIBLE TO TilaSLM
WB/WT# INIT SMI# R/S# PEN# STPCLK# EWBE# HOLD
CPU_RST KEN#
BOFF# A20M# INTR NMI IGNNE# KEN# FLUSH# AHOLD EADS#
T P 16
T P 33
DP4 DP5 DP6 DP7
DP0 DP1 DP2 DP3
E
Date:
Size C
Title
E
Thursday, February 25, 1999
Document Number XXXX-XXX
CPU
Sheet
2
of
8
NOTE 2: ADD ADDITIONAL GND TEST POINTS NEXT TO TEST POINTS ON THIS PAGE
NOTE 1:
DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7
1
TP9
B
G4 J4 K4 M4 N4 T4 V2 W3 Y3 AA4 AB4 AC5 AD5 AC7 AC9 AC10 AC11 K23 J23 H23 G23 F23 E23 D23 C22 C20 D18 AC17 AC22 Y23 V23 U23 T23 R23 N23 D16 D14 D11 D10 D6 D4 F4 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 V2_5 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
A
R4 R3 U4 V3 Y2 AA3 AB2 AC4 AC6 AC8 AC13 AC14 AC15 L23 C21 D19 D17 AC16 AE17 AE18 AC18 AD19 AC19 AC20 AC21 AC23 AB23 D15 D13 D12 D9 D7 C6 D5 E4 F3 V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU) V(CPU)
AD11 AD10 AD9 AD8 AD7 AD6 AD4 AD3 AC3 AB3 AA2 Y4 W4 W2 V4 U3 T3 P3 P4 N3 M3 K3 H3 AD13 AD14 AD15 M23 L24 J24 H24 G24 F24 E24 C24 D22 D21 D20 C19 C18 C17 C16 AD16 AD17 AD18 AE19 AE20 AD20 AD21 AD24 AA23 W23 U24 T24 R24 P23 C15 C14 C13 C12 B11 C10 C9 D8 C7 B6 C5 C3 D3 E2 E3 F2
TP 1
TP 1
Rev B.0
1
2
3
4
22
22
1 2 3 4
R39
R38
1 2 3 4
1 2 3 4
22
22
22
8 7 6 5
8 7 6 5
8 7 6 5
R7
R37
R41
8 7 6 5
8 7 6 5
SUS_CLK SUS_STAT1#
HA26 HA27
CKE0 CKE1 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 SCASA# SCASB# SRASA# SRASB# WEB# WEA#
V3_3
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31
TP U18 W20 V20 T17 T19 U19 P17 T18 U20 W16 V15 V16 Y17 T14 U15 Y16 W18 Y18 W19 U17 U16 Y19 P19 M18 N18 P20 V18 R18 T20 R19 V17
V11 Y11 U8 T11 Y8 V8 V7 Y7 W7 U7 Y6 V6 W6 U6 Y5 W5 V5 U5 V9 U10 U9 W10 W9 V10 Y9 Y10 U11 W11 W8 Y20 P18 R17 N17 V19 M16
1 8 2 4 3 9TX
CAS0# CAS1# CAS2# CAS3# CAS4# CAS5# CAS6# CAS7# MAA0/CKE MAA1/CKEB MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11/BA0 SCASA# SCASB# SRASA# SRASB# MWEB# MWE# SUSCLK SUSSTAT1# KRQAK/CS4_64#
A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 RAS0# RAS1# RAS2# RAS3# RAS4# RAS5#
C76 0.1uF
C79 0.1uF
C89 0.1uF
C88 0.1uF
C19 22uF
A
C78 0.01uF
C1 22uF
MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
C77 0.01uF
MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55
C85 0.01uF
MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63
U4
82439TX
MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39
MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23
PLACE AS CLOSE AS POSSIBLE TO TXC V2_5 PINS
C87 0.1uF
PLACE AS CLOSE AS POSSIBLE TO TXC V3_3 PINS
1 2 3 4
1 2 3 4
DO NOT POPULATE R 6 4.7K
R5 22K
V2_5
OUT -66MHZ IN - 60MHz
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25
1
HCLK_TX
CACHE# KEN# SMIACT# ADS# BRDY# NA# AHOLD EADS# BOFF#
MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
V2_5
V3_3
DQM1 DQM5 DQM4 DQM6
DQM2 DQM0 DQM7 DQM3
MA12
MA13
CSA0# CSA1# CSA2# CSA3#
CSB0# CSB1# CSB2# CSB3#
HA28 HA29 HA30 HA31
R34 4.7K
TP
CACHE# KEN# SMIACT# ADS# BRDY# NA# AHOLD EADS# BOFF#
(NOTE 1)
C
MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55
C
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23
B
LOCK# W/R# D/C# M/IO# HITM#
D
E
F05 L16 E12 T13
PHLD# PHLDA# PAR PCIRST# T E ST#
D4 D5 A16 T15 W17
5VREF
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# DEVSEL# IRDY# TRDY# STOP# PLOCK# REQ0# REQ1# REQ2# REQ3# GNT0# GNT1# GNT2# GNT3# A15 A14 B13 A13 C12 B12 A12 C11 A11 C10 B10 A10 C9 B9 A9 C8 C7 B7 A7 C6 B6 A6 C5 B5 D6 C4 B4 A4 B3 A3 B2 A2 B11 B8 A8 A5 E6 E9 E7 E8 E11 E5 D7 D9 D11 D13 D8 D10 D12 D14
E14
PCICLK_IN
E10
C13
D
Date:
C
NOTE 1: PLACE TEST POINTS AS CLOSE AS POSSIBLE TO 82439TX NOTE 2: ADD ADDITIONAL GND TEST POINTS NEXT TO TEST POINTS ON Title THIS PAGE Size
BWE# GWE# COE# CCS# CADS# CADV#
TWE#
VCC5REF
TEST#
RST#
PAR
PHLDA#
PHLD#
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# DEVSEL# IRDY# TRDY# STOP# LOCK# REQ0# REQ1# REQ2# REQ3# GNT0# GNT1# GNT2# GNT3#
PCLKIN
CLKRUN#
R43 1K
V3_3
LOCK# W/R# D/C# M/IO# HITM#
1K R8
E
Thursday, February 25, 1999
Document Number XXXX-XXX
8 2 4 3 9TX
C17 1uF
PCI_RST#
PAR
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# FRAME# DEVSEL# IRDY# TRDY# STOP# PLOCK# REQ0# REQ1# REQ2# REQ3# GNT0# GNT1# GNT2# GNT3#
TP23
BAT54C
D1
Sheet
BWE# GWE# COE# CCS# CADS# CADV#
CTAG0 CTAG1 CTAG2 CTAG3 CTAG4 CTAG5 CTAG6 CTAG7
TWE#
1
4
3
R35 10K
PHLDA#
PHLD#
PCICLK_IN
CLKRUN#
of
V3_3
8
Rev B.0
V3_3
V5_0
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
(NOTE 1)
T P 10
B
MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
1
2
3
V2_5
R34: 512K Cache Select Strap
TP19
Host V2_5
TP
4
8 7 6 5
1 2 3 4
R16 N16 P16 F06 G06 R07 R06 F15 P15 R15 K16 P5 R5 L5 N5 M5 T5 T10 K5 J5 G5 T9 T7 H5 T8 V (SUS) V (SUS) V (SUS) V2_5 V2_5 V2_5 V2_5 V3_3 V3_3 V3_3 HCLKIN BOFF# EADS# AHOLD NA# BRDY# ADS# SMIACT# KEN#/INV CACHE# HLOCK# W/R# D/C# M/IO# HITM# GND GND GND GND GND MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND CADV# CADS# CCS# COE# GND GWE# BWE#
T16 E15 M12 L12 K12 C15 C18 B17 A18 B19 B20 D19 E20 J19 K20 M17 J18 N20 G20 E16 F16 C14 D15 C16 D17 A20 C20 E18 F19 K18 L19 L18 G19 G16 K17 F17 G17 B14 D16 A17 C17 A19 D18 E17 E19 J20 M20 N19 M19 F20 G18 H20 H16 E13 B15 B16 B18 R20 C19 D20 F18 K19 L20 H19 H18 L17 J17 J16 H17 J12 W12 U12 W13 V12 M11 V13 Y12
GND TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 TIO1 TIO0 GND TWE# GND GND GND GND GND GND L11 W14 U13 Y15 W15 T12 V14 Y14 U14 K11 Y13 J11 M10 L10 K10 J10 M9
A
BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# HD63 HD62 HD61 HD60 HD59 HD58 HD57 HD56 HD55 HD54 HD53 HD52 HD51 HD50 HD49 HD48 HD47 HD46 HD45 HD44 HD43 HD42 HD41 HD40 HD39 HD38 HD37 HD36 HD35 HD34 HD33 HD32 HD31 HD30 HD29 HD28 HD27 HD26 HD25 HD24 HD23 HD22 HD21 HD20 HD19 HD18 HD17 HD16 HD15 HD14 HD13 HD12 HD11 HD10 HD9 HD8 HD7 HD6 HD5 HD4 HD3 HD2 HD1 HD0 GND GND GND GND
M1 L4 L3 L2 L1 K4 K3 K2 A1 B1 C3 C2 C1 D2 D3 E3 D1 E2 E4 E1 F3 F4 G3 F1 F2 H3 G1 H4 G4 J3 G2 H2 H1 J4 J1 J2 M4 K1 M2 M3 N4 N2 N3 P4 N1 P2 P3 R4 P1 T3 R2 T4 R3 U2 T2 U4 V2 U3 V4 T1 W4 V3 W3 U1 R1 V1 W2 W1 Y4 Y2 Y3 Y1 T6 J9 K9 L9
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# V3_3 V3_3 V3_3 V3_3
BE5# BE6# BE7# 1
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 BE0# BE1# BE2# BE3# BE4# 1
2
3
4
1
2
3
4
V3_3
L2_ZZ
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31
COE#
CCS#
CCS#
HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31
COE#
V3_3
B
C11 0.1uF
38 39 42
4 11 15 20 27 41 54 61 65 70 77 91 14
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29
64
86
98 97 92
L2 LOW
C3 0.1uF
PBSRAM 64K x 32
NC NC NC
V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V3_3
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32
ZZ
OE#
CE# CE2 CE3#
U3
C5 0.1uF
/ / / /
DQPa DQPb DQPc DQPd
43 66 16
5 10 17 21 26 40 55 60 67 71 76 90
89
37 36 35 34 33 32 100 99 82 81 44 45 46 47 48 49 50
51 80 1 30
31
A
B
R4 1K
V3_3
HCLK_CACHE
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
ADS# CADS#
CADV#
BWE#
GWE#
BE0# BE1# BE2# BE3#
C2 22uF
V3_3
HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
U2
SRAM 32K x 8
V3_3
TAGS
C
D
GND
OE#
CE#
WE#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63
COE#
CCS#
27
14
22
20
TWE#
TWE#
CTAG0 CTAG1 CTAG2 CTAG3 CTAG4 CTAG5 CTAG6 CTAG7
/ / / /
DQPa DQPb DQPc DQPd
MODE
ADSP# ADSC#
ADV#
BWE#
GW#
BW0# BW1# BW2# BW3#
C51 0.1uF
V3_3
NC NC NC
GND GND GND GND GND GND GND GND GND GND GND GND
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 NC / A16
NC NC NC NC
L2 HIGH
C53 0.1uF
PBSRAM 64K x 32
NC NC NC
V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V2_5 V2_5 V3_3 V3_3
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32
ZZ
OE#
CE# CE2 CE3#
CTAG0 CTAG1 CTAG2 CTAG3 CTAG4 CTAG5 CTAG6 CTAG7
38 39 42
4 11 15 20 27 41 54 61 65 70 77 91 14
52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29
64
86
98 97 92
U7
C54 0.1uF
11 12 13 15 16 17 18 19
C52 0.1uF
HCLK_CACHE
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
ADS# CADS#
CADV#
BWE#
GWE#
BE4# BE5# BE6# BE7#
C56 0.1uF
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
ADS# CADS#
CADV#
BWE#
GWE#
BE4# BE5# BE6# BE7#
C6 22uF
C9 0.1uF
D
Date:
Size C
Title
E
E
Thursday, February 25, 1999
Document Number XXXX-XXX
Cache and Tags
PLACE AS CLOSE AS POSSIBLE TO SRAM TAG
43 66 16
5 10 17 21 26 40 55 60 67 71 76 90
89
37 36 35 34 33 32 100 99 82 81 44 45 46 47 48 49 50
51 80 1 30
31
84 85
83
87
88
93 94 95 96
C55 0.1uF
PLACE AS CLOSE AS POSSIBLE TO HIGH SRAM (U5) V3_3
TAG V3_3: 28 TAG GND: 10,14, 20, 22
28
21 23 24 25 26 1 2 3 4 5 6 7 8 9 10
COE#
CCS#
L2_ZZ
C
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63
Route HCLK_CACHE as single trace between U3/U7 T-line into 2 stubs identical length as short as possible.
HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18
ADS# CADS#
84 85
BWE#
GWE#
BE0# BE1# BE2# BE3#
C10 0.1uF
CADV#
C7 0.1uF
83
87
88
93 94 95 96
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
NC NC NC
GND GND GND GND GND GND GND GND GND GND GND GND
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 NC / A16
NC NC NC NC
MODE
ADSP# ADSC#
ADV#
BWE#
GW#
BW0# BW1# BW2# BW3#
C4 0.1uF
PLACE AS CLOSE AS POSSIBLE TO LOW SRAM (U4)
BSRAM V3_3 : 4,11,15,20,27,41,54,61,65,70,77,91 BSRAM GND : 5,10,17,21,26,40,55,60,65,67,71,76,90
L2_ZZ
A
Sheet
5
of
8
Rev B.0
1
2
3
4
1
2
3
4
INIT
A
ITP
J1
1
2
GND_4
GND_3
GND_2
GND_1
GND_0
BSEN#
NC_2
TDO
TDI
TMS
TCLK
TRST#
DBINST#
PRDY
R/S#
NC_1
RESET
INIT
DBRESET
V3_SENSE
SN74LVC04A-DB
U1A
TCK TMS TDI TDO
16 14 12 13
V3_3
17
15
10
8
4
20
R1
V2_5
12
SN74LVC04A-DB
B
UNUSED
14
13
10
PRDY
R/S#
PROBE_RST
SN74LVC04A-DB 7 U1F
14
11
7 U1E
TDO
TDI
TMS
TCK
TRST#
PROBE_INIT
V3_SENSE
TRST#
5
4
SN74LVC04A-DB
U1B
18
19
11
7
9
3
1
2
6
3
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998 TP8 TP 1
6
T P 12
TP
TP18 TP35
14
5
7
SN74LVC04A-DB
U1C
DBRESET
1
TP1 TP 1
B
TP 1
TP 1
TP2
TP3 TP RESET#
1
TP 8
1
9
C
C
R2 0
X4
0
DO NOT POPULATE
R3
X5
CPU_RST
DB_RST
X6
R/S#
AP WB/WT# FLUSH# PEN#
D
1 2 3 4 8.2K
R9
R30
8 7 6 5
3.3K
D
E
V2_5
V2_5
Date:
Size C
Title
R44
R45
E
Thursday, February 25, 1999
Document Number XXXX-XXX
ITP / Strapping Options
HOLD
EWBE#
Sheet
0
Processor PULLUP / PULLDOWN CONNECTIONS
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
SN74LVC04A-DB
U1D
X3
VIA1 1
VIA2 2
VIA3 3
VIA4 4
VIA1 1
VIA2 2
VIA3 3
VIA4 4
VIA1 1
VIA2 2
VIA3 3
VIA4 4
VIA1 1
VIA2 2
VIA3 3
VIA4 4
A
1K 4.7K
7
of
8
Rev B.0
1
2
3
4
1
2
3
4
100pF
C43
R23 30K 0.1%
C41 100pF
A
0.1uF C40
4
4
4
4
G
G
V5_0
Q4 Si9426DY
Q3 Si9426DY
S
Q2 Si4412DY
Q1 Si4412DY
D
S
D
0.075
33uH/1.68A
0.020
15uH/4.50A
B
R17 0
R26
L2
MBRS140T3
D5
D2 MBRS140T3
R10
L1
C107 150uF 10V 20%
D
R16 3.3K
V5_0
C50 220uF
C37 220uF
C109 220uF
C38 10uF
DO NOT POPULATE
C108 220uF
C48 220uF
C36 220uF
TP5
V3_3
TP4
TP6
TP7
V2_5
D
6. Keep the switching node away from sensitive small signal nodes. Keep this node as remote as reasonably possible from U6.
Date:
Size C
Title
E
Sheet
C48/C50
Thursday, February 25, 1999
Document Number {Doc}
Regulators
4.
5. Keep the (+) plates of C108/C109 as close to the drain of the upper MOSFET (Q4) as possible. (These caps provide the AC current to the MOSFETs.)
The resistive divider R23/R24 must be connected between the (+) plates of Keep the following U6 trace pair routed together with minimum PC trace spacing SENSE2+ (pin 14) and SENSE2- (pin 13)
3.
6
Place TP3 as close to C14 as possible to C22 +
Make the power ground connects to the source of the bottom N-channel MOSFET Q3 2.0V, anode of the Schottky diode D4 2.0V, and (-) plates of C48, C50 as short lead lengths as possible.
VR_PWRGD
V(CPU)
Place TP2 as close to C14 as possible to C22 -
Place TP1 as close to C14 + as possible
2.
C
E
of
8
Rev B.0
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
2.0V Supply NOTES: 1. SGND(2_0) must return to the (-) plate and C48/C50.
0.1uF
C45
D4 CMDSH-3
150uF 10V 20%
C35
D3 CMDSH-3
0.1uF
C32
10
R15
GENERAL NOTE: Keep all components on this page as close as possible to U6. Components shown to the left of the symbol should be layed out to the left of the chip (these are the small signal components/ small signal side of the chip). Connect ground of these components at a single point. Done in layout as a gap in a ground plane slot that divides the chip left/right.
Keep the (+) plate of C107 as close to the drain of the upper MOSFET (Q1) as possible. (These caps provide the AC current to the MOSFETs.) 6. Keep the switching node away from sensitive small signal nodes. Keep this node as remote as reasonably possible from U6.
5.
The resistive divider R11/R12 must be connected between the (+) plates of C36/C37
Keep the following U6 trace pair routed together with minimum PC trace spacing: SENSE1+ (pin 1) and SENSE1- (pin 2)
4.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3.
LTC1438CG-ADJ
RUN/SS2
BOOST2
TGL2
SW2
EXTVcc
BG2
PGND
INTVcc
BG1
Vin
SW1
TGL1
BOOST1
RUN/SS1
Make the power ground connects to the source of the bottom N-channel MOSFET Q2 2.5V, anode of the Schottky diode D2 2.5V, and (-) plates of C36, C37 as short lead lengths as possible.
SENSE+2
SENSE-2
Vosense2
Ith2
SFB1
LBO
LBI
SGND
Cosc
POR2
Ith1
Vosense1
SENSE-1
SENSE+1
SGND(2_5) must return to the (-) plate and C36/C37.
R21 10
R22 10
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U6
2.
0.1uF
C46
220pF
C47
Vout = 1.19 (1+R23/R24)
C42 1000pF
C31 1000pF
R13 10
1.
2.5V Supply NOTES:
1 0 0 0 pF
R24 43K 0.1%
R19 47K 0.1%
C44
R14 10
SET POINT: I/O V-Detect
43K 0.1%
R20
1000pF
68pF
C34
C39
43K 0.1%
R11
SET POINT: CPU CORE SUP PLY 2.0V
220pF
C49
10K
R25
V2_5
220pF
C33
R18 10K
1000pF
C30
C29 0.1uF
C28 100pF
39K 0.1%
R12
Vout = 1.19 (1+R11/R12)
SET POINT FOR I/O SUPPLY 2.5V
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
2 1 1 2
5 6 7 8 1 2 3 5 6 7 8 1 2 3 1 2 3 5 6 7 8 1 2 3 5 6 7 8
2 1 1 2
TP 1 TP 1
C
G
B
D
S
D
G
A
TP 1
TP 1
S
1
2
3
4
1
2
3
4
TP
1
CKE1
STRAP-0 PENTIUM (TM) PROCESSOR
T P 31
MA4 MA8 MA12
SRASB# CSA1# SRASA#
CSB1# SCASA#
MD49 MD51
MD36 MD7
MD0 MD2
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40
TP
TP24
TP
1
1
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40
MD40 MD8 MD9 MD41 MD27 MD29
MD57
PHLDA#
GNT2#
PHLD# FRAME#
AD30 AD22
AD4 C/BE0# AD10 AD13 PAR TRDY#
7 4 2 2 1 - 0 0 1 Berg
AD_STBB G_AD24 GND G_AD29 V3_3 G_AD1 MD1 MD33 MD4 MD38 MD50 MD19 MD53 MD22 MECC0 GND CSB4# SCASB# V3_3 WEA# DQMA4 CSA2# CSA5# GND MAA2 MAB4# MAA5 GND MAB11# Reserved2 MAA13 CKE2 Reserved3 GND V3_3 SUS_STAT1# SUS_CLK V3_3 WSC# GND
TP17
SBA5 G_AD25 G_AD30 RBF# GND V3_3 MD0 MD2 GND MD36 MD7 V3_3 MD49 MD51 GND MECC4 CSB5# CSB1# SCASA# GND SRASB# CSA1# SRASA# Reserved0 MAA4 MAA8 MAA12 MAB8# GND MAB13# CKE1 CKE5 Reserved1 V3_3 V3_3 V3_3 V3_3 GND V3_3 CPU_TYPE
U8A
B
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40
TP
ST1 ST2 SB_STB G_STOP# G_PAR G_AD15 GND G_AD14 V3_3 AD4 C/BE0# AD10 AD13 PAR TRDY# V5_0 AD30 AD22 V5_0 PHOLD# FRAME# V5_0 GND Reserved9 GNT2# GNT4# PHLDA# GND Reserved10 V3_3 MD57 MECC7 MD40 MD8 MD9 MD41 MD27 MD29 V3_3 V5_0
U8D
T P 30 1 TP
TP
B
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40
TP36 1 TP
L2_ZZ
DQM1
7 4 2 2 1 - 0 0 1 Berg
PIPE# SBA1 GND G_AD16 G_AD18 V3_3 G_C/BE1# G_TRDY# G_DEVSEL# GND AD2 AD6 AD7 GND AD15 STOP# AD17 AD24 Reserved11 GND V5_0 C/BE3# AD20 AD31 V5_0 REQ2# GNT0# V3_3 Reserved12 MD26 MD58 MD42 MD10 GND MD13 MD12 MD28 MD61 VR_PWRGD V5_0
1
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
A
MA0
MA11 V3_3
1
DQM0 CSB2#
MD52 MD23
MD3 MD37 MD48
TP21
TP TP TP32 TP29
T P 26
SUS_STAT1# SUS_CLK
MA13 V3_3 1
1
MA5
MA2
WEA# DQM4 CSA2#
SCASB#
MD1 MD33 MD4 MD38 MD50 MD19 MD53 MD22
THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT BEEN VERIFIED FOR MANUFACTURING AS AN END SER U PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
A
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40
TP
TP27
MD13 MD12 MD28 MD61 VR_PWRGD
MD26 MD58 MD42 MD10
1
REQ2# GNT0#
C/BE3# AD20 AD31 1
TP
TP
T P 25 1
MD62 MD30
MD43 MD44 MD11 MD45 MD14
REQ1# REQ3#
AD26 AD28 AD29
C/BE2#
AD8 AD12 C/BE1# DEVSEL#
TP
AD3
AD15 STOP# AD17 AD24 1
T P 14
7 4 2 2 1 - 0 0 1 B erg
G_AD31 SBA4 G_AD27 G_AD6 G_AD5 AD_STBA CLKRUN# MD32 MD35 MD6 MD39 MD18 GND MD21 MD55 V3_3 DQMA2 DQMA6 CSA3# MAB1# Reserved8 WEB# GND MAA3 MAB9# GND MAA9 CKE0 CKE4 MAA10 GND DCLKWR NMI INIT# INTR GND V3_3 PIC_CLK PICD0 GND
AD2 AD6 AD7
TP13
V3_3 SBA6 G_AD26 G_AD4 G_AD3 G_AD2 GND MD3 MD37 MD48 GND MD52 MD23 V3_3 MECC5 DQMA0 CSB2# DQMB5 CSA4# V3_3 MAB0# MAB2# V3_3 MAA0 MAB5# Reserved4 MAB12# MAA11 CKE3 Reserved5 DQMA1 Reserved6 V3_3 L2_ZZ SM_CLK SM_DATA GND Reserved7 PICD1 V3_3
U8B
NMI INIT INTR
MA10
MA9 CKE0
MA3
WEB#
SBA3 SBA2 G_C/BE3# G_AD20 G_AD17 G_C/BE2# G_FRAME# G_IRDY# V3_3 AD3 GND GND GND AD8 AD12 C/BE1# DEVSEL# V5_0 C/BE2# V5_0 AD26 AD28 AD29 Reserved13 REQ1# REQ3# REQ4# Reserved14 GND V3_3 MD43 MD44 MD11 MD45 MD14 V3_3 MD62 MD30 V5_0 V5_0
TP
T P 15
U8E
1
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40
DQM2 DQM6 CSA3#
MD21 MD55
CLKRUN# MD32 MD35 MD6 MD39 MD18
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K40
7 4 2 2 1 - 0 0 1 B erg
GND GCLKIN GCLKO G_AD23 GND G_AD22 G_AD21 G_AD19 G_AD28 AD1 AD5 AD9 AD11 AD14 PLOCK# AD18 AD21 PCLK V5_0 AD25 REQ0# V5_0 MD59 MD46 Reserved16 MD24 MD15 MD47 MD56 MD63 MD31 GND HCLK0 GND HCLK1 GND HCLK2 GND HCLK3 V5_0
FERR# IGNNE# A20M# STPCLK# DB_RST
DQM3
CSA0# CSB3# MA1
MD34 MD5 MD16 MD17 MD20 MD54
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40
1
TP
TP20
HCLK_CACHE
HCLK_TX
HCLK_CPU
MD24 MD15 MD47 MD56 MD63 MD31
MD59 MD46
AD25 REQ0#
AD1 AD5 AD9 AD11 AD14 PLOCK# AD18 AD21 PCICLK_IN
SBA7 SBA0 V3_3 G_AD8 G_C/BE0# GND G_AD7 G_AD0 V3_3 MD34 MD5 MD16 MD17 MD20 MD54 GND DQMB1 CSA0# CSB3# MAA1 MAB3# V3_3 GND MAB6# MAB7# MAB10 GND DCLKO V3_3 DQMA3 V3_3 SLP# GND V3_3 FERR# IGNNE# A20M# STPCLK# DB_RST V3_3
U8C
D
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40
7 4 2 2 1 - 0 0 1 B erg
GND G_REQ# ST0 G_GNT# G_AD13 G_AD12 G_AD10 G_AD11 G_AD9 GND AD0 MECC1 SERR# AD16 V3_3 AD23 AD19 AD27 PCI_RST# GND CSB0# IRDY# GNT3# GNT1# GND GND MAA6 MAA7 MD25 MD60 DQMA5 V3_3 MECC2 DQMA7 MECC6 MECC3 GND SMI# CPU_RST V5_0 SMI# CPU_RST
DQM7
MA6 MA7 MD25 MD60 DQM5
CSB0# IRDY# GNT3# GNT1#
AD23 AD19 AD27 PCI_RST#
AD16
AD0
C
D
Date:
Size C
Title
E
E
Thursday, February 25, 1999
Document Number XXXX-XXX
Connector
NOTE: PLACE ADDITIONAL GND TESTPONTS NEAR CONNECTOR TEST POINTS
THE FOLLOWING V5_0 PINS ARE NO-CONNECTS ON THE CHASKA MODULE: G16, J18, G19, K19, J20, H21, G22, K22, H25. ONLY J39, J40, H40, G40, K40, F40 ARE USED TO SUPPLY THE 1.25A V5_0->V2_5 REGULATOR.
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40
C
Sheet
8
of
8
Rev B.0
1
2
3
4
1
2
3
4
B
V3_3
V2_5
V(CPU)
A
B
THIS DOCUMENT CONTAINS INFORMATION PROPRIETA RY TO INTEL CORPORATION USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF INTE L IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) OF INTEL 1998
A
C67 0.01uF
C74 0.1uF
C68 0.01uF
C71 0.1uF
C86 0.01uF
C72 0.1uF
C97 0.01uF
C63 0.1uF
C96 0.01uF
C64 0.1uF
C95 0.01uF
C65 0.1uF
C105 0.01uF
C59 0.1uF
C104 0.01uF
C60 0.1uF
C102 0.01uF
C61 0.1uF
C101 0.01uF
C69 0.1uF
C99 0.01uF
C73 0.1uF
C18 0.1uF
C22 0.01uF
C24 0.1uF
C16 0.01uF
C15 0.1uF
C
C8 0.01uF
PLACE AT 400PIN CONNECTOR ACROSS 3.3V to GND PLANE.
C106 0.01uF
C58 0.1uF
C66 0.1uF
C90 0.01uF
C84 0.1uF
C94 0.01uF
PLACE AS CLOSE AS POSSIBLE TO PROCESSOR
C57 0.1uF
C92 0.1uF
C70 0.01uF
C98 0.1uF
C82 100uF
C62 0.01uF
C100 0.1uF
C83 100uF
C103 0.01uF
C20 33uF
C81 100uF
C13 100uF
C21 100uF
C12 220uF
C25 0.1uF
C26 0.1uF
C27 0.1uF
V5_0
V3_3
C75 0.1uF
D
C23 0.1uF
C14 0.1uF
V2_5
PLACE ACROSS 3.3v TO 2.5v signal crossing.
V3_3
E
Date:
Size C
Title
E
Thursday, February 25, 1999
Document Number XXXX-XXX
CPU Decoupling
Sheet
3
of
8
Rev B.0
THIS DRAWING CONTAINS INFORMATION WHICH HA S NOT BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE MISUSE OF THIS INFORMATIO N.
D
PLACE ACROSS 3.3v TO 5.0v signal crossing.
C80 0.01uF
C91 0.1uF
C93 0.01uF
PLACE AS CLOSE AS POSSIBLE TO PROCESSOR
C
1
2
3
4
Index #, defined 1-1 82371EB PCI to ISA/IDE Xcelerator (PIIX4E) 3-3
A AGP connector 2-5, 3-5 ATX power connector 4-3
B Beep codes 5-1, 5-15 BIOS 2-7 Basic Setup Screen 5-3 configuring 2-8 Configuring floppy drives 5-4 Configuring IDE drives 5-5 console redirection 5-9 Custom Setup Screen 5-6 Drive assignments 5-4 Integrated BIOS debugger 5-10 Setup Screen System 5-2 Shadow Configuration Setup Screen 5-7 Standard Diagnostics Routines Setup Screen 5-8 BIOS updates 4-1 Block diagram 3-1 Boot ROM 3-3
C CD-ROM drive 2-5 Clock synthesizer 3-5 Connectors J1, ITP connector 4-4 J1, keyboard and mouse 4-4 J11, power connector 4-3 J2, USB connector 4-4 J3, parallel port 4-5 J4, serial ports 4-5 JP1, floppy connector 4-7 JP4/JP3, IDE connector 4-6
D DIMM installing 2-8 Documents online 1-2 Drive assignments 5-4
Embedded BIOS Integrated Debugger 5-8 Embedded BIOS Manufacturing Mode 5-9 Expansion slots 4-2
F Floppy connector 4-7 Floppy drive 2-5, 3-4 installing 2-7
H Hard disk installing 2-7
I I/O, legacy support 3-3 IDE connectors (JP3, JP4) 4-6 IDE interface 3-4 Installation 2-6 Instructions, notational conventions 1-1 ISA connectors 3-4 ITP Debugger connector 4-4
J Jumpers default settings 4-10 J14, enable spread spectrum clocking 4-10 J15, clock frequency selection 4-10 J20, on/off 4-11 J21, flash BIOS VPP select 4-11 J22, flash BIOS boot block control 4-11 J23, SMI# source control 4-10 J24, CMOS RAM clear 4-11
K Keyboard 2-5, 3-4, 4-4 Kit contents 2-2
L Low-power embedded Pentium processor with MMX technology features 3-2
E
M
Embedded BIOS 5-1
Measurements, defined 1-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
Index-1
Mechanical Design 3-1 Memory Map 3-6 Mouse 2-5, 3-4, 4-4
R
N
S
Notational conventions 1-1 NVRAM 3-3
O Online help 1-2
P Parallel port 3-4, 4-5 PCI connectors 3-4 PLD A-1 Post Code Debugger 3-5, 4-2 POST codes 5-1, 5-12 Power connector 4-3 Power LEDs 2-8 Power supply 2-5, 3-3 connecting 2-8 Power-on Self Test (POST) 5-1 Processor assembly 4-1 Product literature, ordering 1-3
RTC 3-3
Serial ports 3-4, 4-5 Setup instructions 2-6 Signals, notational conventions 1-2
T Technical support 1-2
U Units of measure, defined 1-2 URL 1-2 USB connector 4-4 USB support 3-4
V Video Adapter 2-5
W Windows CE 5-10 World Wide Web 1-2 www.intel.com 1-2
Q QNX Real-Time Operating System 2-7
Index-2
Low-Power Pentium® Processor with MMX™ Technology Evaluation Platform Manual
