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Lsm_sst5912_soic

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SST5912 MONOLITHIC DUAL N-CHANNEL JFET Linear Systems replaces discontinued Siliconix & National SST5912 FEATURES  Improved Direct Replacement for SILICONIX & NATIONAL SST5912  LOW NOISE (10KHz)  en~ 4nV/√Hz  HIGH TRANSCONDUCTANCE (100MHz)  gfs ≥ 4000µS  ABSOLUTE MAXIMUM RATINGS 1  @ 25°C (unless otherwise noted)  The SST5912 are monolithic dual JFETs. The monolithic dual chip design reduces parasitics and gives better performance at very high frequencies while ensuring extremely tight matching. These devices are an excellent choice for use as wideband differential amplifiers in demanding test and measurement applications. The SST5912 is a direct replacement for discontinued Siliconix and National SST5912. Maximum Temperatures  Storage Temperature  Operating Junction Temperature  Maximum Power Dissipation  Continuous Power Dissipation (Total)  Maximum Currents  Gate Current  Maximum Voltages  Gate to Drain  Gate to Source        The 8 Pin SOIC provides ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). SST5912 Applications: ƒ Wideband Differential Amps ƒ High-Speed,Temp-Compensated SingleEnded Input Amps ƒ High-Speed Comparators ƒ Impedance Converters and vibrations detectors. MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated)  SYMBOL  CHARACTERISTIC  |VGS1 – VGS2 |  Differential Gate to Source Cutoff Voltage  ∆|VGS1 – VGS2 | / ∆T  Differential Gate to Source Cutoff     Voltage Change with Temperature  IDSS1  / IDSS2  Gate to Source Saturation Current Ratio    |IG1 – IG2 |  Differential Gate Current  500mW  50mA  ‐25V  ‐25V        MIN  ‐‐  ‐‐  TYP  ‐‐  ‐‐  MAX  15  40  UNITS  mV  µV/°C  CONDITIONS  VDG = 10V, ID = 5mA            VDG = 10V, ID = 5mA       TA = ‐55°C to +125°C  VDS = 10V, VGS = 0V  0.95  ‐‐  1  %  ‐‐  ‐‐  20  nA  0.95  ‐‐  1  %  VDG = 10V, ID = 5mA       TA = +125°C   VDS = 10V, ID = 5mA, f = 1kHz  ‐‐  85  ‐‐  dB  VDG = 5V to 10V, ID = 5mA          Click To Buy gfs1 / gfs2    ‐65°C to +150°C  ‐55°C to +135°C  CMRR  Forward Transconductance Ratio2  Common Mode Rejection Ratio  ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL  CHARACTERISTICS  MIN.  BVGSS  Gate to Source Breakdown Voltage  ‐25  VGS(off)  Gate to Source Cutoff Voltage  ‐1  VGS(F)  Gate to Source Forward Voltage  ‐‐  VGS  Gate to Source Voltage  ‐0.3  IDSS  Gate to Source Saturation Current3  7  IGSS  Gate Leakage Current3  ‐‐  IG  Gate Operating Current  ‐‐  gfs  Forward Transconductance  gos  Output Conductance  CISS  CRSS  NF  en  Input Capacitance  Reverse Transfer Capacitance  Noise Figure  Equivalent Input Noise Voltage  4000  4000  ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  TYP.  ‐‐  ‐‐  0.7  ‐‐  ‐‐  ‐1  ‐1  MAX.    ‐5  ‐‐  ‐4  40  ‐50  ‐50  UNITS    V    ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  ‐‐  7  4  10000  10000  100  150  5  1.2  1  20  10    µS      VDG = 10V, ID= 5mA  pF    dB  nV/√Hz  VDG = 10V, ID = 5mA, f = 1MHz  mA    pA  CONDITIONS  IG = ‐1µA, VDS = 0V  VDS = 10V, ID = 1nA  IG =  1mA, VDS = 0V  VDG = 10V, IG = 5mA  VDS = 10V, VGS = 0V  VGS = ‐15V, VDS = 0V  VDG = 10V, ID = 5mA  VDG = 10V, ID = 5mA, f = 10kHz, RG = 100KΩ  VDG = 10V, ID = 5mA, f = 100Hz  VDG = 10V, ID = 5mA, f = 10kHz  Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired      2. Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3% 3. Assumes smaller value in numerator    Available Packages:   Please contact Micross for full package and die dimensions: SST5912 in SOIC SST5912 available as bare die Email: [email protected] Web: www.micross.com/distribution.aspx Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.