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L6464D37-BU1HDC9B 512 Megabyte DDR400 DDR SDRAM
Performance Technology
L6464D37-BU1HDC9B 64x64 512 Megabyte DDR400 DDR SDRAM FEATURES · · · · · · · ·
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184-pin Un-buffered 8-Byte Dual-In-Line DDR SDRAM Two banks 32M × 64 JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single + 2.5 V (±0.2 V) power supply Built with 256 Mbit DDR SDRAMs organized as 32Mb x 8 in 66-Lead TSOPII package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E 2 PROM Jedec standard reference layout Gold plated contacts
GENERAL DESCRIPTION The L6464D37-BU1HDC9B is an industry standard 184-pin 8-byte Dual in-line Memory Module (DIMM) organized as 64M × 64 for main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board.
SERIAL PRESENCE-DETECT OPERATION The module incorporates serial presence-detect (SPD). The first 128 bytes is programmed by Legend to identify the module type and various SDRAM organizations and timing parameters.
ABSOLUTE MAXIMUM RATINGS* Input / Output voltage relative to VSS: 0.5-3.6 V Power supply voltage on VDD/VDDQ to VSS: 0.5-3.6 V Storage temperature range: -55 +125 °C Power dissipation: 8 W Data out current (short circuit): 50 mA * Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability
SUPPLY VOLTAGE LEVELS and DC OPERATING CONDITIONS Parameter
Symbol
Device Supply Voltage Output Supply Voltage Input Reference Voltage Termination Voltage EEPROM supply voltage DC Input Logic High DC Input Logic Low Input Leakage Current Output Leakage Current
V DD V DDQ V REF V TT V DDSPD V IH (DC) V IL (DC) I IL I OL
min. 2.5 2.5 0.49 x V DDQ V REF – 0.04 2.3 V +0.15 – 0.30 – 16 –5
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Limit Values nom. max. 2.6 2.7 2.6 2.7 0.5 x V DDQ 0.51 x V DDQ V REF V REF +0.04 2.5 3.6 V +0.3 V REF – 0.15 16 5
Unit V V V V V V V µA µA
Legend reserves the right to change products or specifications without notice.
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L6464D37-BU1HDC9B 512 Megabyte DDR400 DDR SDRAM
Performance Technology SPECIFICATIONS AND CONDITIONS PARAMETER/CONDITION Operating Current - One bank Active – Precharge Operating Current - One bank Active / Read / Precharge Precharge Power-Down Standby Current Precharge Floating Standby Current Active Power-Down Standby Current Active Standby Current Operating Current - Burst Read Operating Current - Burst Write Auto-Refresh Current Self-Refresh Current Operating Current - Four bank operation
SYMBOL IDD0 IDD1 IDD2P IDD2F IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
UNITS 720 960 160 320 200 400 1640 1840 1680 24 2440
mA
SDRAM COMPONENT AC ELECTRICAL CHARACTERISTICS Symbol t AC t DQSCK t CH t CL t HP t CK t DH t DS t IPW t HZ t LZ t DQSS t DQSQ t QHS t QH t DQSL,H t MRD t WPRES t WPST t WPRE
Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS DQS input low (high) pulse width (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble
t IS
Address and control input setup time fast slew rate
t IH
Address and control input hold time
t RPRE t RPST t RAS t RC t RFC t RCD t RP t RRD t WR t DAL t WTR t REFI t XSC
Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period Active to Read or Write delay Precharge command period Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Average Periodic Refresh Interval Exit Self Refresh to Any Execute Command
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fast slew rate slow slew rate fast slew rate slow slew rate
Min Max -0.7 0.7 -0.55 0.55 0.45 0.55 0.45 0.55 min (t CL, t CH) 5 10 0.45 0.45 2.2 -0.7 0.7 -0.7 0.7 0.75 1.25 0.45 0.55 t HP -t QHS 0.35 2 0 0.4 0.6 0.25 0.6 0.7 0.6 0.7 0.9 1.1 0.4 0.6 40 70,000 58 70 18 18 10 15 (twr/tck) + (trp/tck) 2 7.8 200
Units ns ns t CK t CK ns ns ns ns ns ns ns t CK ns ns ns t CK t CK ns t CK t CK ns ns ns ns t CK t CK ns ns ns ns ns ns ns t CK t CK µs t CK
Legend reserves the right to change products or specifications without notice.
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L6464D37-BU1HDC9B 512 Megabyte DDR400 DDR SDRAM
Performance Technology DRAM PIN ASSIGNMENT
DRAM PIN Description Pin CK, /CK CKE /CS BA0, BA1 A0~A12 /RAS, /CAS, /WE
Description Differential Clock Input Clock Enable Input Chip Select Input Bank Address Input Address Input Command Input
Pin DM
Description Input Data Mask
DQS DQ VDD, VSS, VDDQ, VSSQ VREF NS
DATA Strobe I/O DATA I/O Power Supply Reference Voltage No Connection
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Legend reserves the right to change products or specifications without notice.
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L6464D37-BU1HDC9B 512 Megabyte DDR400 DDR SDRAM
Performance Technology MODULE PIN ASSIGNMENT Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19
Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 KEY 53 54 55 56 57 58 59 60 61
Name A5 DQ24 VSS DQ25 DQS3 A4 VDD DDQ26 DDQ27 A2 VSS A1 CB0* CB1* VDD DQS8* A0 CB2* VSS CB3* BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92
Name VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS WP SDA SCL
Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
Name VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC A13* VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ BA2* DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23
Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 KEY 145 146 147 148 149 150 151 152 153
Name VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4* CB5* VDDQ CK0 /CK0 VSS DM8* A10 CB6* VDDQ CB7* VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44
Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Name /RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
MODULE PIN DESCRIPTION Pin CK0,/CK0,CK1,/CK1,CK2,/CK 2 CS0 CKE0 /RAS, /CAS, /WE A0 ~ A12 BA0, BA1 DQ0~DQ63 DQS0~DQS7 DM0~DM7 VDD
Description Differential Clock Inputs
Pin VDDQ
Description DQs Power Supply
Chip Select Input Clock Enable Input Command Sets Inputs Address Bank Address Data Inputs/Outputs Data Strobe Inputs/Outputs Data-in Mask Power Supply
VSS VREF VDDSPD SA0~SA2 SCL SDA VDDID DU NC
Ground Reference Power Supply Power Supply for SPD E 2 PROM Address Inputs E 2 PROM Clock E 2 PROM Data I/O VDD Identification Flag Do not Use No Connection
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L6464D37-BU1HDC9B 512 Megabyte DDR400 DDR SDRAM
Performance Technology MODULE METROLOGY
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