Mem1g72d2fbd-25a1 8 Gigabyte

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Datasheet | Rev. 1.1 | 2011 MEM1G72D2FBD-25A1 8 Gigabyte (1G x 72 Bit) MEM1G72D2FBD-3A1 8 Gigabyte (1G x 72 Bit) Fully Buffered DDR2 DIMM memory module RoHS Compliant Product Datasheet Version 1.1 1 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Version: Rev. 1.1, MAR 2011 SPD-data for -25 speed added Version: Rev. 1.0, OCT 2010 1.0 Inital release We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] Datasheet Version 1.1 2 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Features                       JEDEC-compatible DDR2 240-Pin Fully Buffered Dual-In-Line Memory Module (FBDIMM) Capacity: 8GB, organized 1Gig x 72 Bit Maximum Data Transfer Rate MEM1G72D2FBD-25A1: 6.40 GB/Sec Maximum Data Transfer Rate MEM1G72D2FBD-3A1: 5.30 GB/Sec 3.2 Gb/s, 4 Gb/s, and 4.8 Gb/s link transfer rates Power Supply for DRAM: VDD, VDDQ =1.8± 0.1 V Power Supply for AMB: VCCFBD =1.5+ 0.075/- 0.045V 72 Bit Data Bus Width with ECC Buffer interface with high-speed differential point-to-point Link at 1.5 volt Channel error detection and reporting Channel fail-over mode support Programmable CAS Latency (CL): 3, 4, 5, 6 (Clock) Posted CAS by programmable additive latency (AL = 0,1,2,3 and 4 Clock) for better command and data bus efficiency Automatic DDR2 DRAM bus and channel calibration MBIST and IBIST test functions Transmitter de-emphasis to reduce ISI Transparent mode for DRAM test support Serial Presence Detect (SPD) with EEPROM Gold Edge Contacts 100% RoHS-Compliant Standard Module Height 30.35mm (1.19 inch) Operating Temperature Range 0 to 95°C tCASE (Note: The average refresh-interval must be reduced to 3.9μs (MAX) when tCASE exceeds +85°C) Datasheet Version 1.1 3 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Table 1 - Ordering Information for RoHS Compliant Product Part Number Speed Memory Clock Clock Cycles (CL-tRCD-tRP Temperature Range MEM1G72D2FBD-25A1L4 PC2-6400 400MHz 0° to 95°C 8GB FBDIMM IDT AMB0780L4 MEM1G72D2FBD-3A1L4 PC2-5300 333Mhz 5-5-5 0° to 95°C Note: The average refresh-interval must be reduced to 3.9μs (MAX) when TCASE exceeds +85°C 8GB FBDIMM IDT AMB0780L4 5-5-5 Module Type AMB type Table 2 - Performance Range Speed Max Clock Frequency (min. Clock Cycle time @ min. CAS Latency) MEM1G72D2FBD-25A1L4 PC2-6400 400MHz (2.5ns@CL=5) 333MHz (3.0ns@CL=5) PC2-5300 266MHz (3.75ns@CL=4) PC2-4200 200MHz (5.0ns@CL=3) PC2-3200 MEM1G72D2FBD-3A1L4 333MHz (3.0ns@CL=5) PC2-5300 266MHz (3.75ns@CL=4) PC2-4200 200MHz (5.0ns@CL=3) PC2-3200 Table 3 – DRAM component information Brand Part No Type. Memphis Memphis MEM2G04D2DABG -25 512Mx4 MEM2G04D2DABG -3 512Mx4 Max. DRAM Speed DDR2-800 @ CL5 DDR2-667 @ CL5 DRAM Packing FBGA 60 ball, lead free FBGA 60 ball, lead free # of DRAMs per module 36 36 Table 4 - Addressing Parameter Value Refresh count Row address Device bank address Device configuration Column address Module rank address Number of devices 8K 32K A[14:0] 8 BA[2:0] 2Gb (512Mx4) 2K A[11, 9:0] 2 /S[1:0] 36 Datasheet Version 1.1 4 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Table 5 - Pin Assignment Pin Name Pin Name Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID1 ̅̅̅̅̅̅̅̅̅ VSS RFU RFU VSS PN0 ̅̅̅̅ VSS PN1 ̅̅̅̅ VSS PN2 ̅̅̅̅ VSS PN3 ̅̅̅̅ VSS PN4 ̅̅̅̅ VSS PN5 ̅̅̅̅ VSS PN13 ̅̅̅̅̅ VSS VSS RFU RFU VSS VSS PN12 ̅̅̅̅̅ VSS PN6 ̅̅̅̅ VSS PN7 ̅̅̅̅ VSS PN8 ̅̅̅̅ VSS PN9 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 VDD VDD VDD VSS VDD VDD VDD VSS VCC VCC VSS VCC VCC VSS VTT VID0 DNU/M_Test VSS RFU RFU VSS SN0 ̅̅̅̅ VSS SN1 ̅̅̅̅ VSS SN2 ̅̅̅̅ VSS SN3 ̅̅̅̅ VSS SN4 ̅̅̅̅ VSS SN5 ̅̅̅̅ VSS SN13 ̅̅̅̅̅ VSS VSS RFU RFU VSS VSS SN12 ̅̅̅̅̅ VSS SN6 ̅̅̅̅ VSS SN7 ̅̅̅̅ VSS SN8 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Datasheet Version 1.1 ̅̅̅̅ VSS SN9 5 Name ̅̅̅̅ VSS PN10 ̅̅̅̅̅ VSS PN11 ̅̅̅̅̅ VSS VSS PS0 ̅̅̅̅ VSS PS1 ̅̅̅̅ VSS PS2 ̅̅̅̅ VSS PS3 ̅̅̅̅ VSS PS4 ̅̅̅̅ VSS VSS RFU RFU VSS VSS PS9 ̅̅̅̅ VSS PS5 ̅̅̅̅ VSS PS6 ̅̅̅̅ VSS PS7 ̅̅̅̅ VSS PS8 ̅̅̅̅ VSS RFU RFU VSS VDD VDD VSS VDD VDD VDD VSS VDD VDD VTT SA2 SDA SCL Pin 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name ̅̅̅̅ VSS SN10 ̅̅̅̅̅ VSS SN11 ̅̅̅̅̅ VSS VSS SS0 ̅̅̅̅ VSS SS1 ̅̅̅̅ VSS SS2 ̅̅̅̅ VSS SS3 ̅̅̅̅ VSS SS4 ̅̅̅̅ VSS VSS RFU RFU VSS VSS SS9 ̅̅̅̅ VSS SS5 ̅̅̅̅ VSS SS6 ̅̅̅̅ VSS SS7 ̅̅̅̅ VSS SS8 ̅̅̅̅ VSS RFU RFU VSS SCK ̅̅̅̅ VSS VDD VDD VDD VSS VDD VDD VTT VDDSPD SA0 SA1 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Table 6 - Pin Description Pin Name Description SCK System Clock Input, positive line1 PN[13:0] PS[9:0] ] SN[13:0] SS[9:0] Pin Name Description AMB reset signal System Clock Input, negative line1 VCC AMB Core Power and AMB Channel Interface Power Primary Northbound Data, positive lines VDD SDRAM Power and AMB DRAM I/O Power Primary Northbound Data, negative lines VTT SDRAM Address/Command/Clock Termination Power (VDD/2) Primary Southbound Data, positive lines VSS Ground Primary Southbound Data, negative lines VDDSPD EEPROM Power Secondary Northbound Data, positive lines SDA EEPROM Data Input / Output Secondary Northbound Data, negative lines SCL EEPROM Clock Input Secondary Northbound Data, positive lines SA[2:0] EEPROM Address Inputs, also used to select DIMM number in the AMB Secondary Northbound Data, negative lines RFU Reserved for Future use2 VID[1:0] Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs. VID[0] is VDD value: OPEN=1.8V, GND=1.5V; VID[1] is VCC value: OPEN=1.5V, GND=1.2V. DNU / M_Test The DNU / M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on the module .It is not intended to be used in normal system operation and must not be connected (DNU) in a system. This test pin may have other features on future card designs and if it does, will be included in this specification at that time. Note: 1 2 System Clock Signals SCK and switch at one half the DRAM CK, frequency. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility. Datasheet Version 1.1 6 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM Notes:  Dimensioning and tolerancing conform to ASME Y14.5M-1994.  Tolerances an all dimensions ± 0.15 unless otherwise specified.  All dimensions are in millimeters. Datasheet Version 1.1 7 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Figure 2 - Dimension with Heatspreader Datasheet Version 1.1 8 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Figure 3 - Functional Block Diagram (Page 1 of 3) /S1 DQS /DQS0 /DQS D0-D3 /DQS DM DM D0-D3 DQS DQS /DQS1 /DQS D0-D3 /DQS DM DM /DQS4 /DQS D0-D3 /DQS DM DM D16-D19 /CS U21 DQS5 DQS DQS /DQS5 /DQS D0-D3 /DQS DM DM D20-D23 D0-D3 U6 U22 /CS /CS U17 /CS D0-D3 U5 D0-D3 U1 /CS DQS /CS DQS1 D4-D7 DQS U18 /CS U2 DQS4 /CS DQS /CS DQS0 D0-D3 /CS /CS /CS /S0 DQS2 DQS DQS DQS6 DQS DQS /DQS2 /DQS D0-D3 /DQS /DQS6 /DQS D0-D3 /DQS DM DM DM DM D0-D3 U20 DQS3 /DQS3 D12-D15 D0-D3 U7 U23 /CS /CS /CS U4 D24-D27 /CS D8-D11 DQS DQS DQS7 DQS DQS /DQS D0-D3 /DQS /DQS7 /DQS D0-D3 /DQS DM DM DM DM D28-D31 U19 D0-D3 U8 U24 DQS8 DQS DQS /DQS8 /DQS D0-D3 /DQS DM DM CB0-CB3 U33 Datasheet Version 1.1 9 /CS /CS U3 D0-D3 D0-D3 U34 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Figure 4 - Functional Block Diagram (Page 2 of 3) /S1 DQS DQS /DQS9 /DQS D0-D3 DM DM DQS DQS /DQS /DQS13 D48-D51 /DQS D0-D3 /DQS D0-D3 DM DM U13 /CS DQS DQS /DQS10 /DQS D0-D3 DM DM U29 DQS14 DQS DQS /DQS /DQS14 D52-D55 /DQS D0-D3 /DQS D0-D3 DM DM U14 U30 /CS /CS U25 /CS U9 D0-D3 /CS DQS10 D0-D3 /CS U26 /CS U10 D36-D39 /CS DQS13 /CS DQS9 D32-D35 /CS /CS /CS /S0 DQS11 DQS DQS DQS15 DQS DQS /DQS11 /DQS D0-D3 /DQS /DQS15 /DQS D0-D3 D56-D59 /DQS D0-D3 DM DM DM DM U28 DQS12 /DQS12 D44-D47 U15 U31 /CS /CS /CS U12 D0-D3 /CS D40-D43 DQS DQS DQS16 DQS DQS /DQS D0-D3 /DQS /DQS16 /DQS D0-D3 D60-D63 /DQS D0-D3 DM DM DM DM U27 U16 U32 DQS17 DQS DQS /DQS17 /DQS D0-D3 /DQS DM DM CB4-CB7 U35 Datasheet Version 1.1 /CS /CS U11 D0-D3 10 D0-D3 U36 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Figure 5 - Functional Block Diagram (Page 3 of 3) VTT Terminators VCC B1 VDDSPD E1, B1 VDD U1-U36, B1 VREF U1-U36 VSS U1-U36, E1, B1 All address / command / control / clock VTT D0-D63 PN0-PN13 CB0-CB7 DQS0-DQS17 /PN0-/PN13 PS0-PS9 /DQS0-/DQS17 /PS0-/PS9 /S0->/CS (U1-U16,U33,U35) SN0-SN13 CKE0->CKE (U1-U16,U33,U35) /S1->/CS (U17-U32,U34,U36) /SN0-/SN13 AMB B1 SS0-SS9 /SS0-/SS9 CKE1->CKE (U17-U32,U34,U36) ODT->ODT0 (U1-U36) SCL BA0-BA2 (U1-U36) SDA A0-A15 (U1-U36) SA1-SA2 /RAS (U1-U36) SA0 /CAS (U1-U36) /RESET /WE (U1-U36) SCK, /SCK CK, /CK (U1-U36) SDA SDA SCL SCL E1 WP SA0 SA1 SA2 SA0 SA1 SA2 Datasheet Version 1.1 VDD VDDSPD 11 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Electrical Parameter Table 7 - Absolute Maximum DC Ratings Parameter Symbol Rating Unit Notes Voltage on any pin relative to VSS Voltage on VCC pin relative to VSS Voltage on VDD pin relative to VSS Voltage on VTT pin relative to VSS Storage temperature DRAM Operation temperature (Ambient) AMB Operation temperature (Ambient) VIN VOUT VCC VDD VTT TSTG TCASE TCASE -0.3V ~ 1.75 -0.3V ~ 1.75 -0.5V ~ 2.3 -0.5V ~ 2.3 -55 ~ 100 0 ~ 95 0 ~ 110 V V V V oC oC oC 1 1 1 1 1 1,2 1 Notes:   tresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate. Table 8 - DC Electrical Characteristics and Operating Conditions Parameter / Condition Symbol Rating Min AMB supply voltage DRAM supply voltage Termination voltage EEPROM supply voltage SPD Input HIGH (logic 1) voltage SPD Input LOW (logic 0) voltage RESET Input HIGH (logic 1) voltage RESET Input LOW (logic 0) voltage Leakage Current (RESET) Leakage Current (link) VCC VDD VTT VDDSPD VIH(DC) VIL(DC) VIH(DC) VIL(DC) IL IL 1.455 1.7 0.48 x VDD 3.0 2.1 1 -90 -5 Typ. 1.50 1.8 0.5 x VDD 3.3 - Units Notes Max 1.575 1.9 0.52 x VDD 3.6 VDDSPD 0.8 0.5 90 5 V V V V V V V V uA uA 1 2 2 3 2 3 4 Notes: 1 2 3 4 Applies to AMD and SPD. Applies to serial memory buffer (SMB) and SPD bus signals. Applies to AMD CMOS signal /RESET. For all other AMB-related DC parameters, please refer to the high-speed differential link interface specification Datasheet Version 1.1 12 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Table 9 - Timing Parameters Parameter / Condition Symbol Min Max Units Notes EI Assertion Pass-Thru Timing tEI Propagtet - 4 clks EI Desertion Pass-Thru Timing tEID - bitlock clks 2 EI Assertion Duration tEI 100 - clks 1,2 Bit Lock Interval tBitLock - 119 frames 1 Frame Lock Interval tFrameLock - 154 frames 1 Notes: 1 2 Defined in FB-DIMM Architecture and Protocol Spec. Clocks defined as core clocks = 2x SCK input Table 10 - IDD Specifications with Conditions and Operation Current Parameter / Condition Symbol Current Units Notes MEM1G72D2FBD- MEM1G72D2FBD25A1L4 3A1L4 Idle current, single, or last DIMM: L0 state; Idle (0% bandwidth); Primary channel enabled; Secondary channel disabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Idle current, first DIMM: L0 state; Idle (0% bandwidth); Primary and secondary channels enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Active power: L0 state; 50% DRAM bandwidth; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH Active power, data pass through: L0 state; 50% DRAM bandwidth to downstream DIMM; 67% READ; 33% WRITE; Primary and secondary channels enabled; DDR2 SDRAM clock active; CKE HIGH; Command and address lines stable Training: Primary and secondary channels enabled; 100% toggle on all channel lanes; DRAMs idle; 0% bandwidth; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active IBIST overall IBIST modes: DRAM idle (0% bandwidth); Primary channel enabled; Secondary channel enabled; CKE HIGH; Command and address lines stable; DDR2 SDRAM clock active Electrical idle: DRAM idle (0% bandwidth); Primary channel disabled; Secondary channel disabled; CKE LOW; Command and address lines floated; DDR2 SDRAM clock active; ODT and CKE driven LOW ICC_IDLE_0 1900 1700 mA @1.5V IDD_IDLE_0 2120 2120 mA @1.8V ICC_IDLE_1 2800 2600 mA @1.5V IDD_IDLE_1 2120 2120 mA @1.8V ICC_ACTIVE_1 3600 3200 mA @1.5V IDD_ACTIVE_1 5810 5810 mA @1.8V ICC_ACTIVE_2 2800 2600 mA @1.5V IDD_ACTIVE_2 2120 2120 mA @1.8V ICC_TRAINING 2700 2500 mA @1.5V IDD_TRAINING 2120 2120 mA @1.8V ICC_IBIST 2900 2700 mA @1.5V IDD_IBIST 2120 2120 mA @1.8V ICC_EI 1800 1600 mA @1.5V IDD_EI 632 632 mA @1.8V Table 11 - VTT currents Parameter / Condition Symbol Typ MAX Units Idle current, DDR2 SDRAM device power down Active power, 50% DDR2 SDRAM BW ITT1 ITT2 - 700 700 mA mA Datasheet Version 1.1 13 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Table 12 - SPD Information Byte NO. Note Description 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1 2 3 4 SPD Revision Key Byte / DRAM Device Type Voltage Levels of this Assembly SDRAM Addressing 5 Module Physical Attributes 6 Module Type / Thickness 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-26 Module Organization Fine Timebase Dividend and Divisor Medium Timebase Dividend Medium Timebase Divisor SDRAM Minimum Cycle Time (tCKmin) SDRAM Maximum Cycle Time (tCKmax) SDRAM /CAS Latencies Supported SDRAM Minimum /CAS Latency Time (tCAS) SDRAM Write Recovery Times Supported SDRAM Write Recovery Time (tWR) SDRAM Write Latencies Supported SDRAM Additive Latencies Supported SDRAM Minimum /RAS to /CAS Delay (tRCD) SDRAM Minimum Row Active to Row Active Delay (tRRD) SDRAM Minimum Row Precharge Time (tRP) SDRAM Upper Nibbles for tRAS and tRC SDRAM Minimum Active to Precharge Time (tRAS) SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC) SDRAM Internal Write to Read Command Delay (tWTR) SDRAM Internal Read to Precharge Command Delay (tRTP) SDRAM Burst Lengths Supported SDRAM Terminations Supported SDRAM Drivers Supported SDRAM Average Refresh Interval (tREFI) / Double Refresh mode bit / High Temperature self-refresh rate support indication Bits 7:4: Tcasemax Delta. Bits 3:0: DT4R4W Delta Thermal resistance of SDRAM device package from top (case) to ambient (Psi T-A SDRAM) at still air condition based on JESD51-2 standard. DT0: Case temperature rise from ambient due to IDD0/activateprecharge operation minus 2.8oC offset temperature DT2N/DT2Q: Case temperature rise from ambient due to IDD2N/precharge standby operation from UDIMM and due to IDD2Q/precharge quiet standby operation for RDIMM. DT2P: Case temperature rise from ambient due to IDD2P/precharge power-down operation DT3N: Case temperature rise from ambient due to IDD3N/active standby operation DT4R/Mode Bit: Bits 7:1 Case temperature rise from ambient due to IDD4R/page open burst read operation. Bit 0: Mode bit to specify if DT4W is greater or less than DT4R. 27 28 29 30 31 32 33 34 35 36 37 38 39 Datasheet Version 1.1 14 Hex MEM1G72D2FBD-25A1 CRC coverage 0-116 Byte, SPD Byte Total: 256Byte, SPD Use: 176Byte Rev 1.1 DDR2 SDRAM FB-DIMM Channel 1.5V; DRAM 1.8V No. of Row: 15; No. of Col: 11; No. of Rank: 8 Height: 30.35mm, Thickness: Max 8mm FB-DIMM, (width: 133.35mm) 2 Rank / x4 5/2 (2.5ps) 1/4 (0.25ns) 1/4 (0.25ns) 2.5ns 8ns CL 3, 4, 5 12.5ns 2, 3, 4, 5 CLK 15ns 2, 3, 4, 5, 6, 7, 8 CLK 0, 1, 2, 3, 4 CLK 12.5ns 7.5ns 12.5ns 45ns 52.5ns 195ns MEM1G72D2FBD-3A1 CRC coverage 0-116 Byte, SPD Byte Total: 256Byte, SPD Use: 176Byte Rev 1.1 DDR2 SDRAM FB-DIMM Channel 1.5V; DRAM 1.8V No. of Row: 15; No. of Col: 11; No. of Rank: 8 Height: 30.35mm, Thickness: Max 8mm FB-DIMM, (width: 133.35mm) 2 Rank / x4 5/2 (2.5ps) 1/4 (0.25ns) 1/4 (0.25ns) 3ns 8ns CL 3, 4, 5 15ns 2, 3, 4, 5 CLK 15ns 2, 3, 4, 5, 6, 7, 8 CLK 0, 1, 2, 3, 4 CLK 15ns 7.5ns 15ns 45ns 60ns 195ns -25A1 92 -3A1 92 11 09 12 69 11 09 12 69 23 23 07 07 10 52 01 04 0A 20 33 32 52 3C 72 50 32 1E 32 00 B4 D2 0C 03 10 52 01 04 0C 20 33 3C 42 3C 72 50 3C 1E 3C 00 B4 F0 0C 03 7.5ns 7.5ns BL 4, 8 50, 75, 150 ohm Weak Driver 7.8us (Double refresh @ above 85oC) 95oC 61 7.5ns 7.5ns BL 4, 8 50, 75, 150 ohm Weak Driver 7.8us (Double refresh @ above 85oC) 95oC 61 1E 1E 03 07 01 C2 1E 1E 03 07 01 C2 50 7A 50 7A - - 48 48 - - 2E 2E - - 36 36 - - 27 27 4C 4C - MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Byte NO. 40 41 42-59 60-78 79 80 81-82 83 84 85 86 87 88 89 90 91 92 93 94-97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115-116 117-118 119 120-121 122-125 126-127 128-145 Note Description MEM1G72D2FBD-25A1 DT5B: Case temperature rise from ambient due to IDD5B/burst refresh operation DT7: Case temperature rise from ambient due to IDD7/bank interleave read mode operation. Reserved Reserved FB-DIMM ODT Values Reserved FB-DIMM Channel Protocols Supported Back-to-Back Access Turnaround Time AMB Read Access Time for DDR2-800 (AMB.LINKPARNXT[1:0]=11) AMB Read Access Time for DDR2-667 (AMB.LINKPARNXT[1:0]=10) AMB Read Access Time for DDR2-533 (AMB.LINKPARNXT[1:0]=01) Thermal Resistance of AMB Package from top (case) to ambient (Psi T-A AMB) AMB DT Idle_0 AMB DT Idle_1 AMB DT Idle_2 AMB DT Active_1 AMB DT Active_2 AMB DT L0s Reserved AMB Case Temperature Maximum (Tcase_max) Airflow impedance and category bits Reserved AMB Personality Bytes: Pre-initialization (1) AMB Personality Bytes: Pre-initialization (2) AMB Personality Bytes: Pre-initialization (3) AMB Personality Bytes: Pre-initialization (4) AMB Personality Bytes: Pre-initialization (5) AMB Personality Bytes: Pre-initialization (6) AMB Personality Bytes: Post-initialization (1) AMB Personality Bytes: Post-initialization (2) AMB Personality Bytes: Post-initialization (3) AMB Personality Bytes: Post-initialization (4) AMB Personality Bytes: Post-initialization (5) AMB Personality Bytes: Post-initialization (6) AMB Personality Bytes: Post-initialization (7) AMB Personality Bytes: Post-initialization (8) AMB Manufacturer’s JEDEC ID Code Module ID: Module Manufacturer’s JEDEC ID Code Module ID: Module Manufacturing Location Module ID: Module Manufacturing Date Module ID: Module Serial Number Cyclical Redundancy Code Module Part Number - -3A1 20 - 23 23 Rank0/1 (150ohm) - 00 00 22 00 02 00 10 54 50 44 32 00 00 22 00 02 00 10 54 50 44 32 44 6C 6C 8B 70 00 00 11 0A 00 A5 03 DA 66 97 9C DB 36 04 AF FA FA E8 E8 7F B3 44 6C 6C 8B 70 00 00 11 0A 00 A5 02 DA 66 97 9C DB 36 04 AF F0 F0 E8 E8 7F B3 6E 88 E1 77 Rank0/1 (150ohm) 111°C Manufacturer's data Manufacturer's data Manufacturer's data Manufacturer's data Manufacturer's data Manufacturer's data 146-147 Module Revision Code Manufacturer's data Manufacturer's data 148-149 SDRAM Manufacturing’s JEDEC ID Code Manufacturer's data Manufacturer's data 150-175 Manufacturer’s Specific Date Manufacturer's data Manufacturer's data 176-255 Open for customer use Manufacturer's data Manufacturer's data Datasheet Version 1.1 15 Hex -25A1 20 111°C Manufacturer's data Manufacturer's data Manufacturer's data Manufacturer's data MEM1G72D2FBD-3A1 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 Contents Features 3 Table 1 - Ordering Information for RoHS Compliant Product 4 Table 2 - Performance Range 4 Table 3 – DRAM component information 4 Table 4 - Addressing 4 Table 5 - Pin Assignment 5 Table 6 - Pin Description 6 Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM 7 Figure 2 - Dimension with Heatspreader 8 Figure 3 - Functional Block Diagram (Page 1 of 3) 9 Figure 4 - Functional Block Diagram (Page 2 of 3) 10 Figure 5 - Functional Block Diagram (Page 3 of 3) 11 Electrical Parameter 12 Table 7 - Absolute Maximum DC Ratings 12 Table 8 - DC Electrical Characteristics and Operating Conditions 12 Table 9 - Timing Parameters 13 Table 10 - IDD Specifications with Conditions and Operation Current 13 Table 11 - VTT currents 13 Table 12 - SPD Information 14 Contents 16 List of Tables 17 List of Figures 17 MEMPHIS | Global Presence 18 Datasheet Version 1.1 16 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 List of Tables Table 1 - Ordering Information for RoHS Compliant Product Table 2 - Performance Range Table 3 – DRAM component information Table 4 - Addressing Table 5 - Pin Assignment Table 6 - Pin Description Table 7 - Absolute Maximum DC Ratings Table 8 - DC Electrical Characteristics and Operating Conditions Table 9 - Timing Parameters Table 10 - IDD Specifications with Conditions and Operation Current Table 11 - VTT currents Table 12 - SPD Information 4 4 4 4 5 6 12 12 13 13 13 14 List of Figures Figure 1 - PCB Dimension 240 Pin DDR2 Fully Buffered DIMM Figure 2 - Dimension with Heatspreader Figure 3 - Functional Block Diagram (Page 1 of 3) Figure 4 - Functional Block Diagram (Page 2 of 3) Figure 5 - Functional Block Diagram (Page 3 of 3) Datasheet Version 1.1 17 7 8 9 10 11 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1 MEMPHIS | Global Presence EMEA (Europe, Middle East, Africa) Germany (Headquarter): Spain: Russia: Memphis Electronic AG Saalburgstr. 155 D-61350 Bad Homburg v.d.H. Germany Phone: +49 (0)6172 90 35 40 Fax: +49 (0)6172 90 35 60 Email: [email protected] Memphis Electronic AG Representative Office Spain Marina 60, 5, 1, 2 Barcelona 08005 Spanien Tel.: +34 93 317 0242 E-Mail: [email protected] Memphis Electronic AG Representative Office Russia Prospect 60 let Oktiabria Office 2 117036 Moscow Russia Phone: +7 925 855 56 91 Email: [email protected] Memphis Electronic Inc. Boston Office 20 Sunset Rock Lane Reading, Massachusetts 01867 USA Phone.: +1 781 872 1366 Fax: +1 713 600 6081 Email: [email protected] Memphis Electronic Inc. San Jose Office 6576 Bose Lane CA 95120 San Jose, USA Phone: +1 408 268 4002 Fax: +1 713.600.6081 Email: [email protected] China: Singapore: Japan: Memphis Electronic Hong Kong Ltd. Room B, 18/F., EGL Tower 83 Hung To Road, Kwun Tong Hong Kong Tel.: +852 2111 1071 Fax: +852 2111 1072 E-Mail: [email protected] Memphis Electronic Hong Kong Ltd. Singapore Representative Office 25 International Business Park #04-103D German Centre 609916 Singapore Phone: +65 68 99 37 90 Fax: +65 6899 3153 Email: [email protected] Memphis Electronic Japan Japan Representative Office #418, Sotokanda Stork bldg.4F, 6-15-14, Sotokanda, Chiyoda-ku Tokyo, 101-0021, Japan Tel.: +81-3-5807-6787 Fax: +81-3-5807-6788 Email: [email protected] Americas (american economic area) USA: Toll Free: +1 877 600 6080 Memphis Electronic Inc. 2323 S Shepherd Dr, Suite 910 Houston, Texas 77019, USA Phone: +1 713.600.6080 Fax: +1 713.600.6081 Email: [email protected] APAC (Asian Pacific economic area) Memphis Electronic Hong Kong Ltd. Shanghai Representative Office Unit 753A, Tower 3, 88 Keyuan Road, Pudong, Shanghai, 201203, China Tel.: +86-21 5130 8707 Fax: +86-21 5130 8789 E-Mail: [email protected] Datasheet Version 1.1 18 MEM1G72D2FBD-25A1 MEM1G72D2FBD-3A1