Transcript
DRAM Memory System: Lecture 3 Spring 2003
Memory System Organization
Bruce Jacob David Wang
Dimm1 Dimm2
Dimm3 Dimm4
University of Maryland
Single Channel SDRAM Controller
“Mesh Topology”
Addr & Cmd Data Bus Chip (DIMM) Select
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang
DRAM System Organization Where is the data?
University of Maryland
Rank? Bank? Row? Column?
CPU
Request (Read) (Physical Address) (Cachline length = 64B)
Data
Data Magic Memory Controller Command Sequence
Rank Address = ? Bank Address = ? Row address = ? Column Address ?
DRAM Memory System: Lecture 3 Spring 2003
Rank Part 1
Bruce Jacob David Wang
Bank
Rank
University of Maryland
Magic Memory Controller
It’s a “bank” of chips that responds to a single command and returns data. “Bank” terminology already used.
DRAM Memory System: Lecture 3 Spring 2003
Rank Part 2
Bruce Jacob David Wang
Rambus RIMM Rank Count is Number of Devices
University of Maryland
SDRAM Double Sided Dimm Two Ranks SDRAM Single Sided Dimm One Rank SDRAM/DDR SDRAM system: 4~6 ranks RDRAM system: <= 32 ranks
DRAM Memory System: Lecture 3
Row, Bitlines and Wordlines
Spring 2003
Bank Bank 2
Bruce Jacob David Wang
Bank 3 Bank 1
University of Maryland Control Logic
Bank 0 Array Bank 0 xArray (8196 512 x 16) Bank 0 (8196 xArray 512 x 16) Bank 0 Array (8196 x 512 x 16) (8196 x 512 x 16) Sense Amp Sense Amp Sense Amp Sense Amp I/O Gating
“Banks” of indepedent memory arrays inside of a DRAM Chip SDRAM/DDR SDRAM system: 4 banks RDRAM system: “32” split or 16 full banks
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang University of Maryland
Row and Column Revisited “Column” Defined Column: Smallest addressable quantity of DRAM on chip SDRAM*: column size == chip data bus width (4, 8,16, 32) RDRAM: column size != chip data bus width (128 bit fixed) SDRAM*: get “n” columns per access. n = (1, 2, 4, 8) RDRAM: get 1 column per access.
4 bit wide columns #0 #1 #2 #3 #4 #5
“One Row” of DRAM
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang University of Maryland
Channel Part 1 Memory Controller
DDR SDRAM
Current “PC Class” memory system. 1 physical channel of DDR SDRAM Memory Controller
DRDRAM DRDRAM
Intel i850 DRDRAM memory system. 2 physical channel. 1 logical channel
Memory Controller
DDR SDRAM DDR SDRAM
Intel “Granite Bay” memory system. 2 physical channel. 1 logical channel
DRAM Memory System: Lecture 3 Spring 2003
Channel Part 2
Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
DRDRAM Memory Controller
DRDRAM DRDRAM DRDRAM DRDRAM
Memory Controller
DRDRAM DRDRAM DRDRAM
Alpha EV7 DRDRAM memory system 8* physical channels. 2 logical channels
DRAM Memory System: Lecture 3 Spring 2003
Address Mapping I
Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
CPU Physical Address Magic Memory Controller
Memory Address Variable numbers of rank, coumn, row.
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Address Mapping II Device config
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 M x 4 x 4 bks 8 M x 8 x 4 bks
4 M x 16 x 4 bks
row addressing
8K (A0 - A12)
8K (A0 - A12)
8K (A0 - A12)
bank addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
col addressing
2K(A0-A9,A11)
1K (A0-A9)
512 (A0- A8)
“DRAM page size” differs with different configurations. 8 of the x8 devices form 64 bit wide data bus 4 of the x16 devices form 64 bit wide data bus
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang
Address Mapping III 32 bit physical address (byte addressable)
University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
no rank memory id
32
1413 12 11
31 29 28 27 26 row id
Device config
bank id
column id
0 not used
16 Meg x 16
Configuration
4 M x 16 x 4 bks
row addressing
8K (A0 - A12)
bank addressing
4 (BA0, BA1)
col addressing
512 (A0- A8)
One Address Mapping Scheme for 512 M B of M em ory
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Where’s the data? Part 1 Read Request Physical Address: 0x0AC75C38
Magic Memory Controller 32 bit physical address (byte addressable)
no rank memory id
32
1413 12 11
31 29 28 27 26 row id
bank id
column id
0 not used
Rank id = 1 Bank id = 1 Row id = 0x0B1D Column id = 0x187
DRAM Memory System: Lecture 3 Spring 2003
Where’s the data? Part 2
Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Bank id = 1 Rank id = 1
Column id = 0x187
Row id = 0x0B1D
FPM / EDO / SDRAM / etc.
DRAM Memory System: Lecture 3 Spring 2003 Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Where’s the data? Part 3 c1 d1 d1 d1 d1 Col id 0x187
Col id 0x186 Col id 0x184
Col id 0x185
Given one column address, SDRAM bursts back “n” beats”, with critical word first. “n” is programmable. n = 4 for 32 byte cache line. n = 8 for 64 byte cache line.
FPM / EDO / SDRAM / etc.
DRAM Memory System: Lecture 3 Spring 2003
Memory Modules I
Bruce Jacob David Wang
Bare DIP’s shoved into sockets
University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Put chips on PCB, make a module
Data
Address FPM / EDO / SDRAM / etc.
Data
DRAM Memory System: Lecture 3 Spring 2003
Memory Modules II
Bruce Jacob David Wang
Registered DIMM
University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Latch Data
Data Address
One extra cycle to buffer and distribute address. More chips (load) can be placed on module
DRAM Memory System: Lecture 3 Spring 2003
Memory Modules III Samsung CL2
Bruce Jacob David Wang
Elpida CL3
Samsung CL2
University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
Magic Memory Controller
tRAS ? tRP ? tCL ? Row count? Column count? 128 Mb *4 128 Mb *8 = 64 MB = 128 MB
256 Mb *4 = 128 MB
How does the system configure itself? SPD.
DRAM Memory System: Lecture 3 Spring 2003
SPD: Serial Presence Detect
Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
SPD: Tiny EEPROM Contains Parameters - Speed settings - Configurations - Programmed by module maker
DRAM Memory System: Lecture 3 Spring 2003
SDRAM Chip: 54 Pin TSOP 16M x 16 32M x 8 64M x 4
Bruce Jacob David Wang University of Maryland then the data is valid on the data bus ... depending on what you are using for in/out buffers, you might be able to overlap a litttle or a lot of the data transfer with the next CAS to the same page (this is PAGE MODE)
VCC DQ0 VCCQ DQ1 DQ2 V SSQ DQ3 DQ4 VCCQ DQ5 DQ6 V SSQ DQ7 VCC DQML W E# CAS# RAS# CS# A 13 (B A 0) A 12 (B A 1) A 10 (A P ) A0 A1 A2 A2 VCC
VCC DQ0 VCCQ NC DQ1 V SSQ NC DQ2 VCCQ NC DQ3 V SSQ NC VCC NC W E# CAS# RAS# CS# A 13 (B A 0) A 12 (B A 1) A 10 (A P ) A0 A1 A2 A2 VCC
VCC NC VCCQ NC DQ0 V SSQ NC NC VCCQ NC DQ1 V SSQ NC VCC NC W E# C A S# R A S# C S# A 1 3(B A 0) A 1 2(B A 1) A 1 0(A P ) A0 A1 A2 A2 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 pin T SO P
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
V SS NC V SSQ NS DQ3 VCCQ NC NC V SSQ NC DQ2 VCCQ NC V SS R E S E RV E D DQM CLK CLKE A 14 A 11 A9 A8 A7 A6 A5 A4 V SS
V SS DQ7 V SSQ NS DQ6 VCCQ NC DQ5 V SSQ NC DQ4 VCCQ NC V SS R E S E RV E D DQM CLK CLKE A 14 A 11 A9 A8 A7 A6 A5 A4 V SS
VSS DQ15 V SSQ DQ14 DQ13 VCCQ DQ12 D Q 11 V SSQ DQ10 DQ9 VCCQ DQ8 VSS R E S E RV E D DQM C LK C LKE A14 A 11 A9 A8 A7 A6 A5 A4 VSS
“Same pinout”, except for DQ - data pins
DRAM Memory System: Lecture 3 Spring 2003
Kingston SDRAM DIMM
Bruce Jacob David Wang University of Maryland
8 Chips. 128 Mbit each. (Infineon)
PC133 CAS 3 Dual Inline Memory Module
SPD
