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Citation
Hans Meyvaert, Tom Van Breussegem, Michiel Steyaert, 2013 A 1.65W Fully Integrated 90nm Bulk CMOS Capacitive DC-DC Converter with Intrinsic Charge Recycling IEEE Transactions on Power Electronics, 28-9, 4327-4334
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Author manuscript: the content is identical to the content of the published paper, but without the final typesetting by the publisher
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http://dx.doi.org/10.1109/TPEL.2012.2230339
Journal homepage http://www.ieee-pels.org/publications/transactions-on-power-electronics Author contact
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A 1.65W Fully Integrated 90nm Bulk CMOS Capacitive DC-DC Converter with Intrinsic Charge Recycling Hans Meyvaert, Student Member, IEEE, Tom Van Breussegem and Michiel Steyaert, Fellow, IEEE
Abstract—A fully integrated high power density capacitive 2:1 step-down DC-DC converter is designed in a standard CMOS technology. The converter implements the presented Flying Well technique and Intrinsic Charge Recycling technique to deliver a maximum output power of 1.65W on a chip area of 2.14mm2 , resulting in a power conversion density of 0.77W/mm2 . A peak power conversion efficiency of 69% is achieved, leading to an efficiency enhancement factor of +36% w.r.t. a linear regulator. This for a voltage step-down conversion from twice the nominal supply voltage of a 90nm technology (2Vdd = 2.4V ) to 1V . Index Terms—Fully integrated, power converter, switchedcapacitor, capacitive, DC-DC converter, Intrinsic Charge Recycling
I. I NTRODUCTION ECENT trends show that the power management unit (PMU) to supply System-on-Chip (SoC) designs is undergoing a transformation and is taking a leap towards monolithic integration. This is a necessary evolution since modern electronic systems rely on a broad spectrum of power management techniques to save power. A lot of these techniques imply the real time regulation of the supply voltage or the presence of multiple supply rails in a single application [1]. Another issue of the PMU is its output impedance and the power grid impedance that is becoming more problematic as circuit supply voltages decrease as this leads to larger supply currents and increased Ohmic losses [2] [3]. All these concerns can be better addressed by means of a number of distributed high performance integrated DCDC converters as opposed to multiple external converters with complex routing to the chip taking up PCB board space and package pins. DC-DC converters that intend to face this challenge should demonstrate high efficiency compared to traditional linear regulation and have a small form factor, i.e. high power density. To obtain such a compact and compatible solution, this paper investigates the opportunities to integrate the DCDC converter in the same standard CMOS technology as the system to be supplied, maximizing the added value of an integrated solution [4]. This approach has the advantage that a portion of the external bulky components and their interconnections are no longer required. On top of that, integrated DCDC converters can be implemented employing state-of-the-art
R
H. Meyvaert and M. Steyaert are with the Department of Electrical Engineering, ESAT-MICAS KU Leuven, 3001 Heverlee, Belgium, e-mail:
[email protected] [email protected] T. Van Breussegem was with ESAT-MICAS KU Leuven and is now with ICsense, 3001 Heverlee, Belgium, e-mail:
[email protected]
circuit techniques such as fragmented operation (interleaving) that proved to be impractical earlier due to a high component count [5]. When integrating conventional DC-DC converters - buck, boost - in a CMOS process, the quality factor of integrated inductors becomes a huge problem. The equivalent series resistance (ESR) of the inductor induces large losses but also the parasitic capacitive coupling between the inductor and the substrate deteriorate the converter’s efficiency. State-of-theart designs in the literature prove that relatively high power densities can be achieved, but at the cost of efficiency [6] [7]. Next to inductive based DC-DC converters, capacitive DCDC converters are gaining interest. In the past they were used for low current, high conversion ratio applications in which efficiency was of secondary importance [8]. These capacitive converters use nothing but switches and capacitors to perform fixed voltage conversions, according to the number of capacitors in the converter topology [9]. Behavioral [10] and State Space models [11] characterize the capacitive converter’s output impedance allowing straightforward design. Recently fully integrated capacitive converters appeared reporting both a high power density and a high efficiency using the advantages of SOI technology [12] and exploiting the capacitance density of deep trenches [13]. Although their baseline CMOS counterparts show high efficiency, they stay behind in power density [14] [15] due to typical limitations resulting from a CMOS implementation. The presented converter employs the Flying Well and Intrinsic Charge Recycling techniques to overcome these drawbacks and demonstrates that these enhancements enable improved specifications, achieving a power density of 0.77W/mm2 and an efficiency of 69%. II. T OPOLOGY AND T ECHNIQUES A. Operation The topology of the capacitive converter’s power conversion core is shown in Fig. 1. It is built up with 4 switches (M 1 − M 4) and a charge transfer capacitor (Cf ly ) to transfer charge from input to output in a 2-phase alternated operation. For sake of simplicity the input voltage is ideal and the output capacitor Co is infinite. Even though this topology is intended to perform a 2:1 step-down, the output voltage Vo is lower than half of the input voltage Vi . This voltage drop VRo is caused by the voltage divider formed by the output impedance Ro of the converter and the load impedance RL (Fig. 5) and this ratio is denoted by parameter γ. Thus Vo = γ V2i = γVo,id , in
TN
M3 (Φb) G
Vo M1 (Φa) Vi
Cfly
TP
M2 (Φa) M4 (Φb)
Co
D
RL
Power conversion cell topology.
N-W
S
B
N-Well
Cpar Fig. 1.
Cfly
Bulk
Fig. 2. Flying Well biasing technique. D/S to N-well junction shorted. Bulk to N-well junction is new Cpar .
Vin
+ -
Vlow
Cfly V out
which Vo,id is the ideal output voltage when no load current is present and consequently no voltage drop over Ro occurs. During phase (Φa ) the flying capacitor is switched between the input terminal (Vi ) and the output terminal (Vo ) by closing switches M 1 and M 2. Hereby Cf ly is charged to a voltage Vi − Vo , which is 2VRo larger than Vo due to the nonzero output impedance as explained above. At the same time charge is delivered to the load because the flying capacitor is charged in series with the output. In the next phase (Φb ), the charge transfer capacitor Cf ly is relocated between the output terminal and ground by closing M 3 and M 4. Cf ly discharges into the output and again charge is delivered. Each conversion cycle Cf ly is charged and discharged by the voltage difference ∆VCf ly = 2(Vo,id − Vo ) = 2VRo . It is this voltage variation that is responsible for the charge transfer. Continuously alternating between these 2 phases results in an output current being supplied to the load.
Fig. 3. Intrinsic Charge Recycling technique. (a) regular case where Cpar is connected to the negative terminal of the flying capacitor Cf ly,− . (b) ICR case: Cpar is connected to the positive terminal of the flying capacitor Cf ly,+ .
B. CMOS integration difficulties
C. Flying Well Technique
Parasitic effects have a large impact on the design of CMOS integrated capacitive converters. Especially the ESR of the flying capacitor (RESR,Cf ly ) and the parasitic capacitor Cpar (= αCf ly ) between the bottom plate and the substrate decrease efficiency and limit the maximum output power. Due to their high capacitance density in comparison to other types of integrated capacitors, MOS capacitors were selected for implementation. Unfortunately these capacitors are also the ones that suffer most from the parasitic effects. On one hand the conductive inversion channel plate of a MOScap imposes a substantial contribution to its equivalent series resistance RESR,Cf ly . This can however be decreased in layout by tuning the W/L ratio of the MOScap. At the cost of a decreased capacitance density, due to fixed drain/source diffusion overhead in layout that do not contribute to the MOScap capacitance, the equivalent series resistance can be lowered by decreasing the channel length. On the other hand the conductive channel is closely embedded in the substrate and exhibits a high parasitic coupling α. Two techniques are proposed to provide a workaround in standard CMOS. The bottom plate parasitic coupling α in this design is reduced by means of the Flying Well technique. The remaining bottom plate parasitic capacitor is exploited to increase the power density by the Intrinsic Charge Recycling (ICR) technique.
Vhigh
Cout Cpar
Cpar Фa
Vin Vhigh
+ -
(a)
Vout
+ Фb
Cfly Cout Vlow
Cfly V out
Cpar
Cout Фa
Vout Cpar
(b)
+ Фb
Cfly Cout
The Flying Well technique lowers the parasitic capacitive coupling to the substrate by biasing the body well such that the regular parasitic capacitance is traded in for a smaller capacitance. The regular parasitic, in case of a PMOScap according to Fig. 2, is mainly formed by the junction capacitance of the drain/source terminals to the n-well body of the transistor. Opposed to tying the n-well to a fixed bias voltage (2Vdd ), in this approach the n-well is connected to the drain/source terminals of the PMOScap as shown in Fig. 2. This shorts the drain/source to n-well junction capacitor, eliminating it. The parasitic capacitance hereby shifts to the capacitor formed by the n-well to bulk junction. This junction capacitance however is much smaller and thus the parasitic coupling is reduced from over 5% of Cf ly to α = 1.3% as demonstrated by simulation results in the case of this converter. D. Intrinsic Charge Recycling Technique Even though the use of the Flying Well technique reduces the parasitic coupling considerably, the remaining parasitic effect still limits the maximum achievable efficiency of the converter in comparison to technologies such as SOI, which inherently suffer less from substrate coupling due to the absence of a semiconductor substrate. The Intrinsic Charge Recycling technique reverses this loss into a recycled benefit.
∆ Eo − ∆ EI * 1/(CparV2o,id)
The aim is to recuperate charge that is stored on the parasitic capacitor and direct it to the output instead of it being wasted towards ground. Fig. 3 shows the difference when the parasitic capacitor is present at the negative terminal of the charge transfer capacitor Cf ly (a) or when it is connected to the positive terminal of Cf ly (b). In case (a), Cpar is first charged during Φa by the output terminal and is discharged in Φb , as Cf ly is relocated between output and ground. Alternatively, in case (b) when the parasitic capacitor Cpar is present at the positive voltage terminal, Cpar is charged by the input in during Φa . Afterwards in Φb the parasitic capacitor discharges into the output. The charge stored on the parasitic capacitor is not lost, it is delivered to the output instead. Hereby the output power is increased. There is however a difference in the charge transportation efficiency from input to output by Cf ly and Cpar . During a charge/discharge cycle the voltage difference, that the flying capacitor is subjected to, is approximately equal to twice the voltage drop over the output impedance (∆VCf ly = 2VRo ) which is supposed to be small (set by voltage division ratio γ) and therefore only a small amount of energy Cf ly ∆VC2f ly is lost. This leads to a very efficient conversion with γ as the theoretical upper boundary. The conversion that is performed by recycling charge from the parasitic capacitor is less efficient due to the voltage variation seen by this capacitor being larger and approximately equal to ( V2i + VRo ). Hereby the conversion contribution of this capacitor equals that of a switched-capacitor resistor and the efficiency of such a conversion is like that of a linear regulator. Even though the conversion associated to the recycling is less efficient than that of the natural converter operation, it is important to note that by applying Intrinsic Charge Recycling in the converter the output impedance is decreased instead of being increased. The performance enhancement realized by using this strategy is that for the same switching frequency the output power will be higher or alternatively that the same output power can be obtained with a lower switching frequency, thus a higher efficiency. Simulations showed that in the case of this prototype converter the output impedance was reduced by 5%. Intrinsic Charge Recycling can easily be established in CMOS by using PMOScaps as the positive capacitor terminal is formed by the inversion channel, closely embedded in the substrate. The location of the parasitic capacitor also has consequences from an energy point of view. Considering the ICR case, it is seen that the parasitic capacitor Cpar in Fig. 3b swings with an amplitude, Vhigh − Vlow , approximately (ignoring the output impedance voltage drop) equal to the amplitude of the regular case of Fig. 3a, ∆VCpar,ICR ≈ ∆VCpar,REG . But in the ICR case this occurs at higher absolute voltages. This means that more energy is lost per converter cycle in the Intrinsic Charge Recycling case. However, the ICR case offers in return the recycling benefits otherwise not present because Cpar is charged by the input and this charge is transferred to output, as opposed to Cpar being charged by the output (charge that has already been transferred at a finite conversion efficiency) and then lost to ground as in the regular case. To investigate the system performance improvement of
1 5γ −4 0.5
0
−0.5 0.7
0.75
0.8
0.85
γ
0.9
0.95
1
Fig. 4. Intrinsic Charge Recycling trade-off. Independent of Cpar and Vo,id , Intrinsic Charge Recycling will perform better then the regular case when γ is above 0.8.
Intrinsic Charge Recycling, the output energy benefit must be compared to the input energy cost. The energy associated to the parasitic capacitor in the regular and ICR case are given in Eq. 1 and Eq. 2 respectively. 2 Ei,Cpar,REG = Cpar Vo,id γ2
(1)
2 Ei,Cpar,ICR = Cpar Vo,id (4 − 2γ)
(2)
With the energy in the regular case already transferred to output at a finite efficiency limited to γ, the energy difference seen by the input is given by Eq. 3. 2 ∆Ei = Cpar Vo,id (4 − 2γ) −
2 γ2 Cpar Vo,id γ
(3)
When looking at both cases regarding the difference in energy at the output, the energy associated to the regular and the ICR case are given in Eq. 4 and Eq. 5 respectively. 2 Eo,Cpar,REG = Cpar Vo,id γ2
(4)
2 Eo,Cpar,ICR = Cpar Vo,id (γ 2 − 2γ)
(5)
The difference between both cases referred to the output is then given by the sum of −Eo,Cpar,ICR and Eo,Cpar,REG (Eq. 6), since the regular case removes charge from the output unlike the ICR case. 2 ∆Eo = −Eo,Cpar,ICR + Eo,Cpar,REG = Cpar Vo,id 2γ
(6)
Therefore only when the benefit in output energy is larger than the cost in input energy it is useful to employ intrinsic charge recycling. Combining Eq. 6 with Eq. 3 demonstrates this trade-off. The result is given by Eq. 7: 2 ∆Eo − ∆Ei = Cpar Vo,id (5γ − 4)
(7)
This concludes that the only the factor γ determines the break even point. Fig. 4 shows that whenever γ is above 0.8 it is beneficial to employ the Intrinsic Charge Recycling technique. Since γ also determines the theoretic maximal efficiency, it should always be designed to be as close as possible to 1 and thus it is always beneficial to employ the proposed technique.
III. C ONVERTER D ESIGN AND O PTIMIZATION
Rroute RESR,Cfly
Chip area is a costly resource, for this reason not only power conversion efficiency should be considered when designing an integrated converter but also power conversion density should be maximized. This means that on a system level the area allocated to each circuit block must minimize the power flow losses from input to output in the converter. Therefore it is necessary to include the additional effects of block interconnections that are normally not part of the converter modeling, as these resistive losses become more important due to the high current density of power dense converters. In [10] the contribution of the flying capacitor Cf ly and the switch on-resistances to the output impedance of the converter is modeled. In a Slow Switching Limit (SSL) case the flying capacitor impedance is dominant (Eq. 8), whereas in the Fast Switching Limit (FSL) case the on-resistance of the switches form the bottleneck given by Eq. 9. X (ac,i )2 (8) Rssl = Ci fsw i X Rf sl = 2 Ri (ar,i )2 (9)
Rssl
Rfsl γ=
n 1
Vo,id
Ro
Ro =
2 Rf2 sl + Rssl
(10)
Parameters ac,i and ar,i are topology specific. The output impedance is then given by Eq. 10. However this model does not yet include the ESR of the flying capacitor RESR,Cf ly and metal routing resistance Rroute as shown in Fig. 5. Both these parasitics contribute to Ro and result in Eq. 11. q 2 (11) Ro = (Rf sl + RESR,Cf ly + Rroute )2 + Rssl From Eq. 8 it can be seen that the Rssl can be made small by either using more capacitance Cf ly or increasing the switching frequency fsw . Integrating a large capacitance in CMOS is very area consuming and thus will be the bottleneck for power density as the switching frequency can not be chosen arbitrarily high without compromising system efficiency. For this reason MOScaps were selected to integrate Cf ly due to their high capacitance density of 10nF/mm2 in comparison to the alternative MIMcap or MOMcap. Achieving high power density requires optimal use of the available Cf ly , i.e. design RESR,Cf ly , Rroute and Rf sl to be low in comparison with Rssl , while limiting the associated cost. Next to the output impedance losses, Fig. 5 shows the dynamic losses (Rdyn ) as result of the switched-mode operation, consisting of the gate drive losses and the flying capacitor’s bottom plate loss. Pdyn,Cpar scales with fsw as α is a technology related and Cf ly is chosen to fit in the target chip area. Pdyn,switches is the associated cost of Rf sl . Optimizing power density results in the minimizing Eq. 11 while targeting a desired minimum efficiency as secondary objective. Fig. 6 depicts the crossover frequency shift of Ro due to Eq. 11. Both RESR,Cf ly and Rroute have an area impact but no cost in the dynamic power and thus they should be designed to be much smaller than Rf sl [14][16] as this contributes, on top of area, to dynamic losses. Regarding
RO+RL
Vo
VRo
Vi
Rdyn
RL
Co
Pdyn,Cpar Pdyn,switches
Fig. 5. Output impedance model for switched-capacitor DC-DC, extended with additional loss contributions.
R
out
Optimal
Suboptimal
R FSL
`
f
i
q
RL
sw
Fig. 6. Crossover frequency shift due to additional parasitics and the influence of Rf sl on total losses.
losses, the ideal value of Rf sl is obtained when its associated cost Pdyn,switches is comparable to the dominant loss caused by Ro (Fig. 6). Indeed Rf sl (and thus Ro ) should be made smaller as long as the cost in additional dynamic power is negligible to the dominant loss. This approach is similar to the output impedance balancing described in [14] and includes the effect of RESR,Cf ly and Rroute . The above design considerations were combined into the automatic procedure that resulted in the proposed converter of which the specifications are later discussed in Section V. Given a fixed area for the flying capacitor Cf ly , as this is the main area bottleneck, an optimal solution is searched for in the design space formed by parameters RESR,Cf ly , Rroute , Rf sl , fsw and γ. IV. I MPLEMENTATION The system architecture is shown in Fig. 7. The converter is built up with power conversion cells, discussed in Section II. These cells contain 2 voltage domains, each with a voltage range of Vdd . Voltage domain 1 ranges from Vdd to 2Vdd and contains transistors M 1 and M 3. Voltages between ground and Vdd form voltage domain 2 and this domain includes transistors M 2 and M 4. The advantage of stacking 2 voltage domains is that the standard thin-oxide transistors (Vdd rated) can be used, instead of the less performing thick-oxide I/O devices (> Vdd rated). This is because each transistor only operates within one voltage domain and undergoes a maximum voltage swing of Vdd . Thin-oxide transistors have a better Qg Rds,on and are preferred over the thick-oxide transistors if the topology suits using voltage domains. Generally capacitive
Vi L E
Drivers
Vdd
E L
Vi
S H I
NON OVERLAP
M1 M2 Cfly
1a
V
Vo
a GND Vdd
Drivers
M3 M4
1b
F T
Vdd Drivers
Vdd
Drivers
b
Vo
Voltage Domain 1
Voltage Domain 2
V 1a
1b
a
b time 21
Biasing 21 1 2
21
1
2
CORE
Biasing
Fig. 7. System architecture: 21-interleaving structure composed of unity converter cells, controlled with 21-tap VCO.
converters can exploit this very well as was demonstrated by [17] in a 12V to 1.5V converter extensively implementing multiple voltage domains. Using many voltage domains also has consequences: level shifters are needed to pass clock signals in between voltage domains and during start up special care must be taken to protect the transistors from overvoltage. In this design an integrated linear regulator, implemented with thick-oxide devices, was included to generate an internal supply voltage of Vdd to ensure safe startup. Proper operation of the power conversion cell requires the 2 phases to be non-overlapping as shown in Fig. 7. A clock signal from the ring oscillator is made non overlapping into Φ2a and Φ2b . Because of the voltage domain approach these non-overlapping signals also need to be present in the Vdd 2Vdd domain. To this end the level shifter proposed in [18] was used. Each core includes 2 level shifters to generate the level shifted counterparts of Φ2a and Φ2b , Φ1a and Φ1b respectively. To decrease the output voltage ripple the converter is fragmented into 21 equal parts and are clocked out of phase. Interleaving the 21 converter cores in this way has a double advantageous effect. First of all the charge transfer is spread out over 21 smaller charge and discharge currents, yielding a decreased output voltage ripple [19] [20]. This greatly relaxes the requirements of the output smoothing capacitor as well as the input smoothing capacitor. Another advantage is that the idle converter cores help smooth the input and output. When 1 of the 21 converter cores switches between phases, 10 other converter cores are located between Vi and Vo (Φa ) and another 10 converter cores are located between Vo and ground (Φb ). Hereby the charge transfer capacitors Cf ly in the idle cores are effectively decoupling the output, with the difference that at a later time they will also be used for charge transfer. When the amount of interleaving is high enough
so that the idle cores are sufficient to smooth a switching converter core, it is even no longer needed to have a dedicated output smoothing capacitor. Valuable chip area is saved and the power conversion density is boosted. In this prototype converter a total of 12nF is divided over the 21 converter cores resulting in a Cf ly per core of 0.57nF . No dedicated output capacitor was integrated and the output voltage ripple did not exceed 8% of the output voltage in steady state. Each converter core is provided with an out-of-phase clock signal generated by a 21-stage voltage controlled ring oscillator (VCO) of which the frequency can be set by an external control voltage. For the interleaving approach to work well, the switching action of each core should be spread out in time with equal intervals. Small levels of phase noise in the VCO however are not a problem because the flying capacitor Cf ly is charged/discharged with exponential decaying current pulses and thereby the interleaving sensitivity to phase noise in the VCO is low. Capacitive converters, as opposed to their inductive counterparts, implement a fixed Voltage Conversion Ratio (VCR) set by the topology of the converter. The topology of Fig. 1 achieves an ideal (unloaded) VCR of 0.5 but under practical conditions the VCR is lower due to the output impedance being non-zero [10]. The voltage drop VRo (set by γ) introduced by this output impedance forms an upper bound for the maximum achievable efficiency. Therefore VRo is desired to be as low as possible. From a regulation perspective this output impedance can also be used to generate intentional voltage drops as to generate voltages below the ideal output voltage of the converter topology. This is similar to adding a linear regulator in series with the ideal converter output as the voltage drop is generated over a series pass device. Control of the output impedance of the capacitive converter can be obtained by changing the switching frequency. The efficiency of generating voltages below the ideal output voltage are thus like that of a linear regulator. However for small deviations below the ideal output voltage this kind of regulation provides only a limited drop in efficiency and on top of that the overall decrease in efficiency is being counteracted by decreased switching losses when the output impedance is increased. For a wider range of output voltage regulation, while maintaining high efficiency, it is necessary for the converter to reconfigure in a different topology with a different corresponding VCR [21] [22]. The total circuit of the proposed converter prototype was implemented in a 90nm Bulk CMOS technology and measures 2.14mm2 . The total amount of integrated flying capacitance is 12nF . A chip photograph is depicted in Fig. 13. V. E XPERIMENTAL V ERIFICATION Fig. 8 shows the efficiency of the converter when a constant output voltage of 1V is delivered to a load. This measurement was conducted by sweeping the load current while the external control voltage was adjusted to set the switching frequency in order to generate 1V at the output. The load is varied from 250mW up to 1050mW and both the converter prototype efficiency as well as the efficiency of a corresponding linear
70%
70%
65%
60%
Measured Converter Vo=1V Vi=2.4V Linear Regulator
55% 50% 45%
Efficiency (%)
Efficiency (%)
65%
40% 35%
0
500
1000
50% 45%
35% 2.3 2.35 2.4 2.45 2.5 2.55 2.6 2.65
1500
Vi (V)
Efficiency during load power Po sweet at constant Vo = 1V .
75%
Fig. 10.
Efficiency while Vo is constant and Vi decreases.
65% 60%
1.7
55% 50%
1.5
45%
1.3
Vo (V)
Vi = 2.4V Vi2.1 = 2.6V Vo at Vi = 2.6V 1.9 Vo at Vi = 2.4V
70%
Efficiency (%)
Converter prototype Vo = 1.03V Io = 775mA Linear Regulator
55%
40%
Po (mW) Fig. 8.
60%
40% 1.1
35% 30% 0
500
1000
1500
0.9 2000
Po (mW) Fig. 9. Efficiency and corresponding Vo (open loop) during load power Po sweep.
regulator is shown. A peak efficiency of 65% at a 1W load is achieved. From Fig. 8 it is clear that the capacitive converter substantially improves upon the linear regulator. The Efficiency Enhancement Factor (EEF) introduced in [7], under a 1W load is +36%, meaning that this prototype converter can extend the battery lifetime with the same amount. A measurement to capture the maximum efficiency for an output power range of 150mW up to 1.65W is performed in Fig. 9. For each point of load the converter efficiency and the corresponding output voltage are plotted. This was measured for both an input voltage of 2.4V and 2.6V . When the converter is supplied with an input voltage of 2.4V the converter efficiency peaks at 69%, while supplying 0.9W to the output. In the case 2.6V is present at the input, the converter prototype is able to deliver a maximum output power of 1.65W , and this at a power conversion efficiency of 60%. Both input voltage cases lead to a performance of over 60% in a broad load power range.
Fig. 11. Load regulation measurement. ∆iL = 529mA → ∆Vo = −95mV : load regulation = −0.175Ω.
As mentioned earlier, capacitive converter topologies implement a fixed VCR, but regulating the output impedance is suitable for generating output voltages with only a small deviation below the ideal output. The external control voltage is used to set the frequency and hereby the output impedance can be controlled by Pulse Frequency Modulation. While an input voltage decline from 2.6V down to 2.35V is supplied to the input of the converter as shown in Fig. 10, a constant output voltage of 1.03V is generated while the load current is 775mA. Both converter efficiency as well as the efficiency of a linear regulator are plotted and the switching converter steadily maintains an efficiency of around 65%. The load regulation of the converter is measured in Fig. 11. Since the converter does not have an integrated closed control loop, the measurement is done on an open loop converter set to switch at a single switching frequency. The load current is stepped between 641mA and 1170mA, represented by the lower (CH1) waveform. The upper waveform (CH2) shows the reaction of the converter to this load variation. The load step causes an output voltage difference of 95mV . This results
1800
R EFERENCES [1] B. Zhai, D. Blaauw, D. Sylvester, and K. Flautner, “The Limit of Dynamic Voltage Scaling and Insomniac Dynamic Voltage Scaling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 11, pp. 1239–1252, 2005. [2] A. V. Mezhiba and E. G. Friedman, “Impedance Characteristics of Power Distribution Grids in Nanoscale Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 11, pp. 1148–1155, 2004. [3] S. Kose and E. G. Friedman, “Effective Resistance of a Two Layer Mesh,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 11, pp. 739–743, 2011.
[12] [1] [13] [2] [7] [3]
[20] [4]
1400 90nm 1200 1000
Bulk CMOS
130nm
SOI
800 51% 32nm
600
130nm
45nm
79.7%
200 0
Deep trench capacitors
32nm
400
0
59% 1000
2000
3000
4000
5000
6000
78% 7000
8000
Power Density (mW/mm2)
Fig. 12. Power versus power density of state of the art at the indicated efficiency.
OUT
GND
OUT Core
IN
VI. C ONCLUSION The converter in this work was designed to have a maximal power density while efficiency was still considered be a secondary objective. To this end Section III provides insight on the parameters and parasitic effects that affect the optimal design point. Section II introduces circuit and layout techniques to overcome the pitfalls that accompany the integration of capacitive DC-DC converters in a cheap Bulk CMOS technology. The proposed Flying Well technique and the Intrinsic Charge Recycling technique offer a performance increase, along with other incorporated techniques as the use of multiple voltage domains and interleaving, resulting in a 2.14mm2 90nm CMOS capacitive 2:1 step-down demonstrator capable of delivering an output power of 1.65W or 0.77W/mm2 . Achieving these specifications, the converter prototype does not escape high temperature operation and metal routing impedance issues that very high power density converters only delivering a low output power are not impeded by. Over a broad load range the efficiency of the proposed converter is above 60%, which is on average a 20% efficiency increase in comparison to a corresponding linear regulator. It is shown that Bulk CMOS is a potential vehicle for high power, high power density converters, without the direct need for special technology options, thus keeping cost down.
This Work
60% 1600
Output Power (mW)
in a load regulation of −0.175Ω. The efficiency in both load current cases was 65%. A comparison to prior art is summarized in Table I and Fig. 12. All converters in the comparison exhibit high power density but each has a different technology or topology background. It is shown that this work improves upon [7] and achieves a high output power on top of a power density comparable to [12], although no special technology options were used in this work and no high capacitance density feature was available as is the case in advanced nanometer technology nodes [23] as used in [12]. The work in [13] achieves a very high power density but the integrated prototype only delivers a peak output power of 8.88mW . The high power density is due to the availability of a very large amount of integrated capacitance made possible by a very non standard technology addition, deep trench capacitors. While [13] only realizes a low output power, problems such as heat dissipation and metal routing impedance are not yet very pronounced and thus extrapolation of the power density is optimistic if it were to be implemented as a full 1mm2 converter delivering 7.4W, but still very high power densities can be achieved by this technology.
IN Switches
GND IN
C1a C1b
START Up Fig. 13.
GND
LS
OUT
PT
C1c
IN
C1d GND
OUT
Chip photograph.
[4] M. Steyaert and P. Vancorenland, “CMOS: A Paradigm for Low Power Wireless?” in Proc. 39th Design Automation Conf, 2002, pp. 836–841. [5] L. Ni, D. J. Patterson, and J. L. Hudgins, “High Power Current Sensorless Bidirectional 16-Phase Interleaved DC-DC Converter for Hybrid Vehicle Application,” IEEE Transactions on Power Electronics, vol. 27, no. 3, pp. 1141–1151, 2012. [6] J. Wibben and R. Harjani, “A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors,” IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 844–854, 2008. [7] M. Wens and M. Steyaert, “A Fully Integrated CMOS 800-mW FourPhase Semiconstant ON/OFF-Time Step-Down Converter,” IEEE Transactions on Power Electronics, vol. 26, no. 2, pp. 326–333, feb. 2011. [8] J. F. Dickson, “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid-State Circuits, vol. 11, no. 3, pp. 374–378, 1976. [9] M. S. Makowski and D. Maksimovic, “Performance Limits of SwitchedCapacitor DC-DC Converters,” in Proc. IEEE Power Electronics Specialists Conf. (PESC), vol. 2, 1995, pp. 1215–1221. [10] M. D. Seeman and S. R. Sanders, “Analysis and Optimization of Switched-Capacitor DC-DC Converters,” IEEE Transactions on Power Electronics, vol. 23, no. 2, pp. 841–851, 2008. [11] J. M. Henry and J. W. Kimball, “Switched-Capacitor Converter State Model Generator,” IEEE Transactions on Power Electronics, vol. 27, no. 5, pp. 2415–2425, 2012. [12] H.-P. Le, S. R. Sanders, and E. Alon, “Design Techniques for Fully Integrated Switched-Capacitor DC-DC converters,” IEEE Journal of Solid-State Circuits, vol. 46, no. 9, pp. 2120–2131, 2011. [13] L. Chang, R. K. Montoye, B. L. Ji, A. J. Weger, K. G. Stawiasz, and R. H. Dennard, “A Fully-Integrated Switched-Capacitor 2:1 Voltage
TABLE I S PECIFICATION COMPARISON TO PRIOR ART
Reference
[12]
[13]
[7]
[14]
Tech node [23]
32nm
45nm
130nm
90nm
This work 90nm
Type
Capacitive
Capacitive
Inductive
Capacitive
Capacitive
Control
Output impedance control
External frequency
SCOOT control loop
SBHC
Output impedance control
Power/area (max.)
0.86W/mm2
7.4W/mm2
0.213W/mm2
0.05W/mm2
0.77W/mm2
Pout,max
325mW
8.88mW
0.8W
0.15W
1.65W
ηmax
85%
90%
58%
77%
69%
Vo ripple spec
Not available
Not available
< 10%Vo
< 5%Vo
< 8%Vo
Tech option
SOI
SOI with deep trench capacitors 200nF/mm2
Bulk CMOS
Bulk CMOS
Bulk CMOS
# interleaving
32
1
4
10
21
[14]
[15]
[16] [17]
[18]
[19] [20]
[21]
[22]
[23]
Converter with Regulation Capability and 90% Efficiency at 2.3A/mm2 ,” in Proc. Symp. VLSI Circuits, 2010, pp. 55–56. T. M. Van Breussegem and M. S. J. Steyaert, “Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 46, no. 7, pp. 1715–1727, 2011. G. V. Pique, “A 41-Phase Switched-Capacitor Power Converter With 3.8mV Output Ripple and 81% Efficiency in Baseline 90nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. Digest of Technical Papers (ISSCC), 2012, pp. 98–100. S. Ben-Yaakov, “On the Influence of Switch Resistances on SwitchedCapacitor Converter Losses,” IEEE Transactions on Industrial Electronics, vol. 59, no. 1, pp. 638–640, 2012. V. W. Ng, M. D. Seeman, and S. R. Sanders, “Minimum PCB Footprint Point-of-Load DC-DC Converter Realized with Switched-Capacitor Architecture,” in Proc. IEEE Energy Conversion Congress and Exposition (ECCE), 2009, pp. 1575–1581. B. Serneels, M. Steyaert, and W. Dehaene, “A High Speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13um CMOS,” in Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS), 2006, pp. 668–671. T. V. Breussegem and M. Steyaert, “A 82% Efficiency 0.5% Ripple 16-Phase Fully Integrated Capacitive Voltage Doubler,” in Proc. Symp. VLSI Circuits, 2009, pp. 198–199. D. Somasekhar, B. Srinivasan, G. Pandya, F. Hamzaoglu, M. Khellah, T. Karnik, and K. Zhang, “Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 751–758, 2010. R. Guo, Z. Liang, and A. Q. Huang, “A Family of Multimodes Charge Pump based DC-DC Converter With High Efficiency over Wide Input and Output range,” IEEE Transactions on Power Electronics, vol. 27, no. 11, pp. 4788–4798, 2012. L. Su and D. Ma, “Monolithic Reconfigurable SC Power Converter with Adaptive Gain Control and On-Chip Capacitor Sizing,” in Proc. IEEE Energy Conversion Congress and Exposition (ECCE), 2010, pp. 2713– 2717. (2009) The international technology roadmap for semiconductors 2009. [Online]. Available: public.itrs.net.
Hans Meyvaert was born in Sint-Truiden, Belgium, on 22 August 1985. He received the Master degree in micro-electronics engineering from the Katholieke Universiteit Leuven (KU Leuven), Heverlee, Belgium in 2009. Since then, he remains at the same university as a Research Assistant at the ESATMICAS laboratory where he has been pursuing the Ph.D. degree, working on integrated power management circuits in CMOS.
Tom Van Breussegem was born in Zottegem (Belgium) on the 10th of April 1982. Received the masters degree in engineering in 2004 from GroupT technology college in Leuven. Was an intern at IMEC (Belgium) in summer 2003 and at Ansem (Belgium) in the summer of 2006. He received a master in Micro-electronics from KU Leuven in 2007. In 2008 he was granted a scholarship by the Flemisch Institute for Innovation, Science and Technology (IWT). In 2012 he finished a PhD on Monolithic CMOS Integrated DC/DC-converters. In April 2012 he joined ICsense, an ic-design house specialized in Power Management, High Voltage and Sensor interfacing, as a senior design engineer.
Michiel Steyaert (IEEE-Fellow 2003) received the masters degree in electrical-mechanical engineering and the Ph.D. degree in electronics from the KU Leuven, Heverlee, Belgium in 1983 and 1987, respectively. From 1983 to 1986 he obtained an IWNOL fellowship (Belgian National Foundation for Industrial Research) which allowed him to work as a Research Assistant at the Laboratory ESAT at KU Leuven. In 1987 he was responsible for several industrial projects in the field of analog micro power circuits at the Laboratory ESAT as an IWONL Project Researcher. In 1988 he was a Visiting Assistant Professor at the University of California, Los Angeles. In 1989 he was appointed by the National Fund of Scientific Research (Belgium) as Research Associate, in 1992 as a Senior Research Associate and in 1996 as a Research Director at the Laboratory ESAT, KU Leuven. Between 1989 and 1996 he was also a part-time Associate Professor. He is now a Full Professor at the KU Leuven. He was the Chair of the Electrical Engineering Department from 2005 until 2012. He is now dean of the faculty of engineering. His current research interests are in high-performance and high-frequency analog integrated circuits for telecommunication systems and analog signal processing. Prof. Steyaert authored or co-authored over 400 papers in international journals or proceedings and co-authored over 15 books. He received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award. He received the 1991 and the 2000 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications. Prof. Steyaert received the 1995 and 1997 IEEE-ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and is currently an IEEE-Fellow. He was also recognized as one of the top 10 authors in the 50-year history of ISSCC.
