Transcript
Low Noise Amplifier with Bypass Switch for 400 to 800 MHz Application Using MGA-785T6
Application Note 5319
Introduction A digital TV system requires a front-end receiver with superb noise figure, high linearity, and gain flatness across operating frequency. This application note discusses the design of a 400–800 MHz LNA circuit using the MGA-785T6 for a digital TV application. This design is suitable for a digital TV application which operates at the 400-800 MHz frequency band (UHF band).
The MGA-785T6 is housed in the Ultra-thin Small Leadless Package (UTSLP) with very low profile (0.4 mm) and small footprint (2.0 x 1.3 mm2) that requires only a small area of printed circuit board space, making it suitable to be integrated in a module, for instance a TV tuner module. Figure 1 shows the simplified schematic of the device.
The MGA-785T6 is a single stage GaAs MMIC low noise amplifier (LNA) with integrated bypass switch function. This LNA offers low noise and high linearity performance at low voltage and current. These characteristics are important in the design of a RF front-end of a portable receiver that requires high sensitivity, excellent power efficiency and wide power handling range.
The purpose of the integral bypass switch is to attenuate any extremely strong received signal. This helps to prevent the backend stage from being overloaded and to preserve the linearity of the system at high received power.
Pin Configuration and Biasing Figure 2 shows the pin configuration for the MGA-785T6.
Vdd Pin 1 Pin 2
RFin
RFout
SWITCH/BIAS
Figure 1. Simplified schematic
Pin 6 Paddle
Pin 3 Pins 1, 3, 4, 6 : Pin 2 : Pin 5 : Center Paddle :
Pin 5 Pin 4
Not Connected RF in Vdd/RF Out RF Ground/Ground
Figure 2. Pin configuration (top view)
The biasing method for the MGA-785T6 is similar to a depletion GaAs FET. There are two methods of biasing this device, known as the source resistor bias and the gate bias method. The source resistor bias method is the recommended method to bias the device because this method is easier and simpler than the gate bias method, as it needs only one positive DC supply. In this design, a voltage supply of +3 V is connected to pin 5 (Vdd/ RF Out) while pin 2 (RF In) is DC grounded by means of a shunt inductor (RF choke). A resistor is connected to the center paddle (RF Ground/Ground) to set the desired current. The center paddle also needs to be RF grounded using a bypass capacitor with an appropriate value to maintain the stability of the circuit. Figure 3 shows the DC schematic of the MGA-785T6 using the source resistor bias method. A lower bias resistor value gives a higher current and better linear-
ity. Figure 4 shows the device current versus the value of the bias resistor. In addition to using the source resistor bias method which is described in the previous paragraphs, the device can also be biased using the gate bias method. In this method, a +3 V is applied to pin 5 (Vdd/ RF Out) and the center paddle is directly DC grounded. The current is set by varying the negative voltage which is applied to pin 2 (RF In) through a shunt inductor (RF choke). This method requires another negative DC supply in addition to the positive DC supply to pin 5 but it gives a better stability to the device because the parasitic source inductance at the center paddle is small due to the short grounding path. The other advantage of this method is it requires fewer external components.
Vdd
RF IN
1
6
MGA 2 785T6
5
3
4
RF OUT
Bias Resistor
Bypass capacitor (RF Ground)
FET or BiPolar switch Vctrl +3V ; Amplifier Mode 0V ; Bypass Mode
required for bypass mode implementation Open circuit -> Bypass mode Short Circuit -> Amplifier mode
Figure 3. Source resistor bias method Idd vs. Rbias 70 60
Vdd
Idd (mA)
50 40
1
6 MGA 2 5 785T6 3 4
30
RF IN
20 10 0 0.1
1
10
100
Rbias (Ohm)
Figure 4. Idd vs. Rbias (source resistor bias method, Vdd = +3 V)
2
1000
–Vg
Figure 5. Gate bias method
RF OUT
Bypass Mode The mode of the device – between amplifier and bypass mode – is controlled by the device current. When the device current is set to zero, the device will automatically be put into bypass mode. The current drawn in the bypass mode is less than 2 PA. For a design that uses the source resistor bias method, the device can be easily switched to bypass mode by increasing the bias resistor value to greater than 1 M: or leaving the center paddle open. For actual application, this can be achieved by having a FET or Bi-Polar switch between the bias resistor and ground. Please refer to Figure 6a, when the switch is opened, the device is in
bypass mode, vice versa. For the gate bias method, the same voltage needs to be applied at both pin 4 (center paddle) and pin 5 (Vdd/RF Out) to switch to the bypass mode. Both pin 4 and pin 5 are connected to 0 V. Simultaneously, a negative voltage of less than -1 V is applied to pin 2 (RF In). In the bypass mode, the internal circuitry duplicates the impedance of the device in amplifier mode. This helps to avoid significant impedance mismatch when switching between the two modes. In addition, the same external matching circuit can be used for both modes, simplifying the external circuitry and reducing the board space. From Microcontroller Vdd -> Logic Hi : 3 V (Amplifier Mode) Vdd -> Logic Lo : 0 V (Bypass Mode)
1
RF IN
2
6
MGA 785T6
3
RF OUT
RF IN
1
6
5
MGA 2 785T6 5
4
3
4
Bias Resistor FET or BiPolar switch
Bypass capacitor (RF Ground)
Vctrl +3V ; Amplifier Mode 0V ; Bypass Mode
required for bypass mode implementation Open circuit -> Bypass mode Short Circuit -> Amplifier mode
Figure 6a. Bypass mode (source resistor bias method)
GAIN vs. Idd 16 14 GAIN (dB)
12 10 8 6 4 2 0
5
10
15 Idd (mA)
Figure 7. Gain vs. Idd (at 600 MHz)
3
20
Vg = -0.6V (Amplifier Mode, Idd = 10 mA)
Vg < -1 V (Bypass Mode)
Figure 6b. Bypass mode (gate bias method)
18
0
SWITCH
25
30
RF OUT
Application Circuit Design for the MGA-785T6 in a Digital TV Application C1
L2
RF IN
1
6 MGA 2 5 785T6 3 4
C6 RF OUT L3
L1 C3
R1
C4
C2 R2
BOARD MATERIAL: 16 mils FR4
C5
Vdd = +3 V + –
Figure 8. Application circuit for the MGA-785T6 at 400-800 MHz frequency band
Figure 7 shows the application circuit for the MGA785T6 at the 400–800 MHz frequency band. In this design, with a +3 V DC supply at pin 5 (Vdd), a series resistor of 68 : or 100 : is used as R2 to set the device current to approximately 10 mA and 7 mA respectively. In this example, the resistor is removed to switch the device to bypass mode. A 200 pF bypass capacitor (C3) is put in parallel to the bias resistor (R2) to maintain the stability of the circuit across the frequency. The value of the bypass capacitor is determined through the iterative process of on-board tuning. R2 and C3 need to be put very close to the device to achieve an unconditionally stable condition across frequency (refer to Figure 16 for the component placement).
4
The input matching circuit is formed using C1, L1 and L2 to achieve wideband noise figure and input return loss. Pin 2 is DC grounded through L1. R1 and C2 are needed to achieve unconditional stability at low frequency. The output matching circuit is formed using L3 and C6. C6 also serves as a blocking capacitor. The RF performance of the design at 600 MHz, as measured on the demonstration board, is summarized in Table 1.
Table 1. RF Performance for the MGA-785T6 at 600 MHz Optimized for Better Input Return Loss Stability Factor, k (0.05 – 20.05 GHz)
Optimized for Better Noise Figure
>1
>1
LNA Mode Current, Id
mA
10
7
10
7
Gain, S21
dB
15.4
14.5
15
14.1
Noise Figure, NF
dB
1.6
1.8
1.5
1.7
Input Return Loss, IRL
dB
-6.9
-6.5
-5.7
-5.1
Output Return Loss, ORL
dB
-11.8
-10.5
-11.3
-9.7
IIP3*
dBm
0.2
-2.4
0.2
-2.4
Output P1dB
dBm
4.4
1.2
3.9
0.8
Insertion Loss, IL
dB
-2.7
-3
Input Return Loss, IRL
dB
-8.8
-6.7
Output Return Loss, ORL
dB
-9.9
-8.3
IIP3**
dBm
28
28
Bypass Mode
*Test condition: FRF1 = 600 MHz, FRF2 = 605 MHz with input power of -25 dBm per tone measured at the worst case side band. **Test condition: FRF1 = 600 MHz, FRF2 = 605 MHz with input power of -15 dBm per tone measured at the worst case side band.
5
0
-10 GAIN (dB)
INPUT RETURN LOSS (dB)
-5
-15 -20
-30
0
0.2
0.4
0.6
0.8
0
18
-1
16
-2
14
-3
12 10
-4 -5
8
-6
6 4 2 0
7 mA 10 mA BYPASS
-25
20
1.0
7 mA 10 mA BYPASS 0
0.2
0.4
0.6 FREQ (GHz)
FREQ (GHz) 0
0 -5 REVERSE ISOLATION (dB)
OUTPUT RETURN LOSS (dB)
-5 -10 -15 -20 -25 7 mA 10 mA BYPASS
-30 -35
0.8
-7 -8 -9 -10 1.0
INTERSECTION LOSS (dB)
The following figures show the plot of the RF parameters at Vdd = 3 V.
0
0.2
0.4
0.6
0.8
-10 7 mA 10 mA BYPASS
-15 -20 -25 -30
1.0
0
0.2
0.4
0.6
FREQ (GHz)
0.8
1.0
FREQ (GHz)
Figure 9. S-parameters for the MGA-78T6 (measured on the board with better input return loss) k FACTOR (0.05 GHz – 20 GHz)
NF vs. FREQ
2.6
9 8 7
2.4
6 5 4
2.0
2.2 NF (dB)
k FACTOR
10
1.8 1.6
3 2 1 0 0.05
1.4
10 mA 7 mA 5.05
10.05
Idd = 7 mA Idd = 10 mA
1.2 1.0 0.4
15.05
0.5
0.6
Figure 10. k factor for the MGA-785T6 (measured on the board with better input return loss)
5
IIP3 (dBm)
OP1dB (dBm)
6
4 3 2 1 0 0.4
0.5
0.6
0.7
0.8
0.9
FREQ (GHz)
Figure 12. Output P1dB for the MGA-785T6 (measured on the board with better input return loss)
6
IIP3 vs. FREQ
3 Idd = 7 mA Idd = 10 mA
7
0.8
0.9
Figure 11. Noise figure for the MGA-785T6 (measured on the board with better input return loss)
OP1dB vs. FREQ
8
0.7 FREQ (GHz)
FREQ (GHz)
35
2
30
1
25 20
0 7 mA 10 mA BYPASS
-1
15
-2
10
-3
5
-4 0.4
0.5
0.6
0.7
0.8
0 0.9
FREQ (GHz)
Figure 13. IIP3 for the MGA-785T6 (measured on the board with better input return loss)
20
0
18
-1
16
-2
-10
14
-3
-15
12 10
-4 -5
8
-6
GAIN (dB)
INPUT RETURN LOSS (dB)
-5
-20 7 mA 10 mA BYPASS
-25 -30
6 4 2 0
0
0.2
0.4
0.6
0.8
1.0
7 mA 10 mA BYPASS 0
0.2
0.4
0.6
0
0
-5
-5
-10 -15 -20 -25 7 mA 10 mA BYPASS
-30 -35
0
0.2
0.4
0.8
FREQ (GHz)
REVERSE ISOLATION (dB)
OUTPUT RETURN LOSS (dB)
FREQ (GHz)
-7 -8 -9 -10 1.0
INTERSECTION LOSS (dB)
0
0.6
0.8
-10 7 mA 10 mA BYPASS
-15 -20 -25 -30
1.0
0
0.2
0.4
0.6
0.8
1.0
FREQ (GHz)
FREQ (GHz)
Figure 14. S-parameter for the MGA-785T6 (measured on the board with better noise figure) k FACTOR (0.05 GHz – 20 GHz)
9 8 7
2.4
6 5 4
2.0
3 2 1 0 0.05
NF vs. FREQ
2.6
2.2 NF (dB)
k FACTOR
10
1.8 1.6 1.4
10 mA 7 mA 5.05
10.05
Idd = 7 mA Idd = 10 mA
1.2 1.0 0.4
15.05
0.5
0.6
Figure 15. k factor for the MGA-785T6 (measured on the board with better noise figure)
5
IIP3 (dBm)
OP1dB (dBm)
6
4 3
0.6
0.7
0.8
0.9
FREQ (GHz)
Figure 17. Output P1dB for the MGA-785T6 (measured on the board with better noise figure)
7
35 30
1
25
0
20
-1
7 mA 10 mA BYPASS
-3
1 0.5
0.9
2
-2
2
0 0.4
IIP3 vs. FREQ
3 Idd = 7 mA Idd = 10 mA
7
0.8
Figure 16. Noise figure for the MGA-785T6 (measured on the board with better noise figure)
OP1dB vs. FREQ
8
0.7 FREQ (GHz)
FREQ (GHz)
-4 0.4
15 10 5
0.5
0.6
0.7
0.8
0 0.9
FREQ (GHz)
Figure 18. IIP3 for the MGA-785T6 (measured on the board with better noise figure)
Bill of Material and Component Placement The performance of this design using the source bias method is demonstrated on a low cost FR4 material. Figure 19 shows the PCB layout and the component placement on the board.
78 C 1L 1 C 2
L2
C 3 R 2
R 1
0 ohm
J um per L3
C 6
C 4 C 5
e x tra tra c e re move d
Figure 19a. PCB layout and component placement
TOP INNER BOTTOM Figure 19b. PCB stacking structure
8
16 mil FR4 MATERIAL TOTAL THICKNESS 62 mils (for MECHANICAL STRENGTH) FR4 MATERIAL/PREPREG (SUPPORT MATERIAL)
Table 2. Bill of Material for MGA-785T6 at the 400-800 MHz Frequency Band Component
Component Value Optimized for Better Input Return Loss
L1 L2
Manufacturer and Part No.
Purpose
TOKO LL1005FHL47NJ
RF Choke
TDK MLK1005S22NJT(1)
Input Matching
Optimized for Better Noise Figure 47 nH
22 nH (1)
15 nH (2)
TDK MLK1005S15NJT(2) L3 C1
27 nH 4.7 pF (1)
5.6 pF (2)
TOKO LL1005FH27NJ
Output Matching/RF Choke
ROHM MCH155A5R6JK(1)
Input Matching
Murata GRM1555C1H4R7CZ01E(2) C2, C4
120 pF
ROHM MCH155A121JK
Bypass capacitor
C3 C5
200 pF
ROHM MCH155A201JK
Bypass capacitor
0.1 PF
Murata GRM155R61A104KA01D
Bypass capacitor
C6
8.2 pF
KEMET C0402C829C3GAC7867
Output Matching
R1
51 :
KAMAYA RMC1/16S JT510
Stability
R2
68 :
ROHM MCR01J680
DC bias (Id = 10 mA)
110 :
–
DC bias (Id = 7 mA)
Summary The MGA-785T6 achieved greater than 15.4 dB gain from 400 MHz to 800 MHz with less than 0.5 dB of gain flatness when operating at 3 V and 10 mA. The gain flatness helps to ensure consistent signal amplification at each channel. The noise figure is 1.6 dB to 2 dB at this frequency range. The output P1dB and the IIP3 is greater than +1 dBm and more than 0 dBm respectively. The excellent linearity helps avoid the generation of third-order intermodulation (IM3) from the strong undesired signal in adjacent channels or channel pairs near to the desired channel. The IM3’s generated will increase the noise power when they fall into the desired channel and cause unreliable reception.
When there is a strong incoming signal, the device can be set to bypass mode. The signal attenuation in the bypass mode is between 2.5 dB and 3.5 dB from 400 MHz to 800 MHz. The device achieved greater than +25 dBm of IIP3 in bypass mode, which helps to improve the dynamic range of the system. Moreover, the current is very small (in the microampere range) in the bypass mode, which is useful to extend the battery life of a mobile receiver.
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-0224EN - April 12, 2011
