Transcript
MGA-310G GNSS Low Noise Amplifier with Variable Bias Current and Shutdown Function
Application Note 5512 Introduction Avago MGA-310G is an easy-to-use, Global Navigation Satellite System (GNSS) band low noise amplifier with variable bias current and shutdown functions. The amplifier has a very low noise figure of less than 0.9 dB while operating at 2.7 V and 8 mA. The LNA is housed in a compact 6-lead UQFN (Ultra-thin Quad Flat No-Lead) package with dimensions of 1.13 mm (L) x 1.1 mm (W) x 0.5 mm (H). All dimensions and a PCB footprint are in the MGA-310G datasheet. The small package can be easily integrated into a compact module. The MGA-310G achieves high gain, low noise figure and high linearity – all at low current – with low external component count. Its adjustable current increases design flexibility. This application note describes the design of LNA circuit for the GPS (1.575 GHz) and GLONASS L1 (1.602 GHz) bands. Figure 1 is a simplified view of the MGA-310G’s internal circuitry. Vsd (pin 4)
Pin Configuration, Variable Bias Current and Shutdown Function Figure 2 shows the pin configuration of the MGA-310G. The bias circuitry is integrated internally to simplify the external biasing circuitry of the module. Unlike the typical depletion-mode pHEMT LNA, Avago’s enhancementmode pHEMT LNA in the MGA-310G requires only one positive voltage supply to bias the LNA. In this design, Vdd (pin 6) and Vsd (pin 4) are supplied with 2.7 V. A 8.2 k: resistor (R1 in Figure 4 and Figure 6) is put between the Vsd pin and the 2.7 V voltage supply to drop the voltage and set the bias current, Idd, to 8 mA. The current drawn by the Vsd pin is in the range of hundreds of microamperes. Pin 3 is not connected internally, but it is recommended to be grounded on the demonstration board. Vdd (pin 6)
RF Out (pin 5)
RF In (pin 1)
Vdd (pin 6) Gnd (pin 2)
Vsd (pin 4)
RFin (pin 1)
Bias / Shutdown Control
RFout (pin 5)
NC (pin 3) BOTTOM VIEW
LNA Gnd (pin 2)
NC – Not Connected
Figure 2. Pin configuration
Package Outline Figure 1. Simplified internal circuitry
The MGA-310G is manufactured with Avago Technologies’ proprietary GaAs E-pHEMT (enhancement-mode pseudomorphic high electron mobility transistor) process to achieve low noise, high gain and high linearity. Operating at 2.7 V and 8 mA, the measured performance of the MGA-310G on the demonstration board shown in Figure 6 was: 0.9 dB Noise Figure, 15 dB gain, +2 dBm input IP3, 2 dBm input P1dB, 9 dB IRL and greater than 10 dB ORL. With Avago’s proprietary GaAs E-pHEMT technology, the MGA-310G is able to operate with a supply voltage down to 1.8 V. MGA-310G performance at 1.8 V is shown in Table 2. Along with the exceptional RF performance, a CMOScompatible shutdown pin is included for turning the LNA on/off or for bias current adjustment. This simplifies the PCB design and the manufacturing process.
The bias current, Idd, can be reduced by increasing the value of R1 to save power consumption. Increasing the bias current by reducing the resistor will improve linearity. Alternatively, the voltage supplied to the Vsd pin can be varied to set the appropriate operating current. The adjustable current allows a designer to make a tradeoff between gain, noise figure, and linearity with current consumption. Performance over different bias current levels can be found in MGA-310G datasheet along with appropriate voltage levels and resistor values. Figure 3 shows bias current versus resistor value at various bias voltages. The LNA module also features a shutdown circuit that is beneficial for portable devices that have limited battery life. When the module is in the shutdown mode, the current consumption is very low 0.5 μA, and the forward isolation is approximately 15 dB. The LNA module can be easily turned off by applying 0 V to 0.3 V to Vsd (pin 4), which is CMOS-compatible. The Vsd pin can be connected to a microcontroller to switch the LNA module to shutdown mode when it is not needed to extend the battery life.
MGA-310G GNSS Receiver Application Circuit Figure 4 shows a MGA-310G GNSS receiver application circuit. The circuit can be used for both GPS (1.575 GHz) and GLONASS L1 band (1.602 GHz) applications. DC blocking capacitors are not needed externally at the device input and output. Resistor R1/Rbias sets the voltage at Vsd (pin 4), which determines the bias current, Idd, into pin 6. A series inductor, L1, followed by a shunt inductor, L2, for optimum noise figure and input return loss, forms the input matching circuit. The series inductor, L1, moves the input impedance close to the Fmin point, *opt. The shunt inductor, L2, moves the input impedance close to the conjugated *in point for good input return loss performance. Figure 5 shows the noise figure circles and the input impedance for a conjugated matching of MGA-310G at 1.575 GHz.
A series inductor alone on the input is sufficient to achieve the best noise figure but with some input return loss degradation. Removing L2 degraded the input return loss to 4 dB and simultaneously reduced the gain by about 1.8 dB. The noise figure improves by 0.1 dB with L2 removed. The L3 biasing inductor together with C2 bypass capacitor sets the output matching and also sets input *in. The internal output coupling capacitor is also part of the output matching network. C3 is a low frequency bypass capacitor for the Vdd line, and C1 decreases the external noise from the Vsd line. The paralleled R2 and L4 are stability components that de-Q C2 and C3. Remove R2 and L4 will cause the K factor <1. Refer to figure 6 for the K factor when R2 and L4 are removed. In addition, R2 and L4 improve the isolation between the external voltage supply and pin 6 of the device.
Idd versus Rbias
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Vsd
Idd, mA
Vdd/Vsd = 1.8 V/ 1.8 V Vdd/Vsd = 2.7 V/ 2.7 V Vdd/Vsd = 3 V/ 3 V Vdd/Vsd = 3.3 V/ 3.3 V Vdd/Vsd = 3.6 V/ 3.6 V
Vdd C3 R2
C1
L4 C2
R1/Rbias 4
L3
6
Bias Control RFin 0
5
10
15
20
25 30 35 Rbias, k ohm
40
45
50
55
L1
1 L2
60
2
MGA-310G
Figure 3. Idd versus Rbias versus Vdd/Vsd
Module Outline Gamma In
Figure 4. GPS LNA application circuit schematic
K factor Versus Frequency
5 4
Gamma Opt K factor
Noise Circles and Input Matching
RFout
5
LNA
3 2
Series inductor L1 Shunt inductor L2
1 0 0.0
cir_pts (0.000 to 51.000) freq (1.400 GHz to 1.700 GHz) Figure 5. MGA-310G Gamma In and Noise Circles at 1.575 GHz.
2
0.5
1.0
1.5
2.0 2.5 Freq, GHz
3.0
3.5
4.0
Figure 6. K factor versus frequency (Measured on demonstration board shown in Figure 7 at 2.7 V/ 8 mA, with R2 and L4 removed)
Component Placement, Bill of Material and PCB Layout The bill of material is shown in Table 1. Performance measured on the demonstration board is summarized in Table 2.
Table 1. Bill of Material Demonstration Board Component
Size
Value
Manufacturer and Part Number
Description
C1
0402
6.8 pF
Murata GRM1555C
Bypass Capacitor
C2
0402
8.2 pF
Murata GRM1555C
Bypass Capacitor/Output Matching
C3
0805
0.1 PF
Murata GRM188R7
Bypass Capacitor
L1
0402
8.2 nH
TOKO LL1005-FHL
Input Matching
L2
0402
15 nH
TOKO LL1005-FHL
Input Matching/ ESD Protection
L3
0402
3.9 nH
TOKO LL1005-FHL
RF Choke/ Output Matching
L4
0402
22 nH
TOKO LL1005-FHL
Stability Enhanced
0402
0:
KOA RK73Z1ELTP
Biasing at 7 mA (Vdd = Vsd = 1.8 V)
0402
8.2 k:
ROHM MCR01J
Biasing at 8 mA (Vdd = Vsd = 2.7 V)
0402
12 :
ROHM MCR01J
Stability Enhanced
R1 R2
L4
Gnd
Vdd
C3
Vsd
Gnd
Component placement on the demonstration board is shown in Figure 7. The demonstration board is fabricated using 10 mil Rogers material supported by additional layers of FR4 and preimpregnated (pre-preg) material to give a total thickness of 62 mils. This thickness gives mechanical rigidity to the whole board and also allows SMA connectors to be easily slipped on both board edges.
R2 C2 L3
L1 L2
300 G
R1
C1
Figure 7. Demonstration board component placement
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Figures 8a and 8b show the layout of each PCB layer and the stacking structure of the demonstration board.
TOP VIEW (TOP METAL)
TOP VIEW (INNER METAL)
TOP VIEW (BOTTOM GROUND METAL)
Figure 8a. Demonstration board Layout
Top Inner
0.5 oz copper
Total Thickness 62 mils
Bottom Figure 8b. PCB stacking structure
Stacking Structure Top Metal
0.5 oz
Top Metal
Substrate
10 mils
Rogers RO4350
Inner Metal
0.5 oz
Ground
FR4
~50 mils
Support Material, for mechanical strength (adjust to achieve total board thickness of 62 mils)
Bottom Metal
0.5 oz
Ground
4
Product Performance Circuit losses are not de-embedded from the demonstration board for all the MGA-310G results published in Table 2.
Table 2. RF Performance for the MGA-310G at 1.575 GHz and 1.602 GHz. Frequency
1.575 GHz
1.602 GHz
Supply Voltage, Vdd
Volts
2.7
1.8
2.7
1.8
Shutdown Voltage, Vsd
Volts
2.7
1.8
2.7
1.8
Bias Current, Idd
mA
8
7
8
7
>1
>1
>1
>1
15
14.7
14.9
14.5
Stability Factor, k (30 kHz – 20 GHz) Gain, S21
dB
Noise Figure @ 1.575 GHz, NF
dB
0.87
0.9
0.88
0.9
Input Return Loss, IRL
dB
9.2
8.2
8.8
8
Output Return Loss, ORL
dB
18.4
20.9
20
21.8
Reverse Isolation
dB
21.6
20.3
21.5
20.4
Input 3rd-order Intercept Point, IIP3 *
dBm
2.1
1.4
5
4.4
@1575.4 MHz Out of band Input 2nd-order Intercept Point, IIP2 **
dBm
17.1 @ 2.7 V/ 8 mA
15.7 @ 1.8 V/ 7 mA
Out of band Input 3rd-order Intercept Point, IIP3 ***
dBm
12.7 @ 2.7 V/ 8 mA
13.4 @ 1.8 V/ 7 mA
* Test condition: FRF1 = 1.5725 GHz, FRF2 = 1.5775 GHz with input power of -20 dBm per tone measured at the worst case side band. ** Test condition: FRF1 = 824.6 MHz and input power level of -17 dBm, FRF2 = 2400 MHz and input power level of -40 dBm. IIP2 = PinRF2 + [PinRF1 – (PoutRF2-RF1 – GPS_Gain)] *** Test condition: FRF1 = 1712.7 MHz and input power level of -20 dBm, FRF2 = 1850 MHz and input power level of -65 dBm. IIP3 = PinRF1 + 0.5*[PinRF2 – (Pout(2 RF2)-RF1 – GPS_Gain)]
Figures 9, 10a, 10b and 10c show the noise figure, gain, return loss, reverse isolation and stability of the MGA-310G on the demonstration board. Noise Figure versus Frequency
1.2
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
Noise Figure, dB
1.1 1.0 0.9 0.8 0.7 0.6 1.570
1.580
1.590
1.600 1.610 Freq, GHz
Figure 9. Noise figure versus frequency
5
1.620
1.630
Input Return Loss Versus Frequency
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
14 12 Gain
Return Loss
10 8 6 4 Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
2 0
0.0
0.5
1.0
1.5
2.0 Freq, GHz
2.5
3.0
3.5
4.0
0.0
Output Return Loss Versus Frequency
0
0.5
1.0
1.5
2.0 Freq, GHz
2.5
3.0
3.5
4.0
Reverse Isolation Versus Frequency
-20
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-5
-25
-10
-30 Reverse Isolation
Return Loss
Gain Versus Frequency
16
-15 -20 -25
-35 -40 -45
-30
-50
-35
-55
-40
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-60 0.0
0.5
1.0
1.5
2.0 Freq, GHz
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0 Freq, GHz
2.5
3.0
3.5
4.0
Figure 10a. Narrow band gain, return loss, and reverse isolation versus frequency Input Return Loss Versus Frequency
0
Gain Versus Frequency
20
-5
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
10 0
-15 Gain
Return Loss
-10
-20 -25
-10 -20
-30 Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-35
-30
-40
-40 2
4
6
8
10 12 Freq, GHz
14
16
18
Output Return Loss Versus Frequency
5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45
2
4
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
6
8
10 12 Freq, GHz
14
16
18
20
16
18
20
Reverse Isolation Versus Frequency
0
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-10 -20 -30 -40 -50 -60 0
2
4
6
8
10 12 Freq, GHz
14
16
18
20
Figure 10b. Wide band gain, return loss, and reverse isolation versus frequency 6
0
20
Reverse Isolation
Return Loss
0
0
2
4
6
8
10 12 Freq, GHz
14
K factor Versus Frequency
5
Vdd/Idd=2.7 V / 8mA Vdd/Idd=1.8 V / 7 mA
3
K factor
K factor
4
2 1 0 0.0
0.5
1.0
1.5
2.0 2.5 Freq, GHz
3.0
3.5
K factor Versus Frequency
20 18 16 14 12 10 8 6 4 2 0
Vdd/Idd=2.7 V / 8mA Vdd/Idd=1.8 V / 7 mA
0
4.0
2
4
6
8
10 12 Freq, GHz
14
16
18
20
Figure 10c. K factor versus frequency
Out-of-band Linearity Performance Figures 11a, 11b and 12 show the out-of-band linearity of the MGA-310G on the demonstration board. Out-of-band IM2 versus Jamming Signal Strength
-20
IM3 at 1575.4 MHz, dBm
IM2 at 1575.4 MHz, dBm
-30 -40 -50 -60 Pin = -20 dBm @ 824.6 MHz Pin = -17 dBm @ 824.6 MHz Pin = -15 dBm @ 824.6 MHz Pin = -10 dBm @ 824.6 MHz
-70 -80 -90 -60
-55
-50
-45
-40 -35 -30 -25 Pin at 2.4 GHz, dBm
-20
-15
-10
Figure 11a. Out-of-band linearity versus jamming signal strength (Refer to Figure 12 for Test Setup)
0 -10 IM2 at 1575.52 MHz
-20
IM2 at 1575.52 MHz versus Jamming Signal Strength Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-40 -50 -60 -70 -80 -35 -30 -25 -20 -15 -10 Jamming Signal Strength at 787.76 MHz, dBm
-5
Figure 12. IM2 performance at 1575.52 MHz versus jamming signal strength at 787.76 MHz (Refer to Figure 14 for Test Setup)
7
Out-of-band IM3 versus Jamming Signal Strength Pin = -20 dBm @ 1712.7 MHz Pin = -15 dBm @ 1712.7 MHz Pin = -10 dBm @ 1712.7 MHz Pin = -5 dBm @ 1712.7 MHz
-55
-50
-45
-40 -35 -30 -25 Pin at 1.85 GHz, dBm
-20
-15
Figure 11b. Out-of-band linearity versus jamming signal strength (Refer to Figure 12 for Test Setup)
-30
-90 -40
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -60
-10
Figure 13 shows the test setup for the measurement results shown in Figure 11a and 11b. Figure 14 shows the test setup for the measurement results shown in Figure 12. Output Power Reference Point Pin (f1)
Signal Generator Signal Generator
Isolator Power Combiner Isolator
10 dB Attenuator
Coaxial Cable
DUT 1.575 GHz K&L Microwave Tunable Bandpass Filter
Spectrum Analyzer
IM2out @ 1575.4 MHz Pin (f2) Input Power Reference Point. Use power meter to read input power.
IIP2 = Pin(f2) + [Pin(f1) – (IM2out-GPS_Gain)] IIP3 = Pin(f1) + 0.5*[Pin(f2) – (IM3out-GPS_Gain)] Figure 13. Test setup for out-of-band linearity versus jamming signal strength
787.76 MHz K&L Microwave Tunable Bandpass Filter
Isolator
1.575 GHz K&L Microwave Tunable Bandpass Filter DUT
Agilent E4438C Signal Generator @787.76 MHz
Cascaded 1.575 GHz K&L Microwave Tunable Notch Filter
Interferer Pin @787.76 MHz
Pout @ 1575.52 MHz
Figure 14. Test setup for IM2 performance at 1575.52 MHz versus jamming signal strength at 787.76 MHz
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Agilent MXA N9020A Spectrum Analyzer
Noise Figure Performance in the Presence of Jamming Signal
Noise Figure Degradation, dB
Figure 15 shows the degradation of the module’s noise figure in the presence of a strong interferer/jamming signal at 1.62 GHz. The degradation is with reference to the module’s noise figure when there is no interferer/ jamming signal presence. The test setup for the measurement is illustrated in Figure 16. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50
Noise Figure Degradation versus Jamming Signal Strength
A GPS bandpass filter is inserted before the noise figure analyzer to prevent the analyzer from being overloaded by the strong jamming signal.
Vdd/Idd = 2.7 V/8 mA Vdd/Idd = 1.8 V/7 mA
-45
The noise source at the GPS frequency is integrated together with the jamming signal by using a power combiner before the signal is delivered to the device under test. The isolator and filters are placed in the jamming signal path to attenuate the noise (at the GPS frequency) generated by the signal generator and prevent it from leaking into the noise figure analyzer, which could cause an inaccurate noise figure measurement.
-40 -35 -30 -25 -20 Jamming Signal Strength, dBm
-15
-10
Figure 15. Noise figure degradation versus jamming signal strength
NF Meter calibration at this point
Input Power Reference Point Use power meter to read input power
Noise Source Agilent N4000A Power Combiner
Signal Generator Agilent E4438C Jamming Signal
Isolator
DUT Coaxial Cable
NF Analyzer Agilent N8975A
1.575 GHz K&L Microwave Tunable Bandpass Filter
1.575 GHz 1.575 GHz Tunable Notch Filter K&L Microwave
1. The bandpass filter will filter the noise generated by the pre-amplifier. 2. The notch filter provides a clean signal at the jammer frequency. The cascaded notch filter gives greater than 100 dB of rejection @ 1.575 GHz. Figure 16. Test setup for noise figure degradation with presence of jamming signal
9
Voltage Supply from RF Output Line
Conclusion
A design may require the voltage supply to come from the RF output line. Figure 17 shows for a design with the voltage supply derived from the RF output. In order to minimize the effect on the RF performance, it is recommended to include the RF choke, RFC, when the voltage supply is derived from the RF output line.
This application note demonstrates MGA-310G performance in a GNSS LNA module that features a very low noise figure, high gain and high linearity even when operated at low voltage and low current. MGA-310G GPS and GLONASS L1 band performance on Avago’s demonstration board is summarized in Table 2. The MGA-310G based module has a low external component count, and it includes a power shutdown circuit and adjustable current capability for long battery life. The MGA-310G is in a compact UQFN package.
Vdd
Vsd DC Voltage
C3 R2
C1
The MGA-310G is an excellent choice for a front-end module that serves GPS and GNSS receiver applications.
L4 Rx
R1/Rbias
C2 L2
RFC
Bias Control RFin
L1
RFout LNA L2 MGA-310 G
Module Outline
A resistor, Rx, can be connected in series to drop the external supply voltage when the external supply voltage is higher than the required Vdd.
RFC Selection to Minimize RF Performance Degradation 1. Select the RFC inductor with a series resonant frequency (SRF) close to and higher than the operating frequency. Or 2. Select the RFC inductor with an impedance ten times higher than the RF output trace.
Figure 17. Voltage supply from RF output line
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2876EN - April 11, 2011
